JP2002299380A - Semiconductor chip mounting structure and method for mounting the semiconductor chip - Google Patents

Semiconductor chip mounting structure and method for mounting the semiconductor chip

Info

Publication number
JP2002299380A
JP2002299380A JP2001099835A JP2001099835A JP2002299380A JP 2002299380 A JP2002299380 A JP 2002299380A JP 2001099835 A JP2001099835 A JP 2001099835A JP 2001099835 A JP2001099835 A JP 2001099835A JP 2002299380 A JP2002299380 A JP 2002299380A
Authority
JP
Japan
Prior art keywords
semiconductor chip
mounting structure
chip mounting
electrode
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001099835A
Other languages
Japanese (ja)
Inventor
Yasushi Tanaka
恭史 田中
Atsushi Tatsuta
淳 立田
Shinobu Kida
忍 木田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2001099835A priority Critical patent/JP2002299380A/en
Publication of JP2002299380A publication Critical patent/JP2002299380A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip mounting structure, capable of sufficiently assuring reliability of electrically connecting a substrate conductive pattern to a conductive adhesive, and to provide a method for mounting the semiconductor chip. SOLUTION: (a) In a flip-chip mounting for disposing a circuit board 1, having a conductive pattern oppositely to an electrode 3 on the surface of the semiconductor chip 2 and electrically connecting the electrode 3 to the board 1; the conductive adhesive 5 is transferred to and coated on the salient electrodes 5; (b) the chip 2 is aligned so that the electrode 4 is contacted with gold stud bumps 6; the adhesive 5 is cured by heating and mounting on the board 2 and is electrically connected; and (c) since a semiconductor chip mounting structure, formed by sealing with a sealing resin 7, can be formed uniformly and stably in a shape of the electrode 4, reliability of the electrical connection can be improved as compared with that by the conventional methods.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを所
定の導電体パターンを設けた基板上に固定し、電気的に
相互接続する半導体チップ実装構造及び半導体チップ実
装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure and a semiconductor chip mounting method for fixing a semiconductor chip on a substrate provided with a predetermined conductor pattern and electrically connecting the semiconductor chips to each other.

【0002】[0002]

【従来の技術】従来、スタッドバンプを形成した半導体
チップを基板に接続する方法としては図9に示すよう
に、導電性接着剤5を、半導体チップ2の電極3に形成
したスタッドバンプ6に転写することによって開始する
方法が一般的である。その後、転写した導電性接着剤5
の粘着力を利用して後述する基板1とスタッドバンプ6
とを接着した後、これを加熱硬化し、更に、後述する封
止樹脂7の注入及び加熱硬化による接続構造の封止を行
い、スタッドバンプ6及び導電性接着剤5を介して半導
体チップ2に設けた電極3と、基板1側の導電体パター
ンとの電気的接続を得るというものである。しかしなが
ら、かかる接続方法には解決すべき課題も指摘されてい
る。最大の課題は、基板導電パターンと導電性接着剤と
の間の接続信頼性の確保である。
2. Description of the Related Art Conventionally, as a method of connecting a semiconductor chip on which a stud bump is formed to a substrate, a conductive adhesive 5 is transferred to a stud bump 6 formed on an electrode 3 of the semiconductor chip 2 as shown in FIG. A common practice is to start by doing. Then, the transferred conductive adhesive 5
The substrate 1 and the stud bump 6 described later by utilizing the adhesive force of
After bonding, the connection structure is sealed by injection of a sealing resin 7 described later and heat curing, and the semiconductor chip 2 is bonded to the semiconductor chip 2 via the stud bumps 6 and the conductive adhesive 5. This is to obtain electrical connection between the provided electrode 3 and the conductor pattern on the substrate 1 side. However, problems to be solved have been pointed out in such a connection method. The greatest challenge is to secure the connection reliability between the substrate conductive pattern and the conductive adhesive.

【0003】即ち、金スタッドバンプ6は、通常、金ワ
イヤの先端を溶融する等の方法で形成されるため、その
形状を均一且つ安定的に形成するのが困難であるとされ
ている。その結果、導電性接着剤の転写量等の制御が困
難となり、基板導電パターンと導電性接着剤との間に充
分な接続信頼性が確保できないというものである。
That is, since the gold stud bump 6 is usually formed by a method such as melting the tip of a gold wire, it is difficult to form the shape uniformly and stably. As a result, it becomes difficult to control the transfer amount of the conductive adhesive and the like, and sufficient connection reliability between the substrate conductive pattern and the conductive adhesive cannot be secured.

【0004】[0004]

【発明が解決しようとする課題】本発明は、上記課題に
鑑みて成されたものであり、その目的とするところは、
基板導電パターンと導電性接着剤との電気的接続の信頼
性が充分に確保できる半導体チップ実装構造及び半導体
チップ実装方法を提供することにある。
DISCLOSURE OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the following:
An object of the present invention is to provide a semiconductor chip mounting structure and a semiconductor chip mounting method capable of sufficiently securing the reliability of electrical connection between a substrate conductive pattern and a conductive adhesive.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、請求項1記載の半導体チップ実装構造の発明にあっ
ては、導電パターンを設けた基板上の突起電極と、半導
体チップ表面の電極部とを対向配置し、相互に電気接続
されたフリップチップ実装構造において、前記基板上の
前記突起電極に塗布された導電性接着剤を介して、前記
半導体チップ表面の前記電極部上に形成したスタッドバ
ンプと接続したことを特徴とするものである。
According to a first aspect of the present invention, there is provided a semiconductor chip mounting structure, comprising: a protruding electrode on a substrate provided with a conductive pattern; and an electrode on a surface of the semiconductor chip. In the flip-chip mounting structure in which the parts are opposed to each other and electrically connected to each other, the flip-chip mounting structure is formed on the electrode part on the surface of the semiconductor chip via a conductive adhesive applied to the protruding electrode on the substrate. It is characterized by being connected to a stud bump.

【0006】請求項2記載の半導体チップ実装構造の発
明にあっては、請求項1記載の半導体チップ実装構造に
おいて、前記突起電極が前記スタッドバンプの頂部に対
応した凸部を有することを特徴とするものである。
According to a second aspect of the present invention, in the semiconductor chip mounting structure according to the first aspect, the protruding electrode has a protrusion corresponding to a top of the stud bump. Is what you do.

【0007】請求項3記載の半導体チップ実装構造の発
明にあっては、請求項1記載の半導体チップ実装構造に
おいて、前記突起電極が前記スタッドバンプの頂部に対
応した凹部を有することを特徴とすることを特徴とする
ものである。
According to a third aspect of the present invention, in the semiconductor chip mounting structure according to the first aspect, the projecting electrode has a concave portion corresponding to a top of the stud bump. It is characterized by the following.

【0008】請求項4記載の半導体チップ実装構造の発
明にあっては、請求項3記載の半導体チップ実装構造に
おいて、前記導電性接着剤の塗布された部位が、前記凹
部内部にのみ限定されることを特徴とするものである。
In the semiconductor chip mounting structure according to a fourth aspect of the present invention, in the semiconductor chip mounting structure according to the third aspect, a portion to which the conductive adhesive is applied is limited only inside the concave portion. It is characterized by the following.

【0009】請求項5記載の半導体チップ実装構造の発
明にあっては、請求項4記載の半導体チップ実装構造に
おいて、前記凹部開口部内径が、前記スタッドバンプの
最大径よりも大きいことを特徴とするものである。
According to a fifth aspect of the present invention, in the semiconductor chip mounting structure according to the fourth aspect, the inner diameter of the opening of the concave portion is larger than the maximum diameter of the stud bump. Is what you do.

【0010】請求項6記載の半導体チップ実装構造の発
明にあっては、請求項1乃至請求項5のいずれかに記載
の半導体チップ実装構造において、隣り合う前記突起電
極間に導電性接着剤流出防止用の隔壁を設けることを特
徴とするものである。
According to a sixth aspect of the present invention, in the semiconductor chip mounting structure according to any one of the first to fifth aspects, the conductive adhesive flows out between the adjacent protruding electrodes. A barrier for prevention is provided.

【0011】請求項7記載の半導体チップ実装構造の発
明にあっては、請求項6記載の半導体チップ実装構造に
おいて、前記隔壁が、少なくとも前記基板、該基板上の
前記突起電極と一体的に同時に成形されてなることを特
徴とするものである。
According to a seventh aspect of the present invention, in the semiconductor chip mounting structure according to the sixth aspect, the partition wall is formed simultaneously with at least the substrate and the protruding electrodes on the substrate at the same time. It is characterized by being formed.

【0012】請求項8記載の半導体チップ実装構造の発
明にあっては、請求項6記載の半導体チップ実装構造に
おいて、前記隔壁が完全硬化前の硬化性樹脂よりなり、
前記半導体チップの接続時に硬化反応を進行させること
により前記半導体チップと前記基板とを固定したことを
特徴とするものである。
According to the invention of a semiconductor chip mounting structure according to claim 8, in the semiconductor chip mounting structure according to claim 6, the partition is made of a curable resin before being completely cured,
The semiconductor chip and the substrate are fixed by advancing a curing reaction when connecting the semiconductor chip.

【0013】請求項9記載の半導体チップ実装構造の発
明にあっては、請求項1乃至請求項8記載の半導体チッ
プ実装構造において、前記基板上に1個又は複数個の封
止樹脂注入孔を設けることを特徴とするものである。
According to a ninth aspect of the present invention, in the semiconductor chip mounting structure according to any one of the first to eighth aspects, one or a plurality of sealing resin injection holes are provided on the substrate. It is characterized by being provided.

【0014】請求項10記載の半導体チップ実装方法の
発明にあっては、導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記基
板上の前記突起電極に導電性接着剤を塗布し、前記半導
体チップ表面の前記電極部上に形成したスタッドバンプ
と接続を行うことを特徴とするものである。
According to a tenth aspect of the present invention, there is provided a flip chip in which a protruding electrode on a substrate on which a conductive pattern is provided and an electrode portion on a surface of a semiconductor chip are opposed to each other, and are electrically connected to each other. In the chip mounting, a conductive adhesive is applied to the protruding electrodes on the substrate, and connection is made with stud bumps formed on the electrode portions on the surface of the semiconductor chip.

【0015】請求項11記載の半導体チップ実装方法の
発明にあっては、導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記接
続前に、前記基板上の前記突起電極の形状に対応して、
前記スタッドバンプを整形することを特徴とするもので
ある。
According to the eleventh aspect of the invention, there is provided a flip chip in which a protruding electrode on a substrate on which a conductive pattern is provided and an electrode portion on a surface of a semiconductor chip are opposed to each other, and a mutual electrical connection is made. In the chip mounting, before the connection, corresponding to the shape of the protruding electrode on the substrate,
The method is characterized in that the stud bump is shaped.

【0016】請求項12記載の半導体チップ実装方法の
発明にあっては、請求項11記載の半導体チップ実装方
法において、前記基板上の前記突起電極に導電性接着剤
を塗布し、前記半導体チップ表面の前記電極部上に形成
したスタッドバンプと接続を行うことを特徴とするもの
である。
According to a twelfth aspect of the present invention, in the semiconductor chip mounting method according to the eleventh aspect, a conductive adhesive is applied to the protruding electrodes on the substrate, and the semiconductor chip surface is provided. And a stud bump formed on the electrode portion.

【0017】[0017]

【発明の実施の形態】以下、本発明の実施形態について
図面に基づき説明する。尚、本発明の半導体チップ接続
構造は、下記の実施形態にのみ限定されるものではな
く、本発明の要旨を逸脱しない範囲内において種々変更
を加え得ることは勿論である。また、下記の実施形態で
は、半導体チップ2を接続する回路基板1としてMID
(射出形成回路部品)により形成したMID回路基板を使
用しているが、本発明の基板はこれらのみに限定される
ものではなく、上記課題解決に寄与する限りにおいて何
ら制約のないことはいうまでもない。更に、下記の実施
形態では、スタッドバンプとして金スタッドバンプ6を
使用しているが、本発明のスタッドバンプはこれのみに
限定されるものではなく、上記課題解決に寄与する限り
において何ら制約のないことはいうまでもない。
Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the semiconductor chip connection structure of the present invention is not limited to the embodiment described below, and it goes without saying that various changes can be made without departing from the spirit of the present invention. Further, in the following embodiment, the MID is used as the circuit board 1 for connecting the semiconductor chip 2.
Although the MID circuit board formed by (injection-formed circuit parts) is used, the board of the present invention is not limited to these, and it goes without saying that there is no limitation as long as it contributes to solving the above-mentioned problem. Nor. Further, in the following embodiment, the gold stud bump 6 is used as the stud bump, but the stud bump of the present invention is not limited to this, and there is no limitation as long as it contributes to solving the above-mentioned problem. Needless to say.

【0018】[第1の実施形態]図1は、本発明の第1
の実施形態に係る半導体チップ実装構造の製造工程の概
略概念を示すもので、 (a)は、実装構造形成前を示す概
略断面図、(b)は、実装構造形成後を示す概略断面図、
(c)は、封止樹脂注入、硬化後を示す概略断面図であ
る。即ち、導電パターン(図示せず)を設けたMID回路
基板1と、半導体チップ2の表面の電極部であるAl電
極3とを対向配置し、電気的接続を行うフリップチップ
実装において、まず、MID回路基板1上に設けた突起
電極4に、導電性接着剤5を転写、塗布し(a)、Al
電極3上に金スタッドバンプ6を形成した半導体チップ
2を突起電極4と金スタッドバンプ6が接触する様に位
置合わせした後、回路基板1に搭載し、加熱により導電
性接着剤5を硬化させ、電気的接続を行う(b)。その
後、封止樹脂7を注入、加熱により硬化させ、半導体チ
ップ接続構造を固定する(c)というものである。
[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
FIGS. 3A and 3B schematically show a concept of a manufacturing process of a semiconductor chip mounting structure according to the embodiment, in which FIG. 3A is a schematic cross-sectional view showing a state before a mounting structure is formed, FIG.
(c) is a schematic sectional view showing the state after the sealing resin is injected and cured. That is, in the flip-chip mounting in which the MID circuit board 1 provided with the conductive pattern (not shown) and the Al electrode 3 which is the electrode portion on the surface of the semiconductor chip 2 are electrically connected to each other, first, the MID circuit board is used. A conductive adhesive 5 is transferred and applied to the protruding electrodes 4 provided on the circuit board 1 (a), and Al
After aligning the semiconductor chip 2 having the gold stud bumps 6 formed on the electrodes 3 so that the bump electrodes 4 and the gold stud bumps 6 are in contact with each other, the semiconductor chip 2 is mounted on the circuit board 1 and the conductive adhesive 5 is cured by heating. And make an electrical connection (b). After that, the sealing resin 7 is injected and cured by heating to fix the semiconductor chip connection structure (c).

【0019】かかる半導体チップ接続構造によれば、金
スタッドバンプ6に導電性接着剤5を転写、塗布する従
来法による接続構造に比較して、金型成形により回路基
板1上の突起電極4が形成されるため、その形状を均一
且つ安定的に形成することが可能となり、その結果、安
定した導電性接着剤5の転写、塗布量を確保でき、電気
的接続の信頼性向上を図ることが可能となる。
According to such a semiconductor chip connection structure, the projecting electrodes 4 on the circuit board 1 are formed by die-molding, as compared with a conventional connection structure in which the conductive adhesive 5 is transferred and applied to the gold stud bumps 6. Since it is formed, it is possible to form the shape uniformly and stably. As a result, it is possible to secure a stable transfer and application amount of the conductive adhesive 5, and to improve the reliability of the electrical connection. It becomes possible.

【0020】[第2の実施形態]図2は、本発明の第2
の実施形態に係る半導体チップ実装構造の要部を示す概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造は、MID回路基板1上に設けた突起電極4が
半導体チップ2のAl電極3上に形成した金スタッドバ
ンプ6の頂部8に対応した凸部4aを有するものであ
る。
[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a main part of a semiconductor chip mounting structure according to the embodiment. That is, in the semiconductor chip mounting structure according to the present embodiment, the projecting electrodes 4 provided on the MID circuit board 1 have the protrusions 4 a corresponding to the tops 8 of the gold stud bumps 6 formed on the Al electrodes 3 of the semiconductor chip 2. Have

【0021】本実施形態においても、実施形態1と同
様、金型成形により回路基板1上の突起電極4が形成さ
れるため、その形状を均一且つ安定的に形成することが
可能となり、その結果、安定した導電性接着剤の転写、
塗布量を確保でき、電気的接続の信頼性向上を図ること
ができる。これに加えて、本実施形態においては、突起
電極4が金スタッドバンプ6の頂部8に対応した凸部4
aを有するため、接続に寄与しうる接着表面積が大きく
なり、一層の電気的接続の信頼性向上を達成することが
できる。
In this embodiment, as in the first embodiment, since the protruding electrodes 4 on the circuit board 1 are formed by molding, it is possible to form the shape uniformly and stably. As a result, Transfer of stable conductive adhesive,
The application amount can be secured, and the reliability of the electrical connection can be improved. In addition, in the present embodiment, in the present embodiment, the protruding electrode 4 corresponds to the convex portion 4 corresponding to the top 8 of the gold stud bump 6.
Due to having a, the bonding surface area that can contribute to the connection is increased, and the reliability of the electrical connection can be further improved.

【0022】[第3の実施形態]図3は、本発明の第3
の実施形態に係る半導体チップ実装構造の要部を示す概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造は、MID回路基板1上に設けた突起電極4が
半導体チップ2のAl電極3上に形成した金スタッドバ
ンプ6の頂部8に対応した凹部4bを有するものであ
る。
[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a main part of a semiconductor chip mounting structure according to the embodiment. That is, in the semiconductor chip mounting structure according to the present embodiment, the protruding electrode 4 provided on the MID circuit board 1 has the concave portion 4 b corresponding to the top 8 of the gold stud bump 6 formed on the Al electrode 3 of the semiconductor chip 2. Things.

【0023】この場合、有効な凹部4bの内径は金スタ
ッドバンプ6の頂部8を構成する金ワイヤの直径よりも
大きければよく、有効な凹部4bの深さは金スタッドバ
ンプ6の外径の10%乃至95%が例示できる。
In this case, the effective inner diameter of the recess 4b may be larger than the diameter of the gold wire forming the top 8 of the gold stud bump 6, and the effective depth of the recess 4b is 10 times the outer diameter of the gold stud bump 6. % To 95%.

【0024】また、本実施形態においても、上記の実施
形態と同様、金型成形により回路基板1上の突起電極4
が形成されるため、その形状を均一且つ安定的に形成す
ることが可能となり、その結果、安定した導電性接着剤
の転写、塗布量を確保でき、電気的接続の信頼性向上を
図ることができる。
Also in this embodiment, similarly to the above embodiment, the projecting electrodes 4 on the circuit board 1 are formed by molding.
Is formed, it is possible to form the shape uniformly and stably, as a result, it is possible to secure a stable transfer and application amount of the conductive adhesive, and to improve the reliability of the electrical connection. it can.

【0025】更に、上記の第2の実施形態と同様、突起
電極4が金スタッドバンプ6の頂部8に対応した凹部4
bを有するため、接続に寄与しうる接着表面積が大きく
なり、一層の電気的接続の信頼性向上を達成することが
できる。
Further, similarly to the above-described second embodiment, the projecting electrode 4 has the concave portion 4 corresponding to the top 8 of the gold stud bump 6.
Due to having b, the bonding surface area that can contribute to the connection increases, and the reliability of the electrical connection can be further improved.

【0026】これに加えて、本実施形態では、突起電極
4の凹部4bに金スタッドバンプ6の頂部8において完
全に又は部分的に埋没する構造となるため、剪断方向の
力に対して接続強度の向上が達成でき、更なる電気的接
続の信頼性向上を達成することができる。
In addition, in the present embodiment, the structure is such that the top 8 of the gold stud bump 6 is completely or partially buried in the recess 4b of the protruding electrode 4, so that the connection strength against the force in the shearing direction. Can be achieved, and the reliability of the electrical connection can be further improved.

【0027】[第4の実施形態]図4は、本発明の第4
の実施形態に係る半導体チップ実装構造の要部を示す概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造も、第3の実施形態と同様、MID回路基板1
上に設けた突起電極4の先端に少なくとも金スタッドバ
ンプ6の頂部8が納まる凹部4cを設け、前記凹部4cの
みに充填した導電性接着剤5により金スタッドバンプ6
の頂部8を挿入、接続するというものである。
[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a main part of a semiconductor chip mounting structure according to the embodiment. That is, similarly to the third embodiment, the semiconductor chip mounting structure according to the present embodiment also has the MID circuit board 1.
At the tip of the protruding electrode 4 provided above, a recess 4c is provided in which at least the top portion 8 of the gold stud bump 6 is accommodated, and the gold stud bump 6 is filled with the conductive adhesive 5 filled only in the recess 4c.
Is inserted and connected.

【0028】この場合も、有効な凹部4cの内径は金ス
タッドバンプ6の頂部8を構成する金ワイヤの直径より
も大きければよく、有効な凹部4cの深さは金スタッド
バンプ6の外径の10%乃至95%が例示できる。
Also in this case, the effective inner diameter of the recess 4c may be larger than the diameter of the gold wire forming the top 8 of the gold stud bump 6, and the effective depth of the recess 4c is smaller than the outer diameter of the gold stud bump 6. 10% to 95% can be exemplified.

【0029】本実施形態においても、上記の第3の実施
形態と同様、突起電極4が金スタッドバンプ6の頂部8
に対応した凹部4cを有するため、同様に、電気的接続
の信頼性向上を達成することができる。これに加えて、
本実施形態では、導電性接着剤5の塗布された部位を、
前記凹部4c内部に限定して、導電性接着剤5の塗布さ
れた部位が、接続部位の側面に露出しない構成としてい
るため、隣り合う電極接続部位間での短絡を有効に回避
でき、更に、安定した電気接続性を得ることができる。
また、この結果、隣り合う電極の間隔のピッチを小さく
設計することが可能となり、実装構造全体の小型、軽量
化にも寄与し得る。
Also in this embodiment, similarly to the third embodiment, the protruding electrode 4 is connected to the top 8 of the gold stud bump 6.
, The reliability of the electrical connection can be similarly improved. In addition to this,
In the present embodiment, the portion where the conductive adhesive 5 is applied is
Only in the recess 4c, the portion where the conductive adhesive 5 is applied is not exposed to the side surface of the connection portion, so that a short circuit between adjacent electrode connection portions can be effectively avoided, and furthermore, Stable electrical connectivity can be obtained.
As a result, it is possible to design the pitch of the interval between the adjacent electrodes to be small, which can contribute to the reduction in size and weight of the entire mounting structure.

【0030】[第5の実施形態]図5は、本発明の第5
の実施形態に係る半導体チップ実装構造の要部を示す概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造は、MID回路基板1上に設けた突起電極4の
先端凹部4dを金スタッドバンプ6全体を納める大きさ
に構成し、突起電極4の凹部4dのみに導電性接着剤5
を充填し、凹部4dに金スタッドバンプ6を埋没、接続
させるというものである。この場合、有効な凹部4dの
内径は金スタッドバンプ6自体の外径よりも大きければ
よく、有効な凹部4dの深さは金スタッドバンプ6の外
径の10%乃至120%が例示できる。
[Fifth Embodiment] FIG. 5 shows a fifth embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a main part of a semiconductor chip mounting structure according to the embodiment. That is, the semiconductor chip mounting structure according to the present embodiment is configured such that the tip recess 4 d of the protruding electrode 4 provided on the MID circuit board 1 is large enough to accommodate the entire gold stud bump 6, and only the recess 4 d of the protruding electrode 4 is provided. Conductive adhesive 5
Is filled, and the gold stud bump 6 is buried and connected to the recess 4d. In this case, the inner diameter of the effective recess 4d may be larger than the outer diameter of the gold stud bump 6 itself, and the effective depth of the recess 4d may be, for example, 10% to 120% of the outer diameter of the gold stud bump 6.

【0031】本実施形態においても、上記の第3の実施
形態、第4の実施形態と同様、突起電極4が金スタッド
バンプ6の頂部8に対応した凹部4dを有するため、同
様に、電気的接続の信頼性向上を達成することができ
る。また、上記の第4の実施形態と同様、導電性接着剤
5の塗布された部位を、前記凹部4c内部に限定して、
導電性接着剤5の塗布された部位が、接続部位の側面に
露出しない構成としているため、隣り合う電極接続部位
間での短絡を有効に回避でき、更に、安定した電気接続
性を得ることができる。また、この結果、上記の第4の
実施形態と同様、隣り合う電極の間隔のピッチを小さく
設計することが可能となり、実装構造全体の小型、軽量
化にも寄与し得る。これに加えて、本実施形態において
は、上記の第4の実施形態と比較して、より広い接着面
積を確保できるので接着力が向上し、接続信頼性の一層
の向上に寄与することができる。
In this embodiment, similarly to the third and fourth embodiments, since the projecting electrode 4 has the concave portion 4 d corresponding to the top 8 of the gold stud bump 6, the electrical connection is similarly made. Improved connection reliability can be achieved. Further, similarly to the fourth embodiment, the portion where the conductive adhesive 5 is applied is limited to the inside of the concave portion 4c,
Since the portion to which the conductive adhesive 5 is applied is not exposed on the side surface of the connection portion, a short circuit between adjacent electrode connection portions can be effectively avoided, and furthermore, stable electrical connectivity can be obtained. it can. Further, as a result, similarly to the fourth embodiment, it is possible to design the pitch of the interval between the adjacent electrodes to be small, which can contribute to the reduction in size and weight of the entire mounting structure. In addition to this, in the present embodiment, a wider bonding area can be secured as compared with the above-described fourth embodiment, so that the bonding strength is improved and the connection reliability can be further improved. .

【0032】[第6の実施形態]図6は、本発明の第6
の実施形態に係る半導体チップ実装構造の要部を示すも
ので、(a)は基板1上の突起電極4と半導体チップ2上
の電極部3の中心線を含む面で切断した概略断面図、
(b)は基板1と平行な突起電極4の横断面で切断した概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造は、導電パターン(図示せず)を設けたMID基
板1上の突起電極4と、半導体チップ表面のAl電極3
とを対向配置して、前記MID基板1上の突起電極4に
導電性接着剤5を塗布し、Al電極3の上に形成した金
スタッドバンプ6と接続することにより構成された半導
体チップ実装構造において、相互に隣接する突起電極4
の間に隔壁9を有することを特徴とするものである。即
ち、突起電極4に転写した導電性接着剤5が電極接続部
位から流出した場合でもこの隔壁9により遮られ、導電
性接着剤5の隣り合う電極接続部位への流出を防止でき
るため、隣り合う電極の間隔が狭ピッチの場合でも隣り
合う電極接続部位間での導電性接着剤塗布部の短絡を有
効に回避でき、また、壁がMID回路基板1と、半導体
チップ2の接続構造におけるスペーサーの役割を果たす
為、前記接続構造における接続ギャップの安定化を達成
できるというものである。
[Sixth Embodiment] FIG. 6 shows a sixth embodiment of the present invention.
(A) is a schematic cross-sectional view cut along a plane including a center line of a protruding electrode 4 on a substrate 1 and an electrode section 3 on a semiconductor chip 2, showing a main part of the semiconductor chip mounting structure according to the embodiment;
FIG. 2B is a schematic cross-sectional view taken along a cross section of the protruding electrode 4 parallel to the substrate 1. That is, the semiconductor chip mounting structure according to the present embodiment includes a projection electrode 4 on the MID substrate 1 provided with a conductive pattern (not shown) and an Al electrode 3 on the surface of the semiconductor chip.
And a semiconductor chip mounting structure formed by applying a conductive adhesive 5 to the protruding electrodes 4 on the MID substrate 1 and connecting to the gold stud bumps 6 formed on the Al electrodes 3. , The adjacent protruding electrodes 4
A partition wall 9 between them. That is, even when the conductive adhesive 5 transferred to the protruding electrode 4 flows out of the electrode connecting portion, the conductive adhesive 5 is blocked by the partition wall 9 and the conductive adhesive 5 can be prevented from flowing out to the adjacent electrode connecting portion. Even when the interval between the electrodes is small, it is possible to effectively avoid short-circuiting of the conductive adhesive application portion between adjacent electrode connection portions, and the wall is formed of a spacer in the connection structure between the MID circuit board 1 and the semiconductor chip 2. Since it plays a role, the stabilization of the connection gap in the connection structure can be achieved.

【0033】また、本実施形態においては、隔壁9をM
ID基板1の形成工程において、基板1、突起電極4等
と一体化した金型等により通常のMIDの成形法によっ
て基板形成と同時成形が可能であり、これにより製造工
程の合理化にも寄与できる。
In the present embodiment, the partition 9 is made of M
In the process of forming the ID substrate 1, it is possible to simultaneously form the substrate and the substrate by a normal MID molding method using a mold or the like integrated with the substrate 1, the protruding electrodes 4, and the like, thereby contributing to the rationalization of the manufacturing process. .

【0034】更に、導電性接着剤流出防止用隔壁9を完
全硬化前の硬化性樹脂より構成し、半導体チップ2の接
続時に硬化反応を進行させ、半導体チップ2と基板1と
を固定する工程を採用すれば、接続時において半導体チ
ップ2と基板1とを確実に固定することが可能となり、
更に充分な初期接続性の向上を達成することができる。
Further, a step of fixing the semiconductor chip 2 and the substrate 1 by forming the partition wall 9 for preventing the conductive adhesive from flowing out of a curable resin before complete curing, and allowing the curing reaction to proceed when the semiconductor chip 2 is connected. If adopted, the semiconductor chip 2 and the substrate 1 can be securely fixed at the time of connection,
Further, it is possible to achieve a sufficient improvement in initial connectivity.

【0035】この場合、導電性接着剤流出防止用隔壁9
を構成する素材としては、例えば、市販の熱硬化性樹脂
を含んでなるフィルム状素材[日東電工(株)製PFM−
21等]の切片等が好適に使用可能であるが、特に限定
はなく、これ以外にも、完全硬化前の硬化性樹脂、即
ち、熱硬化性樹脂、光硬化性樹脂、電子線硬化性樹脂等
を含んでなるものが例示できるが、上記課題解決に寄与
する限りにおいて何ら制約のないことはいうまでもな
い。また、隔壁9の形状についても、導電性接着剤流出
を防止し、隣り合う電極接続部位間での導電性接着剤塗
布部の短絡を有効に回避でき、且つ、封止樹脂7の注
入、充填、硬化を妨げないものであれば、特に図6に例
示した形状に限定されず、上記課題解決に寄与する限り
において何ら制約のないことはいうまでもない。
In this case, the partition 9 for preventing the conductive adhesive from flowing out.
Examples of the material constituting the film include, for example, a film-like material containing a commercially available thermosetting resin [PFM- manufactured by Nitto Denko Corporation]
21 etc.] can be suitably used, but there is no particular limitation. In addition, curable resins before complete curing, that is, thermosetting resins, photocurable resins, and electron beam curable resins And the like can be exemplified, but it goes without saying that there is no restriction as long as it contributes to solving the above-mentioned problem. Also, regarding the shape of the partition wall 9, the conductive adhesive can be prevented from flowing out, a short circuit of the conductive adhesive applied portion between adjacent electrode connection sites can be effectively avoided, and the sealing resin 7 is injected and filled. The shape is not particularly limited to the shape illustrated in FIG. 6 as long as it does not hinder the curing, and it goes without saying that there is no restriction as long as it contributes to solving the above-mentioned problem.

【0036】[第7の実施形態]図7は、本発明の第7
の実施形態に係る半導体チップ実装構造の要部を示すも
ので、(a)は基板1上の突起電極4と半導体チップ2上
の電極部3の中心線を含む面で切断した概略断面図、
(b)は基板1と平行な突起電極4の横断面で切断した概
略断面図である。即ち、本実施形態に係る半導体チップ
実装構造は、上記の第6の実施形態と同様、導電性接着
剤流出防止用の隔壁9を有するMID回路基板1上に、
更に前記隔壁9の近傍の基板上に封止樹脂注入のための
孔10を設け、この孔から封止樹脂7を注入、充填した
後、これを硬化して樹脂封止を行うというものである。
この際、例えば、従来、封止樹脂7の充填が不充分にな
りがちであった回路基板1上の突起部のコーナー部(例
えば、本実施形態の隔壁9のコーナー部)等に封止樹脂
注入孔10を配設することにより封止樹脂7の充填を確
実に行うことができる。これにより、従来の側面からの
封止樹脂7の注入方法とは異なり、ボイド等の発生しに
くい樹脂封止が可能となり、半導体チップ接続構造の接
続信頼性の更なる向上を図ることができる。
[Seventh Embodiment] FIG. 7 shows a seventh embodiment of the present invention.
(A) is a schematic cross-sectional view cut along a plane including a center line of a protruding electrode 4 on a substrate 1 and an electrode section 3 on a semiconductor chip 2, showing a main part of the semiconductor chip mounting structure according to the embodiment;
FIG. 2B is a schematic cross-sectional view taken along a cross section of the protruding electrode 4 parallel to the substrate 1. That is, the semiconductor chip mounting structure according to the present embodiment is, like the sixth embodiment, provided on the MID circuit board 1 having the partition 9 for preventing the conductive adhesive from flowing out.
Further, a hole 10 for injecting a sealing resin is provided on the substrate in the vicinity of the partition wall 9, and after the sealing resin 7 is injected and filled from this hole, it is cured to perform resin sealing. .
At this time, for example, the sealing resin is placed on the corners of the protrusions on the circuit board 1 (for example, the corners of the partition walls 9 of the present embodiment) and the like, which have conventionally tended to be insufficiently filled with the sealing resin 7. By providing the injection hole 10, the sealing resin 7 can be reliably filled. Thereby, unlike the conventional method of injecting the sealing resin 7 from the side, resin sealing in which voids or the like are hardly generated can be performed, and the connection reliability of the semiconductor chip connection structure can be further improved.

【0037】また、封止樹脂注入のための孔10の配設
部位、大きさ、形状、個数等についても、封止樹脂7の
注入、充填、硬化をボイドの発生等をなくして、有利に
実施できるものであれば、特に図7に例示した実施形態
に限定されず、上記課題解決に寄与する限りにおいて何
ら制約のないことはいうまでもない。
The location, size, shape, number, etc., of the holes 10 for injecting the sealing resin are also advantageously reduced by eliminating, filling, and curing the sealing resin 7 by eliminating voids and the like. As long as it can be implemented, it is not particularly limited to the embodiment illustrated in FIG. 7, and it goes without saying that there is no restriction as long as it contributes to solving the above-mentioned problem.

【0038】[第8の実施形態]図8は、本発明の第8
の実施形態に係る半導体チップ実装方法の概略を示すも
ので、(a)は整形前を示す概略断面図、(b)は整形工程を
示す概略断面図、(c)は整形後を示す概略断面図であ
る。即ち、本実施形態に係る半導体チップ実装方法は、
半導体チップ2上のAl電極3に形成した金スタッドバ
ンプ6を金型11により基板1上の突起電極4の形状に
対応して、整形を行い、金スタッドバンプ6の形状の不
均一性を是正するというものである。
[Eighth Embodiment] FIG. 8 shows an eighth embodiment of the present invention.
FIGS. 3A and 3B schematically show a semiconductor chip mounting method according to the embodiment, in which FIG. 3A is a schematic sectional view showing a state before shaping, FIG. 3B is a schematic sectional view showing a shaping step, and FIG. FIG. That is, the semiconductor chip mounting method according to the present embodiment includes:
The gold stud bumps 6 formed on the Al electrodes 3 on the semiconductor chip 2 are shaped by a mold 11 according to the shapes of the protruding electrodes 4 on the substrate 1 to correct the non-uniformity of the shape of the gold stud bumps 6. It is to do.

【0039】これにより、本来、形状を均一且つ安定的
に形成するのが困難な金スタッドバンプ6を形成後、事
後的に整形することにより形状の均一化を図り、導電性
接着剤の転写量の管理を容易にし、安定した接合性を確
保することにより、半導体チップ接続構造の接続信頼性
の更なる向上を図ることができる。具体的なスタッドバ
ンプの整形に要する圧力は、例えば、外径25μの金ワ
イヤから形成した外径100μの金スタッドバンプ6の
場合、1×10-3〜1×10-1Kgf/個で目的を達成
することができる。
Thus, after forming the gold stud bumps 6, which are originally difficult to form the shape uniformly and stably, the shape is made uniform by ex-post shaping, and the transfer amount of the conductive adhesive is obtained. In this case, the connection reliability of the semiconductor chip connection structure can be further improved by facilitating the management of the semiconductor chip and ensuring the stable bonding. The specific pressure required for shaping the stud bump is, for example, 1 × 10 -3 to 1 × 10 -1 Kgf / piece for a gold stud bump 6 having an outer diameter of 100 μ formed from a gold wire having an outer diameter of 25 μ. Can be achieved.

【0040】また、本実施形態に係る半導体チップ接続
方法は、上記した第1乃至第8の実施の形態に係る半導
体チップ接続構造の形成に有利に適用可能であることは
言うに及ばず、導電性接着剤5をまず、スタッドバンプ
に転写することによって開始する上記した従来の半導体
チップ接続方法にも充分適用可能であり、接続信頼性の
向上に寄与することができるものである。
Further, it goes without saying that the semiconductor chip connection method according to the present embodiment can be advantageously applied to the formation of the semiconductor chip connection structures according to the above-described first to eighth embodiments. The method can be sufficiently applied to the above-described conventional semiconductor chip connection method which is started by first transferring the conductive adhesive 5 to the stud bumps, and can contribute to improvement of connection reliability.

【0041】[0041]

【発明の効果】以上のように、請求項1記載の半導体チ
ップ実装構造の発明にあっては、導電パターンを設けた
基板上の突起電極と、半導体チップ表面の電極部とを対
向配置し、相互に電気接続されたフリップチップ実装構
造において、前記基板上の前記突起電極に塗布された導
電性接着剤を介して、前記半導体チップ表面の前記電極
部上に形成したスタッドバンプと接続したことを特徴と
するので、スタッドバンプに導電性接着剤を転写、塗布
する従来法による接続構造に比較して、金型成形により
回路基板上の突起電極を形成することができるため、そ
の突起電極の形状を均一且つ安定的に形成することが可
能となり、導電性接着剤の転写、塗布量を安定的に確保
でき、電気的接続の信頼性向上を図ることができるとい
う優れた効果を奏する。
As described above, in the invention of the semiconductor chip mounting structure according to the first aspect, the protruding electrode on the substrate provided with the conductive pattern and the electrode portion on the surface of the semiconductor chip are arranged so as to face each other. In the flip-chip mounting structure electrically connected to each other, it is connected to a stud bump formed on the electrode portion on the surface of the semiconductor chip via a conductive adhesive applied to the projecting electrode on the substrate. As compared to the conventional connection structure in which conductive adhesive is transferred and applied to stud bumps, the protruding electrodes on the circuit board can be formed by molding, so the shape of the protruding electrodes Can be formed uniformly and stably, the transfer and application amount of the conductive adhesive can be stably secured, and the excellent effect of improving the reliability of the electrical connection can be achieved. That.

【0042】請求項2記載の半導体チップ実装構造の発
明にあっては、請求項1記載の半導体チップ実装構造に
おいて、前記突起電極が前記スタッドバンプの頂部に対
応した凸部を有することを特徴とするので、請求項1記
載の半導体チップ実装構造の発明の効果に加えて、接続
に寄与しうる接着表面積が大きくなるため、一層の電気
的接続の信頼性向上を達成することができるという優れ
た効果を奏する。
According to a second aspect of the present invention, in the semiconductor chip mounting structure according to the first aspect, the protruding electrode has a convex portion corresponding to the top of the stud bump. Therefore, in addition to the effect of the invention of the semiconductor chip mounting structure according to the first aspect, since the bonding surface area that can contribute to the connection is increased, the reliability of the electrical connection can be further improved. It works.

【0043】請求項3記載の半導体チップ実装構造の発
明にあっては、請求項1記載の半導体チップ実装構造に
おいて、前記突起電極が前記スタッドバンプの頂部に対
応した凹部を有することを特徴とするので、請求項1記
載の半導体チップ実装構造の発明の効果に加えて、接続
に寄与しうる接着表面積が大きくなるため、一層の電気
的接続の信頼性向上を達成することができるという優れ
た効果を奏する。これに加えて、本発明では、突起電極
の凹部にスタッドバンプがその頂部において部分的に埋
没する構造となるため、剪断方向の力に対して接続強度
の向上が達成でき、電気的接続の一層の信頼性向上を達
成することができるという優れた効果を奏する。
According to a third aspect of the present invention, in the semiconductor chip mounting structure according to the first aspect, the projecting electrode has a concave portion corresponding to the top of the stud bump. Therefore, in addition to the effect of the invention of the semiconductor chip mounting structure according to the first aspect, since the bonding surface area that can contribute to the connection is increased, the excellent effect that the reliability of the electrical connection can be further improved can be achieved. To play. In addition, according to the present invention, the stud bump has a structure in which the stud bump is partially buried in the concave portion of the protruding electrode at the top, so that the connection strength can be improved with respect to the force in the shear direction, and the electrical connection can be further improved. This has an excellent effect that the reliability can be improved.

【0044】請求項4記載の半導体チップ実装構造の発
明にあっては、請求項3記載の半導体チップ実装構造に
おいて、前記導電性接着剤の塗布された部位が、前記凹
部内部にのみ限定されることを特徴とするので、請求項
3記載の半導体チップ実装構造の発明の効果に加えて、
導電性接着剤の塗布された部位が、接続部位の側面に露
出しない構成を有するため、隣り合う電極接続部位間で
の短絡を有効に回避でき、更に、安定した電気接続性を
得ることができる。また、この結果、隣り合う電極の間
隔のピッチを小さく設計することが可能となり、実装構
造全体の小型、軽量化にも寄与し得るという優れた効果
を奏する。
In the semiconductor chip mounting structure according to a fourth aspect of the present invention, in the semiconductor chip mounting structure according to the third aspect, a portion to which the conductive adhesive is applied is limited only to the inside of the concave portion. Therefore, in addition to the effects of the invention of the semiconductor chip mounting structure according to claim 3,
Since the portion to which the conductive adhesive is applied is not exposed on the side surface of the connection portion, a short circuit between adjacent electrode connection portions can be effectively avoided, and furthermore, stable electrical connectivity can be obtained. . Further, as a result, it is possible to design the pitch of the interval between the adjacent electrodes to be small, and there is an excellent effect that it is possible to contribute to reduction in size and weight of the entire mounting structure.

【0045】請求項5記載の半導体チップ実装構造の発
明にあっては、請求項4記載の半導体チップ実装構造に
おいて、前記凹部開口部内径が、前記スタッドバンプの
最大径よりも大きいことを特徴とするので、請求項4記
載の半導体チップ実装構造の発明の効果に加えて、更に
広い接着面積を確保できるので接着力が向上し、接続信
頼性の更なる向上に寄与することができるという優れた
効果を奏する。
According to a fifth aspect of the present invention, in the semiconductor chip mounting structure according to the fourth aspect, the inner diameter of the opening of the concave portion is larger than the maximum diameter of the stud bump. Therefore, in addition to the effect of the invention of the semiconductor chip mounting structure according to the fourth aspect, an excellent bonding area can be secured, so that the adhesive strength is improved, and it is possible to contribute to further improvement of connection reliability. It works.

【0046】請求項6記載の半導体チップ実装構造の発
明にあっては、請求項1乃至請求項5記載の半導体チッ
プ実装構造において、隣り合う前記突起電極間に導電性
接着剤流出防止用の隔壁を設けることを特徴とするの
で、請求項1乃至請求項5のいずれかに記載の半導体チ
ップ実装構造の発明の効果に加えて、突起電極に転写し
た導電性接着剤が電極接続部位から流出した場合でもこ
の隔壁により遮られ、導電性接着剤の隣り合う電極接続
部位への流出を防止できる。このため、隣り合う電極の
間隔が狭ピッチの場合でも隣り合う電極接続部位間での
導電性接着剤塗布部の短絡を有効に回避でき、併せて、
隔壁が回路基板と半導体チップとの接続構造におけるス
ペーサーの役割を果たす為、この接続構造における接続
ギャップの安定化を達成できるという優れた効果を奏す
る。
According to a sixth aspect of the present invention, in the semiconductor chip mounting structure according to any one of the first to fifth aspects, a partition for preventing a conductive adhesive from flowing out between the adjacent protruding electrodes. Therefore, in addition to the effect of the invention of the semiconductor chip mounting structure according to any one of claims 1 to 5, the conductive adhesive transferred to the protruding electrode flows out of the electrode connection portion. Even in this case, the conductive adhesive is blocked by the partition walls and can be prevented from flowing out to the adjacent electrode connection site. For this reason, even if the interval between adjacent electrodes is a narrow pitch, a short circuit of the conductive adhesive application portion between adjacent electrode connection portions can be effectively avoided, and
Since the partition functions as a spacer in the connection structure between the circuit board and the semiconductor chip, there is an excellent effect that the connection gap in this connection structure can be stabilized.

【0047】請求項7記載の半導体チップ実装構造の発
明にあっては、請求項6記載の半導体チップ実装構造に
おいて、導電性接着剤流出防止用の隔壁が、少なくとも
基板、該基板上の突起電極と一体的に同時に成形されて
なることを特徴とするので請求項6記載の半導体チップ
実装構造の発明の効果に加えて、製造工程の合理化に寄
与できるという優れた効果を奏する。
In the semiconductor chip mounting structure according to a seventh aspect of the present invention, in the semiconductor chip mounting structure according to the sixth aspect, the partition for preventing the conductive adhesive from flowing out is at least a substrate and a projecting electrode on the substrate. Since it is characterized by being formed simultaneously and integrally with the semiconductor chip, in addition to the effect of the invention of the semiconductor chip mounting structure according to claim 6, there is an excellent effect that it can contribute to rationalization of the manufacturing process.

【0048】請求項8記載の半導体チップ実装構造の発
明にあっては、請求項6記載の半導体チップ実装構造に
おいて、導電性接着剤流出防止用の隔壁が完全硬化前の
硬化性樹脂よりなり、半導体チップの接続時に硬化反応
を進行させることにより半導体チップと基板とを固定し
たことを特徴とするので、請求項6記載の半導体チップ
実装構造の発明の効果に加えて、接続時において半導体
チップと基板とを確実に固定することが可能となり、充
分な初期接続性の向上を達成することができるという優
れた効果を奏する。
In the semiconductor chip mounting structure according to the eighth aspect, in the semiconductor chip mounting structure according to the sixth aspect, the partition for preventing the conductive adhesive from flowing out is made of a curable resin before being completely cured, The semiconductor chip and the substrate are fixed by advancing a curing reaction at the time of connection of the semiconductor chip, so that in addition to the effect of the invention of the semiconductor chip mounting structure according to claim 6, the semiconductor chip is connected at the time of connection. An excellent effect that the substrate and the substrate can be securely fixed and sufficient initial connectivity can be achieved can be achieved.

【0049】請求項9記載の半導体チップ実装構造の発
明にあっては、請求項1乃至請求項8記載の半導体チッ
プ実装構造において、基板上に1個又は複数個の封止樹
脂注入孔を設けることを特徴とするので、請求項1乃至
請求項8記載の半導体チップ実装構造の発明の効果に加
えて、従来の側面から封止樹脂を注入する方法とは異な
り、ボイド等の発生しにくい樹脂封止が可能となり、半
導体チップ接続構造の接続信頼性の更なる向上を図るこ
とができるという優れた効果を奏する。
According to a ninth aspect of the present invention, in the semiconductor chip mounting structure according to any one of the first to eighth aspects, one or a plurality of sealing resin injection holes are provided on the substrate. Therefore, in addition to the effect of the invention of the semiconductor chip mounting structure according to claim 1 to claim 8, unlike a conventional method of injecting a sealing resin from a side surface, a resin in which voids and the like hardly occur. Sealing is possible, and an excellent effect that the connection reliability of the semiconductor chip connection structure can be further improved can be achieved.

【0050】請求項10記載の半導体チップ実装方法の
発明にあっては、導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記基
板上の前記突起電極に導電性接着剤を塗布し、前記半導
体チップ表面の前記電極部上に形成したスタッドバンプ
と接続を行うことを特徴とするので、スタッドバンプに
導電性接着剤を転写、塗布する従来の実装方法に比較し
て、金型成形により回路基板上の突起電極を形成するこ
とができるため、その突起電極の形状を均一且つ安定的
に形成することが可能となり、導電性接着剤の転写、塗
布量を安定的に確保でき、電気的接続の信頼性向上を図
ることができるという優れた効果を奏する。
According to a tenth aspect of the present invention, there is provided a flip chip in which a protruding electrode on a substrate on which a conductive pattern is provided and an electrode portion on a surface of a semiconductor chip are opposed to each other, and are electrically connected to each other. In chip mounting, a conductive adhesive is applied to the protruding electrodes on the substrate, and connection is made with stud bumps formed on the electrode portions on the semiconductor chip surface. Compared with the conventional mounting method of transferring and applying the adhesive, the projecting electrodes on the circuit board can be formed by molding, so that the shape of the projecting electrodes can be formed uniformly and stably. Thus, an excellent effect of stably securing the transfer and application amount of the conductive adhesive and improving the reliability of the electrical connection can be achieved.

【0051】請求項11記載の半導体チップ実装方法の
発明にあっては、導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記接
続前に、前記基板上の前記突起電極の形状に対応して、
前記スタッドバンプを整形することを特徴とするもので
あるので、これにより、本来、形状を均一且つ安定的に
形成するのが困難な金スタッドバンプ6を形成後、事後
的に整形することにより形状の均一化を図り、導電性接
着剤の転写量の管理を容易にし、安定した接合性を確保
することにより、半導体チップ接続構造の接続信頼性の
更なる向上を図ることが可能となるという優れた効果を
奏する。
According to the eleventh aspect of the present invention, a flip-chip is provided in which a protruding electrode on a substrate on which a conductive pattern is provided and an electrode portion on the surface of a semiconductor chip are arranged to face each other, and a mutual electrical connection is made. In the chip mounting, before the connection, corresponding to the shape of the protruding electrode on the substrate,
Since the stud bump is shaped, the gold stud bump 6 whose shape is originally difficult to form uniformly and stably is formed, and then the shape is formed by ex post shaping. It is possible to further improve the connection reliability of the semiconductor chip connection structure by making the transfer of the conductive adhesive easier, and ensuring stable bonding by making the transfer of the conductive adhesive uniform. It has the effect.

【0052】請求項12記載の半導体チップ実装構造の
発明にあっては、請求項11記載の半導体チップ実装方
法において、前記基板上の前記突起電極に導電性接着剤
を塗布し、前記半導体チップ表面の前記電極部上に形成
したスタッドバンプと接続を行うことを特徴とするもの
であるので、請求項11記載の半導体チップ実装方法の
発明の効果に加えて、スタッドバンプに導電性接着剤を
転写、塗布する従来の実装方法に比較して、金型成形に
より回路基板上の突起電極を形成することができるた
め、その突起電極の形状を均一且つ安定的に形成するこ
とが可能となり、導電性接着剤の転写、塗布量を安定的
に確保でき、電気的接続の信頼性向上を図ることができ
るという優れた効果を奏する。
According to a twelfth aspect of the present invention, in the method of mounting a semiconductor chip according to the eleventh aspect, a conductive adhesive is applied to the protruding electrodes on the substrate, and the surface of the semiconductor chip is mounted. Since the connection is made with the stud bump formed on the electrode portion, the conductive adhesive is transferred to the stud bump in addition to the effect of the invention of the semiconductor chip mounting method according to claim 11. As compared with the conventional mounting method of coating, the protruding electrodes on the circuit board can be formed by molding, so that the shape of the protruding electrodes can be formed uniformly and stably, and the conductivity can be improved. An excellent effect is obtained in that the transfer and application amount of the adhesive can be secured stably, and the reliability of the electrical connection can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係る半導体チップ実
装構造の製造工程の概略概念を示すもので、 (a)は、実
装構造形成前を示す概略断面図、(b)は、実装構造形成
後を示す概略断面図、(c)は、封止樹脂注入、硬化後を
示す概略断面図である。
FIGS. 1A and 1B schematically show a manufacturing process of a semiconductor chip mounting structure according to a first embodiment of the present invention. FIG. 1A is a schematic cross-sectional view showing a state before a mounting structure is formed, and FIG. FIG. 3C is a schematic cross-sectional view showing a state after the structure is formed, and FIG.

【図2】本発明の第2の実施形態に係る半導体チップ実
装構造の要部を示す概略断面図である。
FIG. 2 is a schematic sectional view showing a main part of a semiconductor chip mounting structure according to a second embodiment of the present invention.

【図3】本発明の第3の実施形態に係る半導体チップ実
装構造の要部を示す概略断面図である。
FIG. 3 is a schematic sectional view showing a main part of a semiconductor chip mounting structure according to a third embodiment of the present invention.

【図4】本発明の第4の実施形態に係る半導体チップ実
装構造の要部を示す概略断面図である。
FIG. 4 is a schematic sectional view showing a main part of a semiconductor chip mounting structure according to a fourth embodiment of the present invention.

【図5】本発明の第5の実施形態に係る半導体チップ実
装構造の要部を示す概略断面図である。
FIG. 5 is a schematic sectional view showing a main part of a semiconductor chip mounting structure according to a fifth embodiment of the present invention.

【図6】本発明の第6の実施形態に係る半導体チップ実
装構造の要部を示すもので、(a)は基板1上の突起電極
4と半導体チップ2上の電極部3の中心線を含む面で切
断した概略断面図、(b)は基板1と平行な突起電極4の
横断面で切断した概略断面図である。
FIGS. 6A and 6B show a main part of a semiconductor chip mounting structure according to a sixth embodiment of the present invention. FIG. 6A shows a center line between a protruding electrode 4 on a substrate 1 and an electrode section 3 on a semiconductor chip 2. FIG. 2B is a schematic cross-sectional view taken along a cross section of the protruding electrode 4 parallel to the substrate 1.

【図7】本発明の第7の実施形態に係る半導体チップ実
装構造の要部を示すもので、(a)は基板1上の突起電極
4と半導体チップ2上の電極部3の中心線を含む面で切
断した概略断面図、(b)は基板1と平行な突起電極4の
横断面で切断した概略断面図である。
FIGS. 7A and 7B show a main part of a semiconductor chip mounting structure according to a seventh embodiment of the present invention. FIG. 7A shows a center line between a protruding electrode 4 on a substrate 1 and an electrode part 3 on a semiconductor chip 2. FIG. 2B is a schematic cross-sectional view taken along a cross section of the protruding electrode 4 parallel to the substrate 1.

【図8】本発明の第8の実施形態に係る半導体チップ実
装方法の概略を示すもので、(a)は整形前を示す概略断
面図、(b)は整形工程を示す概略断面図、(c)は整形後を
示す概略断面図である。
8A and 8B schematically show a semiconductor chip mounting method according to an eighth embodiment of the present invention, wherein FIG. 8A is a schematic sectional view showing a state before shaping, FIG. 8B is a schematic sectional view showing a shaping step, (c) is a schematic sectional view showing the state after shaping.

【図9】従来例に係る半導体チップ実装方法における導
電性接着剤5の転写工程の概略概念をを示すもので、
(a)は転写前を示す概略断面図、(b)は転写後を示す概略
断面図である。
FIG. 9 shows a schematic concept of a transfer step of a conductive adhesive 5 in a semiconductor chip mounting method according to a conventional example.
(a) is a schematic sectional view showing a state before transfer, and (b) is a schematic sectional view showing a state after transfer.

【符号の説明】[Explanation of symbols]

1 基板 2 半導体チップ 3 電極部 4 突起電極 5 導電性接着剤 6 スタッドバンプ 7 封止樹脂 8 頂部 9 隔壁 10封止樹脂注入孔 11金型 DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor chip 3 Electrode part 4 Protruding electrode 5 Conductive adhesive 6 Stud bump 7 Sealing resin 8 Top part 9 Partition 10 Sealing resin injection hole 11 Mold

フロントページの続き (72)発明者 木田 忍 大阪府門真市大字門真1048番地松下電工株 式会社内 Fターム(参考) 5F044 KK17 KK27 LL07 LL11 QQ02 QQ04 Continued on the front page (72) Inventor Shinobu Kida 1048 Kadoma, Kadoma, Osaka Pref. Matsushita Electric Works Co., Ltd. F term (reference) 5F044 KK17 KK27 LL07 LL11 QQ02 QQ04

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 導電パターンを設けた基板上の突起電極
と、半導体チップ表面の電極部とを対向配置し、相互に
電気接続されたフリップチップ実装構造において、前記
基板上の前記突起電極に塗布された導電性接着剤を介し
て、前記半導体チップ表面の前記電極部上に形成したス
タッドバンプと接続したことを特徴とする半導体チップ
実装構造。
In a flip-chip mounting structure in which a protruding electrode on a substrate provided with a conductive pattern and an electrode portion on a surface of a semiconductor chip are opposed to each other and electrically connected to each other, the protruding electrode on the substrate is coated on the protruding electrode. A semiconductor chip mounting structure, wherein the semiconductor chip mounting structure is connected to a stud bump formed on the electrode portion on the surface of the semiconductor chip through the provided conductive adhesive.
【請求項2】 前記突起電極が前記スタッドバンプの頂
部に対応した凸部を有することを特徴とする請求項1記
載の半導体チップ実装構造。
2. The semiconductor chip mounting structure according to claim 1, wherein said projection electrode has a projection corresponding to a top of said stud bump.
【請求項3】 前記突起電極が前記スタッドバンプの頂
部に対応した凹部を有することを特徴とする請求項1記
載の半導体チップ実装構造。
3. The semiconductor chip mounting structure according to claim 1, wherein said protruding electrode has a concave portion corresponding to a top of said stud bump.
【請求項4】 前記導電性接着剤の塗布された部位が、
前記凹部内部にのみ限定されることを特徴とする請求項
3記載の半導体チップ実装構造。
4. A site to which the conductive adhesive is applied,
4. The semiconductor chip mounting structure according to claim 3, wherein the semiconductor chip mounting structure is limited only inside the concave portion.
【請求項5】 前記凹部開口部内径が、前記スタッドバ
ンプの最大径よりも大きいことを特徴とする請求項4記
載の半導体チップ実装構造。
5. The semiconductor chip mounting structure according to claim 4, wherein the inner diameter of the opening of the concave portion is larger than the maximum diameter of the stud bump.
【請求項6】 隣り合う前記突起電極間に導電性接着剤
流出防止用の隔壁を設けることを特徴とする請求項1乃
至請求項5のいずれかに記載の半導体チップ実装構造。
6. The semiconductor chip mounting structure according to claim 1, wherein a partition for preventing the conductive adhesive from flowing out is provided between the adjacent protruding electrodes.
【請求項7】 前記隔壁が、少なくとも前記基板、該基
板上の前記突起電極と一体的に同時に成形されてなるこ
とを特徴とする請求項6記載の半導体チップ実装構造。
7. The semiconductor chip mounting structure according to claim 6, wherein said partition is formed at least simultaneously with said substrate and said projecting electrode on said substrate.
【請求項8】 前記隔壁が完全硬化前の硬化性樹脂より
なり、前記半導体チップの接続時に硬化反応を進行させ
ることにより前記半導体チップと前記基板とを固定した
ことを特徴とする請求項6記載の半導体チップ実装構
造。
8. The semiconductor device according to claim 6, wherein the partition wall is made of a curable resin before complete curing, and the semiconductor chip and the substrate are fixed by advancing a curing reaction when connecting the semiconductor chip. Semiconductor chip mounting structure.
【請求項9】 前記基板上に1個又は複数個の封止樹脂
注入孔を設けることを特徴とする請求項1乃至請求項8
記載の半導体チップ実装構造。
9. The method according to claim 1, wherein one or a plurality of sealing resin injection holes are provided on the substrate.
The semiconductor chip mounting structure described in the above.
【請求項10】 導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記基
板上の前記突起電極に導電性接着剤を塗布し、前記半導
体チップ表面の前記電極部上に形成したスタッドバンプ
と接続を行うことを特徴とする半導体チップ実装方法。
10. In flip-chip mounting in which a protruding electrode on a substrate provided with a conductive pattern and an electrode portion on the surface of a semiconductor chip are opposed to each other and electrically connected to each other, the protruding electrode on the substrate is electrically conductive. A method of mounting a semiconductor chip, comprising applying an adhesive and connecting to a stud bump formed on the electrode portion on the surface of the semiconductor chip.
【請求項11】 導電パターンを設けた基板上の突起電
極と、半導体チップ表面の電極部とを対向配置し、相互
の電気接続を行うフリップチップ実装において、前記接
続前に、前記基板上の前記突起電極の形状に対応して、
前記スタッドバンプを整形することを特徴とする半導体
チップ実装方法。
11. In flip-chip mounting in which a protruding electrode on a substrate provided with a conductive pattern and an electrode portion on a surface of a semiconductor chip are opposed to each other and are electrically connected to each other, before the connection, According to the shape of the protruding electrode,
A method of mounting a semiconductor chip, wherein the stud bump is shaped.
【請求項12】 前記基板上の前記突起電極に導電性接
着剤を塗布し、前記半導体チップ表面の前記電極部上に
形成したスタッドバンプと接続を行うことを特徴とする
請求項11記載の半導体チップ実装方法。
12. The semiconductor according to claim 11, wherein a conductive adhesive is applied to the protruding electrode on the substrate, and a connection is made with a stud bump formed on the electrode portion on the surface of the semiconductor chip. Chip mounting method.
JP2001099835A 2001-03-30 2001-03-30 Semiconductor chip mounting structure and method for mounting the semiconductor chip Pending JP2002299380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2002299380A true JP2002299380A (en) 2002-10-11

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008263001A (en) * 2007-04-11 2008-10-30 Nec Corp Electronic component mounting structure and electronic component mounting method
JP2009267067A (en) * 2008-04-24 2009-11-12 Panasonic Electric Works Co Ltd Structure for mounting semiconductor element and mounting method thereof
JP2014027210A (en) * 2012-07-30 2014-02-06 Fujitsu Semiconductor Ltd Semiconductor device and semiconductor device manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008263001A (en) * 2007-04-11 2008-10-30 Nec Corp Electronic component mounting structure and electronic component mounting method
JP2009267067A (en) * 2008-04-24 2009-11-12 Panasonic Electric Works Co Ltd Structure for mounting semiconductor element and mounting method thereof
JP2014027210A (en) * 2012-07-30 2014-02-06 Fujitsu Semiconductor Ltd Semiconductor device and semiconductor device manufacturing method
US9691676B2 (en) 2012-07-30 2017-06-27 Socionext Inc. Semiconductor device and method for manufacturing the same

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