JP2005136035A - Bump electrode structure and method for forming bumps - Google Patents

Bump electrode structure and method for forming bumps Download PDF

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JP2005136035A
JP2005136035A JP2003368679A JP2003368679A JP2005136035A JP 2005136035 A JP2005136035 A JP 2005136035A JP 2003368679 A JP2003368679 A JP 2003368679A JP 2003368679 A JP2003368679 A JP 2003368679A JP 2005136035 A JP2005136035 A JP 2005136035A
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bump
electrode
bof
tape
lead electrode
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Japanese (ja)
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Takeshi Matsumoto
健 松本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector

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Abstract

<P>PROBLEM TO BE SOLVED: To prevent occurrence of insufficient contact between a bump on the BOF-tape side and an electrode on the semiconductor chip side. <P>SOLUTION: Fine protrusions and recesses 3b are formed on the surface of a bump 3, formed on a lead electrode 2 by employing a lead electrode 2 having a comb-shape 12. Since the part of protrusions and recesses 3b on the bump 3 becomes flat as a whole, contact area between the bump 3 and the semiconductor electrode 5 of a semiconductor chip 4 is widened. Consequently, contact is improved and electrical stability is obtained between them. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、半導体装置を構成する基板上のリード電極上に形成されるバンプ電極構造、およびバンプ形成方法に関するものである。   The present invention relates to a bump electrode structure formed on a lead electrode on a substrate constituting a semiconductor device, and a bump forming method.

従来の半導体基板にバンプ電極（突起電極）を形成するための方法の一例として、特許文献１に記載された技術を例示することができる。   As an example of a method for forming bump electrodes (projection electrodes) on a conventional semiconductor substrate, the technique described in Patent Document 1 can be exemplified.

また、従来の半導体装置のパッケージ形成方法、特にＢＯＦ（Bump On Film）のパッケージ形成方法について、図４〜図６を参照して説明する。   Also, a conventional package forming method for a semiconductor device, particularly a BOF (Bump On Film) package forming method, will be described with reference to FIGS.

図４は従来のＢＯＦパッケージの構成とその組立を説明するための断面図、図５は図４におけるＢＯＦパッケージ用テープにおけるリード電極の形状を示した平面図であって、１はＢＯＦテープ、２はリード電極、３はバンプ、４は半導体チップ、５は半導体電極、６は表面保護膜である。   4 is a cross-sectional view for explaining the structure and assembly of a conventional BOF package, FIG. 5 is a plan view showing the shape of the lead electrode in the BOF package tape in FIG. Is a lead electrode, 3 is a bump, 4 is a semiconductor chip, 5 is a semiconductor electrode, and 6 is a surface protective film.

図６−１と図６−２は前記ＢＯＦテープ１の形成方法を工程順に示す断面図であって、各図において、１はＢＯＦテープ、２はリード電極、２ａは電極層、２ｂは電極エッチングレジスト、３はバンプ、３ａはバンプレジストである。   FIGS. 6A and 6B are sectional views showing the method of forming the BOF tape 1 in the order of steps. In each figure, 1 is a BOF tape, 2 is a lead electrode, 2a is an electrode layer, and 2b is an electrode etching. Resist 3, 3 is a bump, 3a is a bump resist.

以下、従来のＢＯＦテープの形成方法を具体的に説明する。   Hereinafter, a conventional method for forming a BOF tape will be described in detail.

まず、拡散工程において、ウェハ状態で半導体装置を形成し、その際、外部出力と接続する部分について、図４の下側に示す半導体電極５をアルミなどで形成する。その後、半導体電極５以外の部分を表面保護膜６で覆う。通常、表面保護膜６は、窒化膜などを使用する。その後、ダイシング等で半導体チップ４を切り出す。   First, in the diffusion step, a semiconductor device is formed in a wafer state, and at that time, a semiconductor electrode 5 shown on the lower side of FIG. Thereafter, the portion other than the semiconductor electrode 5 is covered with the surface protective film 6. Usually, a nitride film or the like is used as the surface protective film 6. Thereafter, the semiconductor chip 4 is cut out by dicing or the like.

また一方で、図４の上側に示すＢＯＦパッケージ用テープの形成を行う。まず、ポリイミド製のＢＯＦテープ１と電極層２ａの２層構造になっているベースのテープを形成し（図６−１（ａ））、その後、このテープ上の全面に感光性の電極エッチングレジスト２ｂの形成を行う（図６−１（ｂ））。さらにマスクおよび現像工程を経ることで、リード電極２を形成する部分以外のレジストの除去を行い（図６−１（ｃ））、その後、エッチング工程で電極層２ａのエッチングを行った後（図６−１（ｄ））、電極エッチングレジスト２ｂの除去を行う（図６−１（ｅ））。   On the other hand, the BOF package tape shown in the upper side of FIG. 4 is formed. First, a base tape having a two-layer structure of a polyimide BOF tape 1 and an electrode layer 2a is formed (FIG. 6A), and then a photosensitive electrode etching resist is formed on the entire surface of the tape. 2b is formed (FIG. 6-1 (b)). Further, the resist other than the portion where the lead electrode 2 is formed is removed through a mask and a development process (FIG. 6C), and then the electrode layer 2a is etched in the etching process (FIG. 6). 6-1 (d)), the electrode etching resist 2b is removed (FIG. 6-1 (e)).

その後、このテープ全面のバンプレジスト３ａの形成を行い（図６−２（ｆ））、その後、マスクおよび現像工程を経ることで、バンプ３を形成する部分以外のバンプレジスト３ａの除去を行う（図６−２（ｇ））。その後、めっき工程でバンプ３の形成を行う（図６−１（ｈ））。通常、このめっきはＡｕあるいはＣｕめっきであり、電解めっきを用いるのが一般的である。その後、バンプレジスト３ａの除去を行い（図６−２（ｉ））、ＢＯＦパッケージ用テープが完成する。   Thereafter, the bump resist 3a is formed on the entire surface of the tape (FIG. 6-2 (f)), and then the bump resist 3a other than the portion where the bump 3 is formed is removed through a mask and a development process ( Fig. 6-2 (g)). Thereafter, bumps 3 are formed in the plating step (FIG. 6-1 (h)). Usually, this plating is Au or Cu plating, and electrolytic plating is generally used. Thereafter, the bump resist 3a is removed (FIG. 6-2 (i)), and the BOF package tape is completed.

その後、この半導体チップ４とＢＯＦテープ１との組立を行う。その方法としてはまず、半導体チップ４とＢＯＦテープ１との位置合わせを行い、その後、接合させる半導体電極５とバンプ３との位置合わせを行い、両者の接合を行う。   Thereafter, the semiconductor chip 4 and the BOF tape 1 are assembled. As the method, first, the semiconductor chip 4 and the BOF tape 1 are aligned, and then the semiconductor electrode 5 to be bonded and the bump 3 are aligned, and both are bonded.

その後、図４に示すように、半導体チップ４とＢＯＦテープ１とをツールなどを用いて熱圧着させる。このようにすることにより、バンプ３が半導体チップ４上で潰れ、両者の導通が可能となる。またその際、封止樹脂を半導体チップ４およびＢＯＦテープ１の間に注入する。その後、ツールなどを外し、硬化させることによりＢＯＦパッケージが完成する。
特開平７−２２１１０２号公報 Thereafter, as shown in FIG. 4, the semiconductor chip 4 and the BOF tape 1 are thermocompression bonded using a tool or the like. By doing so, the bumps 3 are crushed on the semiconductor chip 4 and the two can be conducted. At that time, a sealing resin is injected between the semiconductor chip 4 and the BOF tape 1. Thereafter, the BOF package is completed by removing the tool and curing it.
JP-A-7-221102

しかしながら、図４，図５，図６−１，図６−２に示すような従来のＢＯＦパッケージ形成方法では、バンプ３自体の形状が先の丸まった突起状であるため、半導体チップ４とＢＯＦテープ１との組立を行った場合、バンプ３と半導体電極５が点接触になってしまい、両者の接触不良が生じやすくなるという課題がある。   However, in the conventional BOF package forming method as shown in FIGS. 4, 5, 6-1 and 6-2, the shape of the bump 3 itself is a rounded protrusion. When the tape 1 is assembled, the bump 3 and the semiconductor electrode 5 are in point contact, and there is a problem that a contact failure between both tends to occur.

本発明は、前記従来の課題を解決し、半導体電極との接触不良を生じないバンプ電極構造、およびバンプ形成方法を提供することを目的とする。   An object of the present invention is to solve the above conventional problems and provide a bump electrode structure and a bump forming method that do not cause poor contact with a semiconductor electrode.

前記目的を達成するため、本発明は、リード電極の形状を櫛状にすることによって、リード電極上に形成するバンプ表面に略平坦なフラット部分を設け、このバンプ表面のフラット部分により、バンプと半導体装置の外部電極との接触を良好にすることを可能にするものである。   To achieve the above object, the present invention provides a substantially flat flat portion on the bump surface formed on the lead electrode by forming the shape of the lead electrode into a comb shape, This makes it possible to improve the contact with the external electrode of the semiconductor device.

本発明によれば、バンプ表面がフラットなため、バンプと半導体装置の外部電極の接触面積が広くなり、このことにより両者の接触が良好になり、電気的に安定した半導体装置パッケージを実現することに寄与する。   According to the present invention, since the bump surface is flat, the contact area between the bump and the external electrode of the semiconductor device is widened, thereby improving the contact between the two and realizing an electrically stable semiconductor device package. Contribute to.

本発明に係るバンプ電極構造、およびバンプ形成方法の実施形態について、以下、図面を参照しながら説明する。   DESCRIPTION OF EMBODIMENTS Embodiments of a bump electrode structure and a bump forming method according to the present invention will be described below with reference to the drawings.

図１は本実施形態のＢＯＦパッケージの構成とその組立を説明するための断面図、図２は図１におけるＢＯＦパッケージ用テープにおけるリード電極の形状を示した平面図であって、１はＢＯＦテープ、２はリード電極、３はバンプ、４は半導体装置の半導体チップ、５は半導体電極、６は表面保護膜、１２は櫛状のリード電極である。   FIG. 1 is a cross-sectional view for explaining the configuration and assembly of the BOF package of this embodiment, FIG. 2 is a plan view showing the shape of the lead electrode in the BOF package tape in FIG. 1, and 1 is the BOF tape 2 is a lead electrode, 3 is a bump, 4 is a semiconductor chip of a semiconductor device, 5 is a semiconductor electrode, 6 is a surface protection film, and 12 is a comb-shaped lead electrode.

図３−１と図３−２は本実施形態におけるＢＯＦテープの形成方法を工程順に示す断面図であって、各図において、１はＢＯＦテープ、２ａは電極層、２ｂは電極エッチングレジスト、３はバンプ、３ａはバンプレジスト、１２は櫛状のリード電極である。   3A and 3B are cross-sectional views showing the BOF tape forming method in this embodiment in the order of steps. In each figure, 1 is a BOF tape, 2a is an electrode layer, 2b is an electrode etching resist, Are bumps, 3a are bump resists, and 12 are comb-shaped lead electrodes.

以下、本実施例のＢＯＦテープの形成方法を具体的に説明する。   Hereinafter, the method for forming the BOF tape of this example will be described in detail.

まず、拡散工程において図１の下側に示す半導体装置の内部回路を形成するとともに、外部電極パッドである半導体電極５を形成する。通常、半導体電極５はＡｌで形成される。また、マイグレーション対策のため、Ｃｕなどを混ぜる場合もある。その後、表面保護膜６で、半導体電極５の全体を覆い、その後、エッチング等で、開口部分を形成する。表面保護膜６の材料としては、Ｐｌ−ＳｉＮが用いられる。その後、半導体チップ４上をポリイミドなどで被う場合もある。その後、ダイシングなどで半導体チップ１を切り出す。   First, in the diffusion step, the internal circuit of the semiconductor device shown in the lower side of FIG. 1 is formed, and the semiconductor electrode 5 which is an external electrode pad is formed. Usually, the semiconductor electrode 5 is made of Al. Also, Cu or the like may be mixed for migration countermeasures. Thereafter, the entire surface of the semiconductor electrode 5 is covered with the surface protective film 6, and then an opening is formed by etching or the like. As a material of the surface protective film 6, Pl-SiN is used. Thereafter, the semiconductor chip 4 may be covered with polyimide or the like. Thereafter, the semiconductor chip 1 is cut out by dicing or the like.

また一方で、図１の上側に示すＢＯＦパッケージ用テープの形成を行う。まず、ポリイミド製のＢＯＦテープ１と電極層２ａの２層構造になっているベースのテープを形成する。電極層２ａは通常、Ｃｕが用いられる（図３−１（ａ））。その後、このテープ上の全面に感光性の電極エッチングレジスト２ｂの形成を行う。通常、この形成には印刷方法などが用いられる（図３−１（ｂ））。その後、マスクおよび現像工程を経ることで、櫛形状のリード電極１２を形成する部分以外のレジストの除去を行い（図３−１（ｃ））、エッチング工程で電極層２ａのエッチングを行った後（図３−１（ｄ））、レジストの除去を行って櫛形状のリード電極１２にする（図３−１（ｅ））。   On the other hand, the BOF package tape shown in the upper side of FIG. 1 is formed. First, a base tape having a two-layer structure of a polyimide BOF tape 1 and an electrode layer 2a is formed. Usually, Cu is used for the electrode layer 2a (FIG. 3-1 (a)). Thereafter, a photosensitive electrode etching resist 2b is formed on the entire surface of the tape. Usually, a printing method or the like is used for this formation (FIG. 3-1 (b)). Thereafter, the resist other than the portion where the comb-shaped lead electrode 12 is formed is removed by passing through a mask and a development process (FIG. 3-1 (c)), and the electrode layer 2a is etched in the etching process. (FIG. 3-1 (d)), the resist is removed to form a comb-shaped lead electrode 12 (FIG. 3-1 (e)).

その後、このテープ全面のバンプレジスト３ａの形成を行い（図３−１（ｆ））、マスクおよび現像工程を経ることで、バンプ３を形成する部分以外のレジストの除去を行う（図３−１（ｇ））。その後、めっき工程でバンプ３の形成を行う（図３−１（ｈ））。通常、このめっきはＡｕあるいはＣｕめっきであり、電解めっきを用いるのが一般的である。その後、このバンプレジスト３ａの除去を行う（図３−１（ｉ））。   Thereafter, a bump resist 3a is formed on the entire surface of the tape (FIG. 3-1 (f)), and the resist other than the portion where the bump 3 is formed is removed through a mask and a development process (FIG. 3-1). (G)). Thereafter, bumps 3 are formed in the plating process (FIG. 3-1 (h)). Usually, this plating is Au or Cu plating, and electrolytic plating is generally used. Thereafter, the bump resist 3a is removed (FIG. 3-1 (i)).

本実施形態においてリード電極１２を櫛状にする理由としては、後工程のめっき工程において、このリード電極１２上にバンプ３を形成したときに、バンプ３の表面において細かい凹凸３ｂを発生させるためである。   The reason why the lead electrode 12 is formed in a comb shape in the present embodiment is that when the bump 3 is formed on the lead electrode 12 in the subsequent plating step, fine irregularities 3b are generated on the surface of the bump 3. is there.

すなわち、リード電極１２を櫛状にすることにより、この部位に電界が加わる部分と加わらない部分が存在することになり、電界が加わる部分にめっきが形成され、また、電界が加わらない部分にはめっきが形成されないことになり、このため、リード電極１２がない部分にはめっきが形成されずに、その部分が凹になる。したがって、櫛状のリード電極１２に対向するバンプ３の部位全体として細かな凹凸３ｂが発生することになり、バンプ３の上面に比較的フラットな部分が形成される。   That is, by forming the lead electrode 12 in a comb shape, there are a portion where an electric field is applied and a portion where an electric field is not applied to this portion, plating is formed in a portion where an electric field is applied, and a portion where an electric field is not applied. Plating will not be formed. For this reason, plating is not formed in a portion where the lead electrode 12 is not provided, and the portion becomes concave. Therefore, fine irregularities 3b are generated in the entire portion of the bump 3 facing the comb-shaped lead electrode 12, and a relatively flat portion is formed on the upper surface of the bump 3.

その後、この半導体チップ４とＢＯＦテープ１との組立を行う（図１）。その方法としては、まず半導体チップ４とＢＯＦテープ１との位置を合わせ、接合させる半導体電極５とバンプ３との位置合わせを行い、両者の接合を行う。その後、半導体チップ４とＢＯＦテープ１とをツールなどで熱圧着させる。   Thereafter, the semiconductor chip 4 and the BOF tape 1 are assembled (FIG. 1). As the method, first, the semiconductor chip 4 and the BOF tape 1 are aligned, the semiconductor electrode 5 to be bonded and the bump 3 are aligned, and the two are bonded. Thereafter, the semiconductor chip 4 and the BOF tape 1 are thermocompression bonded with a tool or the like.

また、その際、封止樹脂を半導体チップ４およびＢＯＦテープ１の間に注入する。これにより、半導体電極５とバンプ３が接合し、電気的に導通する。また、封止樹脂を注入することにより、半導体チップ４とＢＯＦテープ１の間が埋められ、半導体電極５あるいはバンプ３に水分などが触れることにより腐食することを防ぐことができる。   At that time, a sealing resin is injected between the semiconductor chip 4 and the BOF tape 1. Thereby, the semiconductor electrode 5 and the bump 3 are joined and electrically connected. Further, by injecting the sealing resin, the space between the semiconductor chip 4 and the BOF tape 1 is filled, and corrosion due to moisture or the like touching the semiconductor electrode 5 or the bump 3 can be prevented.

本実施形態では、前記のようにバンプ３表面が比較的フラットになるようにＢＯＦパッケージ用テープを作製しているため、バンプ３と半導体電極５との接触面積を広くとることが可能となり、このことにより、バンプ３と半導体電極５とが電気的にオープンすることのない接合が可能となり、より良好なＢＯＦパッケージの製造が実現する。   In this embodiment, since the BOF package tape is manufactured so that the surface of the bump 3 is relatively flat as described above, it is possible to increase the contact area between the bump 3 and the semiconductor electrode 5. As a result, the bump 3 and the semiconductor electrode 5 can be joined without being electrically opened, and a better BOF package can be manufactured.

本発明は、バンプと半導体チップの外部電極との接触を良好にして電気的に安定させるようにするバンプ電極、およびそのバンプ形成方法に適用され、特にＢＯＦ（Bump On Film）のパッケージ形成において有効である。   INDUSTRIAL APPLICABILITY The present invention is applied to a bump electrode that makes the contact between the bump and the external electrode of the semiconductor chip good and is electrically stabilized, and a method for forming the bump, and is particularly effective in forming a BOF (Bump On Film) package. It is.

本発明の実施形態のＢＯＦパッケージの構成とその組立を説明するための断面図Sectional drawing for demonstrating the structure of the BOF package of the embodiment of this invention, and its assembly 図１におけるＢＯＦパッケージ用テープにおけるリード電極の形状を示した平面図The top view which showed the shape of the lead electrode in the tape for BOF packages in FIG. 本実施形態におけるＢＯＦテープの形成方法を工程順に示す断面図Sectional drawing which shows the formation method of the BOF tape in this embodiment in order of a process 本実施形態におけるＢＯＦテープの形成方法を工程順に示す断面図Sectional drawing which shows the formation method of the BOF tape in this embodiment in order of a process 従来のＢＯＦパッケージの構成とその組立を説明するための断面図Sectional drawing for demonstrating the structure of the conventional BOF package, and its assembly 図４におけるＢＯＦパッケージ用テープにおけるリード電極の形状を示した平面図The top view which showed the shape of the lead electrode in the tape for BOF packages in FIG. 従来のＢＯＦテープの形成方法を工程順に示す断面図Sectional drawing which shows the formation method of the conventional BOF tape in order of a process 従来のＢＯＦテープの形成方法を工程順に示す断面図Sectional drawing which shows the formation method of the conventional BOF tape in order of a process

符号の説明Explanation of symbols

１ ＢＯＦテープ
２ リード電極
２ａ 電極層
２ｂ 電極エッチングレジスト
３ バンプ
３ａ バンプレジスト
３ｂ バンプの細かな凹凸
４ 半導体チップ
５ 半導体電極
６ 表面保護膜
１２ 櫛状のリード電極 DESCRIPTION OF SYMBOLS 1 BOF tape 2 Lead electrode 2a Electrode layer 2b Electrode etching resist 3 Bump 3a Bump resist 3b Fine bump unevenness 4 Semiconductor chip 5 Semiconductor electrode 6 Surface protective film 12 Comb-like lead electrode

Claims (2)

櫛状に形成されたリード電極と、前記リード電極上に設けられて該リード電極に対向する外表面が略平坦面をなすバンプとからなり、前記バンプにおける前記略平坦面を半導体装置の外部電極と接触する接触面としたことを特徴とするバンプ電極構造。   A lead electrode formed in a comb shape and a bump provided on the lead electrode and having an outer surface facing the lead electrode having a substantially flat surface. The substantially flat surface of the bump is an external electrode of a semiconductor device. A bump electrode structure characterized by having a contact surface in contact with the electrode. 請求項１記載のバンプ電極構造を形成するバンプ形成方法であって、リード電極をエッチングにより櫛状に形成する工程と、前記リード電極上にバンプを形成し、前記バンプの前記リード電極に対向する外表面に略平坦な部分を形成する工程とを備えたことを特徴とするバンプ形成方法。   2. A bump forming method for forming a bump electrode structure according to claim 1, wherein a step of forming a lead electrode in a comb shape by etching, a bump is formed on the lead electrode, and the bump is opposed to the lead electrode. And a step of forming a substantially flat portion on the outer surface.
JP2003368679A 2003-10-29 2003-10-29 Bump electrode structure and method for forming bumps Pending JP2005136035A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931110A (en) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 Method for packaging semiconductor component
US9293432B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for chip packaging structure
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9548282B2 (en) 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931110A (en) * 2012-11-08 2013-02-13 南通富士通微电子股份有限公司 Method for packaging semiconductor component
US9293432B2 (en) 2012-11-08 2016-03-22 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for chip packaging structure
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9548282B2 (en) 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device

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