CN108447828B - Packaging structure and substrate bonding method - Google Patents

Packaging structure and substrate bonding method Download PDF

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Publication number
CN108447828B
CN108447828B CN201710083448.8A CN201710083448A CN108447828B CN 108447828 B CN108447828 B CN 108447828B CN 201710083448 A CN201710083448 A CN 201710083448A CN 108447828 B CN108447828 B CN 108447828B
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opening
forming
copper pillar
pillar structures
stepped blind
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CN108447828A (en
Inventor
李建财
柯正达
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Xinxing Electronics Co Ltd
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Xinxing Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides packaging structures and a method for bonding the same, wherein the packaging structure comprises a th substrate, a 0 th carrier and a plurality of copper pillar structures, the th substrate has a plurality of stepped blind vias, each of which comprises a th opening, a second opening and a horizontal step surface, the diameter of the second opening is larger than that of the th opening, the horizontal step surface is located at the junction of the th opening and the second opening, the carrier has a plurality of pads disposed on the surface thereof, each of the copper pillar structures has a th end and a second end which are opposite, wherein the th end is in electrical contact with the second end, the second end is connected with the th opening, and each of the stepped blind vias is filled with each of the copper pillar structures.

Description

Packaging structure and substrate bonding method
Technical Field
The invention relates to packaging technologies, in particular to a method for bonding packaging structures and a substrate.
Background
As Semiconductor packaging technology has evolved, Semiconductor devices (Semiconductor devices) have been developed into different packaging types, such as: wire bonding, flip chip, or hybrid (i.e., flip-chip-bonded).
Currently, attention is paid to a chip packaging technology using a copper structure for bonding, which uses a pressing method to bond a chip and a package carrier. However, the current copper bonding can be performed at a temperature of 300 ℃ to 450 ℃ and a pressure as high as 300MPa, so that the high bonding temperature and pressure can not lead to mass production of the package.
Disclosure of Invention
The invention provides kinds of packaging structures, which are suitable for packaging mass production at low temperature and normal pressure.
The present invention also provides kinds of substrate jointing method, which can complete copper jointing under low temperature and normal pressure.
The kinds of package structures of the invention include a substrate, a 0 th carrier, and a plurality of copper pillar structures, the substrate has a plurality of stepped blind vias, each of the stepped blind vias includes a th opening, a second opening and a horizontal step surface, the aperture of the second opening is larger than that of the th opening, the horizontal step surface is located at the junction of the th opening and the second opening, the carrier has a plurality of pads disposed on the surface thereof, each of the copper pillar structures has a th end and a second end opposite to each other, wherein the th end is electrically connected to the pad, the second end is connected to the th opening, and each of the copper pillar structures fills each of the stepped blind vias.
In the embodiment of the invention, the height of the copper pillar structure is greater than or equal to the depth of the stepped blind hole.
In the embodiment of the invention, the wall surface of the hole may be a vertical surface.
In the embodiment of the invention, the wall surface of the hole can be an inclined surface, and the aperture at the intersection of the hole and the horizontal step surface is larger than the aperture of the hole away from the horizontal step surface.
In the embodiment of the invention, the carrier may include a circuit board (circuit board), a carrier (carrier), a package (package) or an electronic component (electronic component).
In of the present invention, the package structure may further include a copper interface layer between the copper pillar structure and the stepped blind via.
The substrate bonding method includes forming multiple stepped blind holes in the substrate, each of which includes a th opening and a second opening, the diameter of the second opening being larger than that of the th opening, forming multiple copper pillar structures on multiple pads on the surface of the th carrier, the diameter of each copper pillar structure being larger than that of the th opening and smaller than that of the second opening, etching the copper pillar structures to make the top surfaces of the copper pillar structures dome, and then pressing the copper pillar structures into the stepped blind holes to fill the stepped blind holes with the copper pillar structures.
In another embodiment of the present invention, the temperature for pressing the copper pillar structure to the stepped blind via is between 60 ℃ and 160 ℃.
In another embodiment of the present invention, the pressure for pressing the copper pillar structure to the stepped blind hole is normal pressure.
In another embodiment of the present invention, the step of forming the stepped blind hole in the th substrate includes sequentially forming a th dielectric layer and a second dielectric layer on the carrier, forming a second opening in the second dielectric layer to expose a portion of the th dielectric layer, and forming a th opening in the exposed th dielectric layer.
In another embodiment of the invention, the method of forming the th opening includes a photolithographic etching process or a laser process.
In another embodiment of the invention, the method of forming the second opening includes a photolithographic etching process.
In another embodiment of the present invention, the step of forming the stepped blind hole in the substrate includes sequentially forming a Photo Imageable Dielectric (PID) layer and a second photo imageable dielectric layer on the carrier, then patterning the second photo imageable dielectric layer to form a second opening and expose a portion of the photo imageable dielectric layer, and then patterning the photo imageable dielectric layer to form a opening.
In another embodiment of the present invention, a copper interface layer may be formed on the inner surface of the stepped blind hole after the stepped blind hole is formed.
In another embodiment of the present invention, the step of forming the copper pillar structure includes forming a seed layer on the pad, forming a passivation layer on the th carrier to cover the seed layer, forming an opening in the passivation layer to expose the seed layer, and forming the copper pillar structure from the seed layer.
Based on the above, the present invention provides kinds of substrates with stepped blind holes and matches with a copper pillar structure with a dome, so that the dome can be joined with the stepped blind hole during the pressing process and stress concentration points are generated during the contact, the processing temperature and pressure of the copper pressing process are effectively reduced, and the processing of the present invention is suitable for mass production.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a cross-sectional view of a package structure according to an embodiment of the invention;
FIGS. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process for forming stepped blind holes in substrate bonding methods according to a second embodiment of the present invention;
FIGS. 3A-3E are schematic cross-sectional views illustrating a manufacturing process for forming a copper pillar structure in substrate bonding methods according to a second embodiment of the invention;
fig. 4A to 4B are schematic cross-sectional views illustrating a pressing process in the substrate bonding method according to the second embodiment of the invention.
Description of reference numerals:
100: packaging structure
102. 400 th th substrate
104. 402 th th carrier
104a, 302 a: surface of
106. 314: copper column structure
106a at th end
106 b: second end
108. 212, and (3): stepped blind hole
110. 208 opening at th
112. 206: second opening hole
114. 210: horizontal step surface
116. 304: connecting pad
118. 306: seed layer
120. 126, 200, 300: bearing plate
122. 202 th dielectric layer
124. 204: a second dielectric layer
128: electronic component
130. 308: protective layer
132. 404: space(s)
214: copper interface layer
302: chip and method for manufacturing the same
310: photoresist
312: opening of the container
314 a: dome
d: depth of field
h: height
r1, r2, r 3: pore diameter
r 4: diameter of
θ: angle of rotation
Detailed Description
The following is a detailed description of embodiments taken in conjunction with the accompanying drawings, which are not intended to limit the scope of the invention.
Further, terms such as "", "second", etc. used herein do not mean order or sequence, and are understood to distinguish elements or operations described in the same technical terms.
Furthermore, as used herein, the terms "comprising," "including," "having," and the like are open-ended terms; that is, including but not limited to.
Furthermore, as used herein, the terms "contacting," "joining," and the like, unless otherwise specified, may refer to direct contact or indirect contact through other layers.
FIG. 1 is a cross-sectional view of a package structure according to an embodiment of the invention.
Referring to fig. 1, a package structure 100 of embodiment includes a th substrate 102, a 0 th carrier 104 and a copper pillar structure 106, a 1 th substrate 102 has a plurality of stepped blind vias 108, each of the stepped blind vias 108 includes a 2 th opening 110, a second opening 112 and a horizontal step surface 114 located at the intersection of the th opening 110 and the second opening 112, an aperture r1 of the second opening 112 is larger than an aperture r2. of the th opening 110. in the example of fig. 1, a wall surface of the th opening 110 is an inclined surface, and an aperture r2 at the intersection of the th opening 110 and the horizontal step surface 114 is larger than an aperture r3 of the th opening 110 away from the horizontal step surface 114. the invention is not limited thereto, and a wall surface of the th opening 110 may also be a vertical surface, that is, and the apertures r2 and r3 of the th opening 110 may be .
The carrier 104 has a plurality of pads (contact pads)116 disposed on a surface 104a thereof, and a seed layer 118 may be disposed between the pads 116 and the copper pillar structures 106 to facilitate growth of the copper pillar structures 106. the copper pillar structures 106 have opposing a and b ends, wherein the a end is in electrical contact with the pads 116, the second end 106 of the copper pillar structures 106 is connected to the opening 110, and each of the copper pillar structures 106 fills each of the stepped blind vias 108.
In this embodiment, the protection layer 130 may cover the third substrate 102 and the protection layer 130 may be disposed in the space 132 between the outer edge of the copper pillar structure 106 and the inner edge of the second opening 112, so as to achieve a sealing effect, wherein the protection layer 130 may be, for example, a molding compound (molding compound) or an underfill (underfill), and when the height h of the copper pillar structure 106 is greater than the depth d of the stepped blind hole 108, the outer edge of the copper pillar structure 106 where the copper pillar structure 106 and the second opening 112 are connected may form an angle θ of , wherein the angle θ is, for example, between 75 degrees and 90 degrees, so that the gap between the third substrate 102 and the carrier may be filled with the underfill layer (underfill layer)130 to achieve the encapsulation effect, but the invention is not limited thereto, and the height h of the copper pillar structure 106 is equal to the depth d of the stepped blind hole 108, so that the third substrate 102 and the may be connected together.
Referring to fig. 1 again, the th substrate 102 with the stepped blind via 108 may be composed of a carrier 120, a th dielectric layer 122 and a second dielectric layer 124, wherein the th opening 110 may be formed in the th dielectric layer 122 and the second opening 112 may be formed in the second dielectric layer 124. the th dielectric layer 122 and the second dielectric layer 124 may be the same material or different materials, the th carrier 104 may be a package comprising the carrier 126 and the electronic component 128, and the pad 116 is usually connected to a component or circuit (not shown) in the electronic component 128, but the invention is not limited thereto, and the reference numeral 128 may also refer to circuit boards or carrier boards.
The substrate bonding methods of the second embodiment of the present invention are described below, wherein the step-shaped blind via and the copper pillar structure can be fabricated in sequence, and are not limited to the sequence described below.
Fig. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process for forming stepped blind holes in substrate bonding methods according to a second embodiment of the invention.
Referring to fig. 2A, a dielectric layer 202 and a second dielectric layer 204 are sequentially formed on an carrier 200, wherein the dielectric layer 202 and the second dielectric layer 204 may be made of different materials or the same material.
Then, referring to fig. 2B, photolithography etching processes are performed to form a plurality of second openings 206 with apertures r1 in the second dielectric layer 204 and expose a portion of the dielectric layer 202.
Referring to FIG. 2C, if the th dielectric layer 202 and the second dielectric layer 204 are made of different materials, a th opening 208 is formed in the exposed th dielectric layer 202 by etching the exposed first dielectric layer 202 with photolithography steps, if the th dielectric layer 202 and the second dielectric layer 204 are made of the same material, a th opening 208 is formed in the exposed second th dielectric layer 202 by, for example, laser processing, and the stepped blind via 212 is formed with a horizontal step 210 at the intersection of the th opening 208 and the second opening 206 in addition to the th opening 208 and the second opening 206. the aperture r1 of the second opening 206 is larger than the aperture r2 of the th opening 208.
In FIG. 2C, the wall of the th hole 208 is an inclined surface, and the aperture r2 at the intersection of the th hole 208 and the horizontal step 210 is larger than the aperture r3 of the th hole 208 away from the horizontal step 210, but the invention is not limited thereto, and the wall of the th hole 208 may be vertical surfaces, i.e., the aperture r2 and the aperture r3 may be the same as .
In addition, in other embodiments, if the th dielectric layer 202 and the 204 th dielectric layer are both Photo Imageable Dielectric (PID) layers, then two photolithography processes can be used to complete the step-like blind via 212 without the need for an etching process.
Subsequently, referring to fig. 2D, a copper interface layer 214 may be formed on the inner surface of the stepped blind via 212 to increase adhesion between the subsequent copper pillar structure and the stepped blind via 212.
Fig. 3A to 3E are schematic cross-sectional views illustrating a manufacturing process for forming a copper pillar structure in substrate bonding methods according to a second embodiment of the invention.
Referring to fig. 3A, a chip 302 is provided on a carrier 300, and a plurality of pads 304 have been formed on a surface 302a of the chip 302, but the invention is not limited thereto, and the chip 302 may represent carrier boards (carriers) or electronic devices, and then a seed layer 306 is selectively formed on the pads 304, wherein the thickness of the seed layer is usually much smaller than that of the pads 304.
Then, referring to fig. 3B, a passivation layer 308 covering the seed layer 306 is formed on the carrier 300, and the passivation layer 308 may cover the entire chip 302; however, the present invention is not limited thereto, and the protective layer 308 may cover only the surface 302a of the chip 302.
Next, referring to fig. 3C, an opening 312 exposing the seed layer 306 is formed in the passivation layer 308 by using a patterned structure such as a photoresist 310; the present invention is not limited in this regard and the opening 312 may be formed directly in the protective layer 308 without using photoresist, such as by exposing and developing a photo-imageable dielectric (PID) material as the protective layer 308.
Thereafter, referring to fig. 3D, the photoresist may be removed, and the copper pillar structure 314 is formed from the seed layer 306 on the bonding pad 304, wherein the diameter r4 of the copper pillar structure 314 is larger than the aperture r2 of fig. 2C and smaller than the aperture r1 of fig. 2A.
Then, referring to fig. 3E, the copper pillar structure 314 is etched, so that the top surface of the copper pillar structure 314 becomes a dome 314 a. The copper pillar structure 314 is etched by a method such as dry etching or wet etching.
Fig. 4A to 4B are schematic cross-sectional views illustrating a pressing process in the substrate bonding method according to the second embodiment of the invention.
After completing the copper pillar structure 314 of fig. 3E and the stepped blind via 212 of fig. 2D, please refer to fig. 4a, align the copper pillar structure 314 with the stepped blind via 212, wherein the th substrate 400 and the th carrier 402 are the structure of fig. 2D and the carrier 300, the chip 302 and the passivation layer 308 of fig. 3E, respectively, but the invention is not limited thereto.
Referring to FIG. 4B, the copper pillar 314 is then pressed into the stepped blind via 212 such that the stepped blind via 212 is filled with the copper pillar 314 at a temperature between, for example, 60 ℃ and 160 ℃, such as 80 ℃, 100 ℃ or 120 ℃, the pressure of the pressing is constant, i.e., no additional pressure is added during the pressing, after the pressing, the passivation layer 308 may be interposed in the space 404 between the outer edge of the copper pillar 314 and the inner edge of the second opening 206 to achieve a sealing effect, and when the height h of the copper pillar 314 is greater than the depth d of the stepped blind via 212, an angle θ of is formed at the outer edge of the contact portion between the copper pillar 314 and the second opening 206, wherein the angle θ is, for example, between 75 degrees and 90 degrees.
In the second embodiment, since stress concentration points are generated between the horizontal step surface 210 and the opening 208 after the dome 314a of the copper pillar structure 314 contacts the horizontal step surface 210, the bonding temperature can be effectively reduced.
In summary, the stepped blind via of the present invention enables stress concentration points to be generated when the dome of the copper pillar structure contacts the stepped blind via during the pressing process of the copper pillar structure, so the processing temperature and pressure for copper pressing are effectively reduced, and the bonding process of the present invention can enter the mass production stage.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (14)

  1. The package structure of , comprising:
    an th substrate having a plurality of stepped blind holes, wherein each of the plurality of stepped blind holes comprises a th opening, a second opening and a horizontal stepped surface, the diameter of the second opening is larger than that of the th opening, and the horizontal stepped surface is located at the intersection of the th opening and the second opening;
    a th carrier having a plurality of pads disposed on the surface of the th carrier, and
    a plurality of domed copper pillar structures, each of the plurality of domed copper pillar structures having opposing nd and second ends, wherein the th end is in electrical contact with the pad, the second end is connected to the th opening, and each of the plurality of domed copper pillar structures fills each of the plurality of stepped blind vias by being press-fit to each of the plurality of stepped blind vias, a height of each of the plurality of domed copper pillar structures being greater than a depth of each of the plurality of stepped blind vias.
  2. 2. The package structure of claim 1, wherein the wall of the th opening is a vertical surface.
  3. 3. The package structure of claim 1, wherein the wall of the th opening is an inclined surface, and the diameter of the hole at the junction of the th opening and the horizontal step surface is larger than the diameter of the th opening away from the horizontal step surface.
  4. 4. The package structure of claim 1, wherein the th carrier comprises a circuit board, a carrier, a package, or an electronic component.
  5. 5. The package structure of claim 1, further comprising a copper interface layer between each of the plurality of domed copper pillar structures and each of the plurality of stepped blind vias.
  6. 6, A substrate bonding method, comprising:
    forming a plurality of stepped blind vias in an th substrate, each of the plurality of stepped blind vias comprising a th opening and a second opening, the second opening having a larger aperture than the th opening;
    forming a plurality of copper pillar structures on a plurality of pads on a surface of an th carrier, each of the plurality of copper pillar structures having a diameter larger than an aperture of the th opening and smaller than an aperture of the second opening;
    etching the plurality of copper pillar structures to dome a top surface of each of the plurality of copper pillar structures, and
    and pressing the plurality of copper pillar structures to the plurality of stepped blind holes so that each of the plurality of copper pillar structures fill each of the plurality of stepped blind holes.
  7. 7. The method of claim 6, wherein the step-shaped blind vias are pressed to the copper pillar structures at a temperature between 60 ℃ and 160 ℃.
  8. 8. The method of claim 6, wherein the pressure applied to the plurality of stepped blind holes is atmospheric pressure.
  9. 9. The substrate bonding method according to claim 6, wherein the step of forming the plurality of stepped blind holes in the th substrate comprises:
    forming the dielectric layer and the second dielectric layer on the carrier plate in sequence;
    forming a plurality of second openings in the second dielectric layer to expose a portion of the th dielectric layer
    Forming the plurality of openings in the exposed th dielectric layer.
  10. 10. The substrate bonding method of claim 9, wherein the method of forming the plurality of second openings comprises a photolithographic etching process.
  11. 11. The substrate bonding method according to claim 9, wherein the method of forming the plurality of th openings comprises a photolithographic etching process or a laser process.
  12. 12. The substrate bonding method according to claim 6, wherein the step of forming the plurality of stepped blind holes in the th substrate comprises:
    forming a photo-imageable dielectric layer and a second photo-imageable dielectric layer sequentially on the carrier;
    patterning the second photoimageable dielectric layer to form the second plurality of openings and expose portions of the th photoimageable dielectric layer, and
    patterning the th photoimageable dielectric layer to form the plurality of th openings.
  13. 13. The method of claim 6, further comprising forming a copper interface layer on an inner face of the plurality of stepped blind holes after forming the plurality of stepped blind holes.
  14. 14. The substrate bonding method of claim 6, wherein the step of forming the plurality of copper pillar structures comprises:
    forming a seed layer on each of the bonding pads;
    forming a protective layer on the surface of the th carrier covering the seed layer;
    forming an opening in the protective layer exposing the seed layer; and
    forming the plurality of copper pillar structures from the seed layer.
CN201710083448.8A 2017-02-16 2017-02-16 Packaging structure and substrate bonding method Active CN108447828B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972191A (en) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 Die package with Openings Surrounding End-portions of Through Package Vias (TPVs) and Package on Package (PoP) Using the Die Package
CN104282648A (en) * 2013-07-10 2015-01-14 矽品精密工业股份有限公司 Semiconductor device and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000269324A (en) * 1999-03-15 2000-09-29 Toshiba Corp Semiconductor device and manufacture thereof
WO2014033977A1 (en) * 2012-08-29 2014-03-06 パナソニック株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972191A (en) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 Die package with Openings Surrounding End-portions of Through Package Vias (TPVs) and Package on Package (PoP) Using the Die Package
CN104282648A (en) * 2013-07-10 2015-01-14 矽品精密工业股份有限公司 Semiconductor device and method for fabricating the same

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