JP2004247415A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004247415A
JP2004247415A JP2003034014A JP2003034014A JP2004247415A JP 2004247415 A JP2004247415 A JP 2004247415A JP 2003034014 A JP2003034014 A JP 2003034014A JP 2003034014 A JP2003034014 A JP 2003034014A JP 2004247415 A JP2004247415 A JP 2004247415A
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semiconductor chip
circuit board
electrode terminal
terminal portion
support
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JP4090906B2 (en
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Kazuo Tamaoki
和雄 玉置
Koji Miyata
浩司 宮田
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the element forming a surface of a semiconductor chip is stably fixed to a circuit board, in the state where the element forming surface of the semiconductor chip is supported in substantially parallel with the circuit board, when the semiconductor chip having an electrode pad called a center pad is flip-chip mounted at a central part on the circuit board, and the connecting fault of the semiconductor chip to the circuit board or the decreases of connecting reliability is prevented, and also to provide a method for manufacturing the same. <P>SOLUTION: When the semiconductor chip 1 having an electrode terminal 5 provided at the central part of the element forming surface is flip-chip mounted in the installing state at the connecting electrode 3 of the circuit board 2, a solder resist opening 12 larger than the element forming surface of the semiconductor chip 1 is provided in an insulator layer 6 on the front surface of the circuit board 2. The connecting electrode 3 having a protruding shape, and a support 4 having substantially the same height as the connecting electrode 3 for supporting the semiconductor chip 1 and the circuit board 2 in substantially parallel with each other, are provided in the solder resist opening 12. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に関するものであり、より詳しくは、素子形成面の中央部に電極を有する半導体チップと、回路基板とを、フリップチップ実装方式により接続する半導体装置及びその製造方法に関するものである。
【０００２】
【従来の技術】
近年、携帯電話等の携帯情報機器の小型化、軽量化の進展にはめざましいものがある。それに伴い、これらの機器に搭載される半導体装置をはじめ、あらゆる部品の小型化、軽量化が求められている。そのようななか、半導体装置においては、半導体チップの実装構造の小型化、回路基板への高密度実装が求められている。
【０００３】
そこで、このような要求に応えるべく、近年、半導体のベアチップを回路基板に直接実装するフリップチップ実装方式を用いた実装（以下、単にフリップチップ実装もしくはフリップチップ実装方法と記す）が実施されている。
【０００４】
上記フリップチップ実装方法としては、半導体チップに設けられた導電性の突起電極（バンプ）を、該突起電極に対応して回路基板に設けられた接続パッドに圧接させた状態で、上記半導体チップと回路基板との間隙を、異方導電性樹脂（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ ｏｒ Ｐａｓｔｅ）や絶縁性樹脂（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ ｏｒ Ｐａｓｔｅ）などの液状またはフィルム状の界面封止樹脂にて封止する方法が一般的に用いられている。このように界面封止樹脂を用いた半導体チップと回路基板との接合は、上記半導体チップと回路基板とを位置合わせした状態で加熱加圧ツールにより上記半導体チップが搭載された回路基板を一定時間保持することで、両者の接続部が保持できる程度に上記異方導電性樹脂を硬化させることにより行われる。
【０００５】
これに対し、近年、圧接ではなく、突起電極（バンプ）の変形を伴う金属接合を用いたフリップチップ実装方法として、超音波を用いたフリップチップ実装（以下、超音波接合と記す）が注目され始めている。該方法においては、半導体チップの電極パッドに設けられた突起電極（バンプ）を回路基板上に設けられた接続パッドに接触させ、超音波による振動を用いて上記突起電極を押圧して変形させることにより、両者の接合を行っている。このため、該方法は、上記圧接による接合方法と比較して短時間で金属接合が可能であり、生産性向上及び信頼性向上の可能性を有している。
【０００６】
しかしながら、何れの場合においても、例えばダイナミックラムと称されるＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）等のように、素子形成面の中央部に複数の電極パッドが直鎖状に配列された、いわゆるセンターパッドを有する半導体チップを用いてフリップチップ実装を行う場合、上記電極パッド上に形成される突起電極（バンプ）を支点として半導体チップが傾き易いという問題がある。このため、そのままでは、半導体チップのフリップチップ実装を行う際に上記半導体チップの素子（能動素子）形成面と回路基板とが実質的に平行な間隔を保持した状態で両者を固定することは困難である。このため、このようにして得られた半導体装置は、半導体チップと回路基板との接続の安定性が悪く、接続不良や信頼性の低下を引き起こす可能性がある。
【０００７】
これに対し、例えば特許文献１には、界面封止樹脂を用いたフリップチップ実装において上記問題点を解決するための方法として、図９に示すように、レジスト層などの絶縁性の支持部材７６を、回路基板７２の四隅に、半導体チップ７１のチップサイズよりも該支持部材７６で囲まれた領域（開口部）の面積が小さくなるように設け、該支持部材７６で上記半導体チップ７１の周辺部を支えることで、半導体チップ７１と回路基板７２とを実質平行に支持し、半導体チップ７１の電極パッド７４（センターパッド）上に形成された突起電極７８と、回路基板７２上に設けられた接続パッド７３とを、界面封止樹脂として異方導電性樹脂７９（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ ｏｒ Ｐａｓｔｅ）を用いて接合する方法が開示されている。
【０００８】
【特許文献１】
特開２０００−３３２０５５号公報（２０００年１１月３０日公開）
【０００９】
【発明が解決しようとする課題】
しかしながら、超音波などを用いて突起電極を変形させることにより金属接合を行うフリップチップ実装において、上述したようにいわゆるセンターパッドを有する半導体チップの実装を行う場合の問題点を解決する方法は未だ知られていない。
【００１０】
そこで、本願発明者等は、上記特許文献１におけるフリップチップ実装方法に、突起電極を変形させることにより金属接合を行うフリップチップ実装方法として上記超音波接合を適用することで、上記した問題点を解決することを試みた。
【００１１】
図１０（ａ）〜（ｃ）は上記超音波接合を前記特許文献１に記載のフリップチップ実装方法を用いた半導体装置の製造方法に適用したときの半導体装置の製造工程を工程順に示す断面図である。
【００１２】
まず、図１０（ａ）に示すように、回路基板７２における、レジスト層などの絶縁性の支持部材７６を含む半導体装置実装対象となる領域に、界面封止樹脂としての異方導電性樹脂７９をコートする。
【００１３】
次いで、上記回路基板７２における接続パッド７３と、半導体チップ７１の電極パッド７４（センターパッド）に設けられた突起電極７８とを位置合わせし、図１０（ｂ）に示すように超音波印加ツール７を用いて上記半導体チップ７１に、加熱状態にて超音波を印加して所定の荷重を加える。これにより、図１０（ｃ）に示すように突起電極７８を塑性変形させて、上記半導体チップ７１が上記支持部材７６によって支持された状態で、上記半導体チップ７１と回路基板７２とを接合する。
【００１４】
このように、超音波接合を特許文献１におけるフリップチップ実装方法に適用した場合、短時間で上記半導体チップ７１と回路基板７２とを金属接合することが可能になる。
【００１５】
しかしながら、上記したように突起電極７８を変形させて上記半導体チップ７１と回路基板７２とを接合させるためには、図１０（ｂ）に示すように、半導体チップ７１に形成された突起電極７８の高さは、レジスト層などの絶縁性の支持部材７６よりも、上記突起電極７８の変形分だけ必ず高くなければならない。
【００１６】
従って、超音波接合を特許文献１におけるフリップチップ実装方法に適用した場合、上記半導体チップ７１の中央部に形成された上記突起電極７８に超音波などを加えて該突起電極７８を変形させるとき、上記半導体チップ７１を、上記回路基板７２に対して実質的に平行に支持するものがないので、上記半導体チップ７１に超音波を印加して所定の荷重を加えたときの半導体チップ７１の挙動が不安定になり、図１０（ｃ）に示すように突起電極７８と接続パッド７３とが位置ずれを起こし、接続不良や接続信頼性の低下を招く可能性がある。
【００１７】
このため、超音波接合のように電極の塑性変形を伴うフリップチップ接合において上記した問題点の解決が望まれる。
【００１８】
また、上記特許文献１は、上述したように回路基板７２の四隅に設けられた、レジスト層などの絶縁性部材からなる支持部材７６により、上記半導体チップ７１の周辺部を支持しているが、このようにレジスト層などの絶縁性部材により上記支持部材７６を形成する場合、フリップチップ実装時に上記半導体チップ７１を押圧するときに、上述したように接続位置の横方向のズレが大きいことは勿論として、縦方向、即ち、電気的な接続の信頼性に関わる高さ方向のばらつきも大きいため、実使用上、問題がある。
【００１９】
つまり、上記回路基板７２側に設けられるレジスト層などの絶縁性部材は、一般的にはソルダレジストと称され、回路基板７２の強度確保や、上記回路基板７２における金属配線の絶縁などのためには必要なものである。ところが、このソルダレジストは、厚みの制御が容易ではなく、材料に起因する厚さのばらつきが比較的大きいという問題点を有している。また、エッチング加工により厚みを制御する場合における制御性においても同様のことが言える。
【００２０】
このため、上記特許文献１に記載のように上記支持部材７６としてソルダレジストを用いた場合、超音波接合を行うか否かに拘らず、回路基板７２毎に、支持部材７６の厚みがばらつくので、各回路基板７２毎に適切なバンプ高さ、つまり上記突起電極７８の高さを設定する必要がある。また、支持部材７６を精度良く形成しようとすると、回路基板７２の製造工程が増加し、コストアップにつながる。
【００２１】
本発明は、上記の問題点に鑑みてなされたものであり、その目的は、中央部に、センターパッドと称される電極パッドを有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができ、半導体チップと回路基板との接続不良や接続信頼性の低下を防止することができる半導体装置及びその製造方法を提供することにある。
【００２２】
【課題を解決するための手段】
本発明にかかる半導体装置は、上記の課題を解決するために、素子形成面の中央部に電極端子部（例えばセンターパッドと称される電極パッド）が設けられた半導体チップが、上記電極端子部にて、回路基板の接続用電極端子部（例えば接続パッド）に架設状態でフリップチップ実装されており、上記回路基板は、上記半導体チップよりも大きく、かつ、表面に絶縁体層（例えばソルダレジスト）が設けられている半導体装置において、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部が突起状に形成されており、上記回路基板表面の絶縁体層は、上記半導体チップの素子（例えば能動素子）形成面よりも大きな開口部（例えばソルダレジスト開口部）を備え、該開口部内で上記半導体チップと回路基板とが架設状態でフリップチップ実装されており、上記半導体チップと回路基板との間隙には、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体が設けられていることを特徴としている。
【００２３】
上記の構成によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、ソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００２４】
特に、上記の構成によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有し、上記絶縁体層と半導体チップとが互いに非接触状態にて上記半導体チップが上記接続用電極端子部にフリップチップ実装されるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体が設けられていることから、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。
【００２５】
よって、上記の構成によれば、半導体チップの素子形成面と回路基板とが実質的に平行に支持された状態で、しかも、上記半導体チップの電極端子部と上記接続用電極端子部とが、横方向に位置ズレすることなくフリップチップ実装されるので、半導体チップと回路基板との接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００２６】
しかも、上記の構成によれば、本発明は、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合にも好適に適用できるので、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００２７】
本発明にかかる半導体装置は、上記の課題を解決するために、上記支持体は、突起状に形成された電極端子部と同じ材料からなることを特徴としている。
【００２８】
上記の構成によれば、上記支持体が、突起状に形成された電極端子部と同じ材料からなることで、既存の技術により、両者の高さを容易に一致させることができる。このため、より一層接続信頼性が高い半導体装置を提供することができる。
【００２９】
しかも、上記の構成によれば、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合、該塑性変形による、上記支持体と、突起状に形成された電極端子部との変形量を容易に一致させることができるので、上記半導体チップと回路基板とを平行に支持した状態で接合することが可能となる。よって、上記の構成によれば、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性がより高い半導体装置を提供することができる。
【００３０】
本発明にかかる半導体装置は、上記の課題を解決するために、上記支持体は金属からなることを特徴としている。
【００３１】
金属材料は、その厚さをエッチング加工する技術が特に充実しており、厚みの制御を容易に行うことができる。このため、上記支持体が金属からなる場合、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより一層厳密かつ容易に制御することが可能となるので、上記支持体の高さを、突起状に形成された電極端子部の高さと容易に合わせることができる。このため、より接続信頼性が高い半導体装置を提供することができる。
【００３２】
本発明にかかる半導体装置は、上記の課題を解決するために、上記半導体チップと回路基板とが、突起状に形成された上記電極端子部及び上記支持体の塑性変形により接合されていることを特徴としている。
【００３３】
上記の構成によれば、上述したように、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合であっても上記半導体チップのフリップチップ実装を行う際に、上記半導体チップを上記回路基板と平行に支持することができるので、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００３４】
なお、従来は、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合に、半導体チップと回路基板とを平行に支持した状態でフリップチップ接続を行う技術は知られておらず、回路基板上に設けられたソルダレジストと称される絶縁体層を、半導体チップを支持する支持部材として用いる技術を、電極端子部の塑性変形を伴う接合に適用した場合、突起電極は必ず半導体チップ側に形成する必要があり、しかも、該突起電極の高さは、該突起電極の変形分、上記絶縁体層からなる支持部材よりも高くする必要がある。このため、従来は、半導体チップと回路基板とを平行に支持した状態でフリップチップ接続を行うことはできなかった。
【００３５】
しかしながら、本発明によれば、上記したように、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００３６】
本発明にかかる半導体装置は、上記の課題を解決するために、上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂（例えば異方導電性樹脂や絶縁性樹脂など）によりさらに固着されていることを特徴としている。
【００３７】
上記の構成によれば、上記半導体チップと回路基板とを、より強固に安定して接合することができる。例えば、上記半導体チップと回路基板との接合が超音波接合によりなされる場合、上記半導体チップの電極端子部と回路基板の接続用電極端子部との溶着（接合）は、一般的に、中心部ではなく、その周辺にドーナツ状に生じる。このため、上記半導体チップと回路基板との間隙を上記界面封止樹脂によりさらに固着することで、両者の接合をより強固で安定したものとすることができる。
【００３８】
本発明にかかる半導体装置は、上記の課題を解決するために、上記接続用電極端子部と半導体チップの電極端子部とが架設状態で圧接されており、上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂により固着されていることを特徴としている。
【００３９】
上記の構成によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、上記のように半導体チップの電極端子部と接続用電極端子部とを圧接させて電気的に接続すると共に上記半導体チップと回路基板とを界面封止樹脂により固着させる場合においても、半導体チップと回路基板とソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００４０】
特に、上記の構成によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有し、上記絶縁体層と半導体チップとが互いに非接触状態にて上記半導体チップが上記接続用電極端子部にフリップチップ実装されるので、半導体チップを支持するための支持部材並びに上記電極端子部（突起電極）の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体が設けられていることから、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となる。
【００４１】
このため、上記の構成によれば、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができ、半導体チップと回路基板との接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００４２】
本発明にかかる半導体装置は、上記の課題を解決するために、上記支持体と半導体チップとの接触面積が、突起状に形成された上記電極端子部と半導体チップとの接触面積よりも大きいことを特徴としている。
【００４３】
上記の構成によれば、上記支持体と半導体チップとの接触面積を、突起状に形成された上記電極端子部と半導体チップとの接触面積よりも大きくすることで、上記支持体が上記半導体チップの素子形成面に当たることによるダメージを軽減することができる。
【００４４】
本発明にかかる半導体装置は、上記の課題を解決するために、上記半導体チップの素子形成面とは反対側の面に少なくとも１つの半導体チップが積層され、該積層された半導体チップの電極端子部と、上記回路基板における上記絶縁体層の開口部内でかつ上記半導体チップのフリップチップ実装領域外に設けられた接続用電極端子部とが金属細線により電気的に接続されていることを特徴としている。
【００４５】
上記の構成によれば、上記半導体装置１個当たり、言い換えれば、上記回路基板上の上記半導体チップ実装領域の面積当たりの、該半導体チップの搭載数が増加し、上記半導体チップの実装密度がより高い半導体装置を実現することができる。
【００４６】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、素子（例えば能動素子）形成面の中央部に電極端子部（例えばセンターパッドと称される電極パッド）が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層（例えばソルダレジスト）が設けられた回路基板における接続用電極端子部（例えば接続パッド）に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部（例えばソルダレジスト開口部）を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを実質平行に支持してフリップチップ実装を行うことを特徴としている。
【００４７】
上記の方法によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、ソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００４８】
特に、上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。
【００４９】
よって、上記の方法によれば、半導体チップの素子形成面と回路基板とが実質的に平行に支持された状態で、しかも、上記半導体チップの電極端子部と上記接続用電極端子部とが、横方向に位置ズレすることなくフリップチップ実装することができるので、半導体チップと回路基板との接続不良を防止することができ、接続信頼性が高い半導体装置を製造することができる。
【００５０】
しかも、上記の方法によれば、本発明は、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合にも好適に適用できるので、上記の方法を用いれば、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を製造することができる。
【００５１】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、素子（例えば能動素子）形成面の中央部に電極端子部（例えばセンターパッドと称される電極パッド）が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層（例えばソルダレジスト）が設けられた回路基板における接続用電極端子部（例えば接続パッド）に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部（例えばソルダレジスト開口部）を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、かつ、少なくとも最表層が上記半導体チップのフリップチップ実装による上記接続用電極端子部との接合条件で塑性変形すると共に、該塑性変形による変形量が、突起状に形成された上記電極端子部とほぼ同じ材料からなり、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合することを特徴としている。
【００５２】
上記の方法によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、ソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００５３】
特に、上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。
【００５４】
よって、上記の方法によれば、半導体チップの素子形成面と回路基板とが実質的に平行に支持された状態で、しかも、上記半導体チップの電極端子部と上記接続用電極端子部とが、横方向に位置ズレすることなくフリップチップ実装することができるので、半導体チップと回路基板との接続不良を防止することができ、接続信頼性が高い半導体装置を製造することができる。
【００５５】
なお、従来は、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合に、半導体チップと回路基板とを平行に支持した状態でフリップチップ接続を行う技術は知られておらず、回路基板上に設けられたソルダレジストと称される絶縁体層を、半導体チップを支持する支持部材として用いる技術を、電極端子部の塑性変形を伴う接合に適用した場合、突起電極は必ず半導体チップ側に形成する必要があり、しかも、該突起電極の高さは、該突起電極の変形分、上記絶縁体層からなる支持部材よりも高くする必要がある。このため、従来は、半導体チップと回路基板とを平行に支持した状態でフリップチップ接続を行うことはできなかった。
【００５６】
しかしながら、上記の方法によれば、上述したように、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合であっても上記半導体チップのフリップチップ実装を行う際に、上記半導体チップを上記回路基板と平行に支持することができるので、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００５７】
なお、本発明によれば、例えば、超音波、熱、圧力のうち少なくとも１つを上記半導体チップと回路基板との接合部に与える（印加する）ことにより、突起状に形成された上記電極端子部及び上記支持体の塑性変形による上記半導体チップと回路基板との接合を行うことができる。
【００５８】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合させた後、上記半導体チップと回路基板との間隙に、該間隙を封止する界面封止樹脂（例えば異方導電性樹脂や絶縁性樹脂など）を注入し、該界面封止樹脂を硬化させることを特徴としている。
【００５９】
上記の方法によれば、上記半導体チップと回路基板とを、より強固に安定して接合することができる。例えば、上記半導体チップと回路基板との接合が超音波接合によりなされる場合、上記半導体チップの電極端子部と回路基板の接続用電極端子部との溶着（接合）は、一般的に、中心部ではなく、その周辺にドーナツ状に生じる。このため、上記半導体チップと回路基板との間隙を上記界面封止樹脂によりさらに固着することで、両者の接合をより強固で安定したものとすることができる。
【００６０】
そして、この場合、本発明においては、上記回路基板表面の絶縁体層が、上記半導体チップのフリップチップ実装領域（実装対象領域）において上記半導体チップの素子形成面よりも大きく開口されていることで、上記半導体チップを上記接続用電極端子部にフリップチップ実装したとき、上記半導体チップと回路基板との間隙に、容易に上記界面封止樹脂を注入することができる。
【００６１】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の片側に、上記接続用電極端子部と平行に上記支持体を形成し、上記半導体チップと回路基板とを接合後に、上記支持体が形成された側とは上記接続用電極端子部を挟んで反対側、もしくは、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することを特徴としている。
【００６２】
上記の方法によれば、上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、上記半導体チップと回路基板とを、より強固に安定して接合することができる。そして、このとき、上記支持体を、上記接続用電極端子部からなる列の片側に、上記接続用電極端子部と平行に上記支持体を形成し、上記支持体が形成された側とは上記接続用電極端子部を挟んで反対側、もしくは、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、該界面封止樹脂の注入性を向上させることができ、効率良く、しかも、上記間隙に上記界面封止樹脂を満遍なく充填させることができる。
【００６３】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の両側に、上記接続用電極端子部と平行に上記支持体を形成し、上記半導体チップと回路基板とを接合後に、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することを特徴としている。
【００６４】
上記の方法によれば、上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、上記半導体チップと回路基板とを、より強固に安定して接合することができる。そして、このとき、上記支持体を、上記接続用電極端子部からなる列の両側に、上記接続用電極端子部と平行に上記支持体を形成し、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、該界面封止樹脂の注入性を向上させることができ、効率良く、しかも、上記間隙に上記界面封止樹脂を満遍なく充填させることができる。
【００６５】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、突起状に形成された上記電極端子部と支持体とによって上記半導体チップと回路基板とを支持する前に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、上記半導体チップと回路基板との間隙を封止する界面封止樹脂からなる層を配し、上記間隙に界面封止樹脂（例えばシート状もしくはペースト状の界面封止樹脂）からなる層が配された状態で、突起状に形成した上記電極端子部と上記支持体とによって、上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体の塑性変形と上記界面封止樹脂の硬化とを、同一の工程において行うことを特徴としている。
【００６６】
上記の方法によれば、上記半導体チップと回路基板との間隙を上記界面封止樹脂によって封止することで、上記半導体チップと回路基板とを、より強固に安定して接合することができる。
【００６７】
この場合、上記の方法によれば、上記半導体チップの電極端子部と接続用電極端子部との電気的な接続と上記界面封止樹脂の硬化とを同時進行させることができるので、上記間隙を界面封止樹脂で封止する場合における半導体チップの実装にかかる時間を短縮させることができる。
【００６８】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体との最表層に、導電性接着剤（例えば半田材料や導電ペーストなど）からなる接合層を各々設けることを特徴としている。
【００６９】
上記の方法によれば、上記半導体チップと回路基板とを、より強固に安定して接合することができる。例えば、上記半導体チップと回路基板との接合が超音波接合によりなされる場合、上記半導体チップの電極端子部と回路基板の接続用電極端子部との溶着（接合）は、一般的に、中心部ではなく、その周辺にドーナツ状に生じる。このため、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体との最表層に上記接合層を設けることで、両者の接合をより強固で安定したものとすることができる。
【００７０】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、素子（例えば能動素子）形成面の中央部に電極端子部（いわゆるセンターパッドと称される電極パッド）が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層（例えばソルダレジスト）が設けられた回路基板における接続用電極端子部（例えば接続パッド）に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部（例えばソルダレジスト開口部）を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップの素子形成面と上記回路基板表面とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で、上記半導体チップと回路基板とを架設状態で実質平行に支持した状態で、上記半導体チップと回路基板との間隙を界面封止樹脂（例えば異方導電性樹脂や絶縁性樹脂など）により封止して上記接続用電極端子部と上記半導体チップの電極端子部とを圧接させることを特徴としている。
【００７１】
上記の方法によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、ソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００７２】
特に、上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。
【００７３】
よって、上記の方法によれば、半導体チップの素子形成面と回路基板とが実質的に平行に支持された状態で、しかも、上記半導体チップの電極端子部と上記接続用電極端子部とが、横方向に位置ズレすることなくフリップチップ実装することができるので、半導体チップと回路基板との接続不良を防止することができ、接続信頼性が高い半導体装置を製造することができる。
【００７４】
上記の方法によれば、従来のように、回路基板上に配されるソルダレジストと称される絶縁体層を、フリップチップ実装時に上記半導体チップを支持する支持部材（支持体）として使用しないので、上記のように半導体チップの電極端子部と接続用電極端子部とを圧接させて電気的に接続すると共に上記半導体チップと回路基板とを界面封止樹脂により固着させる場合においても、半導体チップと回路基板とソルダレジストを上記支持部材として用いた場合における従来の問題点を招来しない。
【００７５】
特に、上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有し、上記絶縁体層と半導体チップとが互いに非接触状態にて上記半導体チップが上記接続用電極端子部にフリップチップ実装されるので、半導体チップを支持するための支持部材並びに上記電極端子部（突起電極）の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体が設けられていることから、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となる。
【００７６】
このため、上記の方法によれば、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができ、半導体チップと回路基板との接続不良が防止され、接続信頼性が高い半導体装置を提供することができる。
【００７７】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、上記界面封止樹脂として、内部に導電粒子が分散された異方導電性樹脂を用いることを特徴としている。
【００７８】
上記の方法によれば、上記異方導電性樹脂中に存在する導電粒子により、より良好な電気的接続を得ることができる。特に、超音波などを用いて電極端子部を塑性変形させることにより上記半導体チップのフリップチップ実装を行う場合、上記半導体チップの電極端子部と接続用電極端子部との接合部に上記導電粒子が埋め込まれ、該導電粒子により、より良好な電気的接続を得ることができる。
【００７９】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体とを、同じ材料で形成することを特徴としている。
【００８０】
上記の方法によれば、上記支持体を、突起状に形成された電極端子部と同じ材料で形成することで、既存の技術により、両者の高さを容易に一致させることができる。このため、上記の方法によれば、より一層接続信頼性が高い半導体装置を製造することができる。
【００８１】
また、上記の方法によれば、上記支持体と、突起状に形成された電極端子部とを、同一工程、例えばエッチング加工やメッキ等の基板配線の形成工程において同時に形成することが可能になるので、工程数の増加を招くこともなく、安価かつ容易に上記支持体を形成することができる。
【００８２】
しかも、上記の方法によれば、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合、該塑性変形による、上記支持体と、突起状に形成された電極端子部との変形量を容易に一致させることができるので、上記半導体チップと回路基板とを平行に支持した状態で接合することが可能となる。よって、上記の方法によれば、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性がより高い半導体装置を製造することができる。
【００８３】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、上記支持体を金属で形成することを特徴としている。
【００８４】
金属材料は、その厚さをエッチング加工する技術が特に充実しており、厚みの制御を容易に行うことができる。このため、上記支持体を金属で形成する場合、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより一層厳密かつ容易に制御することが可能となるので、上記支持体の高さを、突起状に形成された電極端子部の高さと容易に合わせることができる。このため、上記の方法によれば、より接続信頼性が高い半導体装置を製造することができる。
【００８５】
本発明にかかる半導体装置の製造方法は、上記の課題を解決するために、上記接続用電極端子部及び半導体チップの電極端子部のうち上記接続用電極端子部を突起状に形成すると共に、上記接続用電極端子部の形成工程と同一の工程で上記回路基板に上記支持体を形成することを特徴としている。
【００８６】
上記の方法によれば、上記接続用電極端子部及び半導体チップの電極端子部のうち上記接続用電極端子部を突起状に形成すると共に、上記接続用電極端子部の形成工程と同一の工程で上記回路基板に上記支持体を形成することで、上記支持体と、突起状に形成された電極端子部とを、例えばエッチング加工やメッキ等の基板配線の形成工程において、配線の形成と同時に、あるいは、上記配線を利用して形成することが可能になるので、工程数の増加を招くこともなく、安価かつ容易に上記支持体を形成することができる。また、上記の方法によれば、既存の技術により、両者の高さを容易に一致させることができる。このため、上記の方法によれば、より一層接続信頼性が高い半導体装置を、安価かつ容易に製造することができる。
【００８７】
【発明の実施の形態】
〔実施の形態１〕
本発明の実施の一形態について図１（ａ）〜（ｄ）乃至図４に基づいて説明すれば、以下の通りである。なお、図１（ａ）〜（ｄ）は本実施の形態にかかる半導体装置の製造工程の一例を示す断面図であり、そのうち、図１（ｄ）は、本実施の形態にかかる半導体装置の断面の概略構成を示している。また、図２は、図１（ａ）〜（ｄ）に示す半導体チップ１の素子形成面の概略構成を示す平面図であり、図３は、図１（ａ）〜（ｄ）に示す回路基板２の概略構成を示す平面図である。
【００８８】
本実施の形態にかかる半導体装置は、図１（ｄ）に示すように、ボンディングパッドとしていわゆるセンターパッドと称される平面電極（電極パッド）からなる電極端子部５を有する半導体チップ１（ベアチップ）が、回路基板２に、上記電極端子部５に対応して突出して設けられた接続電極３（接続用電極端子部）によってフリップチップ実装されている構成を有している。上記半導体チップ１と回路基板２とは界面封止樹脂８により固着されている。
【００８９】
上記半導体チップ１は、素子（能動素子）形成面の中央部に、平面電極（電極パッド）からなる電極端子部５を有すると共に、該電極端子部５が露出するように該電極端子部５を除く素子形成面、つまり、素子が、絶縁膜１３で覆われた構成を有している。これにより、上記半導体チップ１は、その素子形成面が上記回路基板２と対向するように上記回路基板２にフリップチップ実装されている。以下、本実施の形態において、上記半導体チップ１の素子形成面を素子面と称し、該素子面の反対側の面を裏面と称する。
【００９０】
上記半導体チップ１の例としては、例えばＤＲＡＭなどが挙げられる。ＤＲＡＭなどの半導体チップ１は、例えば、図２に示すように、素子面の中央部に、例えばアルミパッドなどの電極パッドからなる複数の電極端子部５が直鎖状に形成された構成を有し、該電極端子部５…を除く素子面が、該電極端子部５…とほぼ面一となるように該電極端子部５…の厚み（高さ）とほぼ同じ厚みを有する絶縁膜１３で覆われた構成を有している。すなわち、上記絶縁膜１３は、素子形成面を平坦化する平坦化膜としても機能する。
【００９１】
上記半導体チップ１の構造並びに上記電極端子部５の構成は、上記電極端子部５において平面電極（電極パッド）上に突起電極が設けられていないことを除けば、センターパッドを有する従来の半導体チップの構造並びに電極パッドの構成と基本的に同じであり、ここではその説明を省略する。上記電極端子部５（平面電極）の最表層は、接続電極３との電気的接続を良くするため、低抵抗金属、通常はＡｌ、Ｓｉ、Ｃｕなどの金属で構成されているが、これに限定されるものではなく、Ｎｉ、Ｃｒ、Ｔｉ、Ｗなどの、バリアメタルもしくはアンダーバンプメタルに使用される金属で構成されていてもよい。
【００９２】
なお、以下の実施の形態では、上記半導体装置の例として、上記半導体チップ１に、図２に示すＤＲＡＭを用いた場合を例に挙げて説明するものとするが、本発明は、これに限定されるものではない。また、上記電極端子部５の設置数は特に限定されず、任意の数でよい。さらに、上記電極端子部５の配列形態も、これら電極端子部５…がいわゆるセンターパッドと称される形態であれば、特に限定されない。
【００９３】
一方、上記回路基板２は、図１（ａ）〜（ｄ）に示すように、上記半導体チップ１が実装（搭載）される側の面（以下、単に半導体チップ搭載面と記す）に、金属配線などの配線２０（配線パターン）が設けられた構成を有している。上記回路基板２における半導体チップ搭載面（第１面）とは反対側の面（第２面）には、絶縁体層１０（絶縁性部材）が設けられていると共に、半田ボールなどの図示しない外部入出力端子が設けられている構成を有している。上記外部入出力端子は、回路基板２並びに該回路基板２の第２面を覆う上記絶縁体層１０を貫く貫通孔１１を介して上記配線２０と電気的に接続されている。
【００９４】
上記回路基板２は、図３に示すように、上記半導体チップ１よりも縦横共に大きく、該回路基板２における半導体チップ搭載面、つまり、配線２０形成面には、上記半導体チップ１のチップサイズよりも大きく開口（窓開け）された絶縁体層６（絶縁性部材）が設けられている。
【００９５】
上記絶縁体層６は、一般的にソルダレジストと称されるものである。しかしながら、前記したように、ソルダレジストは、例えば金属材料などからなる部材と比較して、厚みの制御が困難であり、材料に起因する厚さのばらつきが比較的大きい。また、エッチング加工により厚みを制御する場合における制御性も、例えば金属材料とソルダレジストとでは大きな差がある。このため、上記ソルダレジストを上記支持部材として使用することは、接続不良や接続信頼性の低下を招くことになるとともに、製造工程の増加やコストアップにつながる。
【００９６】
そこで、本実施の形態においては、上述したように回路基板２の絶縁体層６を半導体チップ１のチップサイズよりも大きく開口することで、上記回路基板２の半導体チップ搭載面に、上記半導体チップ１のチップサイズよりも大きなソルダレジスト開口部１２を形成すると共に、上記回路基板２の半導体チップ搭載面に、上記絶縁体層６とは別に、上記半導体チップ１のフリップチップ実装時に上記半導体チップ１を支持する支持体４（支持部材）を形成している。
【００９７】
つまり、本実施の形態においては、上記絶縁体層６は、図３に示すように、回路基板２の周縁部に形成され、該絶縁体層６により形成されたソルダレジスト開口部１２の面積は回路基板２に搭載される半導体チップ１の素子面の面積よりも大きいことで、該絶縁体層６を、例えば前記特許文献１に示すようにセンターパッドを有する半導体チップのフリップチップ実装のための支持部材としてではなく、ソルダレジストとして、回路基板２の強度確保や、上記回路基板２における配線２０の絶縁状態の確保に使用している。
【００９８】
上記ソルダレジスト開口部１２内には、上記半導体チップ１の電極端子部５に対応して接続電極３が形成されている。該接続電極３は、突出構造を有している。すなわち、本実施の形態において上記回路基板２におけるソルダレジスト開口部１２内には、半導体チップ１の電極端子部５…に対応して、突出構造（突起）を有する複数の接続パッドからなる接続電極３が設けられている。
【００９９】
これら接続電極３…は、上記ソルダレジスト開口部１２内の中央部に配され、上記半導体チップ１は、該半導体チップ１の素子面が上記絶縁体層６と非接触の状態で上記回路基板２にフリップチップ実装されるようになっている。
【０１００】
よって、本実施の形態において、支持体４は、上記ソルダレジスト開口部１２内における上記半導体チップ１の実装対象領域において突起（突出）して設けられ、これにより、上記半導体チップ１のフリップチップ実装時に上記半導体チップ１と回路基板２とを実質平行に支持するようになっている。本実施の形態において、上記半導体チップ１と回路基板２とを実質平行に支持するとは、半導体チップ１の素子面と上記回路基板２表面（基板平面）とを実質平行に支持することを示す。
【０１０１】
上記支持体４は、上記接続電極３とほぼ同じ高さを有し、上記接続電極３の周辺部に、例えば図３に示すように接続電極３…の配列方向に沿ってこれら接続電極３…とほぼ平行に設けられている。
【０１０２】
なお、図３に示す回路基板２では、半導体チップ１の実装対象領域において接続電極３…を挟んで両側に支持体４が設けられている構成としたが、上記支持体４は、上記半導体チップ１のフリップチップ実装時に上記半導体チップ１を上記回路基板２と実質平行に支持することができさえすれば特に限定されるものではなく、例えば、支持体４が回路基板２上に設けられた接続電極３…の片側にのみ設けられている構成としてもよい。
【０１０３】
上記支持体４の材料としては、上記半導体チップ１を、上記回路基板２と実質平行に支持することができると共に上記半導体チップ１のフリップチップ実装条件において塑性変形する材料、好適には上記フリップチップ実装時における変形量が上記接続電極３とほぼ同じ材料、より好適には上記変形量が上記接続電極３と同じ材料が用いられる。
【０１０４】
これにより、上記接続電極３と電極端子部５とを強固に安定してかつ短時間で接合することができると共に、上記変形量の違いに起因する接続不良を抑制、好適には防止することができる。
【０１０５】
上記支持体４の材料のなかでも、特に好ましい材料は、上記の観点から上記接続電極３と同じ材料であり、そのなかでも特に、支持体４の高さ（厚み）の制御が容易であり、また、金属接合により上記接続電極３と電極端子部５とを強固に安定してかつ短時間で接合することができることから、最も好ましくは金属材料である。
【０１０６】
上記接続電極３の材料としては、従来の半導体装置における回路基板の接続電極（接続パッド）もしくは半導体チップにおける電極端子部（突起電極）に用いられている材料と同様の材料を用いることができる。具体的には、上記接続電極３の材料としては、前記電極端子部５を構成する平面電極材料、すなわち、前記例示の金属材料などを用いることができるが、これに限定されるものではない。
【０１０７】
上記接続電極３及び支持体４と前記電極端子部５を構成する平面電極材料との組み合わせは特に限定されるものではないが、上記半導体チップ１のフリップチップ実装に際し、上述したように超音波などを用いて電極の塑性変形を伴う接合（例えば金属接合）を行う場合、上記接続電極３及び支持体４の材料としては、前記電極端子部５を構成する平面電極材料よりも柔らかい材料からなることが望ましい。上記接続電極３及び支持体４の材料としては、例えばＡｕやＳｎなどが好適に用いられるが、これに限定されるものではない。
【０１０８】
また、上記接続電極３及び支持体４としては、Ｓｎ、Ｐｂを主成分とする半田を使用してもよく、公知の半田突起電極（バンプ）を形成する方法を用いて該接続電極３及び支持体４を形成することもできる。
【０１０９】
半田突起電極の形成方法としては、例えば、半田ワイヤを用いて、ワイヤボンディングを応用したワイヤバンプ法や、無電界メッキ、電解メッキを用いる方法などがある。この場合、上記接続電極３及び支持体４の最表面には、酸化防止層として、例えばＡｕメッキが施されていることが望ましい。また、例えば、Ｃｕなどの配線材料上にもＡｕメッキなどが施されている構成としてもよい。なお、上記接続電極３をＡｕで構成する場合は、酸化防止層は特に形成する必要はない。また、上記接続電極３及び支持体４をメッキ処理により形成する場合、上記配線２０上には、メッキ阻止膜が設けられていることが望ましい。
【０１１０】
ソルダレジストと例えば金属材料とでは厚さのコントロール並びにエッチングによる加工時における制御性に大きな差があることは勿論であるが、導電性パターン、特に金属パターンを形成する場合、従来からエッチングによる加工などによりその厚みを制御する技術が充実している。このため、上記支持体４に金属材料を用いることで、上記支持体４の形成に、極めて普遍的な技術を応用することができる。
【０１１１】
よって、上記支持体４に金属材料などの導電性部材を用いる場合、例えば、上記回路基板２側の電極部材（金属部材などの導電性部材）を上記支持体４として用いることもできる。また、この場合、上記電極部材は、信号配線として、上記半導体チップ１の中央部に設けられた電極端子部５…と接続することもできる。
【０１１２】
つまり、図３に示す回路基板２は、例えば図４に示すような断面構造を有していてもよい。図４に示すように回路基板２側の電極部材、例えば配線２０を上記支持体４に用いることで、該支持体４を、エッチングやメッキ等による配線パターン形成工程において、例えば配線２０や接続電極３と同じ材料、例えば同じ金属材料（配線材料）を用いて同時に形成することができる。
【０１１３】
このように上記支持体４が例えば上記接続電極３と同じ材料にて形成されていることで、突起電極である接続電極３の塑性変形により電極端子部５と接続電極３とを接続する際の支持体４と接続電極３との変形量を同じにすることができ、両者の変形量の違いに起因する接続不良を防止することができる。
【０１１４】
また、上記支持体４と接続電極３とを同一工程で形成することにより、両者の高さを容易に同じ高さに形成することができる。
【０１１５】
但し、上記支持体４の構造並びに形成方法は、上記図４に示す構造並びに上述した方法に限定されるものではない。上記支持体４は、他の電極部材とは離間（独立）して設けられた構造を有していてもよく、また、上記接続電極３形成前あるいは形成後に上記支持体４を形成してもよいことは言うまでもないことである。
【０１１６】
図４に示すように、上記接続電極３及び支持体４の高さ（厚みｄ）、つまり、配線２０の厚みを含む、これら接続電極３及び支持体４による突起部分の厚みは、使用する材料や、上記配線２０の厚みなどに応じて、従来、半導体チップと回路基板との接続に用いられている突起電極の高さ（厚み）と同様に設定すればよく、特に限定されるものではないが、２０μｍ〜６０μｍの範囲内とすることが好ましい。
【０１１７】
本実施の形態によれば、上記絶縁体層６を上記半導体チップ１の支持部材として使用しないことで、図４に示すように、上記支持体４を、上記絶縁膜６よりも高さ（層厚）が小さくなるように形成することができる。このように上記支持体４を形成すれば、半導体装置の小型化を図ることが可能になると共に、上記半導体チップ１と回路基板２との接合をより安定して行うことが可能となる。
【０１１８】
また、上記支持体４の先端面の面積、つまり、上記支持体４における該支持体４と半導体チップ１との接触面の面積（以下、説明の便宜上、単に支持体４の面積と記す）は、上記接続電極３の先端面の面積、つまり、上記接続電極３における該接続電極３と半導体チップ１との接触面の面積（以下、説明の便宜上、単に接続電極３の面積と記す）よりも大きく形成されていることが好ましい。
【０１１９】
上記支持体４の面積によっては、半導体チップ１を加圧するとき、半導体チップ１の素子面に支持体４が押圧されることで、該押圧部に応力が集中して上記半導体チップ１の素子面がダメージを受ける可能性がある。よって、支持体４が半導体チップ１の素子面に当たることによるダメージを軽減するためには、該支持体４の面積を前記接続電極３の面積よりも大きくすることが好ましい。
【０１２０】
なお、本実施の形態において、図３に示す回路基板２上に設けられた配線２０、接続電極３、及び支持体４のパターン構造（形状、大きさ）、並びに、ソルダレジスト開口部１２の大きさや形状は、図３に示す構造（形状、大きさ）並びに上記説明に限定されるものではなく、各々の構成要素について上記の条件に適合すれば任意のものでよいものとする。
【０１２１】
なお、上記回路基板２としては、例えば、ワイヤボンドターミナルを有するリードフレームや、ポリイミド樹脂、ＢＴレジン（ビスマレイミド・トリアジン樹脂）等で製作された有機基板などを使用することができるが、特に限定されるものではなく、任意の基板を用いることができる。
【０１２２】
上記半導体チップ１と回路基板２とは、図１（ｄ）に示すように、上記接続電極３…及び電極端子部５…で互いに接合されていると共に、異方導電性導電性樹脂や絶縁性樹脂などの界面封止樹脂８にて上記半導体チップ１と回路基板２との間隙を封止するように固着されている。上記界面封止樹脂８としては、例えばエポキシ樹脂などの熱硬化性樹脂が使用されるが、これに限定されるものではない。
【０１２３】
次に、本実施の形態にかかる上記半導体装置の製造工程の一例について、図１（ａ）〜（ｄ）乃至図４に基づいて以下に説明する。
【０１２４】
先ず、図１（ａ）に示すように、上記半導体装置の製造に用いる半導体チップ１及び回路基板２を準備する。
【０１２５】
上記半導体チップ１の作製においては、図２に示すように該半導体チップ１の素子面中央部に、平面電極からなる電極端子部５…を設けると共に、これら電極端子部５…を除く素子面を、該電極端子部５…と面一となるように該電極端子部５…の厚み（高さ）とほぼ同じ厚みを有する絶縁膜１３で覆っておく。
【０１２６】
一方、上記回路基板２の作製においては、図３に示すように該回路基板２上に、上記半導体チップ１の実装対象領域よりも大きく開口された絶縁体層６を形成する。また、上記回路基板２における上記半導体チップ１の実装対象領域には、上記半導体チップ１の電極端子部５…に対応して接続電極３…を形成すると共に、これら接続電極３とほぼ同じ高さ（厚み）を有する支持体４…を形成する。このとき、上記接続電極３…並びに支持体４…は、突起状に形成する。上記支持体４…は、上記回路基板２上に、接続電極３…や配線２０などをエッチング等により形成するときに同時に作製することができ、かつ、高さを合わせることも容易にできる。
【０１２７】
上記電極端子部５、配線２０、接続電極３、及び支持体４の材料としては、従来の半導体装置において電極や配線に通常使用される材料を用いることができ、前記したように、例えば、Ａｌ、Ｓｉ、Ｃｕ、Ｎｉ、Ｃｒ、Ｔｉ、Ｗ、Ａｕなどの材料を用いることができる。また、上記した以外の半導体チップ１及び回路基板２の構成は、従来と同様に作製することができる。
【０１２８】
次に、図１（ｂ）に示すように、回路基板２に設けられた接続電極３…と半導体チップ１の電極端子部５…とが各々接触するように位置合わせを行う。この際、支持体４の高さが接続電極３とほぼ同じ高さであることにより、半導体チップ１と回路基板２とを容易に実質平行に保持することができる。このため、上記接続電極３…と電極端子部５…との接触を、安定した状態とすることができる。
【０１２９】
続いて、同図１（ｂ）に示すように、上記半導体チップ１と回路基板２とが実質平行に保持され、かつ、上記接続電極３…と電極端子部５とが接触している状態で、超音波印加ツール７または図示しないステージまたはその併用により、加熱状態にて超音波を印加して所定の荷重を加えることにより、上記接続電極３…と電極端子部５…とを、各々電気的に接続する。
【０１３０】
具体的には、上記半導体チップ１と回路基板２との接合部を１００℃〜１５０℃に加熱した状態で、超音波印加ツール７によって４０ｋＨｚの超音波を印可して上記接合部に数Ｎから数十Ｎの荷重を１秒間程度加える。
【０１３１】
これにより、上記半導体チップ１の電極端子部５…と回路基板２の接続電極３…とは、回路基板２に設けられた上記接続電極３…及び支持体４…の塑性変形を伴い、電気的に接続される。このとき接続電極３…と支持体４…とに、ほぼ同じ塑性変形する材料、より好適には同じ塑性変形する材料（例えば同じ材料）を用いることで、両者の変形量をほぼ同じにすることができ、変形量の違いに起因する接続不良を防止することができ、接続電極３と電極端子部５との接続信頼性を向上させることができる。
【０１３２】
次いで、図１（ｃ）に示すように、半導体チップ１の側面からノズル９を用いて、上記接続電極３及び支持体４によって架設された上記半導体チップ１と回路基板２との間隙に、界面封止樹脂８として、液状の界面封止樹脂材料を注入する。
【０１３３】
このとき、図３に示すように、半導体チップ１の素子面の中央部にほぼ直線状に形成されている電極端子部５…に対応して回路基板２における半導体チップ１の実装対象領域の中央部にほぼ直線状に上記接続電極３…が設けられている場合において、上記回路基板２に、これら接続電極３…の配列方向に沿ってこれら接続電極３…と実質的に平行かつこれら接続電極３…の両側に上記支持体４…を形成した場合には、上記間隙に、上記電極端子部５…の配列方向（つまり、接続電極３…の配列方向）に対しほぼ直交する方向から上記界面封止樹脂８に用いられる液状の界面封止樹脂材料を注入することで、該界面封止樹脂８の注入性を向上させることができる。
【０１３４】
一方、半導体チップ１の素子面の中央部にほぼ直線状に形成されている電極端子部５…に対応して回路基板２における半導体チップ１の実装対象領域の中央部にほぼ直線状に上記接続電極３…が設けられている場合において、上記回路基板２に、これら接続電極３…の配列方向に沿ってこれら接続電極３…と実質的に平行かつこれら接続電極３…の片側にのみ上記支持体４…を形成した場合には、上記間隙に、接続電極３…のもう一方の片側、つまり、上記支持体４…が形成されている側とは上記接続電極３…を挟んで反対側、もしくは、上記電極端子部５…の配列方向（つまり、接続電極３…の配列方向）に対しほぼ直交する方向から上記界面封止樹脂８を注入することで、該界面封止樹脂８の注入性を向上させることができる。
【０１３５】
このように本実施の形態では、前記特許文献１に示すようにソルダレジスト、（本実施の形態では回路基板２における絶縁体層６）を半導体チップ１の支持体（支持部材）として使用しないので、該ソルダレジスト（絶縁体層６）によるソルダレジスト開口部１２を、該半導体チップ１のチップサイズよりも大きく設定することができる。このため、図１（ｃ）に示すように上記回路基板２上に半導体チップ１を搭載した後に該半導体チップ１と回路基板２との間隙に上記界面封止樹脂８を注入する場合、該界面封止樹脂８の注入を容易に行うことができる。
【０１３６】
また、本実施の形態によれば、上記したように上記半導体チップ１と回路基板２とを接合した後で、両者の間隙に上記界面封止樹脂８を注入することができることから、前記特許文献１に示すように半導体チップを回路基板に搭載するに際し、両者の接続状態を維持するために界面封止樹脂を硬化させる間、半導体チップを加熱加圧ツールにより一定時間保持（加圧）する必要はない。このため、上記界面封止樹脂８の硬化時に上記半導体チップ１と回路基板２との間のタクト短縮、つまり、上記半導体チップ１の実装（ボンディング固定）に係る時間の短縮を行うことができる。
【０１３７】
本実施の形態においては、上記界面封止樹脂８として、例えば熱硬化性樹脂であるエポキシ樹脂を用いている。該界面封止樹脂８を硬化させることにより、図１（ｄ）に示すように、上記半導体チップ１が上記回路基板２にフリップチップ実装される。
【０１３８】
〔実施の形態２〕
本発明にかかる他の実施形態について、図５（ａ）〜（ｃ）に基づいて説明すれば、以下のとおりである。なお、説明の便宜上、前記実施の形態１にて説明した図面と同じ機能を有する部材については、同じ符号を付記し、その説明を省略する。また、前記実施の形態１で述べた各種の特徴点については、本実施の形態についても組み合わせて適用し得るものとする。
【０１３９】
図５（ａ）〜（ｃ）は本実施の形態にかかる半導体装置の製造工程の一例を示す断面図であり、そのうち、図５（ｄ）は、本実施の形態にかかる半導体装置の断面の概略構成を示している。また、図６は、図５（ｃ）に示す本実施の形態にかかる半導体装置の要部の構成を概略的に示す断面図である。
【０１４０】
前記実施の形態１では、半導体チップ１と回路基板２との間隙を封止する界面封止樹脂として、液状の熱硬化性樹脂を使用した。これに対し、本実施の形態では、界面封止樹脂として、異方導電性樹脂からなる界面封止樹脂２１（異方導電性樹脂フィルム）を使用する。
【０１４１】
本実施の形態にかかる半導体装置は、図５（ｃ）に示すように、半導体チップ１における電極端子部５…と回路基板２における接続電極３…とが、上記界面封止樹脂２１を介してフリップチップ実装された構造を有している。
【０１４２】
図６に示すように、異方導電性樹脂からなる界面封止樹脂２１は、バインダー樹脂２２に導電粒子２３…が分散されてなる。上記界面封止樹脂２１は、例えばフィルム状のエポキシ樹脂中に導電粒子２３が分散しており、導電粒子２３を挟み込む所定の導電部分だけその間隙が導電粒子２３の粒形以下に小さくなることで導電状態が得られ、他は絶縁状態となる特性を有する。
【０１４３】
このため、上記界面封止樹脂２１を介して上記電極端子部５…と接続電極３…とが接合されることで、上記電極端子部５…と接続電極３…とは、上記導電粒子２３を介して電気的に接続される。また、このとき上記電極端子部５…と接続電極３…とは、上記導電粒子２３が両者の接合部にクサビのように埋め込まれた状態で金属接合される。また、熱圧着の際に、フィルム状のバインダー樹脂２２は溶融して一旦ペースト状となり、上記半導体チップ１と回路基板２との間隙を封止すると共に両者を接続する。
【０１４４】
次に、本実施の形態にかかる上記半導体装置の製造工程の一例について、図５（ａ）〜（ｃ）及び図６に基づいて以下に説明する。
【０１４５】
先ず、図５（ａ）に示すように、前記実施の形態１と同様にして上記半導体装置の製造に用いる半導体チップ１及び回路基板２を準備する。但し、本実施の形態においては、同図５（ａ）に示すように、上記半導体チップ１と回路基板２とを接合する前に、予め、上記半導体チップ１の素子面にフィルム状の異方導電性樹脂からなる界面封止樹脂２１（異方導電性樹脂フィルム）を貼り付けておく。
【０１４６】
これにより、本実施の形態においては、上記半導体チップ１は、該半導体チップ１の素子面に上記フィルム状の界面封止樹脂２１が貼り付けられた状態で回路基板２にフリップチップ実装される。
【０１４７】
上記半導体チップ１と回路基板２との接合（実装）は、図５（ｂ）に示すように、上記半導体チップ１の素子面に上記フィルム状の界面封止樹脂２１が貼り付けられた状態で上記半導体チップ１の電極端子部５…と回路基板２の接続電極３…とを位置合わせする。本実施の形態においても、上記支持体４の高さが接続電極３とほぼ同じ高さであることにより、半導体チップ１と回路基板２とを容易に実質平行に保持することができる。このため、上記接続電極３…と電極端子部５…との接触を、安定した状態とすることができる。
【０１４８】
続いて、同図５（ｂ）に示すように、上記半導体チップ１と回路基板２とが実質平行に保持され、かつ、上記接続電極３…と電極端子部５…とが接触している状態で、超音波印加ツール７または図示しないステージまたはその併用により、加熱状態にて超音波を印加して所定の荷重を加えることにより、上記接続電極３…と電極端子部５…とを、各々電気的に接続する。
【０１４９】
但し、本実施の形態においては、電極端子部５…と接続電極３…との電気的な接続と同時に上記界面封止樹脂２１の硬化を進めることで上記５…と接続電極３…との接合部を保持するため、該接合部を１２０℃〜２４０℃に加熱した状態で、超音波印加ツール７によって４０ｋＨｚの超音波を印可して上記接合部に数Ｎから数十Ｎの荷重を３秒間程度加える。
【０１５０】
これにより、上記半導体チップ１と回路基板２とは、上記界面封止樹脂２１によって接続（接合）されると共に、上記接続電極３…及び支持体４…と上記半導体チップ１との各々の接合部において、例えば図６に示すように上記界面封止樹脂２１中の導電粒子２３が、該接合部（特に該接合部における上記接続電極３…及び支持体４…）にクサビのように埋め込まれることで、上記接続電極３…及び支持体４…の塑性変形を伴い、電気的に接続される。
【０１５１】
このように、本実施の形態では、上記半導体チップ１と回路基板２との電気的な接続と同時に上記界面封止樹脂２１の硬化を進めることで、上記半導体チップ１と回路基板２との接続部、特に、上記半導体チップ１と接続電極３…及び支持体４…との接合部を保持する。なお、該工程の後、必要に応じて、オーブンなどの加熱手段を用いて上記界面封止樹脂２１の硬化をさらに進めてもよい。これにより、図５（ｄ）に示すように、上記半導体チップ１と回路基板２とをフリップチップ実装することができる。
【０１５２】
なお、本実施の形態においても、前記実施の形態１と同様、電極端子部５の最表層は、通常、ＡｌやＳｉ、Ｃｕにて形成されるが、より高い接続信頼性を確保するためには、該電極端子部５の表面が、Ｎｉ、Ｃｒ、Ｔｉ、Ｗ、Ａｕなどの金属で構成されており、好ましくはＡｕの厚さが１μｍ程度あるほうがよい。
【０１５３】
以上のように、本実施の形態においては、上記半導体チップ１と回路基板２とを、両者の間隙に設けられる界面封止樹脂２１に異方導電性を持たせるために添加された導電粒子２３を、両者の接合部に噛み混ませた状態で、電気的に接合することで、上記接合部の初期の接続安定性や接続信頼性を向上させることができる。
【０１５４】
さらに、前記実施の形態１では半導体チップ１と回路基板２の電気的な接続を行った後、両者の間隙に液状の界面封止樹脂８を注入して硬化させることによりフリップチップ実装を行ったが、本実施の形態では、予め半導体チップ１の素子面にフィルム状の界面封止樹脂２１が貼り付けられているので、電極端子部５…と接続電極３…との電気的な接続と界面封止樹脂２１の硬化とを同時進行させることができるので、半導体チップ１の実装（ボンディング固定）にかかる時間を短縮させることができる。
【０１５５】
なお、通常、半導体チップの電極端子部の配列に対して垂直方向（側面の方向）から界面封止樹脂を注入すると、該半導体チップの側面方向位置ずれが問題となり、高い位置決め精度を持った装置が必要となるが、上記したようにフィルム状の異方導電性樹脂を半導体チップ１の素子面に貼り付けた状態で上記半導体チップ１の実装を行うことで、該半導体チップ１の横方向のアライメント精度にマージンがあり、半導体装置の側面方向での位置ずれの問題を招来しないので、より安価な構成とすることができる。
【０１５６】
〔実施の形態３〕
本発明にかかるさらに他の実施形態について、図７（ａ）〜（ｄ）に基づいて説明すれば、以下のとおりである。なお、説明の便宜上、前記実施の形態１及び実施の形態２にて説明した図面と同じ機能を有する部材については、同じ符号を付記し、その説明を省略する。また、前記実施の形態１及び実施の形態２で述べた各種の特徴点については、本実施の形態についても組み合わせて適用し得るものとする。
【０１５７】
図７（ａ）〜（ｄ）は本実施の形態にかかる半導体装置の製造工程の一例を示す断面図であり、そのうち、図７（ｄ）は、本実施の形態にかかる半導体装置の断面の概略構成を示している。
【０１５８】
本実施の形態において用いられる回路基板２は、図７（ａ）に示すように、前記実施の形態１及び２に示す接続電極３…及び支持体４…の最表層に、回路基板２と半導体チップ１とを接続（接合）するための接合層３１もしくは接合層３２が設けられている構成を有している。
【０１５９】
すなわち、本実施の形態において用いられる回路基板２は、接続電極及び支持体として、前記実施の形態１及び２に示す接続電極３…及び支持体４…を半導体チップ１と回路基板２とを架設状態で支持する支持層とし、該支持層上に、上記半導体チップ１の実装（接合）条件において塑性変形することにより上記半導体チップ１と回路基板２とを接続（接合）する接合層３１・３２が形成された積層構造を有する接続電極３３（接続用電極端子部）及び支持体３４が設けられている構成を有している。
【０１６０】
例えば、上記接続電極３３及び支持体３４は、上記支持層としての第１導電層（接続電極３もしくは支持体４）上に、接合層３１もしくは接合層３２として、上記第１導電層並びに電極端子部５…よりも柔らかい材料からなる第２導電層が設けられている構成を有している。
【０１６１】
上記接合層３１・３２には、例えば、Ｓｎ、または、Ｓｎを含む半田材料などの導電性材料からなる接続材料が用いられる。しかしながら、上記導電性材料（接続材料）としては、これに限らず、Ａｇやメッキを施した樹脂粒子（導電粒子）を含む導電ペーストなどの導電性接着剤を用いてもよい。
【０１６２】
上記接合層３１・３２は、例えば、上記第１導電層（接続電極３もしくは支持体４）上に上記接続材料を塗布あるいは滴下するなどの方法により容易に形成することができる。また、上記接合層３１・３２は、上記第１導電層の面積よりも該接合層３１・３２の面積、つまり、該接合層３１・３２における半導体チップ１との接触面の面積が大きくなるように設けることができる。
【０１６３】
上記半導体チップ１の電極端子部５の最表層は、通常ＡｌやＳｉやＣｕにより構成されるが、上記接合層３１・３２が半田材料からなる場合にはこれに限らず、ＮｉやＣｒやＴｉやＷなどの、バリアメタルもしくはアンダーバンプメタルに使用される金属で構成されていてもよい。
【０１６４】
本実施の形態においては、図７（ａ）に示すように、接続電極及び支持体として、回路基板２に、上記したように最表層に回路基板２と半導体チップ１とを接続（接合）するための接合層３１もしくは接合層３２を有する接続電極３３及び支持体３４を形成したことを除けば、図７（ｂ）〜（ｄ）に示すように、前記実施の形態１に係る半導体装置と同様の実装工程を経て、半導体装置を製造する。
【０１６５】
本実施の形態においても、上記支持体３４における支持層（第１導電層）は、前記実施の形態１同様、上記回路基板２に、接続電極３３…における支持層（第１導電層）や配線２０などをエッチング等により形成するときに同時に作製することができる。また、上記接合層３１及び接合層３２もまた、同材料で、同時に形成することができる。
【０１６６】
さらに、前記実施の形態１同様、本実施の形態においても、図７（ｂ）に示すように、接続電極３３…と電極端子部５…とを位置合わせし、上記半導体チップ１と回路基板２とが実質平行に保持され、かつ、上記接続電極３３…と電極端子部５…とが接触している状態で、超音波印加ツール７または図示しないステージまたはその併用により、上記半導体チップ１と回路基板２との接合部を１００℃〜１５０℃に加熱し、超音波印加ツール７によって４０ｋＨｚの超音波を印可して上記接合部に数Ｎから数十Ｎの荷重を１秒間程度加えることで、上記接続電極３３及び支持体３４と半導体チップ１とを安定して接合することができる。また、このとき、半田を使用していれば、より強固な金属接合を行うことができる。
【０１６７】
なお、本実施の形態においても、上記半導体チップ１と回路基板２との間隙を封止する界面界面封止樹脂としては、液状の界面封止樹脂８を使用し、上記間隙への界面封止樹脂８の注入は、半導体チップ１の側面から行った。また、上記界面封止樹脂８としては、熱硬化性樹脂であるエポキシ樹脂を用いた。
【０１６８】
以上のように、本実施の形態においては、接続電極及び支持体として、上記接合層３１・３２を有する接続電極３３及び支持体３４を用いた。
【０１６９】
フリップチップ実装において超音波を用いて押圧する方法では、一般的に、電極端子部５の最表層に形成されている金属は、一定の加圧と同時に超音波振動を加えることにより、塑性流動を生じる。この塑性流動には金属の変形と同時に超音波振動による波動的流動も伴っており、このため電極端子部５と接続電極３との両金属界面の酸化膜が破壊され、新生面の接触により接合が生じる。しかし、この超音波による接続では、溶着が加圧の中心部ではなく、その周辺にドーナツ状に生じる。
【０１７０】
そこで、前記実施の形態１では、液状の界面封止樹脂８を用いて上記接合を強くしたが、本実施の形態では、さらに、上記接続電極３及び支持体４上に上記導電性材料からなる接合層３１・３２を設けることにより、より強固な金属接合を可能とした。
【０１７１】
〔実施の形態４〕
本発明にかかるさらに他の実施形態について、図８（ａ）〜（ｄ）に基づいて説明すれば、以下のとおりである。なお、説明の便宜上、前記実施の形態１乃至実施の形態３にて説明した図面と同じ機能を有する部材については、同じ符号を付記し、その説明を省略する。また、前記実施の形態１乃至実施の形態３で述べた各種の特徴点については、本実施の形態についても組み合わせて適用し得るものとする。
【０１７２】
図８（ａ）〜（ｄ）は本実施の形態にかかる半導体装置の製造工程の一例を示す断面図であり、そのうち、図８（ｄ）は、本実施の形態にかかる半導体装置の断面の概略構成を示している。
【０１７３】
なお、本実施の形態においては、半導体チップの電極端子部が形成される面を表面、電極端子部が形成されない面を裏面と称することとする。
【０１７４】
本実施の形態にかかる半導体装置は、前記実施の形態２において、導電粒子２３…が分散された、フィルム状の異方導電性樹脂に代えて、フィルム状の絶縁樹脂からなる界面封止樹脂４７を用いると共に、複数の半導体チップを各半導体チップの厚さ方向に互いに積層してなる構成を有している。
【０１７５】
本実施の形態にかかる半導体装置は、図８（ｃ）・（ｄ）に示すように、センターパッドを有する第１の半導体チップ４１（ベアチップ）が、回路基板４３に、上記第１の半導体チップ４１に設けられた電極端子部５…に対応して突出して設けられた接続電極３…（第１の接続電極、接続用電極端子部）並びに支持体４…によってフリップチップ実装されていると共に、該フリップチップ実装された第１の半導体チップ４１の裏面に、第２の半導体チップ４２の裏面を貼り付けた状態で、該第２の半導体チップ４２が、金属細線４５…により、上記回路基板４３におけるソルダレジスト開口部１２内に設けられた接続パッド４６…（第２の接続電極、接続用電極端子部）に電気的に接続された構成を有している。
【０１７６】
上記第１の半導体チップ４１は、例えば前記実施の形態１〜３に記載の半導体チップ１と同様の構成を有している。また、上記回路基板４３は、該回路基板４３におけるソルダレジスト開口部１２内の半導体チップ形成領域外に、上記ソルダレジスト開口部１２に沿って、上記接続パッド４６…が設けられていることを除けば、例えば前記実施の形態１または２に記載の回路基板２と同様の構成を有している。
【０１７７】
なお、上記半導体装置を構成する第２の半導体チップ４２の種類、サイズは特に限定されず、任意のものを使用することができる。
【０１７８】
上記第２の半導体チップ４２は、該第２の半導体チップ４２における素子面に設けられた電極端子部４４…と、上記接続パッド４６…とを、上記金属細線４５…によりワイヤボンディングすることにより、上記回路基板４３と電気的に接続されている。上記第２の半導体チップ４２における素子面には、電極端子部４４…を除く素子面表面を覆うと共に該素子面表面を平坦化する絶縁膜５０が設けられている。本実施の形態では、平面電極（電極パッド）からなる電極端子部４４…が、上記第２の半導体チップ４２の縁部（端部）に沿って設けられている場合を例に挙げて説明するが、本発明はこれに限定されるものではない。
【０１７９】
上記電極端子部５・４４の材料としては、配線２０、接続電極３、及び支持体４の材料と同様、前記実施の形態１〜３にて説明したように、従来の半導体装置において電極や配線に通常使用される材料を用いることができる。具体的には、前記実施の形態１〜３に記載の金属材料などを用いることができる。
【０１８０】
また、上記第１の半導体チップ４１と回路基板４３との間隙は、上記絶縁樹脂（第１の絶縁樹脂）からなる界面封止樹脂４７により封止されている。上記回路基板４３上には、該回路基板４３の半導体チップ搭載面（すなわち、上記半導体装置の実装面）を、上記第１の半導体チップ４１及び第２の半導体チップ４２ごと封止（被覆）する封止樹脂（第２の絶縁樹脂）からなる封止樹脂層４９が設けられている。これにより、上記第２の半導体チップ４２と上記回路基板４３の接続パッド４６…とを接続する金属細線４５…は、上記半導体装置の実装面を被覆する封止樹脂層４９により保護されている。
【０１８１】
また、上記回路基板４３における半導体チップ搭載面（第１面）とは反対側の面（第２面）には、前記回路基板２同様、絶縁体層１０（絶縁性部材）が設けられていると共に、半田ボールなどの外部入出力端子５３が設けられている。上記外部入出力端子５３は、回路基板４３並びに該回路基板４３の第２面を覆う上記絶縁体層１０を貫く貫通孔５２を介して該回路基板４３の半導体チップ搭載面に設けられた配線２０と電気的に接続されている。
【０１８２】
次に、本実施の形態にかかる上記半導体装置の製造工程の一例について、図８（ａ）〜（ｄ）に基づいて以下に説明する。
【０１８３】
先ず、図８（ａ）に示すように、例えば前記実施の形態１〜３に記載の半導体チップ１及び回路基板２と同様にして上記半導体装置の製造に用いる第１の半導体チップ４１及び回路基板４３を準備する。但し、本実施の形態においては、同図８（ａ）に示すように、上記第１の半導体チップ４１と回路基板４３とを接合する前に、予め、上記上記第１の半導体チップ４１の素子面にフィルム状の絶縁樹脂からなる界面封止樹脂４７（絶縁樹脂フィルム）を貼り付けておく。
【０１８４】
また、上記回路基板４３におけるソルダレジスト開口部１２内には、前記実施の形態１同様、上記第１の半導体チップ４１の実装対象領域に、上記第１の半導体チップ４１の電極端子部５…に対応した接続電極３…並びにこれら接続電極３とほぼ同じ高さ（厚み）を有する支持体４…を形成すると共に、上記第１の半導体チップ４１の実装対象領域外に、上記第１の半導体チップ４１上に積層される第２の半導体チップ４２（図８（ｃ）参照）における電極端子部４４…と接続される接続パッド４６…を形成する。
【０１８５】
上記接続パッド４６…もまた、支持体４…同様、上記回路基板４３上に、接続電極３…や配線２０などをエッチング等により形成するときに同時に作製することができる。
【０１８６】
上記第１の半導体チップ４１と回路基板４３との接合（実装）は、前記実施の形態２における半導体チップ１と回路基板２との接合（実装）工程（方法）と同様の工程（方法）により行うことができる。
【０１８７】
つまり、上記第１の半導体チップ４１と回路基板４３との接合（実装）は、図８（ｂ）に示すように、上記第１の半導体チップ４１の素子面に上記フィルム状の界面封止樹脂４７が貼り付けられた状態で上記第１の半導体チップ４１の電極端子部５…と回路基板４３の接続電極３…とを位置合わせし、上記第１の半導体チップ４１と回路基板４３とが実質平行に保持され、かつ、上記接続電極３…と電極端子部５…とが接触している状態で、超音波印加ツール７または図示しないステージまたはその併用により加熱状態にて上記第１の半導体チップ４１と回路基板４３との接合部に超音波を印加して所定の荷重を加えることにより行われる。
【０１８８】
本実施の形態においても、上記支持体４の高さが接続電極３とほぼ同じ高さであることにより、上記第１の半導体チップ４１と回路基板４３とを容易に実質平行に保持することができ、上記接続電極３…と電極端子部５…との接触を、安定した状態とすることができる。
【０１８９】
次に、図８（ｃ）に示すように、フリップチップ接続された上記第１の半導体チップ４１の裏面に、接着剤層４８を介して、予め準備しておいた第２の半導体チップ４２の裏面を貼り付ける。
【０１９０】
上記接着剤層４８に用いられる接着剤としては、例えば液状の接着剤や、シート状の接着剤などを使用することができる。上記接着剤は、上記第１の半導体チップ４１の裏面と第２の半導体チップ４２の裏面とをその全領域に渡って均一に接着できるものであれば、その種類は問わない。
【０１９１】
続いて、該第２の半導体チップ４２の表面に設けられた電極端子部４４…を、金属細線４５…により、回路基板４３上に設けられた接続パッド４６…と電気的に接続する。上記金属細線４５の材料については特に限定しないが、Ａｌ、Ａｕが好ましい。
【０１９２】
上記電極端子部４４及び接続パッド４６と金属細線４５とを電気的に接続する方法としては、（１）接続部に熱と圧力とを加え、その境界面で塑性変形を起こさせて両者の接続部での酸化膜崩壊、表面の活性化を促し、両金属間の拡散接合によって金属間化合物を形成させることにより両者を接続する、熱圧着を用いたワイヤボンディング法（熱圧着ワイヤボンディング法）、（２）加圧と超音波の印可とにより接続部を固層溶接する、超音波を用いたワイヤボンディング法（超音波ワイヤボンディング法）、及び（３）熱圧着ワイヤボンディング法に超音波を併用するワイヤボンディング法（超音波併用熱圧着ワイヤボンディング法）などが挙げられるが、特に限定されるものではない。
【０１９３】
また、上記電極端子部４４及び接続パッド４６と金属細線４５とをワイヤボンディングする順番、つまり、上記第２の半導体チップ４２及び回路基板４３と金属細線４５とをワイヤボンディングする順番も特に限定されないが、回路基板と金属細線とを接続した後に、第半導体チップと金属細線とを接続するいわゆるリバースワイヤボンディング法が、該リバースワイヤボンディング法と逆の順番で接続を行ういわゆるフォワードワイヤボンディング法に比べて、金属細線の高さを低くすることができ、半導体装置をより一層薄型化することができることからより好ましい。
【０１９４】
リバースワイヤボンディング法を行う場合は、半導体チップに設けられた電極端子上に金バンプを形成し、最初に金属細線と回路基板との接続を行い、その後に上記金属細線と上記金バンプとの接続を行う。
【０１９５】
但し、上記電極端子部４４と接続パッド４６とを接続する方法としては、上記方法に限定されるものではない。
【０１９６】
次に、同図８（ｃ）に示すように、上記電極端子部４４と金属細線４５との接続部を、絶縁膜５１で保護した後、図８（ｄ）に示すように、上記回路基板４３の半導体チップ搭載面全面を、封止樹脂（第２の絶縁樹脂）で覆い、該封止樹脂からなる封止樹脂層４９で上記金属細線４５を保護する。
【０１９７】
本実施の形態では、固形の熱硬化性樹脂を加熱融解させて金型内に移行、充填させ、硬化させるトランスファーモールド法を用いて、エポキシ樹脂により上記封止樹脂層４９を形成した。
【０１９８】
しかしながら、上記封止樹脂層４９の形成方法はこれに限定されるものではなく、例えば、シリンジなどに入った液状の樹脂をディスペンサなどで適量滴下させ、その後加熱硬化させることによって封止するポッティング法、パッケージ内部に液状樹脂を注入する注形法など、任意の方法を適用することができる。また上記封止樹脂の種類も、エポキシ樹脂に限定に限定されるものではなく、任意の熱硬化性樹脂を用いることができる。
【０１９９】
最後に図８（ｄ）に示すように、回路基板４３の裏面に、外部入出力端子５３として半田ボールを形成する。なお、外部入出力端子５３の種類は特に限定されず、任意のものを使用することができる。
【０２００】
なお、本実施の形態では、フリップチップ接続された第１の半導体チップ４１の裏面に、第２の半導体チップ４２を１つ貼り付けたが、積層される半導体チップの個数はこれに限定されるものではなく、任意の数とすることができる。
【０２０１】
なお、上記第１の半導体チップ４１の裏面に、複数の半導体チップを貼り付ける場合、例えば、第２の半導体チップ４２の電極端子部４４と第３の半導体チップの電極端子部とを対向配置させてワイヤボンディングさせることにより共通の信号を用いる構成としてもよく、あるいは、上記第２の半導体チップ４２よりも小さい第３の半導体チップを、上記第２の半導体チップ４２の電極端子部４４と接触しないように上記第２の半導体チップ４２上に積層する構成としてもよく、従来公知の積層型の半導体装置（半導体装置パッケージ）と同様にして上記半導体チップの積層を行うことができる。
【０２０２】
このように複数の半導体チップを回路基板に積層することにより、半導体チップの実装密度の高い半導体装置を実現することができる。
【０２０３】
また、本実施の形態では、上記界面封止樹脂４７に絶縁性樹脂を用いたが、上記界面封止樹脂４７としては、これに限定されるものではなく、前記実施の形態１〜３で使用した界面封止樹脂と同様の界面封止樹脂を用いることができる。また、上記界面封止樹脂４７としては、フィルム状の界面封止樹脂を用いたが、該界面封止樹脂としては、前記実施の形態１及び３に示すように液状であってもよく、また、ペースト状であってもよい。
【０２０４】
さらに、上記各実施の形態においては、電極の塑性変形を伴う接合方法として、超音波接合を用いた場合を例に挙げて説明したが、本発明は、これに限定されるものではなく、例えば、超音波、熱、圧力の何れか、またはそれらを併用し、超音波、熱、圧力のうち少なくとも１つを上記半導体チップと回路基板との接合部に与える（印加する）ことにより、突起状に形成された上記電極端子部及び上記支持体の塑性変形による上記半導体チップと回路基板との接合を行うことができる。
【０２０５】
また、上記接合条件としては、上記電極材料（上記各実施の形態においては接続電極並びに支持体の材料）に応じて、該電極材料が、半導体チップとの接合部において塑性変形するように接合条件を適宜設定すればよい。言い換えれば、上記接合条件において塑性変形する材料により上記電極を形成すればよい。
【０２０６】
上記接合に超音波を用いた場合、短時間で金属接合が可能であり、生産性及び接続信頼性をより一層向上させることができる。
【０２０７】
また、上記した各実施の形態では、超音波を用いて電極端子部を塑性変形させることにより上記半導体チップと回路基板とを接合する場合を例に挙げて説明したが、本発明はこれに限定されるものではなく、半導体チップの電極端子部と接続用電極端子部とを圧接させて電気的に接続すると共に上記半導体チップと回路基板とを界面封止樹脂により固着させる場合にも適用することができる。
【０２０８】
具体的には、例えば、前記実施の形態２において、接合条件を変更、つまり、超音波印加ツール７に代えて加熱加圧ツールを使用し、上記半導体チップ１と回路基板２とを位置合わせした状態で、上記加熱加圧ツールにより上記半導体チップ１が搭載された回路基板２を一定時間保持して異方導電性樹脂からなる界面封止樹脂２１（異方導電性樹脂フィルム）を硬化させることにより、上記半導体チップ１の電極端子部５と回路基板２の接続電極３とを圧接により電気的に接続することができる。また、この場合、上記実施の形態２において、界面封止樹脂２１に代えて、ペースト状の異方導電性樹脂からなる界面封止樹脂、もしくは、フィルム状あるいはペースト状の絶縁性樹脂を用いてもよいことは言うまでもない。
【０２０９】
なお、上記半導体チップ１のフリップチップ実装に際し、超音波などを用いて電極端子部の塑性変形を伴う接合を行う場合、上記支持体４の材料としては、少なくともその最表層に、例えば前記実施の形態１〜４に記載したように、半導体チップ１のフリップチップ実装条件において塑性変形する材料が用いられるが、上記半導体チップ１における電極端子部５と回路基板２における接続電極３とを圧接により接合する場合には、上記支持体４の材料としては、上記半導体チップ１を、上記回路基板２と実質平行に支持することができるものであればよい。
【０２１０】
この場合、上記支持体４の材料としては、圧接による接合条件において塑性変形しないものであればよく、前記実施の形態１〜４と同様の材料を用いることができる。
【０２１１】
上記半導体チップ１における電極端子部５と回路基板２における接続電極３とを圧接により接合する場合にも、制御の容易さから、上記支持体４の材料のなかでも、特に好ましい材料は、上記の観点から上記接続電極３と同じ材料であり、そのなかでも特に、支持体４の高さ（厚み）の制御が容易であり、また、金属接合により上記接続電極３と電極端子部５とを強固に安定してかつ短時間で接合することができることから、最も好ましくは金属材料である。
【０２１２】
以上のように、本発明の実施の一形態にかかる半導体装置の製造方法は、素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを実質平行に支持してフリップチップ実装を行う方法である。
【０２１３】
より具体的には、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、かつ、少なくとも最表層が上記半導体チップのフリップチップ実装による上記接続用電極端子部との接合条件で塑性変形すると共に、該塑性変形による変形量が、突起状に形成された上記電極端子部とほぼ同じ材料からなり、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合する方法である。
【０２１４】
また、上記半導体装置の製造方法は、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップの素子形成面と上記回路基板表面とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で、上記半導体チップと回路基板とを架設状態で実質平行に支持した状態で、上記半導体チップと回路基板との間隙を界面封止樹脂により封止して上記接続用電極端子部と上記半導体チップの電極端子部とを圧接させる方法であってもよい。
【０２１５】
さらには、上記半導体装置の製造方法は、素子形成面の中央部に形成された複数の電極（電極端子部）を含む半導体チップが第１の面及び第２の面を有し、該半導体チップが、上記第１の面に支持体が形成された回路基板上に搭載されてなる半導体装置の製造方法であって、上記回路基板の接続パッド（接続用電極端子部）の周辺に形成された支持体により、上記半導体チップが、上記回路基板に対し、ほぼ平行になる状態で、上記半導体チップの素子形成面の中央部付近に形成された複数の電極と、上記回路基板の第１の面に、上記半導体チップの複数の電極にそれぞれ対応して配置された突起を有する複数の接続パッドとを、超音波、熱、圧力の何れか、またはそれらの併用により、直接または部材を介して、電気的に接続する工程と、上記半導体チップの素子形成面と上記回路基板との間隙に界面封止樹脂を注入する工程と、該界面封止樹脂を硬化させる工程とを含む方法であってもよい。
【０２１６】
また、上記半導体装置の製造方法は、素子形成面の中央部に形成された複数の電極（電極端子部）を含む半導体チップが第１の面及び第２の面を有し、該半導体チップが、上記第１の面に支持体が形成された回路基板上に搭載されてなる半導体装置の製造方法であって、上記回路基板の接続パッド（接続用電極端子部）の周辺に形成された支持体により、上記半導体チップが、上記回路基板に対し、ほぼ平行になる状態で、かつ、予め半導体チップまたは上記回路基板に、界面封止樹脂シートまたは界面封止樹脂ペーストを配置する工程と、上記半導体チップの素子形成面の中央部に形成された複数の電極と、上記回路基板の第１の面に、上記半導体チップの複数の電極にそれぞれ対応して配置された突起を有する複数の接続パッドとを、超音波、熱、圧力の何れか、またはそれらの併用により、直接または部材を介して、電気的に接続すると同時に、界面封止樹脂の硬化を行う、または、少なくとも開始させる工程と、必要に応じて、一括してオーブン等で、該界面封止樹脂の硬化を促進させる工程とを含む方法であってもよい。
【０２１７】
さらには、上記半導体装置の製造方法は、上記回路基板の上記第１の面に、上記半導体チップの複数の電極（電極端子部）にそれぞれ対応して配置された突起を有する複数の接続パッド（接続用電極端子部）を、エッチングやメッキ工程で形成すると同時に、同工程により支持体を形成する方法であってもよい。
【０２１８】
また、上記半導体装置の製造方法は、上記半導体チップの素子形成面と上記回路基板との間隙に設けられる樹脂が異方導電性を有し、上記回路基板の接続パッドの周辺に形成された支持体により、上記半導体チップが、上記回路基板に対してほぼ平行になる状態で、上記半導体チップの素子形成面の中央部に形成された複数の電極（電極端子部）と、上記回路基板の第１の面に、上記半導体チップの複数の電極にそれぞれ対応して配置された突起を有する複数の接続パッド（接続用電極端子部）とを、超音波を必ず印可し、熱、圧力の何れか、またはそれらの併用により電気的に接続すると同時に、界面封止樹脂の硬化を行う、または、少なくとも開始させる工程とを含む方法であってもよい。
【０２１９】
また、上記半導体装置の製造方法は、上記回路基板の第１の面に形成された突起を有する接続パッド（接続用電極端子部）と、支持体の最表層に導電性材料が形成されていて、上記回路基板の接続パッドの周辺に形成された支持体により、上記半導体チップが、上記回路基板に対し、ほぼ平行になる状態で、上記半導体チップの素子形成面の中央部に形成された複数の電極（電極端子部）と、上記回路基板の第１の面に、上記半導体チップの複数の電極にそれぞれ対応して配置された突起を有する複数の接続パッドとを、超音波を必ず印可し、熱、圧力の何れか、またはそれらの併用により電気的に接続すると同時に、界面封止樹脂の硬化を行う、または、少なくとも開始させる工程とを含む方法であってもよい。
【０２２０】
さらに、本発明の一実施形態にかかる半導体装置は、例えば以下の構成とすることができる。
【０２２１】
例えば、上記半導体装置は、半導体チップが、素子形成面の中央部に形成された複数の電極（電極端子部）を含み、第１の面および第２の面を有し、かつ、共に表層は絶縁体層が形成された、上記半導体チップを搭載する回路基板を備え、上記回路基板は、上記第１の面に、上記半導体チップの複数の電極にそれぞれ対応して配置された突起を有する複数の接続パッド（接続用電極端子部）と、上記接続パッドとほぼ同じ高さで、上記接続パッド周辺に形成された支持体と、上記接続パッドと電気的に接続された複数の外部入出力端子と、上記絶縁体層には、少なくとも上記半導体チップよりも大きな開口部を備え、上記半導体装置の素子面と前記回路基板との間隙に設けられる樹脂を備え、上記半導体チップの電極と、上記回路基板の接続パッドをフリップチップ方式で、直接または部材を介して、電気的に接続する構造を有していてもよい。
【０２２２】
また、上記素子形成面の中央部に形成された複数の電極（電極端子部）が、ほぼ直鎖状に形成されている場合、上記支持体が、上記電極に対応した直鎖状の接続パッド（接続用電極端子部）の片側、または両側に配置されている構成であってもよい。
【０２２３】
さらに、上記半導体装置は、上記フリップチップ接続された半導体チップの裏面に、少なくとも１つ以上の半導体チップが積層され、上記積層された半導体チップの電極（電極端子部）と、上記回路基板上の上記半導体チップの外側に配置された接続パッド（接続用電極端子部）がそれぞれ金属細線で結線され、上記回路基板の半導体チップが実装されている面が、封止樹脂で覆われている構成であってもよい。
【０２２４】
また、上記した各実施の形態では、突起構造を有する電極（上記各実施の形態においては接続電極）と支持体とが、共に回路基板に形成されている場合を例に挙げて説明したが、本発明はこれに限定されるものではなく、突起構造を有する電極と支持体とが、例えば半導体チップの素子形成面に形成されている配線を利用するなどして共に半導体チップに形成されている構成としてもよく、突起構造を有する電極と支持体とが、回路基板と半導体チップとに各々別々に設けられている構成としても構わない。
【０２２５】
但し、上記突起構造を有する電極と支持体とは、回路基板または半導体チップの何れか一方に設けられていることが、両者の高さを制御、つまり、両者の高さを合わせる上で好ましく、上記突起構造を有する電極と支持体とが共に回路基板側に設けられていることが、回路基板における配線を利用して例えば該配線と同一材料にて同時に上記突起構造を有する電極と支持体とを形成することができ、厚みの制御が容易となり、安価かつ精度良く上記突起構造を有する電極と支持体とを形成することができる。
【０２２６】
本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。
【０２２７】
【発明の効果】
本発明にかかる半導体装置は、以上のように、素子形成面の中央部に電極端子部が設けられた半導体チップが、上記電極端子部にて、回路基板の接続用電極端子部に架設状態でフリップチップ実装されており、上記回路基板は、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられている半導体装置において、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部が突起状に形成されており、上記回路基板表面の絶縁体層は、上記半導体チップの素子形成面よりも大きな開口部を備え、該開口部内で上記半導体チップと回路基板とが架設状態でフリップチップ実装されており、上記半導体チップと回路基板との間隙には、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体が設けられている構成である。
【０２２８】
上記の構成によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有し、上記絶縁体層と半導体チップとが互いに非接触状態にて上記半導体チップが上記接続用電極端子部にフリップチップ実装されるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体が設けられていることから、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。よって、上記の構成によれば、半導体チップと回路基板との接続不良が防止され、接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２２９】
本発明にかかる半導体装置は、以上のように、上記支持体は、突起状に形成された電極端子部と同じ材料からなる構成である。
【０２３０】
上記の構成によれば、上記支持体が、突起状に形成された電極端子部と同じ材料からなることで、既存の技術により、両者の高さを容易に一致させることができる。このため、より一層接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２３１】
本発明にかかる半導体装置は、以上のように、上記支持体は金属からなる構成である。
【０２３２】
金属材料は、その厚さをエッチング加工する技術が特に充実しており、厚みの制御を容易に行うことができるので、上記支持体が金属からなることで、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより一層厳密かつ容易に制御することができる。よって、上記の構成によれば、より接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２３３】
本発明にかかる半導体装置は、以上のように、上記半導体チップと回路基板とが、突起状に形成された上記電極端子部及び上記支持体の塑性変形により接合されている構成である。
【０２３４】
上記の構成によれば、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合であっても上記半導体チップのフリップチップ実装を行う際に、上記半導体チップを上記回路基板と平行に支持することができるので、塑性変形によって強固に接続され、半導体チップと回路基板との位置ズレがなく、接続不良が防止され、接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２３５】
本発明にかかる半導体装置は、以上のように、上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂によりさらに固着されている構成である。
【０２３６】
上記の構成によれば、上記半導体チップと回路基板との間隙を上記界面封止樹脂によりさらに固着することで、両者の接合をより強固で安定したものとすることができるという効果を奏する。
【０２３７】
本発明にかかる半導体装置は、以上のように、上記接続用電極端子部と半導体チップの電極端子部とが架設状態で圧接されており、上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂により固着されている構成である。
【０２３８】
上記の構成によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有し、上記絶縁体層と半導体チップとが互いに非接触状態にて上記半導体チップが上記接続用電極端子部にフリップチップ実装されるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体が設けられていることから、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となる。このため、上記のように半導体チップの電極端子部と接続用電極端子部とを圧接させて電気的に接続すると共に上記半導体チップと回路基板とを界面封止樹脂により固着させる場合においても、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。よって、上記の構成によれば、半導体チップと回路基板との接続不良が防止され、接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２３９】
本発明にかかる半導体装置は、以上のように、上記支持体と半導体チップとの接触面積が、突起状に形成された上記電極端子部と半導体チップとの接触面積よりも大きい構成である。
【０２４０】
上記の構成によれば、上記支持体と半導体チップとの接触面積を、突起状に形成された上記電極端子部と半導体チップとの接触面積よりも大きくすることで、上記支持体が上記半導体チップの素子形成面に当たることによるダメージを軽減することができるという効果を奏する。
【０２４１】
本発明にかかる半導体装置は、以上のように、上記半導体チップの素子形成面とは反対側の面に少なくとも１つの半導体チップが積層され、該積層された半導体チップの電極端子部と、上記回路基板における上記絶縁体層の開口部内でかつ上記半導体チップのフリップチップ実装領域外に設けられた接続用電極端子部とが金属細線により電気的に接続されている構成である。
【０２４２】
上記の構成によれば、上記半導体装置１個当たりの半導体チップの搭載数が増加し、上記半導体チップの実装密度がより高い半導体装置を実現することができるという効果を奏する。
【０２４３】
本発明にかかる半導体装置の製造方法は、以上のように、素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを実質平行に支持してフリップチップ実装を行う方法である。
【０２４４】
上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となるので、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。よって、上記の方法によれば、半導体チップと回路基板との接続不良を防止することができ、接続信頼性が高い半導体装置を提供することができるという効果を奏する。
【０２４５】
本発明にかかる半導体装置の製造方法は、以上のように、素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、かつ、少なくとも最表層が上記半導体チップのフリップチップ実装による上記接続用電極端子部との接合条件で塑性変形すると共に、該塑性変形による変形量が、突起状に形成された上記電極端子部とほぼ同じ材料からなり、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合する方法である。
【０２４６】
上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となる。
【０２４７】
このため、上記の方法によれば、上述したように、超音波接合などの、電極端子部の塑性変形を伴う接合を行う場合であっても、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができる。よって、上記の方法によれば、半導体チップと回路基板との接続不良を防止することができ、接続信頼性が高い半導体装置を製造することができるという効果を奏する。
【０２４８】
本発明にかかる半導体装置の製造方法は、以上のように、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合させた後、上記半導体チップと回路基板との間隙に、該間隙を封止する界面封止樹脂を注入し、該界面封止樹脂を硬化させる方法である。
【０２４９】
上記の方法によれば、上記半導体チップと回路基板との間隙を上記界面封止樹脂によりさらに固着することができ、両者の接合をより強固で安定したものとすることができるという効果を奏する。また上記の構成によれば、前記したように、上記回路基板表面の絶縁体層が、上記半導体チップのフリップチップ実装領域（実装対象領域）において上記半導体チップの素子形成面よりも大きく開口されていることで、上記半導体チップを上記接続用電極端子部にフリップチップ実装したとき、上記半導体チップと回路基板との間隙に、容易に上記界面封止樹脂を注入することができるという効果を奏する。
【０２５０】
本発明にかかる半導体装置の製造方法は、以上のように、素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の片側に、上記接続用電極端子部と平行に上記支持体を形成し、上記半導体チップと回路基板とを接合後に、上記支持体が形成された側とは上記接続用電極端子部を挟んで反対側、もしくは、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入する方法である。
【０２５１】
上記の方法によれば、上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、上記半導体チップと回路基板とを、より強固に安定して接合することができるという効果を奏する。また、上記の方法によれば、上記支持体を、上記接続用電極端子部からなる列の片側に、上記接続用電極端子部と平行に上記支持体を形成し、上記支持体が形成された側とは上記接続用電極端子部を挟んで反対側、もしくは、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、該界面封止樹脂の注入性を向上させることができ、効率良く、しかも、上記間隙に上記界面封止樹脂を満遍なく充填させることができるという効果を併せて奏する。
【０２５２】
本発明にかかる半導体装置の製造方法は、以上のように、素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の両側に、上記接続用電極端子部と平行に上記支持体を形成し、上記半導体チップと回路基板とを接合後に、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入する方法である。
【０２５３】
上記の方法によれば、上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、上記半導体チップと回路基板とを、より強固に安定して接合することができるという効果を奏する。また、上記の方法によれば、上記支持体を、上記接続用電極端子部からなる列の両側に、上記接続用電極端子部と平行に上記支持体を形成し、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することで、該界面封止樹脂の注入性を向上させることができ、効率良く、しかも、上記間隙に上記界面封止樹脂を満遍なく充填させることができるという効果を併せて奏する。
【０２５４】
本発明にかかる半導体装置の製造方法は、以上のように、突起状に形成された上記電極端子部と支持体とによって上記半導体チップと回路基板とを支持する前に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、上記半導体チップと回路基板との間隙を封止する界面封止樹脂からなる層を配し、上記間隙に界面封止樹脂からなる層が配された状態で、突起状に形成した上記電極端子部と上記支持体とによって、上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体の塑性変形と上記界面封止樹脂の硬化とを、同一の工程において行う方法である。
【０２５５】
上記の方法によれば、上記半導体チップと回路基板との間隙を上記界面封止樹脂によって封止することで、上記半導体チップと回路基板とを、より強固に安定して接合することができるという効果を奏する。また、上記の方法によれば、上記半導体チップの電極端子部と接続用電極端子部との電気的な接続と上記界面封止樹脂の硬化とを同時進行させることができるので、上記間隙を界面封止樹脂で封止する場合における半導体チップの実装にかかる時間を短縮させることができるという効果を併せて奏する。
【０２５６】
本発明にかかる半導体装置の製造方法は、以上のように、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体との最表層に、導電性接着剤からなる接合層を各々設ける方法である。
【０２５７】
上記の方法によれば、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体との最表層に上記接合層を設けることで、両者の接合をより強固で安定したものとすることができるという効果を奏する。
【０２５８】
本発明にかかる半導体装置の製造方法は、以上のように、素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップの素子形成面と上記回路基板表面とを実質平行に支持する支持体を形成し、突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で、上記半導体チップと回路基板とを架設状態で実質平行に支持した状態で、上記半導体チップと回路基板との間隙を界面封止樹脂により封止して上記接続用電極端子部と上記半導体チップの電極端子部とを圧接させる方法である。
【０２５９】
上記の方法によれば、上記絶縁体層が、上記半導体チップの素子形成面よりも大きな開口部を有することで、上記絶縁体層と半導体チップとを互いに非接触状態にて上記半導体チップを上記接続用電極端子部にフリップチップ実装することができるので、上記支持体並びに突起形状を有する電極端子部の形成に際し、上記絶縁体層による制限を受けず、しかも、上記絶縁体層とは別に上記支持体を設けることで、該支持体の形成に際し、材料の選択の自由度が大きく、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより厳密に制御することが可能となる。このため、上記の方法によれば、上記のように半導体チップの電極端子部と接続用電極端子部とを圧接させて電気的に接続すると共に上記半導体チップと回路基板とを界面封止樹脂により固着させる場合においても、上記したように中央部にセンターパッドと称される電極端子部を有する半導体チップを回路基板にフリップチップ実装するに際し、半導体チップの素子形成面と回路基板とを実質的に平行に支持した状態で、安定して固定することができるという効果を奏する。
【０２６０】
本発明にかかる半導体装置の製造方法は、以上のように、上記界面封止樹脂として、内部に導電粒子が分散された異方導電性樹脂を用いる方法である。
【０２６１】
上記の方法によれば、上記異方導電性樹脂中に存在する導電粒子により、より良好な電気的接続を得ることができるという効果を奏する。特に、超音波などを用いて電極端子部を塑性変形させることにより上記半導体チップのフリップチップ実装を行う場合、上記半導体チップの電極端子部と接続用電極端子部との接合部に上記導電粒子が埋め込まれ、該導電粒子により、より良好な電気的接続を得ることができる。
【０２６２】
本発明にかかる半導体装置の製造方法は、以上のように、上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体とを、同じ材料で形成する方法である。
【０２６３】
上記の方法によれば、上記支持体を、突起状に形成された電極端子部と同じ材料で形成することで、既存の技術により、両者の高さを容易に一致させることができる。このため、上記の方法によれば、より一層接続信頼性が高い半導体装置を製造することができるという効果を奏する。また、上記の方法によれば、上記支持体と、突起状に形成された電極端子部とを、同一工程、例えばエッチング加工やメッキ等の基板配線の形成工程において同時に形成することが可能になるので、工程数の増加を招くこともなく、安価かつ容易に上記支持体を形成することができるという効果を併せて奏する。
【０２６４】
本発明にかかる半導体装置の製造方法は、以上のように、上記支持体を金属で形成する方法である。
【０２６５】
上記の方法によれば、上記支持体を金属で形成することで、電気的な接続の信頼性に関わる高さ方向のばらつきの防止や厚みをより一層厳密かつ容易に制御することが可能となるので、より接続信頼性が高い半導体装置を製造することができるという効果を奏する。
【０２６６】
本発明にかかる半導体装置の製造方法は、以上のように、上記接続用電極端子部及び半導体チップの電極端子部のうち上記接続用電極端子部を突起状に形成すると共に、上記接続用電極端子部の形成工程と同一の工程で上記回路基板に上記支持体を形成する方法である。
【０２６７】
上記の方法によれば、上記支持体と、突起状に形成された電極端子部とを、例えばエッチング加工やメッキ等の基板配線の形成工程において、配線の形成と同時に、あるいは、上記配線を利用して形成することが可能になるので、工程数の増加を招くこともなく、安価かつ容易に上記支持体を形成することができるという効果を奏する。また、上記の方法によれば、既存の技術により、両者の高さを容易に一致させることができる。このため、上記の方法によれば、より一層接続信頼性が高い半導体装置を、安価かつ容易に製造することができるという効果を併せて奏する。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は本発明の実施の一形態にかかる半導体装置の製造工程の一例を示す断面図である。
【図２】図１（ａ）〜（ｄ）に示す半導体チップの素子形成面の概略構成を示す平面図である。
【図３】図１（ａ）〜（ｄ）に示す回路基板の概略構成を示す平面図である。
【図４】図３に示す回路基板の要部の構成を概略的に示す断面図である。
【図５】図５（ａ）〜（ｃ）は本発明の他の実施の形態にかかる半導体装置の製造工程の一例を示す断面図である。
【図６】図５（ｃ）に示す半導体装置の要部の構成を概略的に示す断面図である。
【図７】図７（ａ）〜（ｄ）は本発明のさらに他の実施の形態にかかる半導体装置の製造工程の一例を示す断面図である。
【図８】図８（ａ）〜（ｄ）は本発明のさらに他の実施の形態にかかる半導体装置の製造工程の一例を示す断面図である。
【図９】従来の半導体装置の構成を概略的に示す断面図である。
【図１０】図１０（ａ）〜（ｃ）は従来のフリップチップ実装方法を用いた半導体装置の製造方法に超音波接合を適用したときの半導体装置の製造工程を示す断面図である。
【符号の説明】
１ 半導体チップ
２ 回路基板
３ 接続電極（接続用電極端子部）
４ 支持体
５ 電極端子部
６ 絶縁体層
７ 超音波印加ツール
８ 界面封止樹脂
９ ノズル
１０ 絶縁体層
１１ 貫通孔
１２ ソルダレジスト開口部
１３ 絶縁膜
２０ 配線
２１ 界面封止樹脂
２２ バインダー樹脂
２３ 導電粒子
３１ 接合層
３２ 接合層
３３ 接続電極（接続用電極端子部）
３４ 支持体
４１ 第１の半導体チップ
４２ 第２の半導体チップ
４３ 回路基板
４４ 電極端子部
４６ 接続パッド（接続用電極端子部）
４７ 界面封止樹脂
４８ 接着剤層
４９ 封止樹脂層
５０ 絶縁膜
５１ 絶縁膜
５２ 貫通孔
５３ 外部入出力端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device for connecting a semiconductor chip having an electrode at the center of an element formation surface and a circuit board by a flip-chip mounting method, and manufacturing the same. It is about the method.
[0002]
[Prior art]
In recent years, there has been remarkable progress in miniaturization and weight reduction of portable information devices such as mobile phones. Accordingly, there is a demand for miniaturization and weight reduction of all components including a semiconductor device mounted on these devices. In such a situation, in a semiconductor device, there is a demand for miniaturization of a semiconductor chip mounting structure and high-density mounting on a circuit board.
[0003]
In order to meet such a demand, mounting using a flip-chip mounting method of directly mounting a semiconductor bare chip on a circuit board (hereinafter, simply referred to as flip-chip mounting or flip-chip mounting method) has been implemented in order to meet such a demand. .
[0004]
In the flip chip mounting method, a conductive bump electrode (bump) provided on a semiconductor chip is pressed against a connection pad provided on a circuit board corresponding to the bump electrode. A method of sealing a gap with a circuit board with a liquid or film-like interface sealing resin such as an anisotropic conductive resin (Anisotropic Conductive Film or Paste) or an insulating resin (Non Conductive Film or Paste) is generally used. It is used for As described above, the bonding between the semiconductor chip and the circuit board using the interface sealing resin is performed by heating and pressing the circuit board on which the semiconductor chip is mounted for a certain period of time with the semiconductor chip and the circuit board aligned. The holding is performed by curing the anisotropic conductive resin to such an extent that the connection portion between the two can be held.
[0005]
On the other hand, in recent years, flip-chip mounting using ultrasonic waves (hereinafter, referred to as ultrasonic bonding) has attracted attention as a flip-chip mounting method using metal bonding involving deformation of projecting electrodes (bumps) instead of pressure bonding. Has begun. In the method, a protruding electrode (bump) provided on an electrode pad of a semiconductor chip is brought into contact with a connection pad provided on a circuit board, and the protruding electrode is pressed and deformed using ultrasonic vibration. Thus, the two are joined. For this reason, this method can perform metal bonding in a shorter time than the above-described bonding method by pressure welding, and has a possibility of improving productivity and reliability.
[0006]
However, in any case, for example, a so-called center pad in which a plurality of electrode pads are linearly arranged at the center of an element formation surface, such as a DRAM (Dynamic Random Access Memory) called a dynamic ram. When flip-chip mounting is performed using a semiconductor chip having the above, there is a problem that the semiconductor chip is likely to be tilted with the projecting electrode (bump) formed on the electrode pad as a fulcrum. For this reason, it is difficult to fix the element (active element) forming surface of the semiconductor chip and the circuit board while maintaining a substantially parallel space when flip-chip mounting the semiconductor chip. It is. For this reason, the semiconductor device thus obtained has poor connection stability between the semiconductor chip and the circuit board, and may cause poor connection or reduced reliability.
[0007]
On the other hand, for example, Patent Document 1 discloses a method for solving the above-mentioned problem in flip chip mounting using an interface sealing resin, as shown in FIG. Are provided at the four corners of the circuit board 72 such that the area (opening) surrounded by the support member 76 is smaller than the chip size of the semiconductor chip 71, and the periphery of the semiconductor chip 71 is By supporting the portion, the semiconductor chip 71 and the circuit board 72 are supported substantially in parallel, and the protruding electrodes 78 formed on the electrode pads 74 (center pads) of the semiconductor chip 71 and the circuit board 72 are provided. A method of bonding the connection pad 73 to the connection pad 73 using an anisotropic conductive resin 79 (Anisotropic Conductive Film or Paste) as an interface sealing resin. Is disclosed.
[0008]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-332055 (released on November 30, 2000)
[0009]
[Problems to be solved by the invention]
However, there is still no known method for solving the problem of mounting a semiconductor chip having a so-called center pad, as described above, in flip-chip mounting in which metal bonding is performed by deforming projecting electrodes using ultrasonic waves or the like. Not been.
[0010]
The inventors of the present application have solved the above-mentioned problem by applying the ultrasonic bonding as a flip-chip mounting method of performing metal bonding by deforming a protruding electrode to the flip-chip mounting method in Patent Document 1. Tried to solve.
[0011]
FIGS. 10A to 10C are cross-sectional views showing the steps of manufacturing a semiconductor device when the ultrasonic bonding is applied to the method of manufacturing a semiconductor device using the flip-chip mounting method described in Patent Document 1. It is.
[0012]
First, as shown in FIG. 10A, an anisotropic conductive resin 79 as an interface sealing resin is provided on a region of a circuit board 72 on which a semiconductor device is to be mounted including an insulating support member 76 such as a resist layer. Coat.
[0013]
Next, the connection pads 73 on the circuit board 72 and the protruding electrodes 78 provided on the electrode pads 74 (center pads) of the semiconductor chip 71 are aligned, and as shown in FIG. A predetermined load is applied to the semiconductor chip 71 by applying ultrasonic waves in a heated state. As a result, the protruding electrode 78 is plastically deformed as shown in FIG. 10C, and the semiconductor chip 71 and the circuit board 72 are joined with the semiconductor chip 71 supported by the support member 76.
[0014]
As described above, when the ultrasonic bonding is applied to the flip-chip mounting method in Patent Literature 1, it becomes possible to metal-bond the semiconductor chip 71 and the circuit board 72 in a short time.
[0015]
However, in order to bond the semiconductor chip 71 and the circuit board 72 by deforming the protruding electrodes 78 as described above, as shown in FIG. The height must always be higher than the insulating support member 76 such as a resist layer by the deformation of the protruding electrode 78.
[0016]
Therefore, when ultrasonic bonding is applied to the flip-chip mounting method in Patent Document 1, when applying ultrasonic waves or the like to the projecting electrode 78 formed at the center of the semiconductor chip 71 to deform the projecting electrode 78, Since there is no one that supports the semiconductor chip 71 substantially in parallel with the circuit board 72, the behavior of the semiconductor chip 71 when a predetermined load is applied by applying ultrasonic waves to the semiconductor chip 71 As shown in FIG. 10 (c), the projection electrode 78 and the connection pad 73 may be displaced, resulting in a misalignment and a decrease in connection reliability.
[0017]
For this reason, it is desired to solve the above-mentioned problems in flip-chip bonding involving plastic deformation of electrodes, such as ultrasonic bonding.
[0018]
Further, in Patent Document 1, as described above, the peripheral portion of the semiconductor chip 71 is supported by the support members 76 provided at the four corners of the circuit board 72 and made of an insulating member such as a resist layer. When the support member 76 is formed of an insulating member such as a resist layer in this manner, when the semiconductor chip 71 is pressed during flip-chip mounting, the connection position in the lateral direction is obviously large as described above. Since there is a large variation in the vertical direction, that is, in the height direction related to the reliability of electrical connection, there is a problem in practical use.
[0019]
That is, an insulating member such as a resist layer provided on the circuit board 72 is generally referred to as a solder resist, and is used for securing the strength of the circuit board 72 and insulating metal wiring on the circuit board 72. Is necessary. However, this solder resist has a problem that it is not easy to control the thickness and the thickness variation due to the material is relatively large. The same can be said for the controllability in controlling the thickness by etching.
[0020]
Therefore, when a solder resist is used as the support member 76 as described in Patent Document 1, the thickness of the support member 76 varies for each circuit board 72 regardless of whether or not ultrasonic bonding is performed. It is necessary to set an appropriate bump height for each circuit board 72, that is, the height of the protruding electrode 78. Further, if the support member 76 is to be formed with high precision, the number of manufacturing steps of the circuit board 72 increases, which leads to an increase in cost.
[0021]
The present invention has been made in view of the above-described problems, and an object of the present invention is to mount a semiconductor chip having an electrode pad called a center pad in a center portion on a circuit board by flip chip mounting. A semiconductor device capable of stably fixing the element formation surface and the circuit board in a state of being supported substantially in parallel, and preventing poor connection and reduction in connection reliability between the semiconductor chip and the circuit board. And a method for manufacturing the same.
[0022]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor chip according to the present invention includes a semiconductor chip provided with an electrode terminal portion (for example, an electrode pad called a center pad) at a central portion of an element forming surface. The circuit board is flip-chip mounted on a connection electrode terminal portion (for example, a connection pad) of the circuit board, and the circuit board is larger than the semiconductor chip and has an insulating layer (for example, a solder resist) on its surface. ), One of the electrode terminal portion for connection and the electrode terminal portion of the semiconductor chip is formed in a protruding shape, and the insulator layer on the surface of the circuit board is An opening (for example, a solder resist opening) that is larger than a surface of the semiconductor chip on which an element (for example, an active element) is formed; The semiconductor chip and the circuit board are flip-chip mounted in an erect state, and have substantially the same height as the protruding electrode terminals in the gap between the semiconductor chip and the circuit board. It is characterized in that a support for supporting in parallel is provided.
[0023]
According to the above configuration, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In addition, the conventional problems when the solder resist is used as the support member are not caused.
[0024]
In particular, according to the above configuration, the insulator layer has an opening that is larger than the element formation surface of the semiconductor chip, and the insulator layer and the semiconductor chip are in a non-contact state with each other. Since the connection electrode terminal portion is flip-chip mounted, the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer, and the support member is provided separately from the insulator layer. Since the body is provided, when the support is formed, the degree of freedom in selecting a material is large, and it is necessary to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. When a semiconductor chip having an electrode terminal portion called a center pad in the center portion is flip-chip mounted on a circuit board as described above, the element forming surface of the semiconductor chip and the circuit While substantially supported parallel to the plate can be stably fixed.
[0025]
Therefore, according to the above configuration, in a state where the element formation surface of the semiconductor chip and the circuit board are supported substantially in parallel, the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion are Since the semiconductor device is flip-chip mounted without being displaced in the lateral direction, poor connection between the semiconductor chip and the circuit board is prevented, and a semiconductor device with high connection reliability can be provided.
[0026]
In addition, according to the above configuration, the present invention can be suitably applied to the case where bonding involving plastic deformation of the electrode terminal portion such as ultrasonic bonding is performed, so that the semiconductor terminal is firmly connected to the semiconductor chip by plastic deformation. It is possible to provide a semiconductor device which has no positional deviation from a circuit board, prevents poor connection, and has high connection reliability.
[0027]
In order to solve the above problem, the semiconductor device according to the present invention is characterized in that the support is made of the same material as the protruding electrode terminal portion.
[0028]
According to the above configuration, since the support is made of the same material as the electrode terminal portion formed in a protruding shape, the heights of the two can be easily matched by the existing technology. Therefore, a semiconductor device with higher connection reliability can be provided.
[0029]
In addition, according to the above configuration, when performing bonding involving plastic deformation of the electrode terminal portion, such as ultrasonic bonding, deformation of the support and the protruding electrode terminal portion due to the plastic deformation. Since the amounts can be easily matched, it is possible to join the semiconductor chip and the circuit board while supporting them in parallel. Therefore, according to the above configuration, it is possible to provide a semiconductor device which is firmly connected by plastic deformation, has no positional deviation between the semiconductor chip and the circuit board, prevents poor connection, and has higher connection reliability.
[0030]
In order to solve the above problems, the semiconductor device according to the present invention is characterized in that the support is made of metal.
[0031]
The metal material has a particularly rich technique of etching the thickness, and the thickness can be easily controlled. For this reason, when the support is made of metal, it is possible to prevent the variation in the height direction related to the reliability of the electrical connection and to control the thickness more strictly and easily. The height can be easily adjusted to the height of the electrode terminal portion formed in a projection shape. Therefore, a semiconductor device with higher connection reliability can be provided.
[0032]
In order to solve the above problems, the semiconductor device according to the present invention may be configured such that the semiconductor chip and the circuit board are joined by plastic deformation of the protruding electrode terminal portion and the support. Features.
[0033]
According to the above configuration, as described above, even when performing bonding involving plastic deformation of the electrode terminals, such as ultrasonic bonding, when performing flip-chip mounting of the semiconductor chip, the semiconductor chip is removed. Provided is a semiconductor device which can be supported in parallel with the circuit board, is firmly connected by plastic deformation, has no positional displacement between the semiconductor chip and the circuit board, prevents poor connection, and has high connection reliability. Can be.
[0034]
Conventionally, there is no known technique for performing flip-chip connection in a state where a semiconductor chip and a circuit board are supported in parallel when performing bonding involving plastic deformation of an electrode terminal portion, such as ultrasonic bonding. If the technology of using an insulator layer called a solder resist provided on a circuit board as a support member for supporting a semiconductor chip is applied to bonding involving plastic deformation of an electrode terminal, a projection electrode must be a semiconductor. It is necessary to be formed on the chip side, and the height of the projecting electrode needs to be higher than the supporting member made of the insulator layer by the deformation of the projecting electrode. For this reason, conventionally, it has not been possible to perform flip-chip connection while supporting the semiconductor chip and the circuit board in parallel.
[0035]
However, according to the present invention, as described above, there is provided a semiconductor device which is firmly connected by plastic deformation, has no positional displacement between a semiconductor chip and a circuit board, prevents poor connection, and has high connection reliability. Can be.
[0036]
In order to solve the above-mentioned problems, a semiconductor device according to the present invention includes an interface sealing resin (for example, an anisotropic conductive resin) that seals a gap between the semiconductor chip and the circuit board. Or an insulating resin).
[0037]
According to the above configuration, the semiconductor chip and the circuit board can be more firmly and stably joined. For example, when the bonding between the semiconductor chip and the circuit board is performed by ultrasonic bonding, the welding (bonding) between the electrode terminal section of the semiconductor chip and the connecting electrode terminal section of the circuit board is generally performed at the central portion. Instead, it occurs like a donut around it. For this reason, by further fixing the gap between the semiconductor chip and the circuit board with the interfacial sealing resin, the bonding between them can be made stronger and more stable.
[0038]
In order to solve the above problems, the semiconductor device according to the present invention is configured such that the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip are pressed against each other in a state of being bridged, and the semiconductor chip and the circuit board are connected to each other. It is characterized by being fixed by an interface sealing resin for sealing a gap between a semiconductor chip and a circuit board.
[0039]
According to the above configuration, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In the case where the electrode terminal portion of the semiconductor chip and the electrode terminal portion for connection are brought into pressure contact with each other and electrically connected as described above, and the semiconductor chip and the circuit board are fixed with an interface sealing resin, The conventional problems in the case where the circuit board and the solder resist are used as the supporting member are not caused.
[0040]
In particular, according to the above configuration, the insulator layer has an opening that is larger than the element formation surface of the semiconductor chip, and the insulator layer and the semiconductor chip are in a non-contact state with each other. Since the connection electrode terminal portion is flip-chip mounted, the support member for supporting the semiconductor chip and the electrode terminal portion (projection electrode) are not restricted by the insulator layer when forming the electrode terminal portion (projection electrode). Since the support is provided separately from the body layer, the formation of the support has a high degree of freedom in selecting a material, and prevents a variation in the height direction related to the reliability of electrical connection and a thickness. Can be controlled more strictly.
[0041]
Therefore, according to the above configuration, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion is flip-chip mounted on a circuit board as described above, the element formation surface of the semiconductor chip and the circuit board Can be stably fixed in a state of being supported substantially in parallel, and a connection failure between the semiconductor chip and the circuit board can be prevented, and a semiconductor device with high connection reliability can be provided.
[0042]
In the semiconductor device according to the present invention, in order to solve the above-mentioned problem, a contact area between the support and the semiconductor chip is larger than a contact area between the electrode terminal portion formed in a projection shape and the semiconductor chip. It is characterized by.
[0043]
According to the above configuration, the contact area between the support and the semiconductor chip is made larger than the contact area between the electrode terminal portion formed in a projection shape and the semiconductor chip. This can reduce damage caused by hitting the element formation surface.
[0044]
In order to solve the above problem, a semiconductor device according to the present invention has at least one semiconductor chip laminated on a surface of the semiconductor chip opposite to an element forming surface, and has an electrode terminal portion of the laminated semiconductor chip. And a connection electrode terminal portion provided in the opening of the insulator layer in the circuit board and outside the flip chip mounting region of the semiconductor chip, is electrically connected by a thin metal wire. .
[0045]
According to the configuration, the number of semiconductor chips mounted per semiconductor device, in other words, per area of the semiconductor chip mounting area on the circuit board increases, and the mounting density of the semiconductor chips increases. A high semiconductor device can be realized.
[0046]
In order to solve the above-mentioned problems, in the method of manufacturing a semiconductor device according to the present invention, an electrode terminal portion (for example, an electrode pad called a center pad) is provided at the center of a surface on which an element (for example, an active element) is formed. A state in which a semiconductor chip is laid over a connection electrode terminal portion (for example, a connection pad) on a circuit board provided with an insulator layer (for example, a solder resist) on the surface and larger than the semiconductor chip at the electrode terminal portion. In the method for manufacturing a semiconductor device to be flip-chip mounted, an opening (for example, a solder resist opening) larger than an element forming surface of the semiconductor chip is formed in a region of the circuit board where the semiconductor chip is to be flip-chip mounted. ) Is formed, and one of the electrode terminals of the connection electrode terminal and the electrode terminal of the semiconductor chip is formed. A semiconductor chip having a height substantially equal to a height of the electrode terminal portion formed in a projection shape on a surface of one of the semiconductor chip and the circuit board facing the other. And a support for supporting the circuit board substantially in parallel, and the semiconductor chip and the circuit board are formed in the opening of the insulator layer in the circuit board by the electrode terminal portion and the support formed in a projecting shape. And flip-chip mounting is performed by supporting them substantially in parallel.
[0047]
According to the above method, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In addition, the conventional problems when the solder resist is used as the support member are not caused.
[0048]
In particular, according to the above method, the insulator layer has an opening larger than the element forming surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip Can be flip-chip mounted on the connection electrode terminal portion, so that the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer, and the insulator layer Separately, by providing the above-mentioned support, when forming the support, the degree of freedom in selecting a material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. As described above, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion as described above is flip-chip mounted on a circuit board, element formation of the semiconductor chip is performed. And a circuit board in a state of being substantially parallel to the support can be fixed stably with.
[0049]
Therefore, according to the above method, in a state where the element formation surface of the semiconductor chip and the circuit board are supported substantially in parallel, the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion are Since flip-chip mounting can be performed without shifting in the lateral direction, poor connection between the semiconductor chip and the circuit board can be prevented, and a semiconductor device with high connection reliability can be manufactured.
[0050]
Moreover, according to the above-described method, the present invention can be suitably applied to a case where bonding involving plastic deformation of an electrode terminal portion such as ultrasonic bonding is performed. And a semiconductor device having high connection reliability without misalignment between the semiconductor chip and the circuit board, preventing poor connection, can be manufactured.
[0051]
In order to solve the above-mentioned problems, in the method of manufacturing a semiconductor device according to the present invention, an electrode terminal portion (for example, an electrode pad called a center pad) is provided at the center of a surface on which an element (for example, an active element) is formed. A state in which a semiconductor chip is laid over a connection electrode terminal portion (for example, a connection pad) on a circuit board provided with an insulator layer (for example, a solder resist) on the surface and larger than the semiconductor chip at the electrode terminal portion. In the method for manufacturing a semiconductor device to be flip-chip mounted, an opening (for example, a solder resist opening) larger than an element forming surface of the semiconductor chip is formed in a region of the circuit board where the semiconductor chip is to be flip-chip mounted. ) Is formed, and one of the electrode terminals of the connection electrode terminal and the electrode terminal of the semiconductor chip is formed. The portion is formed in a protruding shape, and has a height substantially equal to the electrode terminal portion formed in a protruding shape on a surface of one of the semiconductor chip and the circuit board facing the other, and at least. The outermost layer is plastically deformed under the bonding conditions with the connection electrode terminal portion by flip chip mounting of the semiconductor chip, and the amount of deformation due to the plastic deformation is substantially the same as the electrode terminal portion formed in a projection shape. Forming a support for supporting the semiconductor chip and the circuit board substantially in parallel, and forming the support in the opening of the insulator layer in the circuit board by the electrode terminal portion and the support formed in a protruding shape. The semiconductor chip and the circuit board are supported substantially in parallel in a state of being bridged, and the semiconductor chip and the circuit board are plastically deformed by projecting the electrode terminal portion and the support formed in a protruding shape. It is characterized in that case.
[0052]
According to the above method, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In addition, the conventional problems when the solder resist is used as the support member are not caused.
[0053]
In particular, according to the above method, the insulator layer has an opening larger than the element forming surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip Can be flip-chip mounted on the connection electrode terminal portion, so that the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer, and the insulator layer Separately, by providing the above-mentioned support, when forming the support, the degree of freedom in selecting a material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. As described above, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion as described above is flip-chip mounted on a circuit board, element formation of the semiconductor chip is performed. And a circuit board in a state of being substantially parallel to the support can be fixed stably with.
[0054]
Therefore, according to the above method, in a state where the element formation surface of the semiconductor chip and the circuit board are supported substantially in parallel, the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion are Since flip-chip mounting can be performed without shifting in the lateral direction, poor connection between the semiconductor chip and the circuit board can be prevented, and a semiconductor device with high connection reliability can be manufactured.
[0055]
Conventionally, there is no known technique for performing flip-chip connection in a state where a semiconductor chip and a circuit board are supported in parallel when performing bonding involving plastic deformation of an electrode terminal portion, such as ultrasonic bonding. If the technology of using an insulator layer called a solder resist provided on a circuit board as a support member for supporting a semiconductor chip is applied to bonding involving plastic deformation of an electrode terminal, a projection electrode must be a semiconductor. It is necessary to be formed on the chip side, and the height of the projecting electrode needs to be higher than the supporting member made of the insulator layer by the deformation of the projecting electrode. For this reason, conventionally, it has not been possible to perform flip-chip connection while supporting the semiconductor chip and the circuit board in parallel.
[0056]
However, according to the above-described method, as described above, even when performing bonding involving plastic deformation of an electrode terminal portion, such as ultrasonic bonding, when performing flip-chip mounting of the semiconductor chip, Since the chip can be supported in parallel with the circuit board, it is firmly connected by plastic deformation, there is no displacement between the semiconductor chip and the circuit board, connection failure is prevented, and a semiconductor device with high connection reliability is provided. can do.
[0057]
According to the present invention, for example, at least one of ultrasonic waves, heat, and pressure is applied (applied) to the joint between the semiconductor chip and the circuit board, so that the protruding electrode terminal is formed. The semiconductor chip and the circuit board can be joined by plastic deformation of the portion and the support.
[0058]
In order to solve the above-described problems, the method for manufacturing a semiconductor device according to the present invention includes joining the semiconductor chip and the circuit board by plastically deforming the electrode terminal portion and the support formed in a projecting shape. Thereafter, an interface sealing resin (for example, an anisotropic conductive resin or an insulating resin) for sealing the gap is injected into the gap between the semiconductor chip and the circuit board, and the interface sealing resin is cured. Features.
[0059]
According to the above method, the semiconductor chip and the circuit board can be more firmly and stably joined. For example, when the bonding between the semiconductor chip and the circuit board is performed by ultrasonic bonding, the welding (bonding) between the electrode terminal section of the semiconductor chip and the connecting electrode terminal section of the circuit board is generally performed at the central portion. Instead, it occurs like a donut around it. For this reason, by further fixing the gap between the semiconductor chip and the circuit board with the interfacial sealing resin, the bonding between them can be made stronger and more stable.
[0060]
In this case, according to the present invention, the insulator layer on the surface of the circuit board has a larger opening in the flip chip mounting area (mounting target area) of the semiconductor chip than the element formation surface of the semiconductor chip. When the semiconductor chip is flip-chip mounted on the connection electrode terminal portion, the interface sealing resin can be easily injected into a gap between the semiconductor chip and the circuit board.
[0061]
In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention uses a semiconductor chip having a plurality of electrode terminals arranged in a substantially linear shape in the center of an element forming surface, A plurality of connection electrode terminal portions are provided in a substantially linear manner corresponding to the electrode terminal portions of the semiconductor chip, and one side of a row of the connection electrode terminal portions is parallel to the connection electrode terminal portions. After the support is formed, and after joining the semiconductor chip and the circuit board, the side on which the support is formed is on the opposite side of the connection electrode terminal portion, or from the connection electrode terminal portion. The method is characterized in that the interface sealing resin is injected into a gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to the row.
[0062]
According to the above method, by injecting the interface sealing resin into the gap between the semiconductor chip and the circuit board, the semiconductor chip and the circuit board can be more firmly and stably joined. Then, at this time, the support is formed on one side of the row of the connection electrode terminal portions, and the support is formed in parallel with the connection electrode terminal portions, and the side on which the support is formed is the same as the above. By injecting the interfacial sealing resin into the gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to the opposite side of the connection electrode terminal portion or a row including the connection electrode terminal portion. The injectability of the interface sealing resin can be improved, and the gap can be evenly filled with the interface sealing resin efficiently.
[0063]
In order to solve the above-described problems, a method of manufacturing a semiconductor device according to the present invention uses a semiconductor chip having a plurality of electrode terminals arranged in a substantially linear shape in the center of an element forming surface, A plurality of connection electrode terminals are provided in a substantially linear manner corresponding to the electrode terminals of the semiconductor chip, and on both sides of a row of the connection electrode terminals, the connection electrode terminals are arranged in parallel with each other. After the support is formed and the semiconductor chip and the circuit board are joined, the interface sealing is performed in a gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to a row including the connection electrode terminal portions. It is characterized by injecting resin.
[0064]
According to the above method, by injecting the interface sealing resin into the gap between the semiconductor chip and the circuit board, the semiconductor chip and the circuit board can be more firmly and stably joined. Then, at this time, the support is formed on both sides of the row of the connection electrode terminals in parallel with the connection electrode terminal, and the support is formed on the row of the connection electrode terminals. By injecting the interfacial sealing resin into the gap between the semiconductor chip and the circuit board from a direction substantially perpendicular to the interface sealing resin, the injectability of the interfacial sealing resin can be improved. The interface sealing resin can be evenly filled.
[0065]
In order to solve the above problems, the method for manufacturing a semiconductor device according to the present invention includes the step of supporting the semiconductor chip and the circuit board by supporting the semiconductor chip and the circuit board by the electrode terminal portions and the support formed in a projection shape. A layer made of an interface sealing resin that seals a gap between the semiconductor chip and the circuit board is disposed on a surface of one of the chip and the circuit board facing the other, and an interface sealing resin (for example, In a state where a layer made of a sheet-like or paste-like interface sealing resin) is arranged, the semiconductor chip and the circuit board are substantially parallel to each other in a state of being bridged by the electrode terminals and the support formed in a projecting shape. And the plastic deformation of the protruding electrode terminal portion and the support and the curing of the interfacial sealing resin are performed in the same step.
[0066]
According to the above method, the gap between the semiconductor chip and the circuit board is sealed with the interface sealing resin, so that the semiconductor chip and the circuit board can be more firmly and stably joined.
[0067]
In this case, according to the above method, the electrical connection between the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion and the curing of the interface sealing resin can proceed simultaneously, so that the gap is reduced. The time required for mounting a semiconductor chip when sealing with an interface sealing resin can be reduced.
[0068]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes an outermost layer of a protruding electrode terminal portion and a support of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip. And a bonding layer made of a conductive adhesive (for example, a solder material or a conductive paste).
[0069]
According to the above method, the semiconductor chip and the circuit board can be more firmly and stably joined. For example, when the bonding between the semiconductor chip and the circuit board is performed by ultrasonic bonding, the welding (bonding) between the electrode terminal section of the semiconductor chip and the connecting electrode terminal section of the circuit board is generally performed at the central portion. Instead, it occurs like a donut around it. For this reason, by providing the bonding layer on the outermost layer between the electrode terminal portion formed in a projection shape and the support member among the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip, the bonding between the two is strengthened and stable. It can be done.
[0070]
In order to solve the above-mentioned problems, in the method for manufacturing a semiconductor device according to the present invention, an electrode terminal portion (an electrode pad referred to as a so-called center pad) is provided at the center of an element (for example, an active element) forming surface. A state in which a semiconductor chip is laid over a connection electrode terminal portion (for example, a connection pad) on a circuit board provided with an insulator layer (for example, a solder resist) on the surface and larger than the semiconductor chip at the electrode terminal portion. In the method for manufacturing a semiconductor device to be flip-chip mounted, an opening (for example, a solder resist opening) larger than an element forming surface of the semiconductor chip is formed in a region of the circuit board where the semiconductor chip is to be flip-chip mounted. ) Is formed, and any one of the electrode terminals for connection and the electrode terminals of the semiconductor chip is formed. The semiconductor chip has a height substantially equal to the height of the protruding electrode terminal portion on a surface of one of the semiconductor chip and the circuit board facing the other; A support for supporting the element formation surface of the chip and the surface of the circuit board substantially in parallel is formed, and the electrode terminal portion and the support formed in a protruding shape form an opening in the insulator layer in the circuit board. The gap between the semiconductor chip and the circuit board is sealed with an interface sealing resin (for example, an anisotropic conductive resin or an insulating resin) in a state where the semiconductor chip and the circuit board are supported substantially in parallel in a bridged state. And stopping the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip by pressure.
[0071]
According to the above method, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In addition, the conventional problems when the solder resist is used as the support member are not caused.
[0072]
In particular, according to the above method, the insulator layer has an opening larger than the element forming surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip Can be flip-chip mounted on the connection electrode terminal portion, so that the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer, and the insulator layer Separately, by providing the above-mentioned support, when forming the support, the degree of freedom in selecting a material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. As described above, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion as described above is flip-chip mounted on a circuit board, element formation of the semiconductor chip is performed. And a circuit board in a state of being substantially parallel to the support can be fixed stably with.
[0073]
Therefore, according to the above method, in a state where the element formation surface of the semiconductor chip and the circuit board are supported substantially in parallel, the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion are Since flip-chip mounting can be performed without shifting in the lateral direction, poor connection between the semiconductor chip and the circuit board can be prevented, and a semiconductor device with high connection reliability can be manufactured.
[0074]
According to the above method, unlike the related art, an insulator layer called a solder resist disposed on a circuit board is not used as a support member (support) for supporting the semiconductor chip during flip chip mounting. In the case where the electrode terminal portion of the semiconductor chip and the electrode terminal portion for connection are brought into pressure contact with each other and electrically connected as described above, and the semiconductor chip and the circuit board are fixed with an interface sealing resin, The conventional problems in the case where the circuit board and the solder resist are used as the supporting member are not caused.
[0075]
In particular, according to the above method, the insulator layer has an opening that is larger than the element formation surface of the semiconductor chip, and the insulator chip and the semiconductor chip are in a non-contact state with each other. Since the connection electrode terminal portion is flip-chip mounted, the support member for supporting the semiconductor chip and the electrode terminal portion (projection electrode) are not restricted by the insulator layer when forming the electrode terminal portion (projection electrode). Since the support is provided separately from the body layer, the formation of the support has a high degree of freedom in selecting a material, and prevents a variation in the height direction related to the reliability of electrical connection and a thickness. Can be controlled more strictly.
[0076]
Therefore, according to the above method, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion is flip-chip mounted on a circuit board as described above, the element formation surface of the semiconductor chip and the circuit board Can be stably fixed in a state of being supported substantially in parallel, and a connection failure between the semiconductor chip and the circuit board can be prevented, and a semiconductor device with high connection reliability can be provided.
[0077]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is characterized in that an anisotropic conductive resin having conductive particles dispersed therein is used as the interface sealing resin.
[0078]
According to the above method, a better electric connection can be obtained by the conductive particles present in the anisotropic conductive resin. In particular, when performing flip-chip mounting of the semiconductor chip by plastically deforming the electrode terminal portion using ultrasonic waves or the like, the conductive particles are present at the junction between the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion. By being buried, the conductive particles can provide a better electrical connection.
[0079]
In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device according to the present invention is configured such that, among the electrode terminal portions for connection and the electrode terminal portions of the semiconductor chip, the electrode terminal portion formed in a projecting shape and the support are the same. It is characterized by being formed of a material.
[0080]
According to the above method, by forming the support from the same material as the electrode terminal portion formed in the shape of a protrusion, the heights of the two can be easily matched by the existing technology. For this reason, according to the above method, a semiconductor device with even higher connection reliability can be manufactured.
[0081]
Further, according to the above method, it is possible to simultaneously form the support and the electrode terminal portion formed in the shape of a protrusion in the same step, for example, a step of forming a substrate wiring such as etching or plating. Therefore, the support can be easily and inexpensively formed without increasing the number of steps.
[0082]
In addition, according to the above-described method, when performing bonding involving plastic deformation of the electrode terminal portion, such as ultrasonic bonding, deformation of the support and the protruding electrode terminal portion due to the plastic deformation. Since the amounts can be easily matched, it is possible to join the semiconductor chip and the circuit board while supporting them in parallel. Therefore, according to the above method, it is possible to manufacture a semiconductor device which is firmly connected by plastic deformation, has no positional displacement between the semiconductor chip and the circuit board, prevents poor connection, and has higher connection reliability.
[0083]
A method of manufacturing a semiconductor device according to the present invention is characterized in that in order to solve the above problems, the support is formed of a metal.
[0084]
The metal material has a particularly rich technique of etching the thickness, and the thickness can be easily controlled. For this reason, when the support is formed of metal, it is possible to prevent variations in the height direction related to the reliability of electrical connection and to control the thickness more strictly and easily. Can easily be adjusted to the height of the electrode terminal portion formed in a projection shape. Therefore, according to the above method, a semiconductor device having higher connection reliability can be manufactured.
[0085]
In order to solve the above-described problems, the method for manufacturing a semiconductor device according to the present invention includes forming the connection electrode terminal portion in a protruding shape among the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip. The support is formed on the circuit board in the same step as the step of forming the connection electrode terminal portion.
[0086]
According to the above-described method, the connection electrode terminal portion of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip is formed in a protruding shape, and is formed in the same step as the step of forming the connection electrode terminal portion. By forming the support on the circuit board, the support and the electrode terminal portion formed in a protruding shape, for example, in the step of forming a substrate wiring such as etching or plating, simultaneously with the formation of wiring, Alternatively, since the support can be formed using the wiring, the support can be easily and inexpensively formed without increasing the number of steps. Further, according to the above-described method, the heights of the two can be easily matched by the existing technology. For this reason, according to the above method, a semiconductor device with even higher connection reliability can be manufactured at low cost and easily.
[0087]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
One embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (d) to 4. FIGS. 1A to 1D are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the present embodiment. FIG. 1D is a cross-sectional view of the semiconductor device according to the present embodiment. 1 shows a schematic configuration of a cross section. FIG. 2 is a plan view showing a schematic configuration of an element forming surface of the semiconductor chip 1 shown in FIGS. 1A to 1D, and FIG. 3 is a circuit diagram shown in FIGS. 1A to 1D. FIG. 2 is a plan view showing a schematic configuration of a substrate 2.
[0088]
As shown in FIG. 1D, the semiconductor device according to the present embodiment has a semiconductor chip 1 (bare chip) having an electrode terminal portion 5 composed of a plane electrode (electrode pad) called a so-called center pad as a bonding pad. However, the circuit board 2 is configured to be flip-chip mounted on the circuit board 2 by connection electrodes 3 (connection electrode terminal portions) provided to protrude corresponding to the electrode terminal portions 5. The semiconductor chip 1 and the circuit board 2 are fixed by an interface sealing resin 8.
[0089]
The semiconductor chip 1 has an electrode terminal portion 5 composed of a planar electrode (electrode pad) at the center of the element (active element) formation surface, and the electrode terminal portion 5 is exposed so that the electrode terminal portion 5 is exposed. Except for the element formation surface, that is, the element is covered with the insulating film 13. Thus, the semiconductor chip 1 is flip-chip mounted on the circuit board 2 such that the element formation surface thereof faces the circuit board 2. Hereinafter, in the present embodiment, the element forming surface of the semiconductor chip 1 is referred to as an element surface, and the surface opposite to the element surface is referred to as a back surface.
[0090]
Examples of the semiconductor chip 1 include a DRAM, for example. For example, as shown in FIG. 2, a semiconductor chip 1 such as a DRAM has a configuration in which a plurality of electrode terminal portions 5 formed of an electrode pad such as an aluminum pad are formed in a straight line at the center of an element surface. The insulating film 13 having a thickness (height) substantially equal to the thickness (height) of the electrode terminals 5 so that the element surface except the electrode terminals 5 is substantially flush with the electrode terminals 5. It has a covered configuration. That is, the insulating film 13 also functions as a planarizing film for planarizing the element formation surface.
[0091]
The structure of the semiconductor chip 1 and the configuration of the electrode terminal portion 5 are the same as those of the conventional semiconductor chip having a center pad except that no protruding electrode is provided on a flat electrode (electrode pad) in the electrode terminal portion 5. And the configuration of the electrode pads are basically the same, and description thereof is omitted here. The outermost layer of the electrode terminal portion 5 (plane electrode) is made of a low-resistance metal, usually a metal such as Al, Si, or Cu, in order to improve the electrical connection with the connection electrode 3. It is not limited, and may be made of a metal used as a barrier metal or an under bump metal, such as Ni, Cr, Ti, and W.
[0092]
In the following embodiments, a case where the DRAM shown in FIG. 2 is used as the semiconductor chip 1 will be described as an example of the semiconductor device. However, the present invention is not limited to this. It is not done. The number of the electrode terminals 5 is not particularly limited, and may be any number. Further, the arrangement of the electrode terminals 5 is not particularly limited as long as the electrode terminals 5 are so-called center pads.
[0093]
On the other hand, as shown in FIGS. 1A to 1D, the circuit board 2 is provided with a metal (hereinafter simply referred to as a semiconductor chip mounting surface) on a surface on which the semiconductor chip 1 is mounted (mounted). It has a configuration in which wiring 20 (wiring pattern) such as wiring is provided. An insulating layer 10 (insulating member) is provided on a surface (second surface) of the circuit board 2 opposite to the semiconductor chip mounting surface (first surface), and solder balls and the like are not shown. It has a configuration in which external input / output terminals are provided. The external input / output terminal is electrically connected to the wiring 20 via a through hole 11 penetrating the circuit board 2 and the insulator layer 10 covering the second surface of the circuit board 2.
[0094]
As shown in FIG. 3, the circuit board 2 is larger than the semiconductor chip 1 both vertically and horizontally, and the semiconductor chip mounting surface of the circuit board 2, that is, the wiring 20 forming surface is smaller than the chip size of the semiconductor chip 1. An insulating layer 6 (insulating member) having a large opening (opening a window) is provided.
[0095]
The insulator layer 6 is generally called a solder resist. However, as described above, the thickness of the solder resist is more difficult to control than a member made of, for example, a metal material, and the thickness variation caused by the material is relatively large. Also, the controllability in controlling the thickness by etching has a large difference between, for example, a metal material and a solder resist. Therefore, the use of the solder resist as the support member leads to poor connection and reduced connection reliability, and leads to an increase in the number of manufacturing steps and an increase in cost.
[0096]
Therefore, in the present embodiment, as described above, by opening the insulator layer 6 of the circuit board 2 larger than the chip size of the semiconductor chip 1, the semiconductor chip mounting surface of the circuit board 2 In addition to forming the solder resist opening 12 larger than the chip size of the semiconductor chip 1, the semiconductor chip 1 is mounted on the semiconductor chip mounting surface of the circuit board 2 separately from the insulator layer 6 when the semiconductor chip 1 is flip-chip mounted. Is formed to form a support 4 (support member) for supporting.
[0097]
That is, in the present embodiment, as shown in FIG. 3, the insulator layer 6 is formed on the periphery of the circuit board 2, and the area of the solder resist opening 12 formed by the insulator layer 6 is Since the insulating layer 6 is larger than the area of the element surface of the semiconductor chip 1 mounted on the circuit board 2, the insulating layer 6 can be used for flip-chip mounting of a semiconductor chip having a center pad as disclosed in Patent Document 1, for example. It is used not as a supporting member but as a solder resist for securing the strength of the circuit board 2 and for securing the insulation state of the wiring 20 on the circuit board 2.
[0098]
The connection electrodes 3 are formed in the solder resist openings 12 so as to correspond to the electrode terminals 5 of the semiconductor chip 1. The connection electrode 3 has a protruding structure. That is, in the present embodiment, in the solder resist opening 12 in the circuit board 2, a connection electrode composed of a plurality of connection pads having a protruding structure (projection) corresponding to the electrode terminals 5 of the semiconductor chip 1. 3 are provided.
[0099]
These connection electrodes 3 are arranged at a central portion in the solder resist opening 12, and the semiconductor chip 1 is mounted on the circuit board 2 in a state where the element surface of the semiconductor chip 1 is not in contact with the insulator layer 6. Flip chip mounting.
[0100]
Therefore, in the present embodiment, the support 4 is provided so as to protrude (project) in the mounting target region of the semiconductor chip 1 in the solder resist opening 12, whereby the semiconductor chip 1 is flip-chip mounted. Sometimes, the semiconductor chip 1 and the circuit board 2 are supported substantially in parallel. In the present embodiment, “supporting the semiconductor chip 1 and the circuit board 2 substantially in parallel” means supporting the element surface of the semiconductor chip 1 and the surface of the circuit board 2 (substrate plane) substantially in parallel.
[0101]
The support 4 has substantially the same height as the connection electrodes 3, and is arranged around the connection electrodes 3 along the direction in which the connection electrodes 3 are arranged, for example, as shown in FIG. And are provided substantially in parallel.
[0102]
Note that the circuit board 2 shown in FIG. 3 has a configuration in which the supports 4 are provided on both sides of the connection electrodes 3... In the mounting target area of the semiconductor chip 1. No particular limitation is imposed as long as the semiconductor chip 1 can be supported substantially in parallel with the circuit board 2 at the time of mounting the flip chip 1. For example, a connection in which the support 4 is provided on the circuit board 2 The electrode 3 may be provided on only one side.
[0103]
As the material of the support 4, a material capable of supporting the semiconductor chip 1 substantially in parallel with the circuit board 2 and plastically deforming under the flip chip mounting conditions of the semiconductor chip 1, preferably the flip chip The material whose deformation amount is substantially the same as that of the connection electrode 3 at the time of mounting, more preferably, the material whose deformation amount is the same as that of the connection electrode 3 is used.
[0104]
Thereby, the connection electrode 3 and the electrode terminal portion 5 can be firmly and stably bonded in a short time, and the connection failure due to the difference in the deformation amount is suppressed and preferably prevented. it can.
[0105]
Among the materials for the support 4, a particularly preferable material is the same material as the connection electrode 3 from the above viewpoint, and among them, the control of the height (thickness) of the support 4 is particularly easy, In addition, since the connection electrode 3 and the electrode terminal portion 5 can be firmly and stably bonded in a short time by metal bonding, a metal material is most preferable.
[0106]
As the material of the connection electrode 3, the same material as that used for the connection electrode (connection pad) of the circuit board in the conventional semiconductor device or the electrode terminal portion (projection electrode) of the semiconductor chip can be used. Specifically, as the material of the connection electrode 3, a planar electrode material constituting the electrode terminal portion 5, that is, the above-described metal material or the like can be used, but is not limited thereto.
[0107]
The combination of the connection electrode 3 and the support 4 with the planar electrode material forming the electrode terminal portion 5 is not particularly limited. However, when the semiconductor chip 1 is flip-chip mounted, ultrasonic waves or the like are used as described above. When performing joining (for example, metal joining) accompanied by plastic deformation of the electrode by using a material, the material of the connection electrode 3 and the support 4 is made of a material softer than the flat electrode material constituting the electrode terminal portion 5. Is desirable. As a material of the connection electrode 3 and the support 4, for example, Au, Sn, or the like is preferably used, but is not limited thereto.
[0108]
Further, as the connection electrode 3 and the support 4, a solder containing Sn and Pb as main components may be used, and the connection electrode 3 and the support 4 are formed by using a known method of forming a solder bump electrode (bump). The body 4 can also be formed.
[0109]
As a method for forming the solder bump electrodes, for example, there are a wire bump method using a solder wire and wire bonding, a method using electroless plating, and an electrolytic plating method. In this case, it is desirable that the outermost surfaces of the connection electrode 3 and the support 4 be plated with, for example, Au as an antioxidant layer. Further, for example, a configuration in which Au plating or the like is applied to a wiring material such as Cu may be adopted. When the connection electrode 3 is made of Au, it is not necessary to particularly form the oxidation preventing layer. When the connection electrode 3 and the support 4 are formed by plating, it is preferable that a plating prevention film is provided on the wiring 20.
[0110]
Of course, there is a large difference between the solder resist and the metal material, for example, in control of thickness and controllability during processing by etching. However, when a conductive pattern, particularly a metal pattern is formed, processing by etching has conventionally been performed. The technology to control the thickness is enhanced. Therefore, by using a metal material for the support 4, an extremely universal technique can be applied to the formation of the support 4.
[0111]
Therefore, when a conductive member such as a metal material is used for the support 4, for example, an electrode member (a conductive member such as a metal member) on the circuit board 2 side can be used as the support 4. In this case, the electrode member can be connected to the electrode terminals 5 provided at the center of the semiconductor chip 1 as signal wiring.
[0112]
That is, the circuit board 2 shown in FIG. 3 may have, for example, a cross-sectional structure as shown in FIG. As shown in FIG. 4, by using an electrode member on the circuit board 2 side, for example, the wiring 20 for the support 4, the support 4 can be used in a wiring pattern forming step by etching, plating, or the like. 3 and the same material, for example, the same metal material (wiring material).
[0113]
Since the support 4 is made of, for example, the same material as that of the connection electrode 3, the connection terminal 3 is connected to the electrode terminal 5 by plastic deformation of the connection electrode 3, which is a protruding electrode. The amount of deformation between the support 4 and the connection electrode 3 can be made the same, and poor connection due to the difference in the amount of deformation between the two can be prevented.
[0114]
Further, by forming the support 4 and the connection electrode 3 in the same step, the heights of both can be easily formed to the same height.
[0115]
However, the structure and the forming method of the support 4 are not limited to the structure shown in FIG. 4 and the method described above. The support 4 may have a structure provided separately (independently) from the other electrode members. Alternatively, the support 4 may be formed before or after the connection electrode 3 is formed. The good thing goes without saying.
[0116]
As shown in FIG. 4, the height (thickness d) of the connection electrode 3 and the support 4, that is, the thickness of the projecting portion formed by the connection electrode 3 and the support 4 including the thickness of the wiring 20 depends on the material used. The height (thickness) of the bump electrode conventionally used for connecting the semiconductor chip and the circuit board may be set according to the thickness of the wiring 20 or the like, and is not particularly limited. Is preferably in the range of 20 μm to 60 μm.
[0117]
According to the present embodiment, by not using the insulator layer 6 as a support member for the semiconductor chip 1, as shown in FIG. (Thickness) can be reduced. By forming the support 4 in this way, the size of the semiconductor device can be reduced, and the bonding between the semiconductor chip 1 and the circuit board 2 can be performed more stably.
[0118]
The area of the tip surface of the support 4, that is, the area of the contact surface between the support 4 and the semiconductor chip 1 in the support 4 (hereinafter simply referred to as the area of the support 4 for convenience of description) is , The area of the end face of the connection electrode 3, that is, the area of the contact surface between the connection electrode 3 and the semiconductor chip 1 in the connection electrode 3 (hereinafter simply referred to as the area of the connection electrode 3 for convenience of explanation). It is preferable that it is formed large.
[0119]
Depending on the area of the support 4, when the semiconductor chip 1 is pressed, the support 4 is pressed against the element surface of the semiconductor chip 1, so that stress is concentrated on the pressing portion and the element surface of the semiconductor chip 1 is pressed. May be damaged. Therefore, in order to reduce the damage caused by the support 4 hitting the element surface of the semiconductor chip 1, it is preferable that the area of the support 4 is larger than the area of the connection electrode 3.
[0120]
In the present embodiment, the pattern structure (shape, size) of the wiring 20, the connection electrode 3, and the support 4 provided on the circuit board 2 shown in FIG. The sheath shape is not limited to the structure (shape and size) shown in FIG. 3 and the above description, but may be arbitrary as long as each component meets the above conditions.
[0121]
As the circuit board 2, for example, a lead frame having a wire bond terminal, an organic substrate made of polyimide resin, BT resin (bismaleimide / triazine resin), or the like can be used. Instead, any substrate can be used.
[0122]
As shown in FIG. 1D, the semiconductor chip 1 and the circuit board 2 are joined to each other at the connection electrodes 3 and the electrode terminal portions 5 and anisotropically conductive resin or insulating material. The gap between the semiconductor chip 1 and the circuit board 2 is fixed with an interface sealing resin 8 such as a resin. As the interface sealing resin 8, for example, a thermosetting resin such as an epoxy resin is used, but is not limited thereto.
[0123]
Next, an example of a manufacturing process of the semiconductor device according to the present embodiment will be described below with reference to FIGS.
[0124]
First, as shown in FIG. 1A, a semiconductor chip 1 and a circuit board 2 used for manufacturing the semiconductor device are prepared.
[0125]
In the manufacture of the semiconductor chip 1, as shown in FIG. 2, an electrode terminal portion 5 consisting of a planar electrode is provided at the center of the device surface of the semiconductor chip 1, and the device surface excluding these electrode terminal portions 5 is provided. The electrode terminals 5 are covered with an insulating film 13 having substantially the same thickness (height) as the electrode terminals 5 so as to be flush with the electrode terminals 5.
[0126]
On the other hand, in manufacturing the circuit board 2, as shown in FIG. 3, the insulator layer 6 is formed on the circuit board 2 so as to have an opening larger than the mounting area of the semiconductor chip 1. Further, connection electrodes 3 are formed in regions of the circuit board 2 where the semiconductor chips 1 are to be mounted, corresponding to the electrode terminals 5 of the semiconductor chip 1, and have substantially the same height as the connection electrodes 3. (Thickness) of support 4 are formed. At this time, the connection electrodes 3 and the supports 4 are formed in a projecting shape. The supports 4 can be produced at the same time when the connection electrodes 3 and the wiring 20 are formed on the circuit board 2 by etching or the like, and the heights can be easily adjusted.
[0127]
As a material of the electrode terminal portion 5, the wiring 20, the connection electrode 3, and the support 4, a material usually used for an electrode or a wiring in a conventional semiconductor device can be used. , Si, Cu, Ni, Cr, Ti, W, Au and the like. The configurations of the semiconductor chip 1 and the circuit board 2 other than those described above can be manufactured in the same manner as in the related art.
[0128]
Next, as shown in FIG. 1B, alignment is performed such that the connection electrodes 3 provided on the circuit board 2 and the electrode terminal portions 5 of the semiconductor chip 1 are in contact with each other. At this time, since the height of the support 4 is substantially the same as the height of the connection electrode 3, the semiconductor chip 1 and the circuit board 2 can be easily held substantially in parallel. Therefore, the contact between the connection electrodes 3 and the electrode terminal portions 5 can be stabilized.
[0129]
Subsequently, as shown in FIG. 1B, the semiconductor chip 1 and the circuit board 2 are held substantially parallel, and the connection electrodes 3 and the electrode terminal portions 5 are in contact with each other. The connection electrodes 3 and the electrode terminal portions 5 are electrically connected to each other by applying ultrasonic waves in a heated state and applying a predetermined load by using the ultrasonic application tool 7 or a stage (not shown) or a combination thereof. Connect to
[0130]
Specifically, in a state where the bonding portion between the semiconductor chip 1 and the circuit board 2 is heated to 100 ° C. to 150 ° C., ultrasonic waves of 40 kHz are applied by the ultrasonic wave application tool 7 to apply a number N to the bonding portion. A load of several tens of N is applied for about one second.
[0131]
Thus, the electrode terminals 5 of the semiconductor chip 1 and the connection electrodes 3 of the circuit board 2 are electrically connected with the plastic deformation of the connection electrodes 3 and the support members 4 provided on the circuit board 2. Connected to. At this time, by using substantially the same plastically deformable material, more preferably the same plastically deformable material (for example, the same material) for the connection electrodes 3 and the support members 4, the deformation amounts of both are made substantially the same. Therefore, it is possible to prevent poor connection due to the difference in the amount of deformation, and it is possible to improve the connection reliability between the connection electrode 3 and the electrode terminal portion 5.
[0132]
Next, as shown in FIG. 1C, an interface is formed in the gap between the semiconductor chip 1 and the circuit board 2 spanned by the connection electrodes 3 and the support 4 using a nozzle 9 from the side of the semiconductor chip 1. A liquid interface sealing resin material is injected as the sealing resin 8.
[0133]
At this time, as shown in FIG. 3, the center of the mounting area of the semiconductor chip 1 on the circuit board 2 corresponds to the electrode terminals 5 which are formed substantially linearly at the center of the element surface of the semiconductor chip 1. When the connection electrodes 3 are provided substantially linearly in the portion, the connection electrodes 3 are substantially parallel to the connection electrodes 3 along the arrangement direction of the connection electrodes 3 on the circuit board 2. When the supports 4 are formed on both sides of the electrode 3, the interface is formed in the gap from a direction substantially orthogonal to the arrangement direction of the electrode terminal portions 5 (that is, the arrangement direction of the connection electrodes 3). By injecting the liquid interfacial sealing resin material used for the encapsulating resin 8, the injectability of the interfacial sealing resin 8 can be improved.
[0134]
On the other hand, the connection is substantially linearly formed at the center of the mounting area of the semiconductor chip 1 on the circuit board 2 corresponding to the electrode terminals 5 formed substantially linearly at the center of the element surface of the semiconductor chip 1. In the case where the electrodes 3 are provided, the support is provided on the circuit board 2 substantially in parallel with the connection electrodes 3 along the arrangement direction of the connection electrodes 3 and on only one side of the connection electrodes 3. When the body 4 is formed, the other side of the connection electrode 3, that is, the side opposite to the side on which the support body 4 is formed, is opposite to the other side of the connection electrode 3. Alternatively, by injecting the interface sealing resin 8 from a direction substantially orthogonal to the arrangement direction of the electrode terminal portions 5 (that is, the arrangement direction of the connection electrodes 3), the injectability of the interface sealing resin 8 is increased. Can be improved.
[0135]
As described above, in the present embodiment, the solder resist (in this embodiment, the insulator layer 6 in the circuit board 2) is not used as a support (support member) of the semiconductor chip 1 as described in Patent Document 1. The solder resist opening 12 formed by the solder resist (insulator layer 6) can be set to be larger than the chip size of the semiconductor chip 1. Therefore, when the interface sealing resin 8 is injected into the gap between the semiconductor chip 1 and the circuit board 2 after the semiconductor chip 1 is mounted on the circuit board 2 as shown in FIG. The injection of the sealing resin 8 can be easily performed.
[0136]
Further, according to the present embodiment, after the semiconductor chip 1 and the circuit board 2 are joined as described above, the interface sealing resin 8 can be injected into a gap between the two. As shown in 1, when mounting the semiconductor chip on the circuit board, it is necessary to hold (press) the semiconductor chip with a heating and pressing tool for a certain period of time while curing the interface sealing resin in order to maintain the connection between them. There is no. For this reason, when the interface sealing resin 8 is cured, the tact time between the semiconductor chip 1 and the circuit board 2 can be reduced, that is, the time required for mounting (bonding and fixing) the semiconductor chip 1 can be reduced.
[0137]
In the present embodiment, as the interface sealing resin 8, for example, an epoxy resin which is a thermosetting resin is used. By curing the interface sealing resin 8, the semiconductor chip 1 is flip-chip mounted on the circuit board 2 as shown in FIG.
[0138]
[Embodiment 2]
Another embodiment according to the present invention will be described below with reference to FIGS. 5 (a) to 5 (c). Note that, for convenience of explanation, members having the same functions as those in the drawings described in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. The various features described in the first embodiment can be applied in combination with the present embodiment.
[0139]
5A to 5C are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the present embodiment, and FIG. 5D is a cross-sectional view of the semiconductor device according to the present embodiment. 1 shows a schematic configuration. FIG. 6 is a cross-sectional view schematically showing a configuration of a main part of the semiconductor device according to the present embodiment shown in FIG.
[0140]
In the first embodiment, a liquid thermosetting resin is used as the interface sealing resin for sealing the gap between the semiconductor chip 1 and the circuit board 2. On the other hand, in the present embodiment, an interface sealing resin 21 (anisotropic conductive resin film) made of an anisotropic conductive resin is used as the interface sealing resin.
[0141]
In the semiconductor device according to the present embodiment, as shown in FIG. 5C, the electrode terminal portions 5 on the semiconductor chip 1 and the connection electrodes 3 on the circuit board 2 are connected via the interface sealing resin 21. It has a flip-chip mounted structure.
[0142]
As shown in FIG. 6, the interface sealing resin 21 made of an anisotropic conductive resin is obtained by dispersing conductive particles 23 in a binder resin 22. In the interface sealing resin 21, for example, the conductive particles 23 are dispersed in a film-like epoxy resin, and only a predetermined conductive portion sandwiching the conductive particles 23 has a gap smaller than the particle size of the conductive particles 23. It has the property that a conductive state is obtained and the others are insulated.
[0143]
Therefore, the electrode terminals 5 are connected to the connection electrodes 3 via the interfacial sealing resin 21, so that the electrode terminals 5 and the connection electrodes 3 form the conductive particles 23. Electrically connected via the At this time, the electrode terminals 5 and the connection electrodes 3 are metal-bonded in a state where the conductive particles 23 are embedded like wedges in the joints between them. Further, at the time of thermocompression bonding, the film-like binder resin 22 melts and temporarily becomes a paste, which seals the gap between the semiconductor chip 1 and the circuit board 2 and connects them.
[0144]
Next, an example of a manufacturing process of the semiconductor device according to the present embodiment will be described below with reference to FIGS. 5 (a) to 5 (c) and FIG.
[0145]
First, as shown in FIG. 5A, a semiconductor chip 1 and a circuit board 2 used for manufacturing the semiconductor device are prepared in the same manner as in the first embodiment. However, in the present embodiment, as shown in FIG. 5A, before joining the semiconductor chip 1 and the circuit board 2, a film-shaped anisotropic material is previously applied to the element surface of the semiconductor chip 1. An interface sealing resin 21 (anisotropic conductive resin film) made of a conductive resin is pasted.
[0146]
Thus, in the present embodiment, the semiconductor chip 1 is flip-chip mounted on the circuit board 2 with the film-shaped interface sealing resin 21 adhered to the element surface of the semiconductor chip 1.
[0147]
The bonding (mounting) between the semiconductor chip 1 and the circuit board 2 is performed in a state where the film-shaped interface sealing resin 21 is attached to the element surface of the semiconductor chip 1 as shown in FIG. The electrode terminals 5 of the semiconductor chip 1 and the connection electrodes 3 of the circuit board 2 are aligned. Also in this embodiment, since the height of the support 4 is substantially the same as the height of the connection electrode 3, the semiconductor chip 1 and the circuit board 2 can be easily held substantially in parallel. Therefore, the contact between the connection electrodes 3 and the electrode terminal portions 5 can be stabilized.
[0148]
Subsequently, as shown in FIG. 5B, the semiconductor chip 1 and the circuit board 2 are held substantially in parallel, and the connection electrodes 3 and the electrode terminals 5 are in contact with each other. The connection electrodes 3 and the electrode terminals 5 are electrically connected to each other by applying ultrasonic waves in a heated state and applying a predetermined load by using the ultrasonic wave application tool 7 or a stage (not shown) or a combination thereof. Connection.
[0149]
However, in the present embodiment, the electric connection between the electrode terminal portions 5 and the connection electrodes 3 and the curing of the interfacial sealing resin 21 are promoted simultaneously with the connection between the electrode terminals 5 and the connection electrodes 3. In order to hold the joint, the joint is heated to 120 ° C. to 240 ° C., and ultrasonic waves of 40 kHz are applied by the ultrasonic application tool 7 to apply a load of several N to several tens of N to the joint for 3 seconds. Add about.
[0150]
As a result, the semiconductor chip 1 and the circuit board 2 are connected (joined) by the interface sealing resin 21, and the respective joints between the connection electrodes 3 and the support members 4 and the semiconductor chip 1. In FIG. 6, for example, as shown in FIG. 6, the conductive particles 23 in the interfacial sealing resin 21 are embedded like wedges in the joints (particularly, the connection electrodes 3 and the support members 4 in the joints). Are electrically connected with the plastic deformation of the connection electrodes 3 and the supports 4.
[0151]
As described above, in the present embodiment, the electrical connection between the semiconductor chip 1 and the circuit board 2 and the curing of the interface sealing resin 21 are promoted at the same time as the connection between the semiconductor chip 1 and the circuit board 2. And, in particular, a joint between the semiconductor chip 1 and the connection electrodes 3 and the supports 4. After the step, if necessary, the curing of the interface sealing resin 21 may be further advanced by using a heating means such as an oven. Thereby, as shown in FIG. 5D, the semiconductor chip 1 and the circuit board 2 can be flip-chip mounted.
[0152]
In the present embodiment, as in the first embodiment, the outermost layer of the electrode terminal portion 5 is usually formed of Al, Si, or Cu, but in order to ensure higher connection reliability. The surface of the electrode terminal portion 5 is made of a metal such as Ni, Cr, Ti, W, or Au, and the thickness of Au is preferably about 1 μm.
[0153]
As described above, in the present embodiment, the semiconductor chip 1 and the circuit board 2 are separated from each other by the conductive particles 23 added to the interface sealing resin 21 provided in the gap between them so as to have anisotropic conductivity. Are electrically connected in a state where they are mixed in the joints of the two, thereby improving the initial connection stability and connection reliability of the joints.
[0154]
Further, in the first embodiment, after the semiconductor chip 1 and the circuit board 2 are electrically connected, a liquid interface sealing resin 8 is injected into a gap between the semiconductor chips 1 and cured to perform flip chip mounting. However, in the present embodiment, since the film-shaped interface sealing resin 21 is attached to the element surface of the semiconductor chip 1 in advance, the electrical connection and the interface between the electrode terminal portions 5 and the connection electrodes 3 are performed. Since the curing of the sealing resin 21 can proceed simultaneously, the time required for mounting (bonding and fixing) the semiconductor chip 1 can be reduced.
[0155]
In general, when the interface sealing resin is injected from a direction perpendicular to the arrangement of the electrode terminal portions of the semiconductor chip (direction of the side surface), misalignment of the semiconductor chip in the side direction becomes a problem, and an apparatus having high positioning accuracy is required. However, by mounting the semiconductor chip 1 in a state where the film-shaped anisotropic conductive resin is adhered to the element surface of the semiconductor chip 1 as described above, Since there is a margin in the alignment accuracy and the problem of misalignment in the lateral direction of the semiconductor device is not caused, a more inexpensive configuration can be achieved.
[0156]
[Embodiment 3]
Another embodiment according to the present invention will be described below with reference to FIGS. 7 (a) to 7 (d). For convenience of description, members having the same functions as those in the drawings described in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted. The various features described in the first and second embodiments can be applied in combination with the present embodiment.
[0157]
7A to 7D are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the present embodiment. FIG. 7D is a cross-sectional view of the semiconductor device according to the present embodiment. 1 shows a schematic configuration.
[0158]
As shown in FIG. 7A, the circuit board 2 used in the present embodiment includes a circuit board 2 and a semiconductor on the outermost layers of the connection electrodes 3 and the support members 4 shown in the first and second embodiments. It has a configuration in which a bonding layer 31 or a bonding layer 32 for connecting (bonding) to the chip 1 is provided.
[0159]
That is, the circuit board 2 used in the present embodiment has the connection electrodes 3 and the support 4 shown in the first and second embodiments as the connection electrodes and the support, in which the semiconductor chip 1 and the circuit board 2 are installed. Bonding layers 31 and 32 for connecting (joining) the semiconductor chip 1 and the circuit board 2 to the supporting layer by plastically deforming the semiconductor chip 1 under the mounting (joining) conditions. Is provided with a connection electrode 33 (connection electrode terminal portion) having a laminated structure in which is formed and a support.
[0160]
For example, the connection electrode 33 and the support 34 are formed on the first conductive layer (the connection electrode 3 or the support 4) as the support layer, as the bonding layer 31 or the bonding layer 32, as the first conductive layer and the electrode terminal. It has a configuration in which a second conductive layer made of a material softer than the part 5 is provided.
[0161]
For the bonding layers 31 and 32, for example, a connection material made of a conductive material such as Sn or a solder material containing Sn is used. However, the conductive material (connecting material) is not limited thereto, and a conductive adhesive such as a conductive paste containing Ag or plated resin particles (conductive particles) may be used.
[0162]
The bonding layers 31 and 32 can be easily formed by, for example, applying or dropping the connection material on the first conductive layer (connection electrode 3 or support 4). In addition, the bonding layers 31 and 32 are formed such that the area of the bonding layers 31 and 32, that is, the area of the contact surface between the bonding layers 31 and 32 and the semiconductor chip 1 is larger than the area of the first conductive layer. Can be provided.
[0163]
The outermost layer of the electrode terminal portion 5 of the semiconductor chip 1 is usually made of Al, Si or Cu, but is not limited to the case where the joining layers 31 and 32 are made of a solder material, such as Ni, Cr or Ti. It may be made of a metal used as a barrier metal or an under bump metal, such as W or W.
[0164]
In this embodiment, as shown in FIG. 7A, the circuit board 2 and the semiconductor chip 1 are connected (joined) to the circuit board 2 on the outermost layer as described above, as connection electrodes and a support. 7B to 7D, except that a connection electrode 33 having a bonding layer 31 or a bonding layer 32 and a support 34 are formed. Through a similar mounting process, a semiconductor device is manufactured.
[0165]
Also in the present embodiment, the support layer (first conductive layer) in the support body 34 is provided on the circuit board 2 in the same manner as in the first embodiment. 20 and the like can be produced simultaneously when they are formed by etching or the like. Further, the bonding layer 31 and the bonding layer 32 can also be formed of the same material at the same time.
[0166]
Further, as in the first embodiment, also in this embodiment, as shown in FIG. 7B, the connection electrodes 33 and the electrode terminals 5 are aligned, and the semiconductor chip 1 and the circuit board 2 are aligned. Are held substantially parallel to each other, and the semiconductor chip 1 and the circuit are operated by the ultrasonic wave application tool 7 or a stage (not shown) or a combination thereof in a state where the connection electrodes 33 are in contact with the electrode terminals 5. By heating the joint with the substrate 2 to 100 ° C. to 150 ° C., applying ultrasonic waves of 40 kHz by the ultrasonic wave application tool 7 and applying a load of several N to several tens of N to the joint for about 1 second, The connection electrodes 33 and the support 34 can be stably bonded to the semiconductor chip 1. At this time, if solder is used, stronger metal bonding can be performed.
[0167]
Also in the present embodiment, a liquid interface sealing resin 8 is used as the interface interface sealing resin for sealing the gap between the semiconductor chip 1 and the circuit board 2, and the interface sealing to the gap is performed. The resin 8 was injected from the side of the semiconductor chip 1. Further, as the interface sealing resin 8, an epoxy resin which is a thermosetting resin was used.
[0168]
As described above, in this embodiment, the connection electrode 33 and the support 34 having the bonding layers 31 and 32 are used as the connection electrode and the support.
[0169]
In the method of pressing using an ultrasonic wave in flip-chip mounting, generally, the metal formed on the outermost layer of the electrode terminal portion 5 undergoes plastic flow by applying ultrasonic vibration simultaneously with constant pressing. Occurs. This plastic flow is accompanied by a wave flow caused by ultrasonic vibration at the same time as the deformation of the metal, so that the oxide film at the metal interface between the electrode terminal portion 5 and the connection electrode 3 is destroyed, and the joining occurs due to the contact of the new surface. Occurs. However, in this ultrasonic connection, welding occurs not in the center of pressure but in a donut shape around the center.
[0170]
Therefore, in the first embodiment, the bonding is strengthened by using the liquid interface sealing resin 8, but in the present embodiment, the connection electrode 3 and the support 4 are further formed of the conductive material. By providing the bonding layers 31 and 32, stronger metal bonding is enabled.
[0171]
[Embodiment 4]
Another embodiment according to the present invention will be described below with reference to FIGS. 8 (a) to 8 (d). For convenience of explanation, members having the same functions as those in the drawings described in the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted. In addition, the various features described in the first to third embodiments can be applied in combination with the present embodiment.
[0172]
8A to 8D are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device according to the present embodiment. FIG. 8D is a cross-sectional view of the semiconductor device according to the present embodiment. 1 shows a schematic configuration.
[0173]
In this embodiment, the surface of the semiconductor chip on which the electrode terminals are formed is referred to as the front surface, and the surface of the semiconductor chip on which the electrode terminals are not formed is referred to as the back surface.
[0174]
The semiconductor device according to the present embodiment is different from the second embodiment in that the interface sealing resin 47 made of a film-like insulating resin is used instead of the film-like anisotropic conductive resin in which the conductive particles 23 are dispersed. And a configuration in which a plurality of semiconductor chips are stacked on each other in the thickness direction of each semiconductor chip.
[0175]
In the semiconductor device according to the present embodiment, as shown in FIGS. 8C and 8D, a first semiconductor chip 41 (bare chip) having a center pad is provided on a circuit board 43 by the first semiconductor chip. (First connection electrode, connection electrode terminal portion) and support members 4 which are flip-chip-mounted by the connection electrodes 3 (first connection electrode, connection electrode terminal portion) provided so as to correspond to the electrode terminal portions 5 provided in 41. With the back surface of the second semiconductor chip 42 attached to the back surface of the flip-chip mounted first semiconductor chip 41, the second semiconductor chip 42 is connected to the circuit board 43 by thin metal wires 45. (Second connection electrodes, connection electrode terminal portions) provided in the solder resist opening 12 of the first embodiment.
[0176]
The first semiconductor chip 41 has, for example, the same configuration as the semiconductor chip 1 described in the first to third embodiments. In addition, the circuit board 43 is provided with the connection pads 46... Provided along the solder resist opening 12 outside the semiconductor chip formation region in the solder resist opening 12 in the circuit board 43. For example, it has a configuration similar to that of the circuit board 2 described in the first or second embodiment.
[0177]
The type and size of the second semiconductor chip 42 constituting the semiconductor device are not particularly limited, and any type can be used.
[0178]
The second semiconductor chip 42 is wire-bonded between the electrode terminals 44 provided on the element surface of the second semiconductor chip 42 and the connection pads 46 with the thin metal wires 45. It is electrically connected to the circuit board 43. The element surface of the second semiconductor chip 42 is provided with an insulating film 50 for covering the element surface except for the electrode terminal portions 44 and for planarizing the element surface. In the present embodiment, an example will be described in which the electrode terminal portions 44 composed of planar electrodes (electrode pads) are provided along the edge (end) of the second semiconductor chip 42. However, the present invention is not limited to this.
[0179]
The materials of the electrode terminal portions 5 and 44 are the same as the materials of the wiring 20, the connection electrode 3, and the support 4, as described in the first to third embodiments. The materials commonly used for the above can be used. Specifically, the metal materials described in Embodiment Modes 1 to 3 and the like can be used.
[0180]
The gap between the first semiconductor chip 41 and the circuit board 43 is sealed with an interface sealing resin 47 made of the insulating resin (first insulating resin). On the circuit board 43, the semiconductor chip mounting surface of the circuit board 43 (that is, the mounting surface of the semiconductor device) is sealed (covered) together with the first semiconductor chip 41 and the second semiconductor chip 42. A sealing resin layer 49 made of a sealing resin (second insulating resin) is provided. Thereby, the thin metal wires 45 connecting the second semiconductor chip 42 and the connection pads 46 of the circuit board 43 are protected by the sealing resin layer 49 covering the mounting surface of the semiconductor device.
[0181]
An insulating layer 10 (insulating member) is provided on the surface (second surface) of the circuit board 43 opposite to the semiconductor chip mounting surface (first surface), similarly to the circuit board 2. In addition, an external input / output terminal 53 such as a solder ball is provided. The external input / output terminal 53 is connected to the wiring 20 provided on the semiconductor chip mounting surface of the circuit board 43 through a through hole 52 penetrating the circuit board 43 and the insulator layer 10 covering the second surface of the circuit board 43. Is electrically connected to
[0182]
Next, an example of a manufacturing process of the semiconductor device according to the present embodiment will be described below with reference to FIGS.
[0183]
First, as shown in FIG. 8A, a first semiconductor chip 41 and a circuit board used for manufacturing the semiconductor device in the same manner as the semiconductor chip 1 and the circuit board 2 described in the first to third embodiments, for example. Prepare 43. However, in the present embodiment, as shown in FIG. 8A, before the first semiconductor chip 41 and the circuit board 43 are joined, the elements of the first semiconductor chip 41 are previously determined. An interface sealing resin 47 (insulating resin film) made of a film-like insulating resin is pasted on the surface.
[0184]
Also, in the solder resist opening 12 in the circuit board 43, as in the first embodiment, in the mounting target area of the first semiconductor chip 41, in the electrode terminal portions 5 of the first semiconductor chip 41, etc. Corresponding connection electrodes 3 and a support 4 having substantially the same height (thickness) as the connection electrodes 3 are formed, and the first semiconductor chip 41 is mounted outside the mounting area of the first semiconductor chip 41. The connection pads 46 to be connected to the electrode terminals 44 in the second semiconductor chip 42 (see FIG. 8C) stacked on the base 41 are formed.
[0185]
Like the support 4, the connection pads 46 can also be formed simultaneously with the formation of the connection electrodes 3, the wiring 20, and the like on the circuit board 43 by etching or the like.
[0186]
The bonding (mounting) between the first semiconductor chip 41 and the circuit board 43 is performed by the same step (method) as the bonding (mounting) step (method) between the semiconductor chip 1 and the circuit board 2 in the second embodiment. It can be carried out.
[0187]
That is, the bonding (mounting) of the first semiconductor chip 41 and the circuit board 43 is performed by bonding the film-shaped interface sealing resin to the element surface of the first semiconductor chip 41 as shown in FIG. The electrode terminals 5 of the first semiconductor chip 41 are aligned with the connection electrodes 3 of the circuit board 43 in a state in which the first semiconductor chip 41 is adhered, and the first semiconductor chip 41 and the circuit board 43 are substantially aligned. With the connection electrodes 3 and the electrode terminals 5 in contact with each other and in parallel with each other, the first semiconductor chip is heated by the ultrasonic wave application tool 7 or a stage (not shown) or a combination thereof. This is performed by applying an ultrasonic wave to a joint portion between the circuit board 41 and the circuit board 43 to apply a predetermined load.
[0188]
Also in the present embodiment, since the height of the support 4 is substantially the same as the height of the connection electrode 3, the first semiconductor chip 41 and the circuit board 43 can be easily held substantially in parallel. And the contact between the connection electrodes 3 and the electrode terminal portions 5 can be stabilized.
[0189]
Next, as shown in FIG. 8C, the second semiconductor chip 42 prepared in advance is provided on the back surface of the first semiconductor chip 41 connected by flip chip bonding via an adhesive layer 48. Paste the back.
[0190]
As the adhesive used for the adhesive layer 48, for example, a liquid adhesive, a sheet-like adhesive, or the like can be used. The type of the adhesive is not limited as long as the adhesive can uniformly adhere the back surface of the first semiconductor chip 41 and the back surface of the second semiconductor chip 42 over the entire area.
[0191]
Subsequently, the electrode terminal portions 44 provided on the surface of the second semiconductor chip 42 are electrically connected to the connection pads 46 provided on the circuit board 43 by thin metal wires 45. The material of the thin metal wire 45 is not particularly limited, but Al and Au are preferable.
[0192]
The method of electrically connecting the electrode terminal portions 44 and the connection pads 46 to the thin metal wires 45 is as follows. (1) Heat and pressure are applied to the connection portion to cause plastic deformation at the boundary surface to connect the two. A wire bonding method using thermocompression bonding (thermocompression wire bonding method), which promotes oxide film collapse and surface activation in the part and connects the two by forming an intermetallic compound by diffusion bonding between the two metals; (2) Ultrasonic wire bonding method using ultrasonic wave (ultrasonic wire bonding method), which solid-state welds the connection part by applying pressure and applying ultrasonic wave, and (3) thermocompression wire bonding method using ultrasonic wave together Wire bonding method (ultrasonic combined thermo-compression wire bonding method) and the like, but are not particularly limited.
[0193]
The order of wire bonding between the electrode terminal portions 44 and the connection pads 46 and the fine metal wires 45, that is, the order of wire bonding between the second semiconductor chip 42 and the circuit board 43 and the fine metal wires 45 is not particularly limited. After connecting the circuit board and the thin metal wire, the so-called reverse wire bonding method of connecting the semiconductor chip and the thin metal wire is compared with the so-called forward wire bonding method of connecting the reverse wire bonding method in the reverse order. This is more preferable because the height of the thin metal wire can be reduced and the semiconductor device can be further reduced in thickness.
[0194]
In the case of performing the reverse wire bonding method, a gold bump is formed on an electrode terminal provided on a semiconductor chip, and first, a thin metal wire is connected to a circuit board, and thereafter, a thin metal wire is connected to the gold bump. I do.
[0195]
However, the method of connecting the electrode terminal portion 44 and the connection pad 46 is not limited to the above method.
[0196]
Next, as shown in FIG. 8C, the connection between the electrode terminal portion 44 and the thin metal wire 45 is protected by an insulating film 51, and then, as shown in FIG. The entire surface of the semiconductor chip mounting surface 43 is covered with a sealing resin (second insulating resin), and the thin metal wires 45 are protected by a sealing resin layer 49 made of the sealing resin.
[0197]
In the present embodiment, the sealing resin layer 49 is formed of an epoxy resin by using a transfer molding method in which a solid thermosetting resin is heated and melted, transferred into a mold, filled, and cured.
[0198]
However, the method of forming the sealing resin layer 49 is not limited to this. For example, a potting method in which a suitable amount of liquid resin in a syringe or the like is dropped with a dispenser or the like, and then the resin is heated and cured to seal. Any method, such as a casting method of injecting a liquid resin into the package, can be applied. Also, the type of the sealing resin is not limited to the epoxy resin, and any thermosetting resin can be used.
[0199]
Finally, as shown in FIG. 8D, solder balls are formed as external input / output terminals 53 on the back surface of the circuit board 43. It should be noted that the type of the external input / output terminal 53 is not particularly limited, and any type can be used.
[0200]
In the present embodiment, one second semiconductor chip 42 is attached to the back surface of the flip-chip connected first semiconductor chip 41, but the number of stacked semiconductor chips is not limited to this. It is not a thing and can be any number.
[0201]
When a plurality of semiconductor chips are attached to the back surface of the first semiconductor chip 41, for example, the electrode terminal portions 44 of the second semiconductor chip 42 and the electrode terminal portions of the third semiconductor chip are arranged to face each other. A common signal may be used by wire bonding, or a third semiconductor chip smaller than the second semiconductor chip 42 may not be in contact with the electrode terminal portion 44 of the second semiconductor chip 42. As described above, the semiconductor chip may be stacked on the second semiconductor chip 42, and the semiconductor chip can be stacked in the same manner as a conventionally known stacked semiconductor device (semiconductor device package).
[0202]
By stacking a plurality of semiconductor chips on the circuit board in this manner, a semiconductor device with a high mounting density of semiconductor chips can be realized.
[0203]
In this embodiment, an insulating resin is used as the interface sealing resin 47. However, the interface sealing resin 47 is not limited to this, and may be used in the first to third embodiments. The same interface sealing resin as the above-mentioned interface sealing resin can be used. Although the film-shaped interface sealing resin is used as the interface sealing resin 47, the interface sealing resin may be a liquid as shown in the first and third embodiments. , And may be in the form of a paste.
[0204]
Furthermore, in each of the above embodiments, as an example of a joining method involving plastic deformation of an electrode, a case where ultrasonic joining is used has been described.However, the present invention is not limited to this. Any of ultrasonic waves, heat, and pressure, or a combination thereof, and applying (applying) at least one of ultrasonic waves, heat, and pressure to the junction between the semiconductor chip and the circuit board to form a projection. The semiconductor chip and the circuit board can be joined by plastic deformation of the electrode terminal portion and the support formed on the substrate.
[0205]
In addition, the bonding conditions are set so that the electrode material is plastically deformed at the bonding portion with the semiconductor chip according to the electrode material (the material of the connection electrode and the support in the above embodiments). May be set as appropriate. In other words, the electrodes may be formed of a material that is plastically deformed under the above-described joining conditions.
[0206]
When ultrasonic waves are used for the above-described bonding, metal bonding can be performed in a short time, and productivity and connection reliability can be further improved.
[0207]
Further, in each of the above-described embodiments, the case where the semiconductor chip and the circuit board are joined by plastically deforming the electrode terminal portion using ultrasonic waves has been described as an example, but the present invention is not limited thereto. The present invention is also applicable to the case where the electrode terminal portion of the semiconductor chip and the electrode terminal portion for connection are press-contacted and electrically connected, and the semiconductor chip and the circuit board are fixed with an interface sealing resin. Can be.
[0208]
Specifically, for example, in the second embodiment, the bonding conditions were changed, that is, the semiconductor chip 1 and the circuit board 2 were aligned with each other by using a heating / pressing tool instead of the ultrasonic wave application tool 7. In this state, the interface sealing resin 21 (anisotropically conductive resin film) made of anisotropically conductive resin is cured by holding the circuit board 2 on which the semiconductor chip 1 is mounted for a certain period of time by the heating and pressing tool. Thereby, the electrode terminals 5 of the semiconductor chip 1 and the connection electrodes 3 of the circuit board 2 can be electrically connected by pressure welding. In this case, in the second embodiment, instead of the interface sealing resin 21, an interface sealing resin made of a paste-like anisotropic conductive resin, or a film-like or paste-like insulating resin is used. Needless to say, it is good.
[0209]
When the semiconductor chip 1 is flip-chip mounted and the electrode terminals are joined together with plastic deformation using ultrasonic waves or the like, the material of the support 4 is at least on the outermost layer, for example, in the above-described embodiment. As described in Embodiments 1 to 4, a material that plastically deforms under the flip chip mounting condition of the semiconductor chip 1 is used. The electrode terminal portions 5 of the semiconductor chip 1 and the connection electrodes 3 of the circuit board 2 are joined by pressure welding. In this case, the support 4 may be made of any material that can support the semiconductor chip 1 substantially in parallel with the circuit board 2.
[0210]
In this case, as the material of the support 4, any material that does not plastically deform under the joining conditions by pressure welding may be used, and the same materials as those in the first to fourth embodiments can be used.
[0211]
Also in the case where the electrode terminal portion 5 of the semiconductor chip 1 and the connection electrode 3 of the circuit board 2 are joined by pressure welding, among the materials of the support 4, particularly preferable materials are the above-mentioned materials because of ease of control. From the viewpoint, the material is the same as that of the connection electrode 3, and among them, the height (thickness) of the support 4 is particularly easy to control, and the connection electrode 3 and the electrode terminal portion 5 are firmly bonded by metal bonding. Most preferably, it is a metal material because it can be stably bonded in a short time.
[0212]
As described above, in the method for manufacturing a semiconductor device according to one embodiment of the present invention, a semiconductor chip provided with an electrode terminal portion in the center of an element formation surface is formed by using the electrode terminal portion with the semiconductor chip. A semiconductor device which is flip-chip mounted in a state of being bridged over connection electrode terminals of a circuit board provided with an insulator layer on the surface thereof, wherein the semiconductor chip of the circuit board is provided on the surface of the circuit board. Forming an insulating layer having an opening larger than the element forming surface of the semiconductor chip in the flip-chip mounting target region, and forming one of the electrode terminals for connection and the electrode terminals of the semiconductor chip; Are formed in the shape of a protrusion, and the electrode terminal portion formed in the shape of a protrusion is formed on the surface of one of the semiconductor chip and the circuit board facing the other. A support having the same height and supporting the semiconductor chip and the circuit board substantially in parallel is formed, and the insulator layer on the circuit board is formed by the electrode terminal portions and the support formed in a protruding shape. And the flip-chip mounting method in which the semiconductor chip and the circuit board are supported substantially in parallel in the opening.
[0213]
More specifically, an insulating layer having an opening larger than an element forming surface of the semiconductor chip is formed on a surface of the circuit board in a flip-chip mounting area of the semiconductor chip on the circuit board, and One of the electrode terminal portion and the electrode terminal portion of the semiconductor chip is formed in a protruding shape, and the one of the semiconductor chip and the circuit board is formed in a protruding shape on a surface facing the other. And at least the outermost layer is plastically deformed under the bonding condition with the connecting electrode terminal part by flip-chip mounting of the semiconductor chip, and is deformed by the plastic deformation. The supporting member is made of substantially the same material as the electrode terminal portion formed in the shape of a projection, and supports the semiconductor chip and the circuit board substantially in parallel. The semiconductor chip and the circuit board are supported substantially in parallel in the opening of the insulator layer in the circuit board by the electrode terminal portions and the support formed in the shape of a protrusion, and are formed in a projecting shape. A method of plastically deforming the electrode terminal portion and the support to join the semiconductor chip and the circuit board.
[0214]
The method of manufacturing a semiconductor device may further include forming an insulator layer having an opening larger than an element formation surface of the semiconductor chip in a region of the circuit board where a flip chip is to be mounted on the circuit board surface. Forming one of the electrode terminal portions for connection and the electrode terminal portion of the semiconductor chip in a protruding shape, and, on the surface facing one of the semiconductor chip and the circuit board facing the other, A support having substantially the same height as the protruding electrode terminal portion and supporting the element formation surface of the semiconductor chip and the circuit board surface substantially in parallel was formed. In the state where the semiconductor chip and the circuit board are supported substantially in parallel in the state of being erected within the opening of the insulator layer in the circuit board by the electrode terminal portion and the support, The gap between the semiconductor chip and the circuit board is sealed by an interfacial sealing resin may be a method for pressing the electrode terminal portions of the connection electrode terminal portion and the semiconductor chip.
[0215]
Further, in the method of manufacturing a semiconductor device, the semiconductor chip including a plurality of electrodes (electrode terminal portions) formed at the center of the element formation surface has a first surface and a second surface, Is a method for manufacturing a semiconductor device mounted on a circuit board having a support formed on the first surface, wherein the semiconductor device is formed around connection pads (connection electrode terminal portions) of the circuit board. A plurality of electrodes formed near the center of an element forming surface of the semiconductor chip in a state where the semiconductor chip is substantially parallel to the circuit board by the support, and a first surface of the circuit board. In addition, a plurality of connection pads having projections arranged respectively corresponding to the plurality of electrodes of the semiconductor chip, ultrasonic, heat, pressure, or by using a combination thereof, directly or through a member, Electrically connecting; Element formation surface of the serial semiconductor chip and the step of injecting the interfacial sealing resin in a gap between the circuit board may be a method including the step of curing the interfacial sealing resin.
[0216]
Further, in the method of manufacturing a semiconductor device, the semiconductor chip including a plurality of electrodes (electrode terminal portions) formed at the center of the element formation surface has a first surface and a second surface, and the semiconductor chip has A method of manufacturing a semiconductor device mounted on a circuit board having a support formed on the first surface, the support being formed around connection pads (connection electrode terminal portions) of the circuit board. A step of disposing an interface sealing resin sheet or an interface sealing resin paste on the semiconductor chip or the circuit board in a state where the semiconductor chip is substantially parallel to the circuit board, and A plurality of electrodes formed at a central portion of an element formation surface of the semiconductor chip; and a plurality of connection pads having projections arranged on the first surface of the circuit board, respectively, corresponding to the plurality of electrodes of the semiconductor chip. And the super Wave, heat, pressure or any combination thereof, directly or through a member, at the same time as electrically connecting, simultaneously curing the interfacial sealing resin, or at least a step to start, and, if necessary And accelerating the curing of the interfacial sealing resin in an oven or the like.
[0219]
Furthermore, the method of manufacturing a semiconductor device may further include a plurality of connection pads having protrusions disposed on the first surface of the circuit board so as to respectively correspond to a plurality of electrodes (electrode terminal portions) of the semiconductor chip. The connection electrode terminal portion) may be formed by an etching or plating step, and at the same time, a support may be formed by the same step.
[0218]
Further, in the method of manufacturing a semiconductor device, the resin provided in the gap between the element formation surface of the semiconductor chip and the circuit board has anisotropic conductivity, and the support formed around the connection pad of the circuit board The plurality of electrodes (electrode terminal portions) formed at the center of the element formation surface of the semiconductor chip are arranged in a state where the semiconductor chip is substantially parallel to the circuit board by the body. A plurality of connection pads (connection electrode terminal portions) having projections respectively arranged corresponding to the plurality of electrodes of the semiconductor chip are always applied to one surface with ultrasonic waves, and any one of heat and pressure is applied. Alternatively, a method may be used that includes, or at least starting, the step of curing the interfacial sealing resin at the same time as the electrical connection by the combination of the two.
[0219]
Further, in the method of manufacturing a semiconductor device, a conductive pad is formed on a first surface of the circuit board and a conductive material is formed on an outermost layer of a support. A plurality of semiconductor chips formed in a central portion of an element forming surface of the semiconductor chip in a state where the semiconductor chip is substantially parallel to the circuit board by a support formed around connection pads of the circuit board; (Electrode terminal portions) and a plurality of connection pads having projections arranged on the first surface of the circuit board in correspondence with the plurality of electrodes of the semiconductor chip, respectively. The method may include a step of performing, or at least starting, the curing of the interfacial sealing resin at the same time as making the electrical connection by any one of heat, pressure, or a combination thereof.
[0220]
Further, the semiconductor device according to one embodiment of the present invention can have, for example, the following configuration.
[0221]
For example, in the semiconductor device, the semiconductor chip includes a plurality of electrodes (electrode terminal portions) formed in the center of the element formation surface, has a first surface and a second surface, and both have a surface layer. A circuit board on which the semiconductor chip is mounted, on which an insulator layer is formed, wherein the circuit board has, on the first surface, a plurality of protrusions arranged corresponding to a plurality of electrodes of the semiconductor chip, respectively; A connection pad (connection electrode terminal portion), a support substantially at the same height as the connection pad, formed around the connection pad, and a plurality of external input / output terminals electrically connected to the connection pad Wherein the insulator layer has at least an opening portion larger than the semiconductor chip, and a resin provided in a gap between an element surface of the semiconductor device and the circuit board; and an electrode of the semiconductor chip, Board connection The head in flip-chip method, directly or through a member may have a structure for electrically connecting.
[0222]
In the case where the plurality of electrodes (electrode terminal portions) formed at the center of the element formation surface are formed in a substantially linear shape, the support may be a linear connection pad corresponding to the electrode. The configuration may be such that it is arranged on one side or both sides of the (connection electrode terminal section).
[0223]
Further, in the semiconductor device, at least one or more semiconductor chips are stacked on a back surface of the flip-chip-connected semiconductor chip, and electrodes (electrode terminal portions) of the stacked semiconductor chips are formed on the circuit board. Connection pads (connection electrode terminal portions) arranged outside the semiconductor chip are connected by thin metal wires, respectively, and the surface of the circuit board on which the semiconductor chip is mounted is covered with a sealing resin. There may be.
[0224]
Further, in each of the above-described embodiments, the case where the electrode having the protrusion structure (the connection electrode in each of the above-described embodiments) and the support are both formed on the circuit board has been described as an example. The present invention is not limited to this, and the electrode having the protruding structure and the support are formed together on the semiconductor chip by using, for example, wiring formed on the element formation surface of the semiconductor chip. The configuration may be such that the electrode having the protruding structure and the support are separately provided on the circuit board and the semiconductor chip.
[0225]
However, it is preferable that the electrode having the protruding structure and the support are provided on one of the circuit board and the semiconductor chip to control the height of both, that is, in order to match the height of both, Both the electrode having the protruding structure and the support are provided on the circuit board side, and using the wiring on the circuit board, for example, using the same material as the wiring and the electrode having the protruding structure and the support at the same time Can be formed, the thickness can be easily controlled, and the electrode having the protrusion structure and the support can be formed inexpensively and accurately.
[0226]
The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
[0227]
【The invention's effect】
As described above, in the semiconductor device according to the present invention, the semiconductor chip provided with the electrode terminal portion at the center portion of the element forming surface is mounted on the connection electrode terminal portion of the circuit board at the electrode terminal portion. In the semiconductor device, which is flip-chip mounted, the circuit board is larger than the semiconductor chip, and an insulating layer is provided on a surface of the semiconductor device. One of the electrode terminal portions is formed in a protruding shape, and the insulator layer on the surface of the circuit board has an opening larger than the element forming surface of the semiconductor chip, and the semiconductor chip and the circuit are formed in the opening. The substrate and the circuit board are flip-chip mounted, and the gap between the semiconductor chip and the circuit board has substantially the same height as the protruding electrode terminal portion. Is configured to support substantially parallel to the support is provided with a circuit board and.
[0228]
According to the above configuration, the insulator layer has an opening larger than the element formation surface of the semiconductor chip, and the semiconductor chip is connected to the semiconductor chip in a state where the insulator layer and the semiconductor chip are not in contact with each other. Since it is flip-chip mounted on the electrode terminal part for use, the formation of the support and the electrode terminal part having a protruding shape is not restricted by the insulator layer, and the support is separate from the insulator layer. Since it is provided, when forming the support, the degree of freedom in selecting a material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. Therefore, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion is flip-chip mounted on a circuit board as described above, the element formation surface of the semiconductor chip and the circuit board While substantially parallel to the support, it can be stably fixed. Therefore, according to the above configuration, it is possible to prevent a connection failure between the semiconductor chip and the circuit board and to provide a semiconductor device having high connection reliability.
[0229]
As described above, the semiconductor device according to the present invention has a configuration in which the support is made of the same material as the electrode terminal portions formed in a protruding shape.
[0230]
According to the above configuration, since the support is made of the same material as the electrode terminal portion formed in a protruding shape, the heights of the two can be easily matched by the existing technology. For this reason, there is an effect that a semiconductor device with higher connection reliability can be provided.
[0231]
As described above, the semiconductor device according to the present invention has a configuration in which the support is made of metal.
[0232]
The metal material has a particularly rich technique of etching the thickness, and the thickness can be easily controlled. Therefore, since the support is made of metal, the reliability of the electrical connection is affected. It is possible to prevent variations in the height direction and control the thickness more strictly and easily. Therefore, according to the above configuration, it is possible to provide a semiconductor device having higher connection reliability.
[0233]
As described above, the semiconductor device according to the present invention has a configuration in which the semiconductor chip and the circuit board are joined by plastic deformation of the protruding electrode terminal portion and the support.
[0234]
According to the above configuration, even when performing bonding involving plastic deformation of the electrode terminals, such as ultrasonic bonding, when performing flip-chip mounting of the semiconductor chip, the semiconductor chip is parallel to the circuit board. Can be firmly connected by plastic deformation, there is no misalignment between the semiconductor chip and the circuit board, poor connection is prevented, and a semiconductor device with high connection reliability can be provided. Play.
[0235]
As described above, the semiconductor device according to the present invention has a configuration in which the semiconductor chip and the circuit board are further fixed by an interface sealing resin that seals a gap between the semiconductor chip and the circuit board.
[0236]
According to the above configuration, the gap between the semiconductor chip and the circuit board is further fixed by the interfacial sealing resin, so that the joining between them can be made stronger and more stable.
[0237]
As described above, in the semiconductor device according to the present invention, the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip are press-contacted in a state of being bridged, and the semiconductor chip and the circuit board are in contact with the semiconductor chip and the circuit. This is a configuration in which it is fixed by an interface sealing resin that seals a gap with the substrate.
[0238]
According to the above configuration, the insulator layer has an opening larger than the element formation surface of the semiconductor chip, and the semiconductor chip is connected to the semiconductor chip in a state where the insulator layer and the semiconductor chip are not in contact with each other. Since it is flip-chip mounted on the electrode terminal part for use, the formation of the support and the electrode terminal part having a protruding shape is not restricted by the insulator layer, and the support is separate from the insulator layer. Since it is provided, when forming the support, the degree of freedom in selecting a material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. It becomes. Therefore, even when the electrode terminals of the semiconductor chip and the electrode terminals for connection are brought into pressure contact and electrically connected as described above, and the semiconductor chip and the circuit board are fixed to each other with an interface sealing resin, When flip-chip mounting a semiconductor chip having an electrode terminal portion called a center pad in the center portion on a circuit board as described above, with the element forming surface of the semiconductor chip and the circuit board supported substantially in parallel, Can be fixed stably. Therefore, according to the above configuration, it is possible to prevent a connection failure between the semiconductor chip and the circuit board and to provide a semiconductor device having high connection reliability.
[0239]
As described above, the semiconductor device according to the present invention has a configuration in which the contact area between the support and the semiconductor chip is larger than the contact area between the protruding electrode terminal portion and the semiconductor chip.
[0240]
According to the above configuration, the contact area between the support and the semiconductor chip is made larger than the contact area between the electrode terminal portion formed in a projection shape and the semiconductor chip. This has the effect of reducing the damage caused by hitting the element formation surface.
[0241]
As described above, in the semiconductor device according to the present invention, at least one semiconductor chip is stacked on the surface of the semiconductor chip opposite to the element formation surface, and the electrode terminal portion of the stacked semiconductor chip and the circuit A connection electrode terminal portion provided inside the opening of the insulator layer in the substrate and outside the flip chip mounting region of the semiconductor chip is electrically connected by a thin metal wire.
[0242]
According to the above configuration, the number of semiconductor chips mounted on one semiconductor device increases, and a semiconductor device having a higher mounting density of the semiconductor chips can be realized.
[0243]
The method for manufacturing a semiconductor device according to the present invention is, as described above, a semiconductor chip provided with an electrode terminal portion in the center of the element formation surface, the electrode terminal portion is larger than the semiconductor chip, and In a method of manufacturing a semiconductor device, which is flip-chip mounted in a state of being erected on connection electrode terminals of a circuit board provided with an insulator layer on a surface thereof, a method of mounting the semiconductor chip in the circuit board on the surface of the circuit board, Forming an insulator layer having an opening larger than the element forming surface of the semiconductor chip in the region, and forming one of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip in a projecting shape; And at least one of the semiconductor chip and the circuit board has a height substantially equal to the height of the protruding electrode terminal portion on a surface facing the other. Forming a support for supporting the semiconductor chip and the circuit board substantially parallel to each other, and forming the semiconductor in the opening of the insulator layer in the circuit board by the electrode terminal portion and the support formed in a protruding shape. In this method, a chip and a circuit board are supported substantially in parallel to perform flip-chip mounting.
[0244]
According to the above method, the insulator layer has an opening larger than the element formation surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip is Since the connection electrode terminal portion can be flip-chip mounted, the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer. By providing the support, when forming the support, the degree of freedom in selecting the material is large, and it is possible to prevent variations in the height direction related to the reliability of electrical connection and more strictly control the thickness. Therefore, when a semiconductor chip having an electrode terminal portion called a center pad in the center portion is flip-chip mounted on a circuit board as described above, the semiconductor chip and the element forming surface of the semiconductor chip need to be mounted. A substrate while substantially parallel to the support, can be stably fixed. Therefore, according to the above method, it is possible to prevent poor connection between the semiconductor chip and the circuit board, and to provide a semiconductor device with high connection reliability.
[0245]
The method for manufacturing a semiconductor device according to the present invention is, as described above, a semiconductor chip provided with an electrode terminal portion in the center of the element formation surface, the electrode terminal portion is larger than the semiconductor chip, and In a method of manufacturing a semiconductor device, which is flip-chip mounted in a state of being erected on connection electrode terminals of a circuit board provided with an insulator layer on a surface thereof, a method of mounting the semiconductor chip in the circuit board on the surface of the circuit board, Forming an insulator layer having an opening larger than the element forming surface of the semiconductor chip in the region, and forming one of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip in a projecting shape; And at least one of the semiconductor chip and the circuit board has a height substantially equal to the height of the protruding electrode terminal portion on a surface facing the other. And, at least the outermost layer is plastically deformed under the joining condition with the connection electrode terminal portion by flip chip mounting of the semiconductor chip, and the deformation amount due to the plastic deformation is the electrode terminal portion formed in a projection shape. It is made of substantially the same material and forms a support for supporting the semiconductor chip and the circuit board substantially in parallel. The electrode terminal portion and the support formed in the shape of a protrusion form the support layer of the insulator layer in the circuit board. A method of supporting the semiconductor chip and the circuit board in a state of being bridged in the opening substantially parallel to each other, and plastically deforming the electrode terminal portions and the support formed in a protruding shape, thereby joining the semiconductor chip and the circuit board. It is.
[0246]
According to the above method, the insulator layer has an opening larger than the element formation surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip is Since the connection electrode terminal portion can be flip-chip mounted, the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer. By providing the support, when forming the support, the degree of freedom in selecting the material is large, and it is possible to prevent variations in the height direction related to the reliability of the electrical connection and more strictly control the thickness. It becomes.
[0247]
For this reason, according to the above method, as described above, even when performing bonding involving plastic deformation of the electrode terminal portion, such as ultrasonic bonding, the center portion is referred to as the center pad as described above. When a semiconductor chip having an electrode terminal portion is flip-chip mounted on a circuit board, the semiconductor chip can be stably fixed with the element forming surface of the semiconductor chip and the circuit board supported substantially in parallel. Therefore, according to the above method, it is possible to prevent poor connection between the semiconductor chip and the circuit board, and to produce a semiconductor device having high connection reliability.
[0248]
As described above, the method for manufacturing a semiconductor device according to the present invention is characterized in that the semiconductor chip and the circuit board are joined by plastically deforming the electrode terminal portions and the support formed in a projecting shape, In this method, an interface sealing resin for sealing the gap is injected into a gap between the chip and the circuit board, and the interface sealing resin is cured.
[0249]
According to the above method, the gap between the semiconductor chip and the circuit board can be further fixed by the interfacial sealing resin, so that the joining between them can be made stronger and more stable. Further, according to the above configuration, as described above, the insulator layer on the surface of the circuit board is opened larger than the element formation surface of the semiconductor chip in the flip chip mounting area (mounting target area) of the semiconductor chip. With this configuration, when the semiconductor chip is flip-chip mounted on the connection electrode terminal portion, the effect is obtained that the interface sealing resin can be easily injected into the gap between the semiconductor chip and the circuit board.
[0250]
As described above, the method of manufacturing a semiconductor device according to the present invention uses a semiconductor chip provided with a plurality of electrode terminals in a substantially linear shape at the center of the element forming surface, and the semiconductor substrate is mounted on the circuit board. A plurality of connection electrode terminals are provided substantially linearly in correspondence with the electrode terminal portions of the chip, and the support body is provided on one side of a row of the connection electrode terminal portions in parallel with the connection electrode terminal portions. After bonding the semiconductor chip and the circuit board, the side on which the support is formed is opposite to the side on which the connection electrode terminal portion is sandwiched, or with respect to a row including the connection electrode terminal portion. A method of injecting the interface sealing resin into a gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to the semiconductor chip.
[0251]
According to the above method, by injecting the interface sealing resin into the gap between the semiconductor chip and the circuit board, the semiconductor chip and the circuit board can be more firmly and stably joined. To play. Further, according to the above method, the support is formed on one side of the row of the connection electrode terminal portions, the support is formed in parallel with the connection electrode terminal portions, and the support is formed. The side and the opposite side of the electrode terminal for connection, or, from the direction substantially orthogonal to the row consisting of the electrode terminal for connection, the interface sealing resin in the gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to By injecting, the injectability of the interface sealing resin can be improved, and the effect of efficiently filling the gap with the interface sealing resin can be achieved.
[0252]
As described above, the method of manufacturing a semiconductor device according to the present invention uses a semiconductor chip provided with a plurality of electrode terminals in a substantially linear shape at the center of the element forming surface, and the semiconductor substrate is mounted on the circuit board. A plurality of connection electrode terminal portions are provided substantially linearly in correspondence with the electrode terminal portions of the chip, and the support body is provided on both sides of a row of the connection electrode terminal portions in parallel with the connection electrode terminal portions. Is formed, and after bonding the semiconductor chip and the circuit board, the interface sealing resin is injected into a gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to a row including the connection electrode terminal portions. Is the way.
[0253]
According to the above method, by injecting the interface sealing resin into the gap between the semiconductor chip and the circuit board, the semiconductor chip and the circuit board can be more firmly and stably joined. To play. Further, according to the above method, the support is formed on both sides of the row of the connection electrode terminal portions in parallel with the connection electrode terminal portions, and the support is formed from the connection electrode terminal portions. By injecting the interfacial sealing resin into the gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to the row, the injectability of the interfacial sealing resin can be improved, and more efficiently In addition, there is an effect that the interface sealing resin can be uniformly filled in the gap.
[0254]
As described above, the method of manufacturing a semiconductor device according to the present invention includes the steps of: forming the semiconductor chip and the circuit board before supporting the semiconductor chip and the circuit board by the protruding electrode terminal portions and the support; A layer made of an interface sealing resin that seals a gap between the semiconductor chip and the circuit board is arranged on a surface facing one of the other, and a layer made of an interface sealing resin is arranged in the gap. In this state, the semiconductor chip and the circuit board are supported substantially in parallel in a state of being bridged by the protruding electrode terminal portions and the support, and the protruding electrode terminal portions and the support are supported. This is a method in which plastic deformation of the body and curing of the interface sealing resin are performed in the same step.
[0255]
According to the above method, the gap between the semiconductor chip and the circuit board is sealed with the interface sealing resin, so that the semiconductor chip and the circuit board can be more firmly and stably bonded. It works. Further, according to the above method, the electrical connection between the electrode terminal portion of the semiconductor chip and the connecting electrode terminal portion and the curing of the interface sealing resin can proceed simultaneously, so that the gap is formed at the interface. In addition, there is an effect that the time required for mounting the semiconductor chip when sealing with the sealing resin can be reduced.
[0256]
As described above, the method for manufacturing a semiconductor device according to the present invention is characterized in that the outermost layer of the support electrode and the electrode terminal portion formed in a protruding shape among the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip is electrically conductive. In this method, a bonding layer made of an adhesive is provided.
[0257]
According to the above-described method, by providing the bonding layer on the outermost layer of the electrode terminal portion formed in a projection shape and the support member among the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip, the bonding between the two is performed. This has the effect of being more robust and stable.
[0258]
The method for manufacturing a semiconductor device according to the present invention is, as described above, a semiconductor chip provided with an electrode terminal portion in the center of the element formation surface, the electrode terminal portion is larger than the semiconductor chip, and In a method of manufacturing a semiconductor device, which is flip-chip mounted in a state of being erected on connection electrode terminals of a circuit board provided with an insulator layer on a surface thereof, a method of mounting the semiconductor chip in the circuit board on the surface of the circuit board, Forming an insulator layer having an opening larger than the element forming surface of the semiconductor chip in the region, and forming one of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip in a projecting shape; And at least one of the semiconductor chip and the circuit board has a height substantially equal to the height of the protruding electrode terminal portion on a surface facing the other. Forming a support for supporting the element formation surface of the semiconductor chip and the surface of the circuit board substantially in parallel; and forming the insulating layer on the circuit board by the electrode terminal portions and the support formed in a protruding shape. In the opening, the semiconductor chip and the circuit board are supported substantially in parallel in a state of being bridged, and the gap between the semiconductor chip and the circuit board is sealed with an interface sealing resin to form the connection electrode terminal section. This is a method in which the electrode terminals of the semiconductor chip are brought into pressure contact with each other.
[0259]
According to the above method, the insulator layer has an opening larger than the element formation surface of the semiconductor chip, so that the insulator layer and the semiconductor chip are not in contact with each other and the semiconductor chip is Since the connection electrode terminal portion can be flip-chip mounted, the formation of the support and the electrode terminal portion having a protruding shape is not restricted by the insulator layer. By providing the support, when forming the support, the degree of freedom in selecting the material is large, and it is possible to prevent variations in the height direction related to the reliability of the electrical connection and more strictly control the thickness. It becomes. For this reason, according to the above method, the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion are pressed against each other to electrically connect the semiconductor chip and the circuit board with the interface sealing resin as described above. Even in the case where the semiconductor chip is fixed, when the semiconductor chip having the electrode terminal portion called the center pad in the center portion is flip-chip mounted on the circuit board, the element formation surface of the semiconductor chip and the circuit board are substantially fixed. This has the effect of being able to be fixed stably in a state of being supported in parallel.
[0260]
As described above, the method for manufacturing a semiconductor device according to the present invention is a method in which an anisotropic conductive resin having conductive particles dispersed therein is used as the interface sealing resin.
[0261]
According to the above method, there is an effect that a better electrical connection can be obtained by the conductive particles present in the anisotropic conductive resin. In particular, when performing flip-chip mounting of the semiconductor chip by plastically deforming the electrode terminal portion using ultrasonic waves or the like, the conductive particles are present at the junction between the electrode terminal portion of the semiconductor chip and the connection electrode terminal portion. By being buried, the conductive particles can provide a better electrical connection.
[0262]
In the method of manufacturing a semiconductor device according to the present invention, as described above, of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip, the electrode terminal portion formed in a projecting shape and the support are formed of the same material. Is the way.
[0263]
According to the above method, by forming the support from the same material as the electrode terminal portion formed in the shape of a protrusion, the heights of the two can be easily matched by the existing technology. For this reason, according to the above-described method, there is an effect that a semiconductor device having higher connection reliability can be manufactured. Further, according to the above method, it is possible to simultaneously form the support and the electrode terminal portion formed in the shape of a protrusion in the same step, for example, a step of forming a substrate wiring such as etching or plating. Therefore, there is also an effect that the support can be easily formed at low cost without increasing the number of steps.
[0264]
As described above, the method of manufacturing a semiconductor device according to the present invention is a method of forming the above-mentioned support with a metal.
[0265]
According to the above method, by forming the support body with a metal, it becomes possible to prevent variations in the height direction related to the reliability of electrical connection and to control the thickness more strictly and easily. Therefore, there is an effect that a semiconductor device having higher connection reliability can be manufactured.
[0266]
As described above, the method for manufacturing a semiconductor device according to the present invention includes the step of forming the connection electrode terminal portion of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip in a projecting shape, and the method of manufacturing the connection electrode terminal. This is a method of forming the support on the circuit board in the same step as the step of forming the portion.
[0267]
According to the above-described method, the support and the electrode terminal portion formed in a protruding shape are used simultaneously with the formation of the wiring or in the step of forming the wiring in the step of forming the substrate wiring such as etching or plating. Therefore, the support can be easily and inexpensively formed without increasing the number of steps. Further, according to the above-described method, the heights of the two can be easily matched by the existing technology. Therefore, according to the above-described method, a semiconductor device having even higher connection reliability can be manufactured at low cost and easily.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing a schematic configuration of an element formation surface of the semiconductor chip shown in FIGS. 1 (a) to 1 (d).
FIG. 3 is a plan view showing a schematic configuration of the circuit board shown in FIGS. 1 (a) to 1 (d).
FIG. 4 is a sectional view schematically showing a configuration of a main part of the circuit board shown in FIG. 3;
FIGS. 5A to 5C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
FIG. 6 is a cross-sectional view schematically showing a configuration of a main part of the semiconductor device shown in FIG. 5 (c).
FIGS. 7A to 7D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
8A to 8D are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
FIG. 9 is a cross-sectional view schematically showing a configuration of a conventional semiconductor device.
FIGS. 10A to 10C are cross-sectional views illustrating a semiconductor device manufacturing process when ultrasonic bonding is applied to a semiconductor device manufacturing method using a conventional flip-chip mounting method.
[Explanation of symbols]
1 semiconductor chip
2 Circuit board
3 connection electrode (connection electrode terminal part)
4 Support
5. Electrode terminal
6 Insulator layer
7 Ultrasonic application tool
8 Interface sealing resin
9 nozzles
10 Insulator layer
11 Through hole
12 Solder resist opening
13 Insulating film
20 Wiring
21 Interface sealing resin
22 Binder resin
23 conductive particles
31 bonding layer
32 bonding layer
33 Connection electrode (connection electrode terminal)
34 Support
41 First Semiconductor Chip
42 Second semiconductor chip
43 circuit board
44 Electrode terminal
46 Connection pads (connection electrode terminals)
47 Interface sealing resin
48 adhesive layer
49 sealing resin layer
50 insulating film
51 Insulating film
52 Through hole
53 External input / output terminal

Claims (20)

素子形成面の中央部に電極端子部が設けられた半導体チップが、上記電極端子部にて、回路基板の接続用電極端子部に架設状態でフリップチップ実装されており、上記回路基板は、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられている半導体装置において、
上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部が突起状に形成されており、
上記回路基板表面の絶縁体層は、上記半導体チップの素子形成面よりも大きな開口部を備え、該開口部内で上記半導体チップと回路基板とが架設状態でフリップチップ実装されており、
上記半導体チップと回路基板との間隙には、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体が設けられていることを特徴とする半導体装置。A semiconductor chip provided with an electrode terminal portion at the center of the element forming surface is flip-chip mounted on the electrode terminal portion in a state of being bridged over a connection electrode terminal portion of a circuit board. In a semiconductor device larger than a semiconductor chip and having an insulator layer on the surface,
One of the connection electrode terminal portions and the electrode terminal portion of the semiconductor chip is formed in a protruding shape,
The insulator layer on the surface of the circuit board has an opening larger than the element forming surface of the semiconductor chip, and the semiconductor chip and the circuit board are flip-chip mounted in a state of being bridged in the opening,
In the gap between the semiconductor chip and the circuit board, a support having substantially the same height as the protruding electrode terminal portion and supporting the semiconductor chip and the circuit board substantially in parallel is provided. A semiconductor device. 上記支持体は、突起状に形成された電極端子部と同じ材料からなることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the support is made of the same material as the electrode terminal formed in a protruding shape. 上記支持体は金属からなることを特徴とする請求項１または２記載の半導体装置。3. The semiconductor device according to claim 1, wherein said support is made of metal. 上記半導体チップと回路基板とが、突起状に形成された上記電極端子部及び上記支持体の塑性変形により接合されていることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。4. The semiconductor according to claim 1, wherein the semiconductor chip and the circuit board are joined by plastic deformation of the protruding electrode terminal portion and the support. 5. apparatus. 上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂によりさらに固着されていることを特徴とする請求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the semiconductor chip and the circuit board are further fixed by an interface sealing resin for sealing a gap between the semiconductor chip and the circuit board. 上記接続用電極端子部と半導体チップの電極端子部とが架設状態で圧接されており、
上記半導体チップと回路基板とが、該半導体チップと回路基板との間隙を封止する界面封止樹脂により固着されていることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。The connection electrode terminal portion and the electrode terminal portion of the semiconductor chip are pressed against each other in a bridged state,
4. The semiconductor according to claim 1, wherein the semiconductor chip and the circuit board are fixed with an interface sealing resin that seals a gap between the semiconductor chip and the circuit board. 5. apparatus. 上記支持体と半導体チップとの接触面積が、突起状に形成された上記電極端子部と半導体チップとの接触面積よりも大きいことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a contact area between the support and the semiconductor chip is larger than a contact area between the semiconductor chip and the electrode terminal formed in a protruding shape. 上記半導体チップの素子形成面とは反対側の面に少なくとも１つの半導体チップが積層され、該積層された半導体チップの電極端子部と、上記回路基板における上記絶縁体層の開口部内でかつ上記半導体チップのフリップチップ実装領域外に設けられた接続用電極端子部とが金属細線により電気的に接続されていることを特徴とする請求項１記載の半導体装置。At least one semiconductor chip is stacked on the surface of the semiconductor chip opposite to the element forming surface, and the electrode terminal portion of the stacked semiconductor chip and the semiconductor chip in the opening of the insulator layer in the circuit board are formed. 2. The semiconductor device according to claim 1, wherein the connection electrode terminal portion provided outside the flip chip mounting area of the chip is electrically connected by a thin metal wire. 素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、
上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、
上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、
突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを実質平行に支持してフリップチップ実装を行うことを特徴とする半導体装置の製造方法。A semiconductor chip provided with an electrode terminal portion in the center of the element forming surface is connected to a connection electrode terminal on a circuit board which is larger than the semiconductor chip at the electrode terminal portion and has an insulator layer provided on the surface. In a method of manufacturing a semiconductor device to be flip-chip mounted in a state of being mounted on a part,
An insulating layer having an opening larger than an element forming surface of the semiconductor chip is formed in a region of the circuit board where the semiconductor chip is to be flip-chip mounted on the surface of the circuit board, and the connection electrode terminal portion and the semiconductor chip are formed. While forming one of the electrode terminal portions in the shape of a protrusion,
The semiconductor chip and the circuit board have substantially the same height as the electrode terminal portions formed in a protruding shape on a surface facing the other one of the semiconductor chip and the circuit board, and support the semiconductor chip and the circuit board substantially in parallel. To form a support,
The flip chip mounting is performed by supporting the semiconductor chip and the circuit board substantially in parallel in the opening of the insulating layer in the circuit board by the electrode terminal portions and the support formed in a projecting shape. Manufacturing method of a semiconductor device. 素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、
上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、
上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、かつ、少なくとも最表層が上記半導体チップのフリップチップ実装による上記接続用電極端子部との接合条件で塑性変形すると共に、該塑性変形による変形量が、突起状に形成された上記電極端子部とほぼ同じ材料からなり、上記半導体チップと回路基板とを実質平行に支持する支持体を形成し、
突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で上記半導体チップと回路基板とを架設状態で実質平行に支持し、突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合することを特徴とする半導体装置の製造方法。A semiconductor chip provided with an electrode terminal portion in the center of the element forming surface is connected to a connection electrode terminal on a circuit board which is larger than the semiconductor chip at the electrode terminal portion and has an insulator layer provided on the surface. In a method of manufacturing a semiconductor device to be flip-chip mounted in a state of being mounted on a part,
On the surface of the circuit board, an insulator layer having an opening larger than an element formation surface of the semiconductor chip is formed in a flip chip mounting target area of the semiconductor chip on the circuit board,
One of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip is formed in a projection shape, and the projection is formed on a surface of one of the semiconductor chip and the circuit board facing the other. Having approximately the same height as the electrode terminal portion formed in a shape, and at least the outermost layer is plastically deformed under bonding conditions with the connection electrode terminal portion by flip-chip mounting of the semiconductor chip, and The amount of deformation due to deformation is made of a material substantially the same as the electrode terminal portion formed in the shape of a protrusion, forming a support that supports the semiconductor chip and the circuit board substantially in parallel,
The semiconductor chip and the circuit board are supported substantially in parallel in the opening of the insulator layer in the circuit board by the electrode terminal portions and the support formed in the projecting shape, and are formed in the projecting shape. A method of manufacturing the semiconductor device, wherein the semiconductor terminal and the circuit board are joined by plastically deforming the electrode terminal portion and the support. 突起状に形成された上記電極端子部及び上記支持体を塑性変形させて上記半導体チップと回路基板とを接合させた後、上記半導体チップと回路基板との間隙に、該間隙を封止する界面封止樹脂を注入し、該界面封止樹脂を硬化させることを特徴とする請求項１０記載の半導体装置の製造方法。An interface for sealing the gap between the semiconductor chip and the circuit board after plastically deforming the electrode terminal portion and the support formed in the shape of a protrusion to join the semiconductor chip and the circuit board. The method of manufacturing a semiconductor device according to claim 10, wherein a sealing resin is injected and the interface sealing resin is cured. 素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、
上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の片側に、上記接続用電極端子部と平行に上記支持体を形成し、
上記半導体チップと回路基板とを接合後に、上記支持体が形成された側とは上記接続用電極端子部を挟んで反対側、もしくは、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することを特徴とする請求項１１記載の半導体装置の製造方法。Using a semiconductor chip in which a plurality of electrode terminals are provided in a substantially linear manner in the center of the element forming surface,
The circuit board is provided with a plurality of connection electrode terminals in a substantially linear manner corresponding to the electrode terminals of the semiconductor chip, and the connection electrode terminals are provided on one side of a row of the connection electrode terminals. Forming the support in parallel with the part,
After joining the semiconductor chip and the circuit board, the side on which the support is formed is opposite to the side on which the connection electrode terminal portion is interposed, or substantially orthogonal to a row including the connection electrode terminal portions. 12. The method according to claim 11, wherein the interface sealing resin is injected into a gap between the semiconductor chip and the circuit board from a direction. 素子形成面の中央部にほぼ直鎖状に複数の電極端子部が設けられた半導体チップを使用し、
上記回路基板に、上記半導体チップの電極端子部に対応してほぼ直鎖状に複数の接続用電極端子部を設けると共に、上記接続用電極端子部からなる列の両側に、上記接続用電極端子部と平行に上記支持体を形成し、
上記半導体チップと回路基板とを接合後に、上記接続用電極端子部からなる列に対し、ほぼ直交する方向から上記半導体チップと回路基板との間隙に上記界面封止樹脂を注入することを特徴とする請求項１１記載の半導体装置の製造方法。Using a semiconductor chip in which a plurality of electrode terminals are provided in a substantially linear manner in the center of the element forming surface,
A plurality of connection electrode terminals are provided on the circuit board in a substantially linear manner corresponding to the electrode terminals of the semiconductor chip, and the connection electrode terminals are provided on both sides of a row of the connection electrode terminals. Forming the support in parallel with the part,
After joining the semiconductor chip and the circuit board, the interface sealing resin is injected into a gap between the semiconductor chip and the circuit board from a direction substantially orthogonal to a row including the connection electrode terminal portions. The method for manufacturing a semiconductor device according to claim 11, wherein 突起状に形成された上記電極端子部と支持体とによって上記半導体チップと回路基板とを支持する前に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、上記半導体チップと回路基板との間隙を封止する界面封止樹脂からなる層を配し、
上記間隙に界面封止樹脂からなる層が配された状態で、突起状に形成した上記電極端子部と上記支持体とによって、上記半導体チップと回路基板とを架設状態で実質平行に支持し、
突起状に形成された上記電極端子部及び上記支持体の塑性変形と上記界面封止樹脂の硬化とを、同一の工程において行うことを特徴とする請求項１０記載の半導体装置の製造方法。Before the semiconductor chip and the circuit board are supported by the electrode terminal portions and the support formed in a protruding shape, the semiconductor chip is disposed on a surface of one of the semiconductor chip and the circuit board facing the other. And a layer made of an interfacial sealing resin that seals a gap between the
In the state where the layer made of the interface sealing resin is arranged in the gap, the electrode terminal portion and the support formed in a protruding manner support the semiconductor chip and the circuit board substantially in parallel in a bridged state,
11. The method of manufacturing a semiconductor device according to claim 10, wherein the plastic deformation of the protruding electrode terminal portion and the support and the curing of the interface sealing resin are performed in the same step. 上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体との最表層に、導電性接着剤からなる接合層を各々設けることを特徴とする請求項１０記載の半導体装置の製造方法。A bonding layer made of a conductive adhesive is provided on an outermost layer of the electrode terminal portion and the support, which are formed in a protruding shape, of the electrode terminal portion for connection and the electrode terminal portion of the semiconductor chip, respectively. 11. The method for manufacturing a semiconductor device according to item 10. 素子形成面の中央部に電極端子部が設けられた半導体チップを、上記電極端子部にて、上記半導体チップよりも大きく、かつ、表面に絶縁体層が設けられた回路基板における接続用電極端子部に架設状態でフリップチップ実装する半導体装置の製造方法において、
上記回路基板表面に、該回路基板における上記半導体チップのフリップチップ実装対象領域に上記半導体チップの素子形成面よりも大きな開口部を有する絶縁体層を形成し、
上記接続用電極端子部及び半導体チップの電極端子部のうち何れか一方の電極端子部を突起状に形成すると共に、上記半導体チップ及び回路基板のうち何れか一方における他方との対向面に、突起状に形成された上記電極端子部とほぼ同じ高さを有し、上記半導体チップの素子形成面と上記回路基板表面とを実質平行に支持する支持体を形成し、
突起状に形成された上記電極端子部と支持体とによって、上記回路基板における上記絶縁体層の開口部内で、上記半導体チップと回路基板とを架設状態で実質平行に支持した状態で、上記半導体チップと回路基板との間隙を界面封止樹脂により封止して上記接続用電極端子部と上記半導体チップの電極端子部とを圧接させることを特徴とする半導体装置の製造方法。A semiconductor chip provided with an electrode terminal portion in the center of the element forming surface is connected to a connection electrode terminal on a circuit board which is larger than the semiconductor chip at the electrode terminal portion and has an insulator layer provided on the surface. In a method of manufacturing a semiconductor device to be flip-chip mounted in a state of being mounted on a part,
On the surface of the circuit board, an insulator layer having an opening larger than an element formation surface of the semiconductor chip is formed in a flip chip mounting target area of the semiconductor chip on the circuit board,
One of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip is formed in a projection shape, and the projection is formed on a surface of one of the semiconductor chip and the circuit board facing the other. A support that has substantially the same height as the electrode terminal portion formed in a shape and supports the element formation surface of the semiconductor chip and the circuit board surface substantially in parallel;
In the state where the semiconductor chip and the circuit board are supported substantially in parallel in an extended state in the opening of the insulator layer in the circuit board by the electrode terminal portion and the support formed in a protruding shape, A method for manufacturing a semiconductor device, comprising: sealing a gap between a chip and a circuit board with an interface sealing resin to press-contact the connection electrode terminal portion and the semiconductor chip electrode terminal portion. 上記界面封止樹脂として、内部に導電粒子が分散された異方導電性樹脂を用いることを特徴とする請求項１４または１６に記載の半導体装置の製造方法。17. The method according to claim 14, wherein an anisotropic conductive resin having conductive particles dispersed therein is used as the interface sealing resin. 上記接続用電極端子部及び半導体チップの電極端子部のうち突起状に形成する電極端子部と支持体とを、同じ材料で形成することを特徴とする請求項９、１０、１６の何れか１項に記載の半導体装置の製造方法。17. The semiconductor device according to claim 9, wherein the connecting electrode terminal portion and the electrode terminal portion of the semiconductor chip, the electrode terminal portion formed in a projection shape and the support are formed of the same material. 13. The method for manufacturing a semiconductor device according to item 13. 上記支持体を金属で形成することを特徴とする請求項９、１０、１６、１８の何れか１項に記載の半導体装置の製造方法。19. The method according to claim 9, wherein the support is formed of a metal. 上記接続用電極端子部及び半導体チップの電極端子部のうち上記接続用電極端子部を突起状に形成すると共に、
上記接続用電極端子部の形成工程と同一の工程で上記回路基板に上記支持体を形成することを特徴とする請求項９、１０、１６、１８の何れか１項に記載の半導体装置の製造方法。While forming the connection electrode terminal portion of the connection electrode terminal portion and the electrode terminal portion of the semiconductor chip in a projecting shape,
19. The semiconductor device according to claim 9, wherein the support is formed on the circuit board in the same step as the step of forming the connection electrode terminal. Method.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644623B2 (en) 2007-01-30 2010-01-12 Denso Corporation Semiconductor sensor for measuring a physical quantity and method of manufacturing the same
CN115580983A (en) * 2022-09-30 2023-01-06 荣耀终端有限公司 Circuit board assembly and electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644623B2 (en) 2007-01-30 2010-01-12 Denso Corporation Semiconductor sensor for measuring a physical quantity and method of manufacturing the same
CN115580983A (en) * 2022-09-30 2023-01-06 荣耀终端有限公司 Circuit board assembly and electronic device
CN115580983B (en) * 2022-09-30 2023-08-29 荣耀终端有限公司 Circuit board assembly and electronic equipment

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