JP3903025B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP3903025B2
JP3903025B2 JP2003198678A JP2003198678A JP3903025B2 JP 3903025 B2 JP3903025 B2 JP 3903025B2 JP 2003198678 A JP2003198678 A JP 2003198678A JP 2003198678 A JP2003198678 A JP 2003198678A JP 3903025 B2 JP3903025 B2 JP 3903025B2
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semiconductor chip
substrate
electrode
back surface
wiring
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JP2004158825A (en
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誠 照井
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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Abstract

<P>PROBLEM TO BE SOLVED: To effectively utilize solder balls in a ball grid array package. <P>SOLUTION: Electrodes of a semiconductor chip 28 mounted on a front side of a copper plate 21 are connected to the solder balls 34 by copper foil wires 23 formed via an insulation material 22 on the copper plate 21. Through-holes 30 insulated from the copper plate 21 are formed to the copper plate 21. Electrodes of a semiconductor chip 36 mounted on a rear side of the copper plate 21 are connected to the through-holes 30 by copper foil wires 26 formed via an insulation material 25 on the copper plate 21, and connected to the solder balls 34 by way of the through-holes 30. Thus, the excess solder balls 34 not connected to the electrodes of the semiconductor chip 28 can be used for terminals of the semiconductor chip 36. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関するもので、詳しくはボールグリッドアレイ（以下、ＢＧＡパッケージという）パッケージの製造方法に関するものである。
【０００２】
【従来の技術】
図２（ａ），（ｂ）は、従来のＢＧＡパッケージの一例を示す断面図である。図３（ａ），（ｂ）は、従来のＢＧＡパッケージの他の例を示す断面図であり、図２中の要素と共通の要素には共通の符号が付されている。一般的な放熱性を考慮したＢＧＡパッケージでは、厚さ０．３〜０．４ｍｍの銅板１に、厚さ１０〜３０μｍのポリイミド等からなる絶縁材２が、貼付けられている。絶縁材２の上に、厚さ１２〜３５μｍの銅箔配線３が形成されている。銅板１の表面側には、図２のように、切削加工よって半導体チップ４の搭載箇所５ａが形成されるか、図３のように、金型絞り加工によって半導体チップ４の搭載箇所５ｂが形成され、基板が構成されている。
【０００３】
半導体チップ４は、電極が形成された電極面とその反対側の背面とを有している。搭載箇所５ａ，５ｂの底部に導電性或いは絶縁性のペースト６が塗布され、そこに半導体チップ４が背面を向けて固着されている。半導体チップ４の電極と銅箔配線３とがボンディングワイヤ７で接続され、該半導体チップ４の搭載されているキャビティ部分が、エポキシ樹脂８によって充填されている。基板の表面側のエポキシ樹脂８のない部分に、半田ボール９が格子状に取り付けられている。基板の表面側のエポキシ樹脂８及び半田ボール９のない場所は、レジスト膜１０で覆われている。なお、封止後の基板の反り対策或いは汚れ防止対策として、基板の裏面側に、図３のように絶縁材１１が貼付けられる場合もある。
【０００４】
【発明が解決しようとする課題】
しかしながら、従来の図２及び図３のＢＧＡパッケージでは、次のような課題があった。図４（ａ），（ｂ）は、図２及び図３のＢＧＡパッケージの課題の説明図である。多ピン化に対応するために、半田ボール９からなる格子状の端子の列数を増加したり、該端子のピッチを狭くすると、図４（ａ）のように、銅箔配線３の幅とギャップからの制約により、半導体チップ４の電極とボンディングワイヤ７で接続されるボンディングポスト１２に結線されない余剰端子１３が多数発生する。また、図２或いは図３のＢＧＡパッケージを、図４（ｂ）のようにマザーボード１４に実装しようとしても、多ピン化に伴って該ＢＧＡパッケージの外形寸法が増加するので実装面積が増大する。よって、マザーボード１４の寸法も増大させる必要があった。
【０００５】
【課題を解決するための手段】
前記課題を解決するために、本発明のうちの第１の発明は、ＢＧＡパッケージにおいて、次のような構成にしている。即ち、表面と裏面とを有する板状の基材と、電極が形成された電極面と該電極面の反対側で該電極を持たない背面とを有し、背面が基材の表面側に固着された第１の半導体チップと、基材の表面側に配列された複数の半田ボールと、基材の表面側に形成され、複数の半田ボールのうちの一部の半田ボールと導通を持つ第１の配線パターンと、第１の半導体チップの電極と第１の配線パターンとを接続する第１の接続部材と、基材の裏面側に形成された第２の配線パターンと、電極面及び背面を有し、基板の裏面側に搭載された任意数の第２の半導体チップと、第２の半導体チップの電極と第２の配線パターンとを接続する第２の接続部材と、基材に形成され、基材の表面側の複数の半田ボールのうちの残った半田ボールと基材の裏面側の第２の配線パターンとを接続するスルーホールと、第１の半導体チップの電極面を封止する第１の封止部材と、第２の半導体チップの電極面を封止する第２の封止部材とを、備えている。
【０００６】
第２の発明は、第１の発明における第２の半導体チップは、背面を基材の裏面側に固定し、第２の接続部材は、ボンディングワイヤで構成している。第３の発明は、第１の発明における第２の接続部材は、第２の半導体チップの電極に突設された複数のバンプで構成し、第２の半導体チップは、電極側が基材の裏面側に対向し、バンプによって電極が第２の配線パターンに接続されている。
【０００７】
第４の発明は、ＢＧＡパッケージにおいて、次のような構成にしている。即ち、表面と裏面とを有する板状の基材と、電極が形成された電極面と該電極面の反対側で該電極を持たない背面とを有し、背面が基材の表面側に固着された第１の半導体チップと、基材の表面側に配列された複数の半田ボールと、基材の表面側に形成され、複数の半田ボールのうちの一部の半田ボールと導通を持つ第１の配線パターンと、第１の半導体チップの電極と第１の配線パターンとを接続する第１の接続部材と、基材の裏面側に形成された第２の配線パターンと、端子のみが露出し、他が既に封止された任意数の半導体装置と、半導体装置の端子と第２の配線パターンとを接続する第２の接続部材と、基材に形成され、基材の表面側の複数の半田ボールのうちの残った半田ボールに基材の裏面側の第２の配線パターンを接続するスルーホールと、第１の半導体チップの電極面を封止する第１の封止部材とを備えている。
【０００８】
第５の発明は、第３の発明のＢＧＡパッケージを製造するＢＧＡパッケージの製造方法において、次のような製造方法を講じている。即ち、表面と裏面とを有する板状の基材にスルーホールを形成し、該基材の表面側に第１の配線パターンを形成すると共に基材の裏面側にスルーホールと導通を持つ第２の配線パターンを形成するパターン形成処理とを最初に行う。そして、パターン形成処理の後に、電極が形成された電極面と該電極面の反対側で該電極を持たない背面とを有する第１の半導体チップを、背面を基材の表面側に向けて固着し、第１の半導体チップの電極と第１の配線パターンとを第１の接続部材で接続する第１の搭載処理と、第１の半導体チップの前記電極面を第１の封止樹脂で封止する第１の封止処理と、パターン形成処理の後の第１の搭載処理及び第１の封止処理の前または後に、電極が形成された電極面と電極面の反対側で該電極を持たない背面とを有し、電極には導電性のバンプが突設された第２の半導体チップを、電極面側を基材の裏面側に対向させ、第２の配線パターンに該バンプを加熱圧着することにより、第２の半導体チップを該基材に搭載する第２の搭載処理と、搭載された第２の半導体チップと基材の間に、第２の半導体チップの横から液状の第２の封止樹脂を注入し、液状の第２の封止樹脂を硬化させて第２の半導体チップの電極面を封止する第２の封止処理と、基材の表面側に、第１の配線パターンと導通を持つ半田ボール及びスルーホールと導通を持つ半田ボールを形成する半田ボール形成処理とを行うようにしている。
【０００９】
第６の発明は、第３の発明のＢＧＡパッケージを製造するＢＧＡパッケージの製造方法において、次のような製造方法を講じている。即ち、表面と裏面とを有する板状の基材にスルーホールを形成し、該基材の表面側に第１の配線パターンを形成すると共に該基材の裏面側に該スルーホールに導通を持つ第２の配線パターンを形成するパターン形成処理と、前記パターン形成処理の前または後に、基材の第２の半導体チップ搭載予定領域に表面から裏面に貫通する孔を形成する貫通孔形成処理とを行う。そして、パターン形成処理及び貫通孔形成処理の後に、電極が形成された電極面と該電極面の反対側で電極を持たない背面とを有し、電極には導電性のバンプが突設された第２の半導体チップを、電極面側を基材の裏面側に対向させ、第２の配線パターンにバンプを加熱圧着することにより、第２の半導体チップを基材に搭載する第１の搭載処理と、第２の半導体チップの電極面と基材の裏面との間に孔を介して液状の第２の封止樹脂を注入し、液状の第２の封止樹脂を硬化させて第２の半導体チップの電極面を封止する第１の封止処理と、第１の封止処理の後に、電極が形成された電極面と該電極面の反対側で電極を持たない背面とを有する第１の半導体チップを、背面を基材の表面側に向けて固着し、第１の半導体チップの電極と第１の配線パターンとを第１の接続部材で接続する第２の搭載処理と、第１の半導体チップの電極面を第１の封止樹脂で封止する第１の封止処理と、基材の表面側に、第１の配線パターンと導通を持つ半田ボール及びスルーホールと導通を持つ半田ボールを形成する半田ボール形成処理とを行うようにしている。
【００１０】
第７の発明は、第３の発明のＢＧＡパッケージを製造するＢＧＡパッケージの製造方法において、次のような製造方法を講じている。即ち、表面と裏面とを有する板状の基材にスルーホールを形成し、基材の表面側に第１の配線パターンを形成すると共に基材の裏面側にスルーホールに導通を持つ第２の配線パターンを形成するパターン形成処理を行う。そして、パターン形成処理の後に、電極が形成された電極面と該電極面の反対側で該電極を持たない背面とを有する第１の半導体チップを、背面を基材の表面側に向けて固着し、第１の半導体チップの電極と第１の配線パターンとを第１の接続部材で接続する第１の搭載処理と、第１の半導体チップの電極面を第１の封止樹脂で封止する第１の封止処理と、パターン形成処理の後の第１の搭載処理及び第１の封止処理の前または後に、基材の第２の半導体チップ搭載予定領域にテープ状の第２の封止樹脂を置くテープ載置処理と、電極が形成された電極面と該電極面の反対側で該電極を持たない背面とを有し、電極には導電性のバンプが突設された第２の半導体チップを、電極面側を基材の裏面側に対向させ、第２の配線パターンに該バンプを加熱圧着することにより、第２の半導体チップを基材に搭載する第２の搭載処理と、これと同時に行われ、第２の封止樹脂を溶融させた後に硬化させ、第２の半導体チップの電極面を封止する第２の封止工程と、基材の表面側に、第１の配線パターンと導通を持つ半田ボール及びスルーホールと導通を持つ半田ボールを形成する半田ボール形成工程とを、行うようにしている。
【００１１】
第１から第７の発明によれば、以上のようにＢＧＡパッケージ及び該ＢＧＡパッケージの製造方法を構成したので、基材の表面側には、第１の半導体チップが搭載され、基材の裏面側には第２の半導体チップまたは半導体装置が搭載される。この第２の半導体チップの電極または半導体装置の端子は、第２の配線パターン及びスルーホールを介して基材の表面側の半田ボールと接続される。そのため、第２の半導体チップまたは半導体装置への信号の入出力には、その半田ボールが用いられる。
【００１２】
また、第８の発明は、半導体装置において、表面と裏面とを有する基板と、その基板の表面に形成された第１の外部電極と、基板の表面に搭載されるとともに、第１の外部電極と電気的に接続された第１の半導体チップと、基板の表面に形成された第２の外部電極と、基板の裏面に搭載されるとともに、第２の外部電極と、基板に形成されたスルーホールを介して電気的に接続された第２の半導体チップとを含むようにしている。
【００１３】
第９の発明は、第８の発明の半導体装置において、第１の半導体装置は、基板の表面に形成された第１の配線パターンを介して第１の外部電極に電気的に接続し、第２の半導体チップは、基板の裏面に形成された第２の配線パターンを介して第２の外部電極に電気的に接続した構成にしている。
【００１４】
第１０の発明は、第８の発明の半導体装置における第２の外部電極は実質的に、基板のコーナー部近傍に設けている。第１１の発明は、第８の発明の半導体装置において、基板には凹部を形成し、第１の半導体チップはこの凹部内に配置している。第１２の発明は、第８の発明の半導体装置において、第１の外部電極及び第２の外部電極は半田ボールで構成している。第８から第１２の発明によれば、以上のように半導体装置を構成したので、基板の表面に第１の外部電極及び第２の外部電極が形成されている。基板の表面に第１の半導体チップが搭載され、裏面に第２の半導体チップが搭載される。第１の半導体チップは第１の外部電極に電気的に接続され、第２の半導体チップは、スルーホールを介して第２の外部電極に電気的に接続される。そのため、第２の半導体チップへの信号の入出力は、基板の表面に形成された第２の外部電極が用いられる。
【００１５】
【発明の実施の形態】
第１の実施形態図１は、本発明の第１の実施形態を示すＢＧＡパッケージの断面図である。図５（ａ）〜（ｃ）は、図１のＢＧＡパッケージのベースとなる基板２０を示す図であり、図１中の要素と共通の要素には共通の符号が付されている。このＢＧＡパッケージのベースとなる基板２０には、厚さ０．３〜０．４ｍｍの銅板２１が基材として用いられている。銅板２１の表面側には、従来と同様に厚さ１０〜３０μｍのポリイミド等からなる絶縁材２２が貼付けられ、該絶縁材２２の上に厚さ１２〜３５μｍの第１の配線パターンである銅箔配線２３が形成されている。銅箔配線２３の上部は、一部を残してソルダーレジスト２４が塗布されている。銅板２１の裏面側には、図５（ｂ）のように、厚さ１０〜３０μｍのポリイミド等からなる絶縁材２５が貼付けられ、該絶縁材２５の上に厚さ１２〜３５μｍの第２の配線パターンである銅箔配線２６が形成されている。銅箔配線２６の上は、一部を残してソルダーレジスト２７が塗布されている。
【００１６】
例えば、金型絞り加工により、銅板２１の表面側には、第１の半導体チップ２８の搭載箇所２９が凹状に形成されている。銅板２１には、さらに、表面と裏面をつなぐスルーホール３０が形成されている。スルーホール３０は、銅板２１とは絶縁されている。各銅箔配線２３，２６の一端が、後述するボンディングワイヤに接続されるボンディングポスト２５ａ，２６ａになっている。裏面側の銅箔配線２６の他端は、スルーホール３０に接続されている。搭載箇所２９に例えば絶縁ペースト３１が塗布され、該搭載箇所２９に、半導体チップ２８が電極面とは反対の背面を向けて固着されている。半導体チップ２８の電極と銅箔配線２３とが第１の接続部材であるボンディングワイヤ３２で接続され、該半導体チップ２８の搭載されているキャビティ部分が、第１の封止樹脂のエポキシ樹脂３３によって封止されている。基板２０の表面側には、複数の半田ボール３４が例えば格子状に配置されている。銅箔配線２３のソルダーレジスト２７の開口した部分に、半田ボール３４が形成され、さらに、各スルーホール３０も半田ボール３４と導通を持つように形成されている。
【００１７】
このような基板２０の裏面側の一部に導電性或いは絶縁性のペースト３５が塗布され、図１のように、第２の半導体チップ３６が搭載され、半導体チップ３６の背面がペースト３５によって固着されている。半導体チップ３６の電極と銅箔配線２６のボンディングポスト２６ａとが、第２の接続部材であるボンディングワイヤ３７により、接続されている。この半導体チップ３６も、第２の封止樹脂であるエポキシ樹脂３８により、封止されている。半導体チップ２８，３６が搭載された図１のＢＧＡパッケージでは、信号が半田ボール３４及び銅箔配線２３を介して半導体チップ２８に入出力されるばかりでなく、半田ボール３４、スルーホール３０及び銅箔配線２６を介して半導体チップ３６に信号が入出力される。
【００１８】
以上のように、この第１の実施形態では、基材２１の表面側と裏面側の両方に銅泊配線２３，２６を形成すると共に、該基材２１にスルーホール３０を設け、基材２１の裏面側に搭載した半導体チップ３６の電極を表面側に配列した半田ボール３４に接続したので、半導体チップ２８に接続できなかった半田ボール３４、つまり、余剰端子を半導体チップ３６の端子として有効に使用することができる。また、半導体チップ２８と半導体チップ３６とを基材２１の両側に搭載するので、マザーボードに実装する時の実装面積を低減でき、マザーボードの面積も小さくできる。
【００１９】
第２の実施形態図６は、本発明の第２の実施形態を示すＢＧＡパッケージの断面図である。図７（ａ），（ｂ）は、図６のＢＧＡパッケージのベースとなる基板４０を示す図であり、図６中の要素と共通の要素には共通の符号が付されている。このＢＧＡパッケージのベースとなる基板４０は、第１の実施形態と同様の銅板４１が基材として用いられ、該銅板４１の表面側には、厚さ１０〜３０μｍの絶縁材４２が貼付けられている。絶縁材４２の上に、厚さ１２〜３５μｍの第１の配線パターンである銅箔配線４３が形成されている。銅箔配線４３の上部は、一部を残してソルダーレジスト４４が塗布されている。
【００２０】
銅板４１の裏面側には、図７（ｂ）のように、厚さ１０〜３０μｍのポリアミド等からなる絶縁材４５が貼付けられ、該絶縁材４５の上に、厚さ１２〜３５μｍの第２の配線パターンである銅箔配線４６が形成されている。銅箔配線４６の上は、一部を残してソルダーレジスト４７が塗布されている。金型絞り加工により、銅板４１の表面側に第１の半導体チップ４８の搭載箇所４９が凹状に形成されている。銅板４１には、さらに、該銅板４１とは絶縁され、表面側と裏面側をつなぐスルーホール５０が形成されている。銅箔配線４３の一端が、ボンディングワイヤに接続されるボンディングポスト４３ａになっている。裏面側の銅箔配線４６の一端が後述する金バンプに接続されるランド４６ａになっており、例えば該ランド４６ａには、下地にＮｉメッキが施され、さらに、その上に金メッキが施されている。
【００２１】
銅箔配線４６の他端は、スルーホール５０に接続されている。搭載箇所４９の底部には例えば絶縁ペースト５１が塗布され、該搭載箇所４９に、第１の半導体チップ４８が電極面とは反対の背面を向けて搭載されている。半導体チップ４８の電極と銅箔配線４３とが第１の接続部材であるボンディングワイヤ５２で接続され、該半導体チップ４８の搭載されているキャビティ部分が、第１の封止樹脂のエポキシ樹脂５３によって封止されている。複数の半田ボール５４が基板５０の表面側に例えば格子状に配置されている。各銅箔配線４３のソルダーレジスト４７の開口した部分に、半田ボール５４が形成され、さらに、各スルーホール５０も半田ボール５４に接続されている。
【００２２】
以上のような基板４０の裏面側に、第２の接続部材である金バンプ５５が電極に突設された第２の半導体チップ５６が搭載されている。この場合、半導体チップ５６の電極が金バンプで銅箔配線４６に接続されているので、基板４０の裏面側に該半導体チップ５６の電極面が対向している。基板４０の裏面側と半導体チップ５６の電極面との間が、第２の封止樹脂５７によって封止されている。
【００２３】
図８（ａ）〜（ｄ）は、図６のＢＧＡパッケージの製造工程の概要を示す断面図である。この第２の実施形態のＢＧＡパッケージは、図８（ａ）〜（ｄ）の工程により、製造される。まず、図８の（ａ）の工程において、パターン形成処理により、銅板４１にスルーホール５０を形成し、銅板４１の表面側に絶縁材４２を貼付け、その上に銅箔配線４３を形成し、銅板４１の裏面側に絶縁材４５を貼付け、さらに、該絶縁材４５の上に銅箔配線４６を形成する。銅箔配線４３，４６の必要部分にソルダーレジスト４４，４７を塗布した後、第１の搭載処理により、半導体チップ４８を搭載箇所４９に固着し、該半導体チップ４８の電極をボンディングワイヤ５２で銅箔配線４３と接続する。そして、第１の封止処理を行い、半導体チップ４８の電極面をエポキシ樹脂５３で封止する。一方、半導体チップ５６の電極面の電極には、金バンプ５５を突設させておく。
【００２４】
図８（ｂ）の工程において、第２の搭載処理により、半導体チップ５６の電極面を銅板４１の裏面に対向させて金バンプ５５をランド４６ａに当接し、熱圧着法によって接続する。さらに、半導体チップ５６の電極面と銅板４１の裏面側との間に、液状の樹脂５７を側面から注入する。図８（ｃ）の工程において、第２の封止処理を行い、加熱により、注入した樹脂５７を硬化させ、半導体チップ５６の電極面を封止する。図８（ｄ）の工程において、銅板４１の表面側の銅箔配線４３及びスルーホール５０の該表面側に半田ボール５４を形成する。半導体チップ４８，５６が搭載された図７のＢＧＡパッケージでは、信号が半田ボール５４及び銅箔配線４３を介して半導体チップ４８に入出力されるばかりでなく、半田ボール５４、スルーホール５０及び銅箔配線４６を介して信号が半導体チップ５４に入出力される。
【００２５】
以上のように、この第２の実施形態では、銅板４１の裏面側に形成された銅泊配線４６とスルーホール５０とを設け、銅板４１の裏面側に搭載した半導体チップ４６の電極を表面側に配列した半田ボール５４に接続したので、半導体チップ４８に接続できなかった半田ボール５４を半導体チップ５６の端子として有効に使用することができる。また、半導体チップ４８と半導体チップ５６とを銅板４１の両側に搭載するので、マザーボードに実装する時の実装面積を低減でき、マザーボードの面積も小さくできる。さらに、半導体チップ５６の搭載を金バンプ５５にて行うので、第１の実施形態よりも短時間で接続できる。
【００２６】
第３の実施形態図９（ａ）〜（ｄ）は、本発明の第３の実施形態を示すＢＧＡパッケージの製造方法の断面図であり、第２の実施形態の図６中の要素と共通の要素には共通の符号が付されている。
【００２７】
この第３の実施形態では、図６と同様のＢＧＡパッケージに対する第２の実施形態とは異なる製造方法を説明する。まず、図９（ａ）の工程において、パターン形成処理を行い、銅板４１の表面側に絶縁材４２を貼付け、その上に銅箔配線４３を形成し、銅板４１の裏面側に絶縁材４５を貼付け、該絶縁材４５の上に銅箔配線４６を形成し、さらに、スルーホール５０も基材４１に形成する。銅箔配線４３，４６の必要部分にソルダーレジスト４４，４７を塗布する。また、貫通孔形成処理を行い、銅板４１の表面側から裏面側に貫通する孔６０を、半導体チップ５６の搭載予定位置の中央に形成しておく。一方、半導体チップ５６の電極面の電極には、金バンプ５５を突設させておく。
【００２８】
図９（ｂ）の工程において、第１の搭載処理により、半導体チップ５６の電極面を銅板４１の裏面に対向させて金バンプ５５をランド４６ａに当接し、熱圧着法によって接続する。そして、孔６０を介して液状の樹脂５７を半導体チップ５６の電極面と基板４０の裏面側との間に注入する。図９（ｃ）の工程において、第１の封止処理を行い、液状の樹脂５７を加熱硬化させ、半導体チップ５６の電極面を封止する。
【００２９】
図９（ｄ）の工程において、第２の搭載処理により、半導体チップ４８を搭載箇所４９に固着し、該半導体チップ４８の電極をボンディングワイヤ５２で銅箔配線４３と接続する。そして、第２の封止処理を行い、半導体チップ４８の電極面をエポキシ樹脂５３で封止する。図９（ｅ）の工程において、半田ボール形成処理により、銅板４１の表面側の銅箔配線４３及びスルーホール５０の該表面側に半田ボール５４を形成する。
【００３０】
以上のように、この第３の実施形態では、第２の実施形態と同様に、銅板４１の裏面側に形成された銅泊配線４６とスルーホール５０とを設け、銅板４１の裏面側に搭載した半導体チップ４６の電極を表面側に配列した半田ボール５４に接続したので、半導体チップ４８に接続できなかった半田ボール５４を半導体チップ５６の端子として有効に使用することができる。半導体チップ４８と半導体チップ５６とを銅板４１の両側に搭載するので、マザーボードに実装する時の実装面積を低減でき、マザーボードの面積も小さくできる。さらに、半導体チップ５６の搭載を金バンプ５５にて行うので、第１の実施形態よりも短時間で接続できる。その上、樹脂５７が貫通孔６０から注入されるので、該樹脂５７が均一に分布し、完成後の熱応力による樹脂５７の膨脹収縮が原因で、半導体チップ５６の接続信頼性が劣化することを、予防できる。
【００３１】
第４の実施形態図１０（ａ）〜（ｃ）は、本発明の第４の実施形態を示すＢＧＡパッケージの製造方法の断面図であり、第２の実施形態の図６中の要素と共通の要素には共通の符号が付されている。この第３の実施形態では、図６と同様のＢＧＡパッケージに対する第２の実施形態とは異なる製造方法を説明する。まず、図１０（ａ）の工程において、パターン形成処理を行い、銅板４１の表面側に絶縁材４２を貼付け、その上に銅箔配線４３を形成し、銅板４１の裏面側に絶縁材４５を貼付け、該絶縁材４５の上に銅箔配線４６を形成し、スルーホール５０も基材４１に形成する。銅箔配線４３，４６の必要部分にソルダーレジスト４４，４７を塗布する。ここで、第１の搭載処理により、半導体チップ４８を搭載箇所４９に固着し、該半導体チップ４８の電極をボンディングワイヤ５２で銅箔配線４３と接続する。そして、第１の封止処理を行い、半導体チップ４８の電極面をエポキシ樹脂５３で封止する。一方、半導体チップ５６の電極面の電極には、金バンプ５５を突設させておくと共に、テープ状に形成された樹脂５７を用意する。
【００３２】
図１０（ｂ）の工程において、テープ載置処理により、基板４０の裏面側の半導体チップ５６の搭載予定領域にテープ状の樹脂５７を載置し、続いて、第２の搭載処理を行い、半導体チップ５６の電極面を銅板４１の裏面に対向させて金バンプ５５をランド４６ａに当接し、熱圧着法によって接続する。このとき、第２の封止処理が同時に行われ、テープ状の樹脂５７が加熱されて溶融して硬化するる。よって、半導体チップ５６の電極面が封止される。図１０（ｃ）の工程において、銅板４１の表面側の銅箔配線４３及びスルーホール５０の該表面側に半田ボール５４を形成する。
【００３３】
以上のように、この第４の実施形態では、第２及び第３の実施形態と同様に、銅板４１の裏面側に形成された銅泊配線４６とスルーホール５０とを設け、銅板４１の裏面側に搭載した半導体チップ４６の電極を表面側に配列した半田ボール５４に接続したので、半田ボール５４を半導体チップ５６の端子として有効に使用することができると共に、マザーボードに実装する時の実装面積を低減でき、マザーボードの面積も小さくできる。その上、半導体チップ５６の搭載を金バンプ５５にて行うので、第１の実施形態よりも短時間で接続できる。さらに、半導体チップ５６の封止を、バンプ５５の接続と同時にできるので、第２及び第３の実施形態よりも、短時間で封止できることなる。
【００３４】
第５の実施形態図１１は、本発明の第５の実施形態を示すＢＧＡパッケージの断面図である。図１２（ａ），（ｂ）は、図１１のＢＧＡパッケージのベースとなる基板７０を示す図であり、図１１中の要素と共通の要素には共通の符号が付されている。このＢＧＡパッケージのベースとなる基板７０は、第１の実施形態と同様の銅板７１が基材として用いられ、該銅板７１の表面側には、厚さ１０〜３０μｍの絶縁材７２が貼付けられている。絶縁材７２の上に、厚さ１２〜３５μｍの第１の配線パターンである銅箔配線７３が形成されている。銅箔配線７３の上部は、一部を残してソルダーレジスト７４が塗布されている。
【００３５】
銅板７１の裏面側には、図１２（ｂ）のように、厚さ１０〜３０μｍのポリイミド等からなる絶縁材７５が貼付けられ、該絶縁材７５の上に、厚さ１２〜３５μｍの第２の配線パターンである銅箔配線７６が形成されている。銅箔配線７６の上は、一部を残してソルダーレジスト７７が塗布されている。金型絞り加工により、銅板７１の表面側に第１の半導体チップ７８の搭載箇所７９が凹状に形成されている。銅板７１には、さらに、表面と裏面をつなぐスルーホール８０が形成されている。銅箔配線７３の一端が、ボンディングワイヤに接続されるボンディングポスト７３ａになっている。裏面側の銅箔配線７６の一端が半田ボール接続用ランド７６ａになっており、例えば該ランド７６ａは、例えば耐熱性プリフラックスがコートされている。
【００３６】
銅箔配線７６の他端は、スルーホール８０に接続されている。搭載箇所７９の底部には例えば絶縁ペースト８１が塗布され、該搭載箇所７９に、第１の半導体チップ７８が電極面とは反対の背面を向けて搭載されている。半導体チップ７８の電極と銅箔配線７３とが第１の接続部材であるボンディングワイヤ８２で接続され、該半導体チップ７８の搭載されているキャビティ部分が、第１の封止樹脂のエポキシ樹脂８３によって封止されている。複数の半田ボール８４が基板８０の表面側に例えば格子状に配置されている。各銅箔配線７３のソルダーレジスト７７の開口した部分に、半田ボール８４が形成され、さらに、各スルーホール８０も半田ボール８４に接続されている。
【００３７】
以上のような基板７０の裏面側に、第２の接続部材となる半田ボール８５のみが電極面から露出したチップ・サイズ・パッケージ等の半導体装置８６が搭載されている。半導体装置８６の端子が半田ボール８５で銅箔配線７６のランド７６ａに接続されている。このようなＢＧＡパッケージを製造する場合には、半導体装置８６の半田ボール８５を加熱リフローしては、該半導体装置８６の端子を銅箔配線７６のランド７６ａに接続し、最後に、半田ボール８４を形成することにより、半田ボール８４の変形が防止される。
【００３８】
以上のように、この第５の実施形態では、銅板７１の裏面側に形成された銅泊配線７６とスルーホール８０とを設け、銅板７１の裏面側に搭載した半導体装置８６の端子を表面側に配列した半田ボール８４に接続したので、半導体チップ７８に接続できなかった半田ボール８４を半導体装置８６の端子として有効に使用することができる。その上，半導体装置８６は、事前に封止されているので、第２から第４の実施形態では必要であった樹脂５７が不要であり、部材費の低減が可能である。なお、本発明は、上記実施形態に限定されず種々の変形が可能である。例えば、第１、第２及び第４の実施形態では、基板２０，４０の表面側の半導体チップ２８，４８をよりも先に搭載しているが、逆に、半導体チップ３６，５６を先に搭載するようにしていもよい。
【００３９】
【発明の効果】
以上詳細に説明したように、第１から第７の発明によれば、基材に形成されたスルーホールと、該基材の裏面側に形成された第２の配線パターンとを有すると共に、基材の表面側に第１の半導体チップを搭載し、基材の裏面側に第２の半導体チップまたは半導体装置を搭載し、該第２の半導体チップまたは半導体装置の電極或いは端子を第２の配線パターン及びスルーホールを介して半田ボールと接続したので、第１の半導体チップに接続できなかった半田ボール、つまり、余剰端子を第２の半導体チップまたは半導体装置の端子として有効に使用することができる。マザーボードに実装する時の実装面積を低減でき、マザーボードの面積も小さくできる。
【００４０】
第８から第１２の発明によれば、第１の半導体チップを基板の表面に搭載し、第２の半導体チップを基板の裏面に搭載し、これら第１及び第２の半導体チップの信号の入出力が、共に基板の表面に形成された第１及び第２の外部電極で行うようにしたので、マザーボードに実装する時の実装面積を低減でき、マザーボードの面積を小さくできる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示すＢＧＡパッケージの断面図である。
【図２】従来のＢＧＡパッケージの一例を示す断面図である。
【図３】従来のＢＧＡパッケージの他の例を示す断面図である。
【図４】図２及び図３のＢＧＡパッケージの課題の説明図である。
【図５】図１のＢＧＡパッケージのベースとなる基板２０を示す図である。
【図６】本発明の第２の実施形態を示すＢＧＡパッケージの断面図である。
【図７】図６のＢＧＡパッケージのベースとなる基板４０を示す図である。
【図８】図６のＢＧＡパッケージの製造工程の概要を示す断面図である。
【図９】本発明の第３の実施形態を示すＢＧＡパッケージの製造方法の断面図である。
【図１０】本発明の第４の実施形態を示すＢＧＡパッケージの製造方法の断面図である。
【図１１】本発明の第５の実施形態を示すＢＧＡパッケージの断面図である。
【図１２】図１１のＢＧＡパッケージのベースとなる基板７０を示す図である。
【符号の説明】
２１，４１，７１ 銅板
２３，２６，４３，４６，７３，７６ 銅箔配線
２８，３６，４８，５６ 半導体チップ
３０，５０，８０ スルーホール
３２，３７，４２，８２ ボンディングワイヤ
３４，５４，８４ 半田ボール
６０ 貫通孔
８６ 半導体装置[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a ball grid array (hereinafter referred to as BGA package) package.
[0002]
[Prior art]
2A and 2B are cross-sectional views showing an example of a conventional BGA package. FIGS. 3A and 3B are cross-sectional views showing other examples of the conventional BGA package. Elements common to those in FIG. 2 are denoted by common reference numerals. In a BGA package considering general heat dissipation, an insulating material 2 made of polyimide or the like having a thickness of 10 to 30 μm is attached to a copper plate 1 having a thickness of 0.3 to 0.4 mm. A copper foil wiring 3 having a thickness of 12 to 35 μm is formed on the insulating material 2. On the surface side of the copper plate 1, as shown in FIG. 2, the mounting portion 5a of the semiconductor chip 4 is formed by cutting or the mounting portion 5b of the semiconductor chip 4 is formed by die drawing as shown in FIG. The substrate is configured.
[0003]
The semiconductor chip 4 has an electrode surface on which electrodes are formed and a back surface on the opposite side. Conductive or insulating paste 6 is applied to the bottoms of the mounting locations 5a and 5b, and the semiconductor chip 4 is fixed thereto with the back side facing. The electrode of the semiconductor chip 4 and the copper foil wiring 3 are connected by the bonding wire 7, and the cavity portion on which the semiconductor chip 4 is mounted is filled with the epoxy resin 8. Solder balls 9 are attached in a grid pattern on the surface side of the substrate where there is no epoxy resin 8. A portion where the epoxy resin 8 and the solder balls 9 are not present on the surface side of the substrate is covered with a resist film 10. In some cases, as shown in FIG. 3, the insulating material 11 is attached to the back side of the substrate as a countermeasure against warping or contamination prevention of the substrate after sealing.
[0004]
[Problems to be solved by the invention]
However, the conventional BGA package of FIGS. 2 and 3 has the following problems. FIGS. 4A and 4B are explanatory diagrams of the problems of the BGA package of FIGS. In order to cope with the increase in the number of pins, when the number of rows of grid-like terminals made of solder balls 9 is increased or the pitch of the terminals is reduced, the width of the copper foil wiring 3 is increased as shown in FIG. Due to the restriction from the gap, a large number of surplus terminals 13 that are not connected to the bonding posts 12 connected to the electrodes of the semiconductor chip 4 by the bonding wires 7 are generated. Further, even if the BGA package of FIG. 2 or FIG. 3 is to be mounted on the mother board 14 as shown in FIG. 4B, the mounting area increases because the external dimensions of the BGA package increase with the increase in the number of pins. Therefore, it is necessary to increase the size of the mother board 14.
[0005]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, a first invention of the present invention is configured as follows in a BGA package. That is, it has a plate-like substrate having a front surface and a back surface, an electrode surface on which an electrode is formed, and a back surface on the opposite side of the electrode surface that does not have the electrode, and the back surface is fixed to the surface side of the substrate A first semiconductor chip formed, a plurality of solder balls arranged on the surface side of the base material, and a first conductive chip formed on the surface side of the base material and electrically connected to some of the plurality of solder balls. 1 wiring pattern, the 1st connection member which connects the electrode of a 1st semiconductor chip, and the 1st wiring pattern, the 2nd wiring pattern formed in the back surface side of a substrate, an electrode surface, and the back An arbitrary number of second semiconductor chips mounted on the back side of the substrate, a second connection member for connecting the electrode of the second semiconductor chip and the second wiring pattern, and a base material Of the plurality of solder balls on the front surface side of the substrate and the second solder ball on the back surface side of the substrate. A through hole connecting the wiring pattern, a first sealing member for sealing the electrode surface of the first semiconductor chip, and a second sealing member for sealing the electrode surface of the second semiconductor chip. Have.
[0006]
In the second invention, the second semiconductor chip in the first invention has the back surface fixed to the back surface side of the base material, and the second connecting member is constituted by a bonding wire. In a third invention, the second connecting member in the first invention is composed of a plurality of bumps protruding from the electrodes of the second semiconductor chip, and the second semiconductor chip has the electrode side on the back surface of the base material The electrodes are connected to the second wiring pattern by bumps.
[0007]
The fourth invention has the following configuration in the BGA package. That is, it has a plate-like substrate having a front surface and a back surface, an electrode surface on which an electrode is formed, and a back surface on the opposite side of the electrode surface that does not have the electrode, and the back surface is fixed to the surface side of the substrate A first semiconductor chip formed, a plurality of solder balls arranged on the surface side of the base material, and a first conductive chip formed on the surface side of the base material and electrically connected to some of the plurality of solder balls. 1 wiring pattern, a first connecting member for connecting the electrode of the first semiconductor chip and the first wiring pattern, a second wiring pattern formed on the back side of the substrate, and only the terminals are exposed. And any number of other semiconductor devices that are already sealed, a second connection member that connects the terminal of the semiconductor device and the second wiring pattern, and a plurality of semiconductor devices formed on the base, The second wiring pattern on the back side of the base material is connected to the remaining solder balls of the solder balls And a first sealing member for sealing the Horu, the electrode surface of the first semiconductor chip.
[0008]
The fifth invention employs the following manufacturing method in the manufacturing method of the BGA package for manufacturing the BGA package of the third invention. That is, a through hole is formed in a plate-like base material having a front surface and a back surface, a first wiring pattern is formed on the front surface side of the base material, and a second having conduction with the through hole on the back surface side of the base material. First, a pattern forming process for forming the wiring pattern is performed. Then, after the pattern formation process, the first semiconductor chip having the electrode surface on which the electrode is formed and the back surface not having the electrode on the opposite side of the electrode surface is fixed with the back surface facing the surface side of the substrate. Then, a first mounting process for connecting the electrode of the first semiconductor chip and the first wiring pattern with a first connecting member, and sealing the electrode surface of the first semiconductor chip with a first sealing resin. The first sealing process to be stopped, the first mounting process after the pattern forming process, and the first sealing process before or after the first sealing process, the electrode is formed on the opposite side of the electrode surface and the electrode surface. A second semiconductor chip having a back surface that does not have a conductive bump on the electrode, the electrode surface facing the back surface of the substrate, and heating the bump to the second wiring pattern A second mounting process for mounting the second semiconductor chip on the substrate by pressure bonding; A liquid second sealing resin is injected between the second semiconductor chip and the base material from the side of the second semiconductor chip, and the liquid second sealing resin is cured to form a second semiconductor. Second sealing process for sealing the electrode surface of the chip, and solder ball forming process for forming a solder ball having conductivity with the first wiring pattern and a solder ball having conductivity with the through hole on the surface side of the substrate And do.
[0009]
The sixth invention employs the following manufacturing method in the manufacturing method of the BGA package for manufacturing the BGA package of the third invention. That is, a through-hole is formed in a plate-like base material having a front surface and a back surface, a first wiring pattern is formed on the front surface side of the base material, and conduction is provided to the through hole on the back surface side of the base material. A pattern forming process for forming a second wiring pattern, and a through hole forming process for forming a hole penetrating from the front surface to the back surface in the second semiconductor chip mounting planned region of the base material before or after the pattern forming process. Do. Then, after the pattern formation process and the through hole formation process, the electrode surface on which the electrode was formed and the back surface having no electrode on the opposite side of the electrode surface, and the conductive bumps protruded from the electrode A first mounting process for mounting the second semiconductor chip on the base material by causing the electrode surface side to face the back side of the base material and heat-bonding the bumps to the second wiring pattern. And injecting a liquid second sealing resin through the hole between the electrode surface of the second semiconductor chip and the back surface of the base material to cure the second liquid sealing resin A first sealing process for sealing an electrode surface of a semiconductor chip; and an electrode surface on which an electrode is formed after the first sealing process and a back surface having no electrode on the opposite side of the electrode surface. 1 semiconductor chip is fixed with the back surface facing the front surface side of the substrate, and the first semiconductor chip electrode and the first semiconductor chip A second mounting process for connecting the line pattern with the first connecting member; a first sealing process for sealing the electrode surface of the first semiconductor chip with the first sealing resin; and a surface of the substrate. On the side, a solder ball forming process for forming a solder ball having electrical continuity with the first wiring pattern and a solder ball having electrical continuity with the through hole is performed.
[0010]
The seventh invention employs the following manufacturing method in the manufacturing method of the BGA package for manufacturing the BGA package of the third invention. That is, a through hole is formed in a plate-like base material having a front surface and a back surface, a first wiring pattern is formed on the front surface side of the base material, and the second hole having conduction to the through hole on the back surface side of the base material. A pattern forming process for forming a wiring pattern is performed. Then, after the pattern formation process, the first semiconductor chip having the electrode surface on which the electrode is formed and the back surface not having the electrode on the opposite side of the electrode surface is fixed with the back surface facing the surface side of the substrate. Then, a first mounting process for connecting the electrode of the first semiconductor chip and the first wiring pattern with the first connecting member, and sealing the electrode surface of the first semiconductor chip with the first sealing resin Before or after the first sealing process, the first mounting process after the pattern forming process, and the first sealing process, the second semiconductor chip mounting region of the substrate A tape mounting process for placing a sealing resin; an electrode surface on which an electrode is formed; and a back surface not having the electrode on the opposite side of the electrode surface; and a conductive bump protruding from the electrode. 2 with the electrode side facing the back side of the base material and the bumps on the second wiring pattern A second mounting process for mounting the second semiconductor chip on the base material by thermocompression bonding is performed simultaneously with the second mounting process. After the second sealing resin is melted and cured, the second semiconductor chip of the second semiconductor chip is cured. A second sealing step for sealing the electrode surface, and a solder ball forming step for forming a solder ball having electrical continuity with the first wiring pattern and a solder ball having electrical continuity with the through hole on the surface side of the substrate. To do.
[0011]
According to the first to seventh inventions, since the BGA package and the method for manufacturing the BGA package are configured as described above, the first semiconductor chip is mounted on the front surface side of the base material, and the back surface of the base material A second semiconductor chip or semiconductor device is mounted on the side. The electrodes of the second semiconductor chip or the terminals of the semiconductor device are connected to the solder balls on the surface side of the substrate through the second wiring pattern and the through holes. Therefore, the solder balls are used for signal input / output to / from the second semiconductor chip or semiconductor device.
[0012]
According to an eighth aspect of the present invention, in the semiconductor device, a substrate having a front surface and a back surface, a first external electrode formed on the surface of the substrate, a first external electrode mounted on the surface of the substrate A first semiconductor chip electrically connected to the substrate, a second external electrode formed on the front surface of the substrate, a second external electrode mounted on the back surface of the substrate, and a through formed in the substrate And a second semiconductor chip electrically connected through a hole.
[0013]
According to a ninth invention, in the semiconductor device according to the eighth invention, the first semiconductor device is electrically connected to the first external electrode through the first wiring pattern formed on the surface of the substrate. The second semiconductor chip is configured to be electrically connected to the second external electrode through a second wiring pattern formed on the back surface of the substrate.
[0014]
According to a tenth aspect, the second external electrode in the semiconductor device according to the eighth aspect is substantially provided in the vicinity of the corner portion of the substrate. According to an eleventh aspect, in the semiconductor device according to the eighth aspect, a recess is formed in the substrate, and the first semiconductor chip is disposed in the recess. According to a twelfth aspect, in the semiconductor device according to the eighth aspect, the first external electrode and the second external electrode are formed of solder balls. According to the eighth to twelfth aspects, since the semiconductor device is configured as described above, the first external electrode and the second external electrode are formed on the surface of the substrate. A first semiconductor chip is mounted on the front surface of the substrate, and a second semiconductor chip is mounted on the back surface. The first semiconductor chip is electrically connected to the first external electrode, and the second semiconductor chip is electrically connected to the second external electrode through a through hole. Therefore, the second external electrode formed on the surface of the substrate is used for input / output of signals to the second semiconductor chip.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment FIG. 1 is a cross-sectional view of a BGA package showing a first embodiment of the present invention. FIGS. 5A to 5C are diagrams showing a substrate 20 serving as a base of the BGA package of FIG. 1, and common elements to those in FIG. 1 are denoted by common reference numerals. A copper plate 21 having a thickness of 0.3 to 0.4 mm is used as a base material for the substrate 20 serving as a base of the BGA package. An insulating material 22 made of polyimide or the like having a thickness of 10 to 30 μm is pasted on the surface side of the copper plate 21 as in the past, and a copper that is a first wiring pattern having a thickness of 12 to 35 μm is formed on the insulating material 22. A foil wiring 23 is formed. An upper portion of the copper foil wiring 23 is coated with a solder resist 24 except for a part. As shown in FIG. 5B, an insulating material 25 made of polyimide or the like having a thickness of 10 to 30 μm is attached to the back surface side of the copper plate 21, and a second 12 to 35 μm thick second material is formed on the insulating material 25. A copper foil wiring 26 which is a wiring pattern is formed. On the copper foil wiring 26, a solder resist 27 is applied leaving a part.
[0016]
For example, the mounting portion 29 of the first semiconductor chip 28 is formed in a concave shape on the surface side of the copper plate 21 by die drawing. The copper plate 21 is further formed with a through hole 30 that connects the front surface and the back surface. The through hole 30 is insulated from the copper plate 21. One end of each copper foil wiring 23, 26 is a bonding post 25a, 26a connected to a bonding wire described later. The other end of the copper foil wiring 26 on the back side is connected to the through hole 30. For example, an insulating paste 31 is applied to the mounting location 29, and the semiconductor chip 28 is fixed to the mounting location 29 with the back surface opposite to the electrode surface facing. The electrode of the semiconductor chip 28 and the copper foil wiring 23 are connected by a bonding wire 32 which is a first connecting member, and the cavity portion on which the semiconductor chip 28 is mounted is formed by an epoxy resin 33 which is a first sealing resin. It is sealed. On the surface side of the substrate 20, a plurality of solder balls 34 are arranged, for example, in a lattice shape. A solder ball 34 is formed in the opening portion of the solder resist 27 of the copper foil wiring 23, and each through hole 30 is also formed to be electrically connected to the solder ball 34.
[0017]
A conductive or insulating paste 35 is applied to a part of the back side of the substrate 20, and the second semiconductor chip 36 is mounted as shown in FIG. 1, and the back surface of the semiconductor chip 36 is fixed by the paste 35. Has been. The electrode of the semiconductor chip 36 and the bonding post 26a of the copper foil wiring 26 are connected by a bonding wire 37 that is a second connecting member. The semiconductor chip 36 is also sealed with an epoxy resin 38 which is a second sealing resin. In the BGA package of FIG. 1 on which the semiconductor chips 28 and 36 are mounted, not only signals are input to and output from the semiconductor chip 28 via the solder balls 34 and the copper foil wiring 23, but also the solder balls 34, the through holes 30 and the copper. Signals are input to and output from the semiconductor chip 36 through the foil wiring 26.
[0018]
As described above, in the first embodiment, the copper retaining wires 23 and 26 are formed on both the front surface side and the back surface side of the base material 21, and the through holes 30 are provided in the base material 21. Since the electrodes of the semiconductor chip 36 mounted on the back surface side of the semiconductor chip 36 are connected to the solder balls 34 arranged on the front surface side, the solder balls 34 that cannot be connected to the semiconductor chip 28, that is, surplus terminals are effectively used as the terminals of the semiconductor chip 36. Can be used. Further, since the semiconductor chip 28 and the semiconductor chip 36 are mounted on both sides of the base member 21, the mounting area when mounted on the mother board can be reduced, and the area of the mother board can also be reduced.
[0019]
Second Embodiment FIG. 6 is a sectional view of a BGA package showing a second embodiment of the present invention. FIGS. 7A and 7B are views showing a substrate 40 that is a base of the BGA package of FIG. 6, and common elements to those in FIG. 6 are denoted by common reference numerals. The substrate 40 serving as the base of the BGA package uses a copper plate 41 similar to that of the first embodiment as a base material, and an insulating material 42 having a thickness of 10 to 30 μm is attached to the surface side of the copper plate 41. Yes. On the insulating material 42, a copper foil wiring 43 that is a first wiring pattern having a thickness of 12 to 35 μm is formed. The upper part of the copper foil wiring 43 is coated with a solder resist 44 leaving a part.
[0020]
As shown in FIG. 7B, an insulating material 45 made of polyamide or the like having a thickness of 10 to 30 μm is attached to the back surface side of the copper plate 41, and a second 12 to 35 μm thick second material is formed on the insulating material 45. The copper foil wiring 46 which is the wiring pattern is formed. On the copper foil wiring 46, a solder resist 47 is applied leaving a part. A mounting portion 49 of the first semiconductor chip 48 is formed in a concave shape on the surface side of the copper plate 41 by die drawing. The copper plate 41 is further formed with a through hole 50 that is insulated from the copper plate 41 and connects the front surface side and the back surface side. One end of the copper foil wiring 43 is a bonding post 43a connected to the bonding wire. One end of the copper foil wiring 46 on the back surface is a land 46a connected to a gold bump, which will be described later. For example, the land 46a is plated with Ni and further plated with gold. Yes.
[0021]
The other end of the copper foil wiring 46 is connected to the through hole 50. For example, an insulating paste 51 is applied to the bottom of the mounting location 49, and the first semiconductor chip 48 is mounted on the mounting location 49 with the back surface opposite to the electrode surface facing. The electrode of the semiconductor chip 48 and the copper foil wiring 43 are connected by a bonding wire 52 as a first connecting member, and the cavity portion on which the semiconductor chip 48 is mounted is formed by an epoxy resin 53 of the first sealing resin. It is sealed. A plurality of solder balls 54 are arranged on the surface side of the substrate 50 in, for example, a lattice shape. Solder balls 54 are formed in the openings of the solder resists 47 of the copper foil wirings 43, and the through holes 50 are also connected to the solder balls 54.
[0022]
On the back side of the substrate 40 as described above, the second semiconductor chip 56 in which the gold bump 55 as the second connecting member is provided protruding from the electrode is mounted. In this case, since the electrodes of the semiconductor chip 56 are connected to the copper foil wiring 46 by gold bumps, the electrode surface of the semiconductor chip 56 faces the back side of the substrate 40. A space between the back surface of the substrate 40 and the electrode surface of the semiconductor chip 56 is sealed with a second sealing resin 57.
[0023]
8A to 8D are cross-sectional views showing an outline of the manufacturing process of the BGA package of FIG. The BGA package according to the second embodiment is manufactured by the steps shown in FIGS. First, in the step of FIG. 8A, through holes 50 are formed in the copper plate 41 by pattern formation processing, the insulating material 42 is pasted on the surface side of the copper plate 41, and the copper foil wiring 43 is formed thereon, An insulating material 45 is attached to the back side of the copper plate 41, and a copper foil wiring 46 is formed on the insulating material 45. After the solder resists 44 and 47 are applied to the necessary portions of the copper foil wirings 43 and 46, the semiconductor chip 48 is fixed to the mounting location 49 by the first mounting process, and the electrodes of the semiconductor chip 48 are bonded to the copper by the bonding wires 52. Connect to the foil wiring 43. Then, a first sealing process is performed, and the electrode surface of the semiconductor chip 48 is sealed with the epoxy resin 53. On the other hand, gold bumps 55 are projected from the electrodes on the electrode surface of the semiconductor chip 56.
[0024]
In the step of FIG. 8B, the gold bump 55 is brought into contact with the land 46a with the electrode surface of the semiconductor chip 56 facing the back surface of the copper plate 41 by the second mounting process, and is connected by the thermocompression bonding method. Further, a liquid resin 57 is injected from the side surface between the electrode surface of the semiconductor chip 56 and the back surface side of the copper plate 41. In the step of FIG. 8C, a second sealing process is performed, and the injected resin 57 is cured by heating, and the electrode surface of the semiconductor chip 56 is sealed. 8D, solder balls 54 are formed on the copper foil wiring 43 on the surface side of the copper plate 41 and on the surface side of the through hole 50. In the step of FIG. In the BGA package of FIG. 7 in which the semiconductor chips 48 and 56 are mounted, not only signals are input to and output from the semiconductor chip 48 via the solder balls 54 and the copper foil wiring 43, but also the solder balls 54, the through holes 50, and the copper. Signals are input to and output from the semiconductor chip 54 via the foil wiring 46.
[0025]
As described above, in the second embodiment, the copper stay wiring 46 and the through hole 50 formed on the back surface side of the copper plate 41 are provided, and the electrodes of the semiconductor chip 46 mounted on the back surface side of the copper plate 41 are provided on the front surface side. Therefore, the solder balls 54 that could not be connected to the semiconductor chip 48 can be used effectively as the terminals of the semiconductor chip 56. Moreover, since the semiconductor chip 48 and the semiconductor chip 56 are mounted on both sides of the copper plate 41, the mounting area when mounted on the mother board can be reduced, and the area of the mother board can also be reduced. Furthermore, since the semiconductor chip 56 is mounted by the gold bumps 55, the connection can be made in a shorter time than in the first embodiment.
[0026]
Third Embodiment FIGS. 9A to 9D are sectional views of a method for manufacturing a BGA package showing a third embodiment of the present invention, and are common to the elements in FIG. 6 of the second embodiment. These elements are denoted by common reference numerals.
[0027]
In the third embodiment, a manufacturing method different from that of the second embodiment for a BGA package similar to that of FIG. 6 will be described. First, in the process of FIG. 9A, pattern formation processing is performed, the insulating material 42 is pasted on the front surface side of the copper plate 41, the copper foil wiring 43 is formed thereon, and the insulating material 45 is formed on the back surface side of the copper plate 41. The copper foil wiring 46 is formed on the insulating material 45 and the through holes 50 are also formed in the base material 41. Solder resists 44 and 47 are applied to necessary portions of the copper foil wirings 43 and 46. Further, a through hole forming process is performed, and a hole 60 penetrating from the front surface side to the back surface side of the copper plate 41 is formed at the center of the planned mounting position of the semiconductor chip 56. On the other hand, gold bumps 55 are projected from the electrodes on the electrode surface of the semiconductor chip 56.
[0028]
9B, in the first mounting process, the gold bump 55 is brought into contact with the land 46a with the electrode surface of the semiconductor chip 56 opposed to the back surface of the copper plate 41, and is connected by the thermocompression bonding method. Then, liquid resin 57 is injected between the electrode surface of the semiconductor chip 56 and the back surface side of the substrate 40 through the hole 60. In the step of FIG. 9C, a first sealing process is performed to heat and cure the liquid resin 57 and seal the electrode surface of the semiconductor chip 56.
[0029]
In the step of FIG. 9D, the semiconductor chip 48 is fixed to the mounting location 49 by the second mounting process, and the electrode of the semiconductor chip 48 is connected to the copper foil wiring 43 by the bonding wire 52. Then, a second sealing process is performed, and the electrode surface of the semiconductor chip 48 is sealed with the epoxy resin 53. 9E, solder balls 54 are formed on the copper foil wiring 43 on the surface side of the copper plate 41 and on the surface side of the through holes 50 by a solder ball forming process.
[0030]
As described above, in the third embodiment, the copper stay wiring 46 and the through hole 50 formed on the back surface side of the copper plate 41 are provided and mounted on the back surface side of the copper plate 41 as in the second embodiment. Since the electrodes of the semiconductor chip 46 are connected to the solder balls 54 arranged on the surface side, the solder balls 54 that cannot be connected to the semiconductor chip 48 can be used effectively as terminals of the semiconductor chip 56. Since the semiconductor chip 48 and the semiconductor chip 56 are mounted on both sides of the copper plate 41, the mounting area when mounted on the mother board can be reduced, and the area of the mother board can also be reduced. Furthermore, since the semiconductor chip 56 is mounted by the gold bumps 55, the connection can be made in a shorter time than in the first embodiment. In addition, since the resin 57 is injected from the through hole 60, the resin 57 is uniformly distributed, and the connection reliability of the semiconductor chip 56 is deteriorated due to the expansion and contraction of the resin 57 due to the thermal stress after completion. Can be prevented.
[0031]
Fourth Embodiment FIGS. 10A to 10C are sectional views of a method for manufacturing a BGA package showing a fourth embodiment of the present invention, and are common to the elements in FIG. 6 of the second embodiment. These elements are denoted by common reference numerals. In the third embodiment, a manufacturing method different from that of the second embodiment for a BGA package similar to that of FIG. 6 will be described. First, in the process of FIG. 10A, a pattern forming process is performed, an insulating material 42 is pasted on the front surface side of the copper plate 41, a copper foil wiring 43 is formed thereon, and an insulating material 45 is formed on the back surface side of the copper plate 41. The copper foil wiring 46 is formed on the insulating material 45 and the through holes 50 are also formed in the base material 41. Solder resists 44 and 47 are applied to necessary portions of the copper foil wirings 43 and 46. Here, by the first mounting process, the semiconductor chip 48 is fixed to the mounting portion 49, and the electrode of the semiconductor chip 48 is connected to the copper foil wiring 43 by the bonding wire 52. Then, a first sealing process is performed, and the electrode surface of the semiconductor chip 48 is sealed with the epoxy resin 53. On the other hand, a gold bump 55 is projected from the electrode on the electrode surface of the semiconductor chip 56, and a resin 57 formed in a tape shape is prepared.
[0032]
In the step of FIG. 10B, a tape-like resin 57 is placed on the mounting area of the semiconductor chip 56 on the back surface side of the substrate 40 by a tape placement process, followed by a second placement process. The gold bump 55 is brought into contact with the land 46a with the electrode surface of the semiconductor chip 56 opposed to the back surface of the copper plate 41, and is connected by a thermocompression bonding method. At this time, the second sealing process is performed simultaneously, and the tape-shaped resin 57 is heated and melted and cured. Therefore, the electrode surface of the semiconductor chip 56 is sealed. 10C, solder balls 54 are formed on the copper foil wiring 43 on the surface side of the copper plate 41 and on the surface side of the through hole 50. In the step of FIG.
[0033]
As described above, in the fourth embodiment, the copper stay wiring 46 and the through hole 50 formed on the back surface side of the copper plate 41 are provided as in the second and third embodiments, and the back surface of the copper plate 41 is provided. Since the electrodes of the semiconductor chip 46 mounted on the side are connected to the solder balls 54 arranged on the front surface side, the solder balls 54 can be used effectively as terminals of the semiconductor chip 56, and the mounting area when mounted on the motherboard And the area of the motherboard can be reduced. In addition, since the semiconductor chip 56 is mounted by the gold bumps 55, the connection can be made in a shorter time than in the first embodiment. Furthermore, since the semiconductor chip 56 can be sealed simultaneously with the connection of the bumps 55, it can be sealed in a shorter time than in the second and third embodiments.
[0034]
Fifth Embodiment FIG. 11 is a sectional view of a BGA package showing a fifth embodiment of the present invention. FIGS. 12A and 12B are views showing a substrate 70 which is a base of the BGA package of FIG. 11, and common elements to those in FIG. 11 are denoted by common reference numerals. The base plate 70 of this BGA package uses a copper plate 71 similar to that of the first embodiment as a base material, and an insulating material 72 having a thickness of 10 to 30 μm is pasted on the surface side of the copper plate 71. Yes. On the insulating material 72, a copper foil wiring 73 which is a first wiring pattern having a thickness of 12 to 35 μm is formed. An upper portion of the copper foil wiring 73 is coated with a solder resist 74 leaving a part.
[0035]
As shown in FIG. 12B, an insulating material 75 made of polyimide or the like having a thickness of 10 to 30 μm is attached to the back surface side of the copper plate 71. A second 12 to 35 μm thick second material is attached on the insulating material 75. A copper foil wiring 76 which is a wiring pattern of is formed. On the copper foil wiring 76, a solder resist 77 is applied leaving a part. A mounting portion 79 of the first semiconductor chip 78 is formed in a concave shape on the surface side of the copper plate 71 by die drawing. The copper plate 71 is further formed with a through hole 80 connecting the front surface and the back surface. One end of the copper foil wiring 73 is a bonding post 73a connected to the bonding wire. One end of the copper foil wiring 76 on the back surface side is a solder ball connecting land 76a. For example, the land 76a is coated with a heat-resistant preflux, for example.
[0036]
The other end of the copper foil wiring 76 is connected to the through hole 80. For example, an insulating paste 81 is applied to the bottom of the mounting location 79, and the first semiconductor chip 78 is mounted on the mounting location 79 with the back surface opposite to the electrode surface facing. The electrode of the semiconductor chip 78 and the copper foil wiring 73 are connected by a bonding wire 82 as a first connecting member, and the cavity portion on which the semiconductor chip 78 is mounted is formed by an epoxy resin 83 of a first sealing resin. It is sealed. A plurality of solder balls 84 are arranged, for example, in a lattice pattern on the surface side of the substrate 80. Solder balls 84 are formed in the openings of the solder resists 77 of the copper foil wirings 73, and the through holes 80 are also connected to the solder balls 84.
[0037]
On the back side of the substrate 70 as described above, a semiconductor device 86 such as a chip size package in which only the solder balls 85 serving as the second connection members are exposed from the electrode surface is mounted. A terminal of the semiconductor device 86 is connected to a land 76 a of the copper foil wiring 76 by a solder ball 85. When manufacturing such a BGA package, the solder balls 85 of the semiconductor device 86 are heated and reflowed to connect the terminals of the semiconductor device 86 to the lands 76a of the copper foil wiring 76. Finally, the solder balls 84 are connected. By forming, deformation of the solder ball 84 is prevented.
[0038]
As described above, in the fifth embodiment, the copper stay wiring 76 and the through hole 80 formed on the back surface side of the copper plate 71 are provided, and the terminals of the semiconductor device 86 mounted on the back surface side of the copper plate 71 are provided on the front surface side. Since the solder balls 84 connected to the semiconductor chip 78 are connected, the solder balls 84 that cannot be connected to the semiconductor chip 78 can be used effectively as terminals of the semiconductor device 86. In addition, since the semiconductor device 86 is sealed in advance, the resin 57 that is necessary in the second to fourth embodiments is unnecessary, and the member cost can be reduced. In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the first, second, and fourth embodiments, the semiconductor chips 28 and 48 on the front surface side of the substrates 20 and 40 are mounted earlier than the semiconductor chips 36 and 56. It may be installed.
[0039]
【The invention's effect】
As described in detail above, according to the first to seventh inventions, the through hole formed in the base material and the second wiring pattern formed on the back surface side of the base material, A first semiconductor chip is mounted on the front surface side of the material, a second semiconductor chip or semiconductor device is mounted on the back surface side of the base material, and electrodes or terminals of the second semiconductor chip or semiconductor device are connected to the second wiring. Since the solder ball is connected via the pattern and the through hole, the solder ball that cannot be connected to the first semiconductor chip, that is, the surplus terminal can be effectively used as the terminal of the second semiconductor chip or the semiconductor device. . The mounting area when mounted on the motherboard can be reduced, and the area of the motherboard can also be reduced.
[0040]
According to the eighth to twelfth inventions, the first semiconductor chip is mounted on the front surface of the substrate, the second semiconductor chip is mounted on the back surface of the substrate, and signals of the first and second semiconductor chips are input. Since the output is performed both by the first and second external electrodes formed on the surface of the substrate, the mounting area when mounted on the motherboard can be reduced, and the area of the motherboard can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a BGA package showing a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an example of a conventional BGA package.
FIG. 3 is a cross-sectional view showing another example of a conventional BGA package.
4 is an explanatory diagram of a problem of the BGA package of FIGS. 2 and 3. FIG.
FIG. 5 is a diagram showing a substrate 20 that is a base of the BGA package of FIG. 1;
FIG. 6 is a cross-sectional view of a BGA package showing a second embodiment of the present invention.
7 is a diagram showing a substrate 40 that is a base of the BGA package of FIG. 6;
8 is a cross-sectional view showing an outline of a manufacturing process of the BGA package of FIG. 6;
FIG. 9 is a cross-sectional view of a method for manufacturing a BGA package showing a third embodiment of the present invention.
FIG. 10 is a cross-sectional view of a method for manufacturing a BGA package showing a fourth embodiment of the present invention.
FIG. 11 is a cross-sectional view of a BGA package showing a fifth embodiment of the present invention.
12 is a diagram showing a substrate 70 which is a base of the BGA package of FIG. 11. FIG.
[Explanation of symbols]
21, 41, 71 Copper plate
23, 26, 43, 46, 73, 76 Copper foil wiring
28, 36, 48, 56 Semiconductor chip
30, 50, 80 Through hole
32, 37, 42, 82 Bonding wire
34, 54, 84 Solder balls
60 Through hole
86 Semiconductor devices

Claims (5)

表面と裏面とを有し、複数の導電性スルーホールが設けられた基板を準備し、
第１の配線と、前記スルーホールと接続する第２の配線とを前記表面上に形成し、
前記スルーホールと接続する第３の配線を前記裏面上に形成し、
前記表面に第１の半導体チップを搭載し、
前記第１の半導体チップと前記第１の配線とを電気的に接続し、
前記裏面に第２の半導体チップを搭載し、
前記第２の半導体チップと前記第３の配線とを電気的に接続し、
前記第１の配線と電気的に接続される前記第１の外部電極と、前記第２の配線と電気的に接続され、前記基板のコーナー部近傍に位置する前記第２の外部電極とを、格子状の複数電極列を構成するように形成することを特徴とする半導体装置の製造方法。And a front surface and a back surface, and providing a substrate conductive through holes multiple is provided,
A first wiring and a second wiring connected with said through hole is formed on said surface,
A third wiring to be connected before SL through hole is formed on the back surface,
A first semiconductor chip is mounted on the surface ;
Electrically connecting the first semiconductor chip and the first wiring;
A second semiconductor chip is mounted on the back surface ;
Electrically connecting the second semiconductor chip and the third wiring;
The first external electrode that is electrically connected to the first wiring, and the second external electrode that is electrically connected to the second wiring and located near a corner of the substrate, A method of manufacturing a semiconductor device , comprising forming a plurality of grid-like electrode arrays. 前記基板は銅で構成され、前記基板の前記表面には凹部が設けられ、前記裏面には前記凹部に対応する凸部が設けられ、前記第１の半導体チップは前記凹部内に配置され、前記第２の半導体チップは前記凸部上に配置されていることを特徴とする請求項１記載の半導体装置の製造方法。The substrate is made of copper, a concave portion is provided on the front surface of the substrate, a convex portion corresponding to the concave portion is provided on the back surface, and the first semiconductor chip is disposed in the concave portion, The method of manufacturing a semiconductor device according to claim 1, wherein the second semiconductor chip is disposed on the convex portion . 前記基板は、前記凸部と凹部とを貫通する貫通孔を有し、前記第２の半導体チップを搭載する際に、前記貫通孔から前記基板と前記第２の半導体チップとの間に樹脂を注入することを含む請求項２記載の半導体装置の製造方法。The substrate has a through-hole penetrating the convex portion and the concave portion, and when mounting the second semiconductor chip, a resin is inserted between the substrate and the second semiconductor chip from the through-hole. The method of manufacturing a semiconductor device according to claim 2 , comprising implanting. 前記第２の半導体チップを搭載する際に、前記基板と前記第２の半導体チップとの間に樹脂を注入することを含む請求項１〜３のいずれか記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, further comprising injecting a resin between the substrate and the second semiconductor chip when mounting the second semiconductor chip. 5. 前記第２の半導体チップを搭載する際に、前記基板と前記第２の半導体チップとの間にテープ状の樹脂を介在させることを含む請求項１〜３のいずれか記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to any one of claims 1 to 3, further comprising interposing a tape-like resin between the substrate and the second semiconductor chip when mounting the second semiconductor chip. .
JP2003198678A 2003-07-17 2003-07-17 Manufacturing method of semiconductor device Expired - Fee Related JP3903025B2 (en)

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