JP2002289848A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DTMISFET which simplifies manufacturing process. SOLUTION: A semiconductor device is provided with a silicon substrate 100; an insulation film 101 formed at a part on the silicon substrate 100, turned into a gate insulation film in a channel region and provided with a contact hole 106, exposing the surface of a semiconductor substrate at a part of the area other than the channel area; a metal electrode 102 formed on the insulation film 101, turned into gate electrode on the gate insulation film, directly connected to the silicon substrate 100 in the contact hole and constituted of a metal material; and a source 103 and a drain 104 formed on the semiconductor substrate, so as to clamp the channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a MISFET in which a semiconductor substrate and a gate electrode are electrically connected, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a power supply voltage _Vdd has been continuously reduced in order to reduce power consumption. However, the threshold voltage V _{th of the} MISFET has not been reduced so much in order to prevent an increase in off current. Therefore, it tended to drive capability I _d of the transistor is reduced. DTMIS (Dynamic threshold-voltageM
ISFET) was proposed (reference: Fariborz Assaderagh)
i, et al, "Dynamic threshold-voltage MOSFET (DTMOS)
for Ultra-Low voltage VLSI ", IEEE Trans. Electron
Devices, vol.44, pp.414-421, 1997).

[0003] DTMISFET is (in the case of SOI substrate Si-Body) gate electrode and the well is a MISFET for electrically connecting the, merit supply voltage V _dd is large even driving capability small and low off-state current Device.

The reason for such an advantage is that the threshold voltage V _th is low when the transistor is on and the threshold voltage V _th is high when the transistor is off, because the gate voltage is transmitted to the substrate and a substrate bias effect is generated. The operation principle will be described.

Further, as another advantage, (1)
The DTMISFET has a small electric field in the vertical direction (perpendicular to the channel surface) and has a high carrier mobility, which is one of the reasons why a high driving capability can be realized. S-fact
or is always an ideal value (best value) of 60 mV / decade, and (3) a low threshold voltage V _th which is said to be difficult to realize with a MISFET using a metal gate of a mid-gap work function. Can be realized.

FIG. 13 shows a schematic configuration of a conventional DTMISFET. FIG. 13A is a plan view of the semiconductor device, and FIG.
FIG. 13B is a cross-sectional view taken along the line AA ′ of FIG.
FIG. 13C is a cross-sectional view taken along the line BB ′ of FIG.
(D) is a cross-sectional view taken along the line CC ′ in FIG.

In FIG. 13, reference numeral 1300 denotes a p-type silicon substrate, 1301 denotes a gate insulating film, 1302 denotes n ⁺ pol
A gate electrode made of y-Si, 1303 is a source, 13
04 is a drain, 1305 is a p ⁺ diffusion layer region, 1306
Is a metal plug made of Al.

In such a DTMISFET, a contact hole and a metal plug 1306 are required to connect the gate electrode 1302 made of n ⁺ poly-Si to the p ⁺ diffusion layer region 1305. The formation of the contact hole and the metal plug has a problem that the manufacturing process is complicated.

[0009]

As described above, the conventional DTMISFET has a problem that a contact hole and a metal plug electrode must be formed, and the manufacturing process is complicated.

An object of the present invention is to provide a semiconductor device having a DTMISFET in which a semiconductor substrate and a gate electrode are electrically connected, and to provide a semiconductor device capable of simplifying a manufacturing process and a manufacturing method thereof. .

[0011]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object. (1) The semiconductor device of the present invention is formed on a semiconductor substrate and a part of the semiconductor substrate, becomes a gate insulating film in a channel region, and exposes a surface of the substrate in a part of a region other than the channel region. An insulating film having a contact hole, a metal electrode formed on the insulating film, serving as a gate electrode on the gate insulating film, directly connected to the semiconductor substrate in the contact hole, and made of a metal material;
A source and a drain formed on the semiconductor substrate so as to sandwich the channel region.

Preferred embodiments of the present invention are described below.
The metal electrode is composed of two or more metal films, the lowermost metal film constituting the metal electrode is formed only on the insulating film, and the second and subsequent metal films constituting the metal electrode from the bottom. And the semiconductor substrate are in direct contact with each other.

(2) The method of manufacturing a semiconductor device according to the present invention
Forming a dummy gate in a region where a gate electrode is formed on a semiconductor substrate; introducing impurity ions into the semiconductor substrate using the dummy gate as a mask to form a source and a drain; Forming an insulating film on the substrate and around the dummy gate;
Removing the dummy gate to form a gate groove having a side wall made of the insulating film; forming a gate insulating film on the bottom surface of the gate groove;
Forming a first metal layer composed of at least one layer, patterning the first metal layer and the gate insulating film to form a contact hole exposing a surface of the semiconductor substrate, Forming a second metal layer composed of one or more layers.

[Function] The present invention has the following functions and effects by the above configuration. Since the gate electrode is made of a metal material, the electrical connection between the metal electrode and the semiconductor substrate is made directly without any intervening material, so that there is no need to form a contact electrode and the manufacturing process is simplified. . Further, since the gate electrode is made of a metal material, n-
Electrical connection can be easily made to both the well and the p-well.

After the first metal layer is laminated on the gate insulating film, the gate insulating film and the first metal layer are patterned to form a contact exposing the semiconductor substrate, and then the second metal layer is formed. By forming, it is not necessary to pattern the contact hole for connecting the metal gate electrode and the semiconductor substrate directly above the gate insulating film.
The reliability of the gate insulating film is improved.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. Figure 1
FIG. 1A is a plan view of a semiconductor device, and FIG.
1 (c) is a sectional view taken along the line AA 'of FIG.
FIG. 1D is a cross-sectional view taken along the line CC ′ in FIG. 1A.

In the semiconductor device shown in FIG. 1, a bulk p-type silicon substrate 100 is used as a semiconductor substrate, and illustration of an element isolation structure is omitted.

In the present embodiment, N using a metal gate
A channel MISFET is formed. The metal gate and p-silico are partly formed on the surface of the Si
n (p + region) are directly connected.

As shown in FIG. 1, a contact hole 106 is formed in the gate insulating film 101, and the metal gate electrode 102 is directly connected to the silicon substrate 100 at the contact hole 106. A p ⁺ diffusion layer region 105 is formed in the silicon substrate 100 in a region connected to the gate electrode 102.

Next, referring to FIG. 2, an n-channel MISFE
The metal gate electrode structure of T will be described. FIG. 2A is a cross-sectional view corresponding to the line BB ′ in FIG. 1A, and FIG. 2B is a cross-sectional view along the line CC ′ in FIG. 1A.

Generally, a metal gate electrode is often formed of a laminated film of a plurality of metal materials. For example, W / T
As a barrier metal of a main material (W, Al, Ru, or the like) such as iN, Al / TiN, or Ru / TiN, TiN is often used for a lower layer. The role of TiN is to prevent diffusion of the upper layer metal and to control the work function of the gate electrode. In the MISFET shown in FIG. 2, after a contact hole 106 is formed in the gate insulating film 101, the barrier metal layer 20 is formed.
1. An upper metal layer 202 is sequentially deposited to form a metal gate electrode 102.

According to such a configuration, the electrical connection between the metal gate electrode 102 and the p ⁺ diffusion layer region 105 is made directly without using any other material, so that the manufacturing process is simplified. Note that since the gate electrode 102 is formed of a metal material, electrical connection can be easily made to both the n-well and the p-well. Conventional Poly-S
In the case of the i-gate, a metal plug or the like must be formed between the gate and the Si-well of the opposite conductivity type when connecting the gate and the gate, and the process is complicated.

(Second Embodiment) FIGS. 3A and 3B are cross-sectional views in the BB 'direction for explaining a metal gate structure of an N-channel MISFET according to a second embodiment of the present invention. FIG. 4 shows a cross-sectional view in the CC ′ direction. The basic structure is the same as in the first embodiment.

In the MISFET of this embodiment, as shown in FIG. 3, a barrier metal layer 301 made of, for example, TiN is formed only on the gate insulating film 101, and W, Al, and Ru are directly formed on the p ⁺ diffusion layer region 105. Upper metal layer 30 such as
2 are connected.

In this structure, after a barrier metal layer 301 is formed on a gate insulating film 101, both films 101 and 30 are formed.
After etching contact hole 106 to form contact hole 106,
It is formed by forming the upper metal layer 302.

In the present apparatus, the following advantages are obtained in addition to the same effects as those of the first embodiment. That is, since it is not necessary to pattern the contact hole for connecting the metal gate electrode and the semiconductor substrate directly above the gate insulating film, the gate insulating film is not contaminated by the resist, and the reliability of the gate insulating film is improved. improves.

A method of manufacturing an N-channel MISFET according to the second embodiment of the present invention will be described with reference to FIGS. 4 to 11 are process cross-sectional views showing a process for manufacturing an N-channel MISFET according to the second embodiment of the present invention.

4A to 11, each figure (a) corresponds to FIG.
1B corresponds to a cross-sectional view taken along the line AA ′ of FIG.
This corresponds to a cross-sectional view of a portion -B '.

First, as shown in FIG. 4, an STI (Shallow Tren) is formed on a silicon substrate 100 as shown in FIG.
An element isolation layer 401 having a depth of about 200 nm is formed by using a (ch Insulation) technique. A thermal oxide film 402 of about 5 nm is formed on the surface of the silicon substrate 100.

Next, as shown in FIG.
A poly-Si film 403 of about m is deposited by LPCVD. This Poly-Si is later used as an ion implantation mask, a CMP stopper and the like. A resist pattern (not shown) for forming a dummy gate is formed, and the Poly-Si film 403 is etched. Here, in order to form the source / drain, ion implantation is performed, and the source 103 and the drain 10 made of an n ⁺ diffusion layer are formed.
4 is formed.

If necessary, an LDD structure is formed here.
May be. LDD structure is n^-After the formation of the diffusion layer, the Si
_ThreeN_FourA side wall film is formed on the side surface of the dummy gate. For example,
Si _ThreeN_FourThe thickness of the film side film is about 20 nm, n^-Shape the diffusion layer
The ion implantation conditions for the formation are As, 15 keV, 3 ×
10¹⁴cm^-2It is about. These are not shown.

N⁺Source 103 and drain made of diffusion layer
The ion implantation conditions for forming the in 104 are, for example, A
s ions are accelerated at an acceleration voltage of 45 keV and a dose of 3 × 10¹⁵
cm ^-2It is. Activity of source 103 and drain 104
(Up to 1000 ° C.).

Next, as shown in FIG.
After depositing the S-SiO ₂ film 404, TEOS-SiO
₂ The surface of the film 404 is subjected to CMP (Chemical Mechanical Poli).
shing) and dummy gate Poly-Si
The upper surface of the film 403 is exposed.

Next, as shown in FIG. 7, the dummy gate Poly-Si film 403 is removed by CDE or the like, and a gate groove 405 is formed in a region where a gate electrode is to be formed. H
The thermal oxide film 402 is also removed by F-based wet etching.

Next, an original gate insulating film is formed. Since the source 103 and the drain 104 have already been formed, there will be no high-temperature heat treatment step at 600 ° C. or higher in the future.
Therefore, not only the SiO ₂ film but also the Hf
O ₂ film, ZrO ₂ film, Ta ₂ O ₅ film, TiO ₂ film and (B
(a, Sr) A high dielectric film such as TiO ₃ or a ferroelectric film can be used, and a metal material can be used for the gate electrode. When a high dielectric film or a ferroelectric film is used for the gate insulating film, it is necessary to select a gate electrode material according to the gate insulating film used, and Al, W, Ru, or the like can be used. Further, it is desirable to form a thin film such as TiN or WN as a barrier metal between the gate insulating film and the gate electrode material. Here, a Ta ₂ O ₅ film is used as a High-k gate insulating film, and Ru / Ti is used as a gate electrode.
An example using N is shown.

As shown in FIG. 8, after the substrate surface is thinly nitrided, a Ta ₂ O ₅ gate insulating film 10 having an actual film thickness of about 3 nm is formed.
After forming 1, as the first-layer metal gate electrode,
A barrier metal layer 301 is formed by depositing a TiN film having a thickness of about 10 nm by a CVD method.

Next, as shown in FIG. 9, a resist film 406 is applied on the barrier metal layer 301, and the contact holes 407 are patterned. When the contact hole 407 is formed in this manner, it is not necessary to pattern the contact hole for connecting the gate and the well directly above the gate insulating film, so that the reliability of the gate insulating film is improved. If a resist is directly attached on the gate insulating film and patterned, the reliability of the gate insulating film deteriorates.

Next, as shown in FIG. 10, after removing the resist film 406, a Ru film is deposited to a thickness of about 300 nm to form an upper metal layer 302, and a metal gate electrode is formed in the gate groove 405 by using a damascene method. To form

After the formation of the metal gate, the process is the same as the ordinary LSI manufacturing process. As shown in FIG. 11, a TEOS interlayer insulating film 408 is deposited by a CVD method, contact holes are formed on the source 103, the drain 104, and the metal gate electrode 102, and an upper metal wiring 409 made of, for example, Al is formed.

As described above, according to the present embodiment, the electrical connection between the metal gate electrode and the semiconductor substrate is directly made without any intervening material, so that the manufacturing process is simplified.
Since the gate is formed of a metal material, the n-well,
Electrical connection can be easily made to both p-wells, which is advantageous for forming a C-MISFET. Poly
In the case of the -Si gate, a metal plug or the like must be formed between the gate and the Si-well of the opposite conductivity type when connecting the gate and the gate, and the process is complicated.

If the resist is directly attached on the gate insulating film and patterned, the reliability of the gate insulating film deteriorates. However, according to the manufacturing method of this embodiment, the contact hole for connecting the gate and the well is formed. Since it is not necessary to perform the patterning of 407 right above the gate insulating film 101, the reliability of the gate insulating film 101 is improved.

In addition, according to the operation principle of the DTMISFET, a low threshold voltage V _th (up to 0.2 V), which is said to be difficult to realize with a MISFET using a metal gate of a mid-gap work function, can be realized. Become.

However, in order to sufficiently reduce Vth, it is necessary to optimize the impurity profile of the channel and increase the substrate bias coefficient (ΔVth / ΔVb). Therefore, it is necessary to adopt an SSRG (Super Step Retrograded) channel or a buried channel structure using counter ion implantation.

FIG. 12 is a diagram showing a configuration of a modification of the second embodiment. As shown in FIG. 12, the second-layer metal formed on the first-layer metal 301 is composed of a laminated film of a barrier metal 303 and a main material (Ru, Al, etc.) 302. The barrier metal 303 can prevent the metal 302 and the Si substrate from reacting or interdiffusing.

It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented in various modifications without departing from the gist thereof.

[0046]

As described above, according to the present invention, since the gate electrode is made of a metal material, the electrical connection between the metal electrode and the semiconductor substrate is made directly without any other material. There is no need to form a contact electrode, and the manufacturing process is simplified.

[Brief description of the drawings]

FIG. 1A is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment, FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG. (C) is B- in FIG.
FIG. 1D is a cross-sectional view taken along the line CC ′ of FIG. 1A.

FIG. 2 is a diagram showing the configuration of the semiconductor device shown in FIG. 1 in more detail;

FIG. 3 is a diagram illustrating a schematic configuration of a semiconductor device according to a second embodiment;

FIG. 4 is a process sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 5 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 6 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a process sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 8 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 9 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 10 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 11 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 12 is a diagram showing a configuration of a modification of the semiconductor device according to the second embodiment.

FIG. 13 is a diagram showing a schematic configuration of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 silicon substrate 101 gate insulating film 102 metal gate electrode 103 source 104 drain 105 p ⁺ diffusion layer region 106 contact hole

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 29/78 301P 301S F term (reference) 4M104 AA01 BB04 BB30 BB33 CC05 DD03 DD15 DD16 DD23 DD26 DD43 DD75 EE03 EE16 FF18 GG09 GG10 HH20 5F048 AA09 AC03 BA01 BB04 BB09 BB12 BB14 BE03 BE09 BF02 BF17 BF18 5F140 AA40 AB03 AC10 BA01 BD11 BD12 BD13 BE01 BE03 BF10 BF11 BF15 BF17 BG04 BG08 BG14 BG36 CC03 B0515 CC04

Claims (3)

[Claims] 1. A semiconductor substrate comprising: a semiconductor substrate; and a contact hole formed in a part of the semiconductor substrate, serving as a gate insulating film in a channel region, and exposing a surface of the substrate in a part of a region other than the channel region. An insulating film, formed on the insulating film, serving as a gate electrode on the gate insulating film, being directly connected to the semiconductor substrate in the contact hole, and sandwiching the metal electrode made of a metal material and the channel region. And a source and a drain formed on the semiconductor substrate. 2. The method according to claim 1, wherein the metal electrode is formed of two or more metal layers, and a lowermost metal layer forming the metal electrode is formed only on the insulating film.
The semiconductor device according to claim 1, wherein a metal layer after the first layer and the semiconductor substrate are directly connected. 3. A step of forming a dummy gate in a region on the semiconductor substrate where a gate electrode is formed, and forming a source and a drain by introducing impurity ions into the semiconductor substrate using the dummy gate as a mask. Forming an insulating film on the semiconductor substrate and around the dummy gate; removing the dummy gate to form a gate groove having a side wall made of the insulating film; and a bottom surface of the gate groove. Forming a first metal layer composed of one or more layers on the gate insulating film; patterning the first metal layer and the gate insulating film to form the semiconductor; Forming a contact hole exposing the surface of the substrate; and forming a second metal layer composed of at least one layer in the gate groove. Manufacturing method.