JP2002280308A - Method of growing nitride semiconductor and element using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a growth method for a nitride semiconductor, which can be used for element structure in the arrangement of the element structure of a counter electrode, out of, by reducing the through transposition of a nitride semiconductor. SOLUTION: This growth method possesses a process of selectively forming a first surface 1 on the surface of a first nitride semiconductor 1 and a second surface 2 larger in the growth speed of a nitride semiconductor than that first surface, and a process of growing the a second nitride semiconductor 12 on the first surface 1 and the second surface of the first nitride semiconductor 1. Hereby, the growth from the second surface is performed to cover the first surface 1, whereby defect density can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for growing a nitride semiconductor and a nitride semiconductor device using the same, and more particularly, to a nitride semiconductor substrate and a device using the same.

[0002]

2. Description of the Related Art A laser device using a nitride semiconductor mainly oscillates a laser beam having a short wavelength of blue to violet, and various uses thereof such as an optical disk device are under study. The continuous oscillation of this laser device has been realized and put into practical use in recent years, but the characteristics of the device are not sufficiently satisfactory in its application, and further improvement in device characteristics is required. In addition, an LED using a nitride semiconductor element can emit light in the ultraviolet region to red, and can be used for various elements such as a light receiving element and a transistor.

[0003] Such a nitride semiconductor device is mainly formed by forming a low-temperature growth buffer layer on a heterogeneous substrate made of a different material from the nitride semiconductor, and then growing the buffer layer at a temperature higher than that temperature. An element structure is formed via the underlayer. However, among the above-mentioned elements, LDs requiring high current and high output driving, high output type LEDs, etc.
Crystal defects, particularly dislocation densities such as threading dislocations, are a major factor in determining device characteristics. This is because, when the dislocation density is increased, the element characteristics are deteriorated under the above-mentioned large current and high output driving, and it is difficult to obtain a practically usable element. For this reason, such a nitride semiconductor device includes ELOG (Ep
By using a nitride semiconductor layer formed using lateral growth such as itaxially lateral overgrowth as an underlayer and forming an element structure on the underlayer, a substrate with a good dislocation density can be used. Can solve the above problem. Alternatively, after forming a nitride semiconductor substrate using lateral growth such as ELOG on a heterogeneous substrate, the heterogeneous substrate may be removed to form a nitride semiconductor single substrate. Such an underlayer and a nitride semiconductor substrate can be applied to the other devices described above.

[0004]

As described above, the EL
A method known as a nitride semiconductor formed with lateral growth, such as OG, is used to selectively deposit S on the nitride semiconductor.
There is a method in which a mask of iO ₂ or the like is formed on the surface, a nitride semiconductor is grown from a mask opening, and a lateral direction is grown so as to cover the mask above the mask, thereby forming a film. However, in this method, the mask material is left inside the nitride semiconductor, and depending on the element structure, the flow of current is hindered by the mask, so that the element structure may be limited. In addition, as shown in FIG. 6, in the lateral growth, a film is formed by joining with each of the adjacent laterally grown nitride semiconductors. Since each nitride semiconductor grown from a different mask opening is in a state of being grown separately, a difference in the growth rate of each nitride semiconductor causes
Since the position of the junction shown in the figure changes and each nitride semiconductor grows individually, it is difficult to control this. As a result, the bonding failure shown in the figure is caused, there is a portion that is not bonded depending on the location, or a variation occurs in the bonding position, which makes the nitride semiconductor substrate difficult to handle. In the method of growing a nitride semiconductor through the step of growing separately as described above, there is also a method that does not use a mask material, for example, a method of growing from a nitride semiconductor having islands or irregularities formed by etching, Until bonding, the individual nitride semiconductors grow laterally without interfering with each other. Therefore, even a slight difference in the growth rate in the horizontal direction causes variations in bonding positions and poor bonding.

Therefore, in a method of growing a nitride semiconductor having excellent crystallinity, a method which is excellent in controllability and has a small variation in the crystallinity of the obtained nitride semiconductor is required for mass production and the like.

Further, as shown in FIG. 6, even in the case of growing in the lateral direction, growth in the film thickness direction also occurs, which indicates that the distance between the mask region or the growth surface of the adjacent nitride semiconductor, that is, As the distance for lateral growth increases, the film tends to be thicker. As the thickness of the nitride semiconductor increases, the cost increases. In addition, when the nitride semiconductor is grown on a heterogeneous substrate, the substrate warps, and as the film thickness increases, the warpage increases. The material semiconductor is difficult to handle in forming an element structure or the like. For this reason, it is preferable that the nitride semiconductor be formed as thin as possible. On the other hand, when the lateral growth region is enlarged, in the region formed by the lateral growth, threading dislocations progress with the growth of the nitride semiconductor and dislocations do not progress in the film thickness direction. In the LD, LED, and the like, the low dislocation defect density region is used as a gain region, a current injection region, or a light emitting recombination region. This is advantageous for the characteristics. Therefore, in the conventional method for growing a nitride semiconductor, in order to form a region having a low defect density such as threading dislocations, it is necessary to increase the distance or area for the lateral growth. As a result, the thickness of the nitride semiconductor becomes large, which is disadvantageous for use in nitride semiconductor devices.
In addition, when the lateral growth distance becomes longer, the occurrence rate of bonding failure due to the difference between the growth rates of the respective nitride semiconductors also increases, and good bonding becomes difficult at last. That is, it is considered that this problem is also caused by the fact that each nitride semiconductor is separated and grown individually during the lateral growth.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and in particular, to provide a method for growing a nitride semiconductor which has reduced dislocation density and is excellent in its control.

The present invention solves the problem by the following constitutions (1) to (5). (1) selectively forming, on the first nitride semiconductor surface, a first surface and a second surface having a higher growth rate of the nitride semiconductor than the first surface; And a step of growing a second nitride semiconductor on the first surface and the second surface of the first nitride semiconductor. By this method, the second
Are grown at different growth rates from the first surface and the second surface, thereby realizing different growth morphologies on each surface, and consequently, the second semiconductor layer on the first surface. A low defect density region with reduced threading dislocations is formed in the nitride semiconductor layer. Further, since the nitride semiconductor grows from the first surface and the second surface, the nitride semiconductor does not grow independently as in the conventional case. By reducing the size, threading dislocations can be reduced and a mirror surface can be obtained, and the growth can be easily controlled. At this time, a plurality of first surfaces and a plurality of second surfaces are provided on the first nitride semiconductor layer, and preferably, the first surface and the second surface are alternately provided. In addition, the shapes of the first surface and the second surface are not particularly limited, but are preferably formed alternately in a stripe shape, so that a favorable second nitride semiconductor layer can be grown. (2) The method for growing a nitride semiconductor according to claim 1, wherein the first surface has irregularities larger than the second surface. As a result, the above-described difference in growth rate occurs, which contributes to a reduction in dislocation defect density. In addition, since the surface has irregularities, the first surface having irregularities has two-dimensional growth in the initial stage of growth.
It is considered that a complex growth mode in which three-dimensional growth is mixed occurs, whereby the number of threading dislocations propagating from the first nitride semiconductor layer to the second nitride semiconductor layer can be reduced. (3) The step of forming the first surface and the second surface includes selectively forming a mask on the surface of the first nitride semiconductor, and forming a first mask on a non-mask region where the mask is not formed.
3. The nitride semiconductor according to claim 1, wherein a portion of the nitride semiconductor is removed by thermal decomposition to form a first surface, and the mask is removed to form a second surface. Growth method. Thus, the first surface and the second surface
By forming the surface, a surface having a difference in growth rate is easily formed, and a surface having irregularities for reducing threading dislocations propagating to the second nitride semiconductor layer is easily formed. be able to. (4) A nitride semiconductor device in which the second nitride semiconductor is used as an underlayer, and an element structure having the nitride semiconductor is provided on the underlayer. By using the second nitride semiconductor layer as a growth substrate, an element structure with excellent crystallinity is formed,
Further, by selectively providing a current region in which current flows through the active layer in the low defect density region B, a nitride semiconductor device with high output and long life can be obtained. (5) The nitride semiconductor device, wherein the second nitride semiconductor is provided in an element structure including the nitride semiconductor. Unlike the conventional lateral growth method, the second nitride semiconductor layer of the present invention can be formed as a thin film having a good mirror surface. Therefore, the second nitride semiconductor layer can be provided in the element structure. And the degree of freedom in element structure design is increased.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The nitride semiconductor used in the present invention is:
A nitride semiconductor formed on a heterogeneous substrate made of a material different from that of the nitride semiconductor may be used.
A single substrate of a nitride semiconductor such as N or AlN, or a singulated nitride semiconductor substrate described later may be used.
Specifically, as the first nitride semiconductor layer, a nitride semiconductor formed on a heterogeneous substrate, another nitride semiconductor, or a nitride semiconductor formed on a nitride semiconductor substrate can be used. . In addition, the composition of the nitride semiconductor in the present invention is not particularly limited, but specifically, a material known as a group III-V gallium nitride-based compound semiconductor can be used. _x A
_{l y Ga 1-xy N (} 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y
≦ 1), InAlGaBN further added with B, P, etc.
It can also be applied to InAlGaNP and the like. Preferably, I
By using a nitride semiconductor that does not contain n, that is, a nitride semiconductor having an In mixed crystal ratio of 0, the decomposition temperature is low, it is easily decomposed, and the crystal growth temperature is low. Can grow. Also, when the constituent elements are small, good crystallinity tends to be obtained.
In the case of growth with a film thickness exceeding μm, using a ternary mixed crystal and a binary mixed crystal nitride semiconductor can obtain a good crystalline nitride semiconductor, and can also control crystal growth. It is advantageous. For this reason, AlN, AlGaN, and GaN are preferably used for the second nitride semiconductor formed with a relatively thick film. In particular, AlGaN has a mixed crystal ratio y of Al, for example, y ≦ 0.3. By suppressing the concentration, a nitride semiconductor having good crystallinity can be formed, and GaN is particularly preferable because a nitride semiconductor having excellent crystallinity can be obtained. Further, the nitride semiconductor serving as such a substrate includes p
A type impurity or an n-type impurity may be doped, and when formed undoped, excellent crystallinity is obtained.

[0010] The compositions of the first nitride semiconductor and the second nitride semiconductor are not particularly limited, and nitride semiconductors having the same composition may be used or different compositions. Preferably, the composition of the two is determined so that the lattice mismatch is reduced. Therefore, by selecting a composition that is as close as possible to the composition, or more preferably, by making the two have the same composition, The inconsistency problem is solved. Further, the first nitride semiconductor layer and the second nitride semiconductor layer may be doped with an n-type impurity or a p-type impurity, or may be grown undoped. In order to improve the crystallinity, the impurity concentration is set to 1 × 10 ¹⁸ / cm ³ or less and doped at a low concentration to obtain a nitride semiconductor which retains carriers and maintains crystallinity, more preferably 5 × 10 ¹⁸ / cm ^{3. 16} / cm
^By setting the doping amount to be less than ³ , the crystallinity is further improved, and by undoping, the nitride semiconductor having the highest crystallinity can be grown.

In the present invention, the thicknesses of the first nitride semiconductor layer and the second nitride semiconductor layer are not particularly limited, and a flat surface is formed in the second nitride semiconductor layer. It is formed with a film thickness. The thickness of the first nitride semiconductor layer is
It is sufficient that the thickness is such that the first surface and the second surface are formed.

As the heterogeneous substrate used for growing the nitride semiconductor of the present invention, for example, sapphire or spinel (MgA1 ₂ O ₄ ) having any one of C-plane, R-plane and A-plane as a main surface.
It is possible to grow a nitride semiconductor such as an insulating substrate such as SiC (including 6H, 4H, and 3C), an oxide substrate lattice-matched with ZnS, ZnO, GaAs, Si, and a nitride semiconductor. And a substrate material different from the nitride semiconductor can be used. Preferred heterosubstrates include sapphire and spinel.
In addition, the heterogeneous substrate may be off-angled. In this case, it is preferable to use a substrate that is off-angled in a step-like manner because the underlayer made of gallium nitride tends to grow with good crystallinity. At this time, the off angle is set to 0.
By setting the angle to 1 ° to 0.5 °, preferably 0.1 ° to 0.2 °, favorable crystal growth of the nitride semiconductor becomes possible.
For example, a sapphire C-plane substrate that is off-angle within the above range can be used. In addition to the above, in the present invention, a single substrate of a nitride semiconductor can be used. In order to obtain a single substrate, there is a method of growing a thick nitride semiconductor (third nitride semiconductor layer) on the above-mentioned heterogeneous substrate and removing the heterogeneous substrate. in this case,
Specifically, the nitride semiconductor is formed to have a thickness of 50 μm or more, and can remove a heterogeneous substrate.
By setting the thickness to 00 μm or more, it is possible to efficiently remove different kinds of substrates. Further, when forming a first nitride semiconductor layer and a second nitride semiconductor layer on the heterogeneous substrate via a low-temperature growth buffer layer, and then growing a third nitride semiconductor layer, The substrate may be warped due to lattice mismatch with the substrate and a difference in thermal expansion coefficient.
It is preferable that the thickness be in the range of not less than μm and not more than 120 μm.
This single substrate may be used as the first nitride semiconductor layer, or the nitride semiconductor layer grown on the single substrate may be used as the first nitride semiconductor layer.

As described above, the first nitride semiconductor of the present invention may be formed on a heterogeneous substrate, or may be formed on a nitride semiconductor substrate. In the case where the first nitride semiconductor is formed over a different kind of substrate, an underlayer may be provided between the different kind of substrate and the first nitride semiconductor. At this time, AlGaN or GaN is preferably used as a base layer provided between the heterogeneous substrate and the first nitride semiconductor, whereby a first nitride semiconductor having good crystallinity can be formed. . More preferably, the first nitride semiconductor can be formed with good crystallinity by using AlGaN or GaN having an Al mixed crystal ratio of 0.3 or less. Specific examples of the underlayer (substrate) include undoped (undope), AlGaN and GaN doped with n-type impurities such as Si, Ge, and S, and preferably undoped. By using, compared to the case of using a nitride semiconductor having another composition, excellent crystallinity and excellent surface morphology as a growth substrate can be formed. When an underlayer is provided between the nitride semiconductor substrate and the first nitride semiconductor, a similar underlayer can be used.

Further, in the case of forming the underlayer and the first nitride semiconductor layer, a buffer layer grown at a lower temperature than the buffer layer is provided between the heterogeneous substrate or the nitride semiconductor substrate and the underlayer. This makes it possible to realize preferable growth of the nitride semiconductor, that is, formation of a favorable underlayer.
This buffer layer is a low-temperature growth buffer layer grown at a temperature lower than the growth temperature of the above-described underlayer and first nitride semiconductor layer, and specifically, AlN, GaN, AlGa
N, of InGaN, etc. _{In x Al y Ga 1-xy} N (0 ≦ x ≦
1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) is used and 300
At a temperature of not less than 900 ° C and not more than 0.5 μm
Å (angstrom) or more. At this time, a preferable composition is Al _x Ga _1-x N (0 <x ≦
By setting it as 1), it functions as a good buffer layer, and furthermore, AlGaN and Ga having an Al mixed crystal ratio x of 0.5 or less.
N can be used as a preferred buffer layer. This buffer layer may be doped with impurities or undoped. In particular, by forming such a buffer layer in contact with a heterogeneous substrate, an excellent buffer function can be used. By forming the base layer or the first nitride semiconductor layer thereon, With good crystallinity, a nitride semiconductor can be grown on a heterogeneous substrate. That is, when the first nitride semiconductor layer is formed on the heterogeneous substrate, at least the low-temperature growth buffer layer is provided between the first nitride semiconductor layer and the heterogeneous substrate, so that the first nitride semiconductor layer is formed. The crystallinity of the nitride semiconductor layer can be improved, and in addition, by providing an underlayer between the first nitride semiconductor layer and the low-temperature growth buffer layer,
Further, the crystallinity can be improved. At this time, the underlying layer and the first nitride semiconductor layer are grown at a temperature higher than that of the low-temperature growth buffer layer, specifically, in a temperature range of 800 ° C. or more and 1200 ° C. or less.

In the method for growing a nitride semiconductor according to the present invention, the method for growing the nitride semiconductor is not particularly limited, but includes MOVPE (metal organic chemical vapor deposition), HV
PE (halide vapor phase epitaxy), MBE (molecular beam epitaxy), MOCVD (metal organic chemical vapor phase epitaxy), etc.
All known methods for growing nitride semiconductors can be applied. As a preferred growth method, a film thickness of 50
When the thickness is less than μm, the growth rate can be easily controlled by using the MOCVD method. When the film thickness is 50 μm or less, the growth rate is high in HVPE and the control tends to be difficult.
For a film thickness of 50 μm or more, it is preferable to use HVPE having a high growth rate.

On the surface of the first nitride semiconductor layer of the present invention, a first surface and a second surface are formed. The first surface has a surface at which the growth rate of the second nitride semiconductor is lower than that of the second surface. Specifically, as shown by the length of the arrow in FIG. 2A and the magnitude of the growth rate, a region having a small growth rate is defined as a first surface on the first nitride semiconductor surface. And a second surface having a region where the growth rate is higher than the surface. Here, the arrow in FIG. 2A indicates that the longer the arrow, the higher the growth rate of the nitride semiconductor. FIGS. 2B to 2D illustrate the second nitride semiconductor. It is sectional drawing which shows a mode that a layer grows typically. According to the manufacturing method of the present invention, the first surface 1 and the second surface 2 having a higher growth rate of the nitride semiconductor than the first surface 1 are provided on the surface of the first nitride semiconductor layer 11. (FIG. 2A), a second nitride semiconductor layer is grown on the surface of the first nitride semiconductor layer (FIGS. 2B to 2D). Thus, according to the present invention, the second nitride semiconductor layer 12 is formed on the surface of the first nitride semiconductor layer 11 having different growth rates.
Is grown, the nitride semiconductor from the second surface grows in the film thickness direction, as shown in FIG. 2, grows in a different direction, and grows in the lateral direction (FIG. 2B It is considered that the arrow direction in ()) is realized. For this reason,
The growth of the nitride semiconductor grown from the first surface 1 is hindered, and threading dislocations extending from the first surface 1 along with the growth of the nitride semiconductor in the film thickness direction may be displaced in the film thickness direction. Therefore, it is considered that a region B having a low dislocation defect density is formed on the surface of the second nitride semiconductor layer 12 on the first surface 1 as a result. Hereinafter, this will be described in detail. <Growth Mode of Second Nitride Semiconductor> The second nitride semiconductor 12 of the present invention has a larger thickness direction in the region where the second nitride semiconductor is grown in the lateral direction as compared with the conventional lateral growth method shown in FIG. Is that a nitride semiconductor that grows on the substrate exists. As shown in the schematic cross-sectional view of FIG. 6, a conventional typical lateral growth method uses a mask 41 on the surface of the nitride semiconductor
8 (FIG. 6A), a nitride semiconductor 413a is grown from the opening of the mask 418 (FIG. 6B), lateral growth is performed on the mask 418, and each mask opening is formed. The nitride semiconductor 413a grown from above is bonded above the mask 418 (FIG. 6C), and a film is formed.
In another method, as shown in FIGS. 6 (x) to 6 (z), the base layer 412 of the nitride semiconductor is provided with irregularities, Alternatively, by selectively growing from the nitride semiconductor 412 in the island portion, the film is grown in the lateral direction as shown by the arrow in FIG. Become. In either method, a region where a nitride semiconductor is selectively grown and a region where the nitride semiconductor is not grown are provided in the plane,
The nitride semiconductor is grown individually from the region where the nitride semiconductor is grown. In addition, since threading dislocations can be reduced in the region grown in the lateral direction, the laterally grown region is enlarged, and in FIG. 6, the width of the mask 418 is increased, and the interval between adjacent convex portions or island portions is increased. However, if the growth in the lateral direction is prolonged, the nitride semiconductor film becomes thick because of poor bonding, abnormal growth, variation in the bonding position, and growth in the film thickness direction.

The second nitride semiconductor 12 of the present invention is shown in FIG.
As shown in (1), the conventional problem can be solved by growing the first nitride semiconductor layer 11 having a surface growing at different growth rates. This is an optional first
When a nitride semiconductor is grown from the surface 1 and the second surface 2 of the first nitride semiconductor, as shown in FIG. A nitride semiconductor layer 12 is formed. When the growth further proceeds from this state, the nitride semiconductor grown from the second surface 2 forms a projection as shown by a dotted line and an arrow in FIG. It is thought that lateral growth will also begin. Therefore, as shown in FIG.
In the next stage, the second nitride semiconductor 12 grows from a dotted line portion to a solid line portion and the first surface 1 Growth from the second surface 2 is considered to be disturbed by growth from the second surface 2. By doing so, the area from the first surface 1 tends to shrink, while the area from the second surface 2 tends to increase. That is, it is considered that the growth of the nitride semiconductor from the second surface 2 takes a higher priority than the growth of the nitride semiconductor from the first surface.

Finally, as the growth of the second nitride semiconductor 12 further proceeds, most of the growth from the first surface 1 is cut off, and the nitride semiconductor grown from the second surface 2 It is supposed that it takes a form that plays a major role in the growth of the nitride semiconductor 12 of No. 2. The second nitride semiconductor 12 formed in such a growth mode has a region A above the second surface 2.
Is formed by growth from the second surface 2 in the film thickness direction. On the other hand, in the region B above the first surface 1, the film is grown from the first surface 1 in the film thickness direction. Is formed by lateral growth from the second surface 2 so as to cover it. As a result, on the surface of the second nitride semiconductor 12, in the region A, most of the growth form grows in the film thickness direction and becomes a region with a high threading dislocation density (high defect density region), and in the region B, Since the directional growth is considered to be included during the growth, the region becomes a region having a low dislocation density (low defect density region). Therefore, in the present invention,
By growing the second nitride semiconductor layer, threading dislocations on the first surface can be reduced, and threading dislocations can be selectively distributed on the second surface.

FIG. 3 is an enlarged view of a part of FIG. 2, in which the growth form of the second nitride semiconductor 12 is indicated by a dotted line.
This shows how threading dislocations 14 propagate. As can be seen from the above, in the present invention, the first nitride semiconductor 11
By growing second nitride semiconductor 12 from the surface of, threading dislocations can be reduced. That is, as the growth proceeds, the threading dislocations extending from the first surface 1 stop during the growth, while the information includes the lateral growth that has grown from the second surface 2 and the first surface 1
Threading dislocations extend in the lateral direction so as to cover. According to the present invention, unlike the conventional method, since the nitride semiconductor is grown even in the region where the lateral growth is performed, the growth is easy to control, and the adjacent first surface 1 and second The second nitride semiconductor 1 grows together from the surface 2
No. 2 is formed on the entire surface in the same manner as in the conventional growth method only in the film thickness direction, so that the control is easy as in the conventional growth method. Further, since the second nitride semiconductor 12 grows simultaneously from the first surface 1 and the second surface 2, the film thickness for obtaining a flat surface is also smaller than that of the conventional lateral growth method. . Specifically, FIGS. 6 (a) to 6 (c)
In the method shown in (1), the selective growth region (lateral growth region) 413 having a size of at least 5 μm or more depends on the mask pattern.
In the method of the present invention, a film thickness of 10 μm or more is required if the mask width is increased and the lateral growth region is increased by enlarging the mask width. Although it differs depending on the area, shape, and pattern of No. 2, a good surface tends to be obtained even if the film thickness is smaller than that of the conventional method. Specifically, as is apparent from a comparison between Example 1 and Comparative Example 1 described later, when the pitch of the first surface and the second surface and the pitch of the mask in Comparative Example 1 are the same, In Example 1, a flat surface was obtained with a film thickness of about 5 μm, and in Comparative Example 1, a flat surface was obtained by growing with a film thickness of about 10 μm. With a thickness of 3 to 1/2, the defect density can be reduced. Further, as shown in Example 4, in order to obtain a surface morphology that enables good growth of the nitride semiconductor layer by using the surface of the second nitride semiconductor layer as a good mirror surface, the film is further grown to a thickness of 3 μm. Let it. Thus, the second aspect of the present invention
After the nitride semiconductor layer is grown and a flat surface is obtained, by further growing, the effect of the underlayer is obtained, the surface morphology is improved, and a mirror surface is obtained.

As the n-type impurity used in the nitride semiconductor of the present invention, a group IV or group VI element such as Si, Ge, Sn, S, O, Ti, or Zr can be used. Preferably, Si, Ge is used. , Sn, and most preferably Si
By using, a good carrier can be generated. The p-type impurity is not particularly limited,
Be, Zn, Mn, Cr, Mg, Ca and the like,
Preferably, Mg is used. <First Surface and Second Surface of First Nitride Semiconductor Layer> A first surface and a second surface are selectively formed on the first nitride semiconductor layer of the present invention. The shape and pattern of the first surface and the second surface are not particularly limited.
It may be formed in a stripe shape, an island shape, a lattice shape, a hexagonal pattern according to the crystal orientation of the nitride semiconductor, or a honeycomb shape. At this time, such a first surface,
The pattern on the second surface may be regular or periodic, irregular, or non-periodic. For the patterns on the first surface and the second surface, a method that can easily control the growth can be appropriately selected from these. Among them, a stripe shape is preferable because the growth of the nitride semiconductor is relatively easily controlled and the manufacturing process tends to be simplified as compared with other patterns. . In order to form the first surface and the second surface in a stripe shape, another surface may be formed at various intervals with another surface interposed therebetween, but preferably, the respective surfaces are alternately provided. As described above, it is possible to grow while being influenced by each other, which is preferable. That is, even if the first surface and the second surface of any pattern are formed, the first surface and the second surface are provided adjacent to each other so that they affect each other. Preferably, for example, as shown in FIG. 2, the second nitride semiconductor can be grown, and the first surface and the second surface are alternately formed.
In addition, it is possible to maximize the use of such a growth mode by providing the layers repeatedly periodically.

When the first surface and the second surface are formed in stripes on the surface of the first nitride semiconductor layer, the period, pitch and the like are not particularly limited, and the composition of the second nitride semiconductor is , Depending on the growth conditions. Specifically, since a region having a low defect density is formed in the second nitride semiconductor region B above the first surface as described above,
Is preferable because the low defect density region B occupying the entire surface of the second nitride semiconductor layer increases. For example, the width of the first surface is 1 μm to 20 μm, preferably 1 μm to 10 μm, and the width of the second surface is 3 μm.
m to 20 μm, preferably 10 μm to 19 μm
By forming the following, favorable crystal growth of the second nitride semiconductor is realized, which is preferable. Further, under these conditions, the second nitride semiconductor layer has a thickness of 10 μm
A film having a flat surface is formed below, and when the first surface and the second surface in a stripe shape are further formed under the above preferable conditions, a film having a thickness of 5 μm or less can be formed. this is,
Compared with the conventional growth method shown in FIG. 6, in the method of the present invention, the first growth and the second surface are simultaneously grown as shown in FIG. By doing so, it is considered that a film can be formed with a small film thickness.

The first nitride semiconductor layer has a first nitride semiconductor layer on the surface thereof.
When the surface of the second surface is formed in a stripe shape
Is a sapphire whose main surface is C and a sapphire whose main surface is A.
Different from fire or spinel with (111) plane as main surface
It is preferably used as a growth substrate for a seed substrate. Less than,
To explain the case of using different types of substrates,
Tables 1 and 2 for sapphire whose main surface is C
The surface stripes are almost
It is preferable to have the stripe direction in the vertical direction
Also, the main surface is off angle from the sapphire C surface
Off angle is in the range of 0.1 ° to 0.5 °.
Enclosure, preferably in the range of 0.1 ° or more and 0.2 ° or less.
You. Here, when the main surface is a sapphire C surface,
Is a direction that is slightly inclined from the direction perpendicular to the A-plane by θ.
The direction may be the trip direction. At this time, θ is 0.1
It is preferable that the angle is in the range of about 0.4 °. The first,
When the surface of No. 2 is formed in a stripe shape, the surface A is mainly used.
When the sapphire is a plane, the first and second surfaces
If the ripe is almost perpendicular to the R-plane of the sapphire
It is preferable to have a stripe direction in the
When the spinel has a (111) plane as a main surface, the first,
2, the spinel (MgAl
_TwoO_Four) In the direction almost perpendicular to the (110) plane.
Has an Ip direction, or as shown in FIG.
From these vertical directions,
Is preferable. Because the heterogeneous substrate and the first and second
If the surface stripe direction is the above combination, the substrate
In the plane (in a plane parallel to the first main surface of the heterogeneous substrate)
The growth of the nitride semiconductor is anisotropic and the lateral growth of the selective growth layer
Growth (direction perpendicular to the stripe direction) is nitride semiconductor
Easy growth of the body and favorable lateral growth
This is because they tend to be performed. Above, growing heterogeneous substrates
For growing the first nitride semiconductor layer as a substrate
As mentioned above, nitrides grown on heterogeneous substrates
Semiconductors are also suitable for single substrates obtained by removing different types of substrates.
Can be used. In this case, when forming the nitride semiconductor substrate,
Determine the stripe direction according to the direction of the heterogeneous substrate
You.

As described above, the first surface and the second surface in the present invention are surfaces at which the growth rate of the nitride semiconductor on the first surface is smaller than that of the second surface.
Hereinafter, the first surface and the second surface will be described. The second surface only needs to have a surface on which a normal nitride semiconductor can be grown, and the growth surface of the first nitride semiconductor can be used as it is. The first surface needs to be subjected to a surface treatment so that the growth rate is lower than that of the second surface. Further, it is possible to apply some treatment to both the first surface and the second surface.
It is preferable to apply a surface treatment only to the surface of the above because the manufacturing process is shortened.

It is considered that there are various methods for forming a nitride semiconductor surface having a lower growth rate than a normal nitride semiconductor surface. For example, a method of thermally decomposing a nitride semiconductor surface, a method of etching, a method of implanting impurity ions, a method of forming a surface with poor crystallinity, and the like, damage or alter the crystal surface by various methods. This is feasible. In order to damage the crystal surface by etching, the crystal is damaged by dry etching, for example, reactive ion etching (RIE), reactive ion beam etching (RIBE), electron cyclotron etching (ECR), or ion beam etching. It is good to form a given surface. At this time, as the etching gas, a conventionally known etching gas for a nitride semiconductor may be appropriately selected. In the method of ion-implanting impurities, it is preferable to damage the crystal surface by implanting the above-described n-type impurities, p-type impurities, B, Al, and the like. The surface on which a nitride semiconductor layer doped with these impurities at a high concentration is grown can also be used because the crystal is damaged. With either of these methods,
By selectively forming a mask and performing these surface treatments on the mask opening, that is, the window, the first surface and the second surface are selectively formed.

Of the above methods, most preferably, thermal decomposition is used, whereby the first surface and the second surface can be formed by a simple manufacturing process, and the second nitride Semiconductor growth with good reproducibility and easy control,
Threading dislocations can be reduced. Hereinafter, a method of forming the first surface by thermal decomposition will be described with reference to FIG.

As shown in FIG. 1, a mask 20 is selectively formed on the surface of the first nitride semiconductor layer 11, and heat treatment and heating are performed to open the mask 20 as shown in FIG. In the part, the first surface partially pyrolyzed
Is formed on the nitride semiconductor layer. Subsequently, the mask 20 is removed (FIG. 1C), and a second nitride semiconductor layer is grown (FIG. 2D). When the second nitride semiconductor layer is grown in the growth mode as described above, FIG.
As shown in (2), a second nitride semiconductor substrate having a surface 12b of a region B with a low defect density and a surface 12a of a region A with a high defect density is formed. This low defect density region has a dislocation density of 1 × 10 ¹⁰ / cm ² or less, preferably 1 × 10 ¹⁰ / cm ^2.
It is 10 ⁸ / cm ² or less. Further, in a high defect density region, the dislocation density becomes 1 × ¹⁰ 10 / cm ² or more, if there are many defects in which the ¹ × ¹⁰ 1 3 / cm ² or more. Further, as shown in FIG. 4, the first and second nitride semiconductor layer growth steps are repeated twice or more, or as shown in FIG. 5, the first growth of the first and second nitride semiconductor layers is performed. After the process, a second growth process of the first and second nitride semiconductor layers is performed through a third nitride semiconductor layer growth process (thickening process), and further, the first and second nitride semiconductors are grown. growth process of the layers, by repeating the thick film process, to further reduce the dislocation density of the low defect density region B becomes possible, can be obtained a second nitride semiconductor layer surface of 10 ⁶ Order Becomes <Mask material> In the present invention, when a mask is formed on the surface of the first nitride semiconductor layer and the surface of the mask opening is selectively thermally decomposed to form the first surface, a mask material is used. It is only necessary that the surface of the first nitride semiconductor layer in the region covered with the mask can be protected during the heat treatment. Specifically, even if the heat treatment conditions, the mask material, and the like may affect the surface of the first nitride semiconductor layer covered with the mask, the second surface has a growth rate of the first surface. Since a larger surface may be formed, a protective film material that performs such a protective function is appropriately selected. That is, the second
And a mask material that is less thermally decomposed than the first surface of the mask opening. Preferably, the second surface covered with the mask is formed by thermal decomposition. The purpose is to provide a mask that has almost no surface. As a specific mask material, silicon oxide (S
iO _x ), silicon nitride (Si _x N _y ), titanium oxide (Ti
O _X), an oxide such as zirconium oxide (ZrO _X), can be used nitride, and these multi-layered films, metals, alloys, and the like. Examples of metals and alloy materials include Cu, Au, Cr and the like.
Is selected so that a mask pattern on the order of microns can be formed so that the surface of the substrate is formed. By using such a material, the nitride semiconductor is protected during the heat treatment, and the mask material is not diffused into the nitride semiconductor. As a method of forming these protective films, conventionally known vapor deposition techniques such as vapor deposition, sputtering, and CVD can be used.

In the present invention, the first nitride semiconductor layer is thermally decomposed by heat treatment to form the first surface.
By performing the heat treatment in the temperature range, it can be thermally decomposed, and as shown in FIG. 1, an uneven surface is formed. An embodiment of the method will be described below.

After the formation of the first nitride semiconductor layer, a mask is selectively formed on the surface thereof, and then placed in a reaction vessel of a growth apparatus known for growing the above-described nitride semiconductor. Here, the first vessel is placed in the reaction vessel of the MOCVD apparatus.
The wafer on which the nitride semiconductor is formed is set. Subsequently, the inside of the reaction vessel is maintained at a growth temperature region of the nitride semiconductor for a certain period of time while supplying a carrier gas or the like. In this way, the mask opening is thermally decomposed as shown in FIG. At this time, the heat treatment temperature is, as described above, a temperature at which the first nitride semiconductor is selectively thermally decomposed, and also depends on the shape and position of the heater, the reaction vessel, and the like. Specifically, the substrate temperature 30
0 ° C. to 1300 ° C., preferably 800 to 1200
In the range of ° C.

Further, since supplying the gas into the reaction vessel has an effect of selectively thermally decomposing the mask opening, it is better to appropriately select a gas suitable for such an operation. This is due to the fact that an atmosphere gas and a flow gas in the reaction vessel are in direct contact with the first nitride semiconductor layer exposed in the opening at the mask opening, so that a thermal decomposition action is effected. At this time, the temperature of the atmosphere in the reaction vessel is not particularly limited. Specifically, the heat treatment can be performed by setting the temperature in a range of 700 ° C. or more and 900 ° C. or less.
By setting the temperature in the range of 0 ° C. to 850 ° C., a heat treatment mode in which only the mask opening is selectively heat-treated without thermally decomposing the nitride semiconductor layer under the mask can be realized. In addition, as the atmospheric gas and the flow gas in the reaction vessel, specifically, I
It is preferable to use an atmosphere gas such as a carrier gas without supplying a source gas such as a group II element or a group V element or a source gas of a conductive impurity into the reaction vessel. This is because when a source gas serving as a nitride semiconductor material is supplied, it is difficult to obtain the thermal decomposition suitable for the first surface as described above. When a group III source gas is used, group III elements such as Ga and Al tend to adhere to the first nitride semiconductor layer as metal drops. Therefore, it is preferable not to supply the group III element into the reaction vessel. For this reason,
By using a group V source gas and a carrier gas, the first surface with a low growth rate is formed. When the source gas and the carrier gas are combined, a preferable heat treatment is realized by using the carrier gas and the ammonia gas in combination. More preferably,
By supplying only the carrier gas without supplying the source gas, a first surface for lowering the growth rate can be obtained. In addition, the case where the source gas of group V element NH ₃ is supplied and the case where it is not supplied In comparison with the above, it is preferable not to supply it because thermal decomposition is realized by heat treatment at a low temperature. At this time,
The carrier gas is not particularly limited, but an inert gas such as N ₂ , H _2, or the like can be used. Here, M
Although the heat treatment method using the OCVD apparatus has been described, it goes without saying that a carrier gas (atmosphere), a source gas, and the like are appropriately selected according to the reaction apparatus. When a gas is supplied into the reaction vessel, a mask material that can withstand these gases is selected. In addition, regarding the atmospheric pressure in the reaction vessel, there is no particular change in the heat treatment due to the difference, so that the pressure is reduced, the atmospheric pressure (normal pressure),
Either under pressure may be used.

At this time, the nitrogen atoms in the first nitride semiconductor layer are mainly thermally decomposed by the heat treatment using the above-mentioned gas, and In _x Al _y Ga _{1 -xy} N (0 ≦ x ≦ 1, 0 ≦ y ≦
In the case where the first nitride semiconductor layer composed of (1,0 ≦ x + y ≦ 1) is used, Al, In, Ga, and the like adhere to the first surface without being decomposed by the heat treatment. In this case, when removing the mask, the remaining Al, In, and Ga may be removed using a solution that can be dissolved or removed or washed. When the first surface and the second surface are formed on the surface of the first nitride semiconductor layer by heat treatment, Ga
By using N, it is possible to form a first surface which is excellent in growing the second nitride semiconductor layer. This nitride semiconductor containing Al, for example _{Al x Ga 1-x N (} 0 <x
≦ 1) is used for the first nitride semiconductor layer, the heat treatment temperature is higher than that in the case where Al is not included, so that the mask material is easily thermally decomposed, and the available mask material is limited. Since thermal decomposition also occurs on the second surface covered with the mask, the heat treatment tends to be difficult to control. As a result, the difference in growth rate between the obtained first surface and the second surface becomes small, and it becomes difficult to obtain the above-described growth form of the second nitride semiconductor layer. In addition, a nitride semiconductor containing In, for example, In _y Ga _1-y N (0 <y ≦ 1) is used as a first semiconductor.
When the nitride semiconductor layer is used, In is easily thermally decomposed, so that the heat treatment also affects the second surface covered with the mask, thereby selectively forming the first surface and controlling the first surface. It tends to be difficult.

When the first surface of the present invention is formed by the above-mentioned heat treatment, as shown in FIG.
The second nitride semiconductor layer 12 grown above has an effect of reducing the number of threading dislocations propagating from the first nitride semiconductor layer 11. Although this is not known in detail, it is considered that this may be due to the formation of moderate irregularities due to the heat treatment. Furthermore, as described above, during the heat treatment, the effect of reducing threading dislocations can be easily selected by supplying a gas into the reaction vessel and performing the heat treatment. Further, when only the carrier is used,
The reduction effect tends to be most easily obtained. <Application of Nitride Semiconductor Substrate of the Present Invention> In the present invention, it is also possible to form a plurality of second nitride semiconductor layers. Specifically, as shown in FIG. 4, after growing the second nitride semiconductor layer 12, the first nitride semiconductor
By forming the surface 12a and the second surface 12b, another nitride semiconductor layer 13 can be formed. in this way,
The first nitride semiconductor layer and the second nitride semiconductor can be grown two or more times. At this time, the second nitride semiconductor layer 12 formed at the first time has a low defect density region 12a formed on the first surface 1 and a high defect density region 12a formed on the second surface 2. 12b, the next layer 13 is formed so as to reduce threading dislocations in the high defect density region 12b.
Grow. By doing so, a nitride semiconductor layer having a low defect density can be formed on almost the entire surface. Referring to FIG. 4, after growing the second nitride semiconductor layer 12 for the first time, as shown in FIGS. 4A and 4B, it is selectively thermally decomposed to form irregularities. A second first surface 1 (12b) and a second surface 2 (12a) are formed. In this manner, the second surface 12a of the second growth is placed on the first surface 1 at the time of the first growth, and the first surface of the second growth is placed on the second surface 2 of the first growth. The surface 12b is provided. At this time, by forming the second second surface 12a so as to cover the first second surface 2, the threading dislocation extending from the first second surface 2 as shown in FIG. At the time of the second growth. Subsequently, by growing a nitride semiconductor layer 13 to be a second nitride semiconductor layer for the second time, a nitride semiconductor with reduced defects in both the region A and the region B is formed on the surface of the nitride semiconductor layer 13. Is obtained. On the contrary, 2
In the first growth, the defect density of the low defect density region B formed by the first growth is further reduced,
The second first surface and the second surface are formed in a pattern opposite to that shown in the figure, and the second first surface is formed on the first first surface to further reduce the low defect density region B. Defect reduction can also be achieved.

Further, as shown in FIG. 7, the second nitride semiconductor of the present invention comprises an element structure 104-112 and a substrate 101
And can be used as a base layer, and can also be provided inside the element structure as shown in FIG.

As shown in FIG. 5A, the nitride semiconductor layer grown on the second nitride semiconductor layer 12 has a low defect density as shown by hatching in the figure. In the region 12a and the high defect density region 12a, such a distribution of the defect density tends to be inherited as the regions A and B even in the nitride semiconductor grown thereon. A thick third nitride semiconductor layer 15 is formed on the second nitride semiconductor layer 12.
Are stacked to form a first nitride semiconductor layer 11 serving as an underlayer,
Second nitride semiconductor layer 12, third nitride semiconductor layer 15
Can be removed to form a nitride semiconductor single crystal. This is shown in FIGS. 5A and 5C.
As indicated by the arrow in the removal region C, the removal is performed from the heterogeneous substrate 10 side, and at least the space between the heterogeneous substrate and the first nitride semiconductor layer 11 is removed, that is, at least the first nitride semiconductor layer 11 is removed. By removing the material semiconductor layer 11,
Realize the simplification of nitride semiconductors. Thereby, the first nitride semiconductor layer having the first surface 1 and the second surface 2 is removed, so that a single substrate is obtained in which a region with low crystallinity is removed, and the electrode formation from the back surface is good. Substrate. More preferably, by removing the second nitride semiconductor layer, the above-mentioned growth form of the second nitride semiconductor is formed with lateral growth. As shown in FIG. 3, many defects are provided in the second nitride semiconductor layer, which causes the propagation of defects. More preferably, FIG.
A single substrate is formed so that a part of the third nitride semiconductor layer is removed as shown as a removal region C in (b), whereby the crystallinity is excellent and the warpage is reduced. It becomes a single substrate.

When a single substrate is obtained, as described above, the thickness of the thick third nitride semiconductor layer 15 or the total thickness of the nitride semiconductor grown on the heterogeneous substrate is at least 50 μm or more. By doing so, it is possible to form a single substrate, preferably 100 μm or more, which facilitates handling when the single substrate is taken out, and improves the yield of taking out the single substrate. Further, in consideration of the warpage of the substrate before the removal, it is preferable that the thickness be in the range of 80 μm to 120 μm as described above. In order to form such a thick third nitride semiconductor layer 15, HVPE having a high growth rate is preferably used, but the thick third nitride semiconductor layer 15 is preferably used.
Is formed by HVPE, there is a tendency that a domain formed by nucleus growth from a generated nucleus grows in a film thickness direction and a three-dimensional growth form is formed in which each domain is combined and formed into a film.
In such a case, threading dislocations also propagate along with nucleus growth, so that threading dislocations tend to be dispersed. For example, as shown in FIG. 5A, when the third nitride semiconductor layer 15 is grown on the low defect density region 12b and the high defect density region 12a, threading dislocations are dispersed, and In the regions A and B corresponding to the respective regions of the semiconductor, the defect density difference is reduced or averaged to show a uniform distribution.
Such a growth mode tends to be obtained by increasing the growth rate of HVPE, and specifically, 10 μm
When growing at a growth rate of / hr or more, dispersion of threading dislocations tends to be confirmed. Needless to say, the thickness of the second nitride semiconductor layer 12 may be increased to form a third nitride semiconductor layer.

In the present invention, as shown in FIG.
After the formation of the nitride semiconductor layer 12 or the third nitride semiconductor layer 15 grown thereon, the heterogeneous substrate used as the growth substrate and the first nitride semiconductor layer having the first surface are removed. For example, as shown in FIG. 5B, after the nitride semiconductor single substrate is formed, another nitride semiconductor layer 16a, 16b can be further grown on the growth surface and the removed surface. When this method is used, a first nitride semiconductor layer and a second nitride semiconductor layer are grown on a heterogeneous substrate, and the third nitride semiconductor layer is further thickened. Since the warpage of the substrate due to lattice mismatch with the third nitride semiconductor substrate 15a becomes large, the third nitride semiconductor substrate 15a from which the dissimilar substrate has been removed is formed, and then the fourth nitride semiconductor layer 16 is formed on the single substrate.
By growing the film to increase the film thickness, the warpage of the substrate can be reduced. At this time, the thickness of the nitride semiconductor layer to be grown on the single substrate is specifically 100 μm to 400 μm.
The following is preferable because warpage is reduced. Further, when HVPE is used when growing a nitride semiconductor on a single substrate, dispersion of threading dislocations described above progresses, and the distribution of threading dislocation density tends to disappear. The composition of the nitride semiconductor of the third nitride semiconductor is the above-mentioned In _x Al _y Ga
_1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1)
In represented can be a nitride semiconductor of the composition, preferably _{Al x Ga 1-x N (} 0 ≦ x ≦ containing no In
By using 1), a thick film having good crystallinity can be formed. Further, by using the same composition as that of the second nitride semiconductor layer serving as an underlayer of the third nitride semiconductor layer, crystal growth without lattice mismatch can be performed, which is preferable. Also,
When the third nitride semiconductor layer is grown using HVPE, good growth is possible by using a nitride semiconductor layer containing no In, and further, a ternary mixed crystal represented by AlGaN It is more preferable to use a binary mixed crystal of AlN and GaN because good crystal growth can be achieved.

As described above, the present invention can be used for forming a single substrate, and a first nitride semiconductor layer and a second nitride semiconductor layer are formed on different kinds of substrates to reduce threading dislocations. A first step, after the first step, a second step of increasing the film thickness by, for example, growing a thick third nitride semiconductor layer,
After the step, the heterogeneous substrate used for the growth, a part or all of the first nitride semiconductor layer and the second nitride semiconductor layer, and a part of the third nitride semiconductor layer are removed and nitrided. Through the third step of obtaining the single substrate of the product semiconductor, the single substrate can be formed. Furthermore, after the third step, the single substrate is formed in the first nitride semiconductor layer or the second time in which the first nitride semiconductor layer is formed on the single substrate and the second nitride semiconductor layer is formed. And the second step
Through the step described above, the film may be thickened. Furthermore, after the second first step or the second second step, in the third step, a part of the nitride semiconductor substrate can be removed to adjust the film thickness to be small. Sometimes it is good to reduce the warpage of the substrate. Further, after the first step and the second step, a third step may be provided through a laminating step of laminating an element structure. That is, in the second step, a thick nitride semiconductor from which a single substrate can be taken out is formed, an element structure is formed thereon, and then the heterogeneous substrate is removed (third step).
Then, take out the chip with cleavage of nitride semiconductor,
The wafer can be divided. Further, as another mode, as described above, after the first, second, and third steps, 2
In the second step, the fourth nitride semiconductor layer 16 is grown to further increase the thickness of the single substrate, thereby reducing the warpage of the substrate as described above. In order to carry out the thickening by the second step two or more times, it is necessary to remove the heterogeneous substrate and singulate the nitride semiconductor through the third step after at least the first second step. By doing so, it is possible to prevent the substrate from cracking when the film is made thick. Therefore, after the first, second, and third steps, the first step and the second step are variously combined to reduce threading dislocations in the first step and increase the film thickness in the second step. Although it is possible to repeatedly perform the warpage reduction, the surface morphology tends to be deteriorated in the second step two or more times, such as formation of a large step on the substrate surface. For this reason, after the first, second, and third steps, the nitride semiconductor single substrate obtained is subjected to only one thickening step (second second step).
In this case, a nitride semiconductor single substrate having excellent surface morphology and reduced threading dislocations and warpage can be obtained.

As a mode in which the second nitride semiconductor layer of the present invention is used for a nitride semiconductor device, as shown in FIG. The second nitride semiconductor layer 12 may be provided in the element structure as shown in FIG. In the second nitride semiconductor layer 12, a low defect density region is formed on the first surface and a high defect density region is formed on the first surface. A structure may be formed. Specifically, as shown in FIG. 7, the low defect density region 1 provided in the second nitride semiconductor layer 12
A ridge is provided so that a stripe-shaped waveguide region of the laser element is formed on 2b, and a plurality of waveguide regions are formed by applying the ridge to a low defect density region as shown in FIG. In addition to forming a laser element provided on 12b,
As shown in FIG. 10, a structure in which current flows selectively over the low defect density region 12b can be a light emitting element. The nitride semiconductor device having such a structure has a structure in which a current flows through the active layer on the low defect density region 12b provided in the second nitride semiconductor layer 12 in common to both. With such a structure, FIGS.
Since the low defect density region is inherited in the element structure by hatching, current is selectively passed through the low defect density region in the active layer, and a high-output nitride semiconductor device is obtained.

[0038]

Embodiments of the present invention will be described below.

Example 1 A sapphire substrate having a thickness of 425 μm, a diameter of 2 inches, a main surface of a C-plane, and an orientation flat surface (hereinafter referred to as an orientation flat surface) of an A-plane is used as a heterogeneous substrate on which a nitride semiconductor is grown. Prepare the MOCV
The wafer is set in the reaction vessel D. Next, the first
Temperature of 5 as an underlayer for growing a nitride semiconductor layer of
At 10 ° C., hydrogen was used as a carrier gas, ammonia and TMG (trimethylgallium) were used as source gases, and a low-temperature growth buffer layer made of GaN was formed on a sapphire substrate by about 2 μm.
The substrate is grown to a thickness of 00 ° (angstrom), the temperature is further set to 1050 ° C., and an underlayer made of undoped GaN using TMG and ammonia as source gases is 2.5 μm.
It is grown to a thickness of m. Using this base layer, a first nitride semiconductor layer and a second nitride semiconductor layer are formed. As shown in FIG. 1, on the first nitride semiconductor layer 11, θ = 0.3 from a direction perpendicular to the orientation flat surface (A surface) of the sapphire substrate.
Mask 2 made of striped SiO ₂ tilted by °
0 is formed under the conditions of a width of 14 μm and an interval (width of the opening) of 6 μm. Subsequently, the wafer is transferred into a MOCVD reaction vessel, the temperature in the reaction vessel is set to 760 ° C., and H ₂ , N ₂
While supplying 5 l (liter) / min.
Minutes. By this heat treatment, as shown in FIG.
Is formed. Subsequently, by immersing the substrate in buffered hydrofluoric acid to remove the stripes, Ga on the first surface deposited by the heat treatment is simultaneously removed by washing.
At this time, as a method for removing the mask 20, the inside of the reaction vessel is rapidly cooled after the heat treatment, and the mask 20 and the first nitride semiconductor layer 11 are separated by using a difference in thermal expansion coefficient between the mask 20 and the first nitride semiconductor layer 11, and the wafer is removed from the reaction vessel. Remove the mask 20 without taking it out,
The next second nitride semiconductor 12 can also be grown.

As a result of the heat treatment, the second surface 2 of the mask region and the thermally decomposed first surface 1 are formed on the first nitride semiconductor layer 11, and the second nitride As a semiconductor layer, undoped GaN is formed to a thickness of 5 μm. By growing the second nitride semiconductor layer 12, as shown in FIG. 1C, the growth region having the irregularities grown from the first surface 1 shrinks, and The grown nitride semiconductor spreads and grows. In the obtained second nitride semiconductor layer 12, a low defect density region B is formed on the first surface 1 and a high defect density region A is formed on the second surface 2. This is because the nitride semiconductor grown from the first surface 1 significantly reduces threading dislocations inherent in the first nitride semiconductor layer 11 as shown in FIG. Is grown, the growth region from the first surface 1 is narrowed, and the second nitride semiconductor layer 12 is grown, whereby threading dislocations from the first surface 1 are further reduced. In addition, threading dislocations in a region of the second surface 2 near the first surface 1 are also reduced. Here, the second nitride semiconductor layer 12 was grown with a thickness of 5 μm. However, as shown in Example 4, the growth with a thickness of 5 μm only flattens the surface. In order to obtain the effect of the underlayer for improving the crystallinity and the surface morphology, it is preferable to form the element structure after further growing the film to a thickness of 3 μm and a total of 8 μm.

Thus, the second nitride semiconductor layer 12
Is a nitride semiconductor substrate suitable for forming an element structure.
As shown in FIG. 1, the grown second nitride semiconductor layer 1
2, a low defect density region B (12b) and a high defect density region A (12a) are formed on the first surface in a stripe shape corresponding to the second surface, and have a width of about 6 μm and a width of 14 μm, respectively.
And the defect density is about 10 ⁸ , 10 ¹⁰ / cm ² .

Example 2 The procedure of Example 1 was repeated, except that only H ₂ was used as the gas to be supplied into the reaction vessel during the heat treatment. 2 are formed. As in the first embodiment, the obtained second nitride semiconductor layer has a defect density distributed in a stripe shape, and has a threading dislocation greatly reduced at the upper portion of the first surface. Further, the heat treatment conditions were changed to N ₂
When NH ₃ and NH ₃ are used, a large number of threading dislocations tend to be generated in the second nitride semiconductor layer grown on the first surface as compared with the first embodiment. The reduction in threading dislocations is smaller than when used for heat treatment.

[Example 3] Under the heat treatment conditions of Example 1, when the temperature inside the reaction vessel was set to 800 ° C and thermal decomposition was performed, thermal decomposition was partially caused even on the second surface protected by the mask. It is observed and exhibits slight surface irregularities as compared to the first surface of the mask opening. Subsequently, when a second nitride semiconductor layer is grown in the same manner as in Example 1, a difference in growth rate between the first surface and the second surface is not observed as in Example 1, and the second nitride semiconductor layer is grown from the first surface. Growth region from the second surface is narrowed and the tendency for the growth region from the second surface to expand is weakened, and threading dislocations from the first surface reach the surface.
Because part of the surface was also thermally decomposed,
Threading dislocations on the surface tend to decrease. As a result, as compared with Example 1, the second nitride semiconductor layer has a smaller defect density difference, weaker stripe-shaped defect density distribution, and a surface in which threading dislocations are dispersed. Thus, a nitride semiconductor with reduced threading dislocations is obtained.
However, on the other hand, since the difference in growth rate between the first surface and the second surface is small, the lateral growth of the nitride semiconductor grown from the second surface is reduced, and therefore, the first In the region of the surface of the second nitride semiconductor layer on the surface,
The effect of reducing threading dislocations is smaller than that of the first embodiment, and when a selectively formed low defect density region is used for the element structure, the number of defects is larger than that of the first embodiment.

[Embodiment 4] Hereinafter, as Embodiment 4, the laser device structure of the schematic sectional view shown in FIG. 7 will be described step by step.

After forming a low-temperature growth buffer layer 102, a first nitride semiconductor layer 11, and a second nitride semiconductor layer 12 on a sapphire substrate 101 in the same manner as in the first embodiment, A buffer layer 103 made of undoped AlGaN having an Al composition ratio of 0.01 is formed as a buffer layer 103 on the semiconductor layer. At this time, the second nitride semiconductor layer 12 is grown to a thickness of 8 μm as shown in Example 1, and as shown in FIG. A low defect density region 12a at the upper portion of the second surface is formed. This buffer layer 10
3 can be omitted, but the second nitride semiconductor layer is made of GaN.
In this case, the pits can be reduced by using the buffer layer 103 made of _a nitride semiconductor having a smaller coefficient of thermal expansion, AlaGa1 _- aN (0 <a ≦ 1). It is preferable that the buffer layer 103 be formed over the second nitride semiconductor layer. This buffer layer 10
No. 3 has a tendency that pits are easily generated in the nitride semiconductor layer formed along with the growth in the film thickness direction and the lateral direction like the second nitride semiconductor layer 12. Has the effect of preventing.

Further, the Al mixed crystal ratio a of the buffer layer 103 is
When 0 <a <0.3, the buffer layer can be formed with good crystallinity. This buffer layer is n
The buffer layer 10 may be formed as a side contact layer.
After the formation of No. 3, n represented by the composition formula of the buffer layer
Alternatively, a buffer layer 103 and an n-side contact layer 104 thereon may have a buffer effect by forming a side contact layer. That is, the buffer layer 103 is provided between the second nitride semiconductor layer and the element structure or between the active layer and the second nitride semiconductor layer in the element structure.
More preferably, at least one or more layers are provided between the lower clad layer and the second nitride semiconductor layer on the substrate side in the device structure, whereby pits can be reduced and device characteristics can be improved. Further, when the n-side contact layer is used as a buffer layer, the Al mixed crystal ratio a of the n-side contact layer is preferably set to 0.1 or less so as to obtain a good ohmic contact with the electrode. The buffer layer provided on the second nitride semiconductor layer may be grown at a low temperature of 300 ° C. or more and 900 ° C. or less, similarly to the buffer layer provided on the heterogeneous substrate described above. The single crystal may be grown at a temperature of preferably 800 ° C. or more and 1200 ° C. or less, and the pit reducing effect described above tends to be obtained. This buffer layer may be doped with n-type or p-type impurities or may be undoped, but is preferably formed undoped in order to improve the crystallinity. When two or more buffer layers are provided, they can be provided by changing the n-type and p-type impurity concentrations and the Al mixed crystal ratio.

The following element structure is formed on the buffer layer 103 made of AlGaN.

N-side contact layer 104: 4 μm thick, S
GaN or A doped with 3 × 10 ¹⁸ / cm ^{3 of} i
l _0.01 Ga _0.99 N anti-crack layer 105: 0.15 μm thick In _0.06 G
a _0.94 N (may be omitted) n-side cladding layer 106: superlattice structure having a _total film thickness of 1.2 μm undoped Al _0.0516 Ga _{0.95 having a} film thickness of 25 _°
N and GaN doped with Si at 1 × 10 ¹⁹ / cm ³ with a thickness of 25 ° are alternately stacked.

N-side light guide layer 107: film thickness 0.15 μm
Undoped GaN active layer 108: multiple quantum well structure with total thickness of 550 ° S
140 ° -thick S doped with 5 × 10 ¹⁸ / cm ^{3 of} i
Barrier layer made of i-doped In _0.05 Ga _0.95 N
(B) and a 50 ° -thick undoped In _0.13 Ga
_The well layer (W) made of _0.87 N is referred to as (B)-(W)-(B)-(W)-
The layers are laminated in the order of (B).

P-side electron confinement layer 109: film thickness 100 °,
P-type Al _0.3 G doped with 1 × 10 ²⁰ / cm ^{3 of} Mg
a _0.7 Np side light guide layer 110: Mg of 0.15 μm thickness is 1 ×
10 ¹⁸ / cm ³ -doped p-type GaN p-side cladding layer 111: a superlattice structure having a total thickness of 0.45 μm and an undoped Al _0.05 Ga _0.95 thickness of 25 °
N and p-type GaN doped with Mg at 1 × 10 ²⁰ / cm ³ with a thickness of 25 ° are alternately stacked.

P-side contact layer 112: 150 ° thick
After forming a p-type GaN device structure doped with Mg at 2 × 10 ²⁰ / cm ^{3, the} wafer is taken out from the MOCVD apparatus, and then the laminated semiconductor layer is finely processed by etching to form a resonator structure as a laser device. To form As shown in FIG. 7, a desired pattern of SiO _{2 is} formed on the surface of the taken-out wafer (the surface of the p-side contact layer 112).
A film is formed by a photolithography technique, and is etched until the n-side contact layer 104 is exposed.
An electrode formation surface is provided. Next, a ridge stripe shown in FIG. 7 is formed in a region where the n-side contact layer 103 is not exposed as described below. First, a mask made of SiO ₂ is formed on the surface of the p-side contact layer 112, and a mask made of 1.8 μm wide stripe-shaped SiO ₂ is formed by photolithography. The p-side contact layer 112, the p-side cladding layer 111, and a part of the p-side light guide layer 110 are etched and removed by RIE using SiCl ₄ gas, and after forming a ridge stripe, the wafer is further placed in a PVD apparatus. The protective film 1 made of Zr (mainly ZrO ₂ ) is transported over the exposed surface of the ridge stripe formed from above the mask made of SiO _2.
62 (buried layer) is formed with a thickness of 0.5 μm, the wafer is immersed in hydrofluoric acid, and the SiO ₂ mask is removed by a lift-off method. Thus, a ridge stripe having a width of 1.8 μm is formed as a stripe-shaped waveguide region as shown in FIG. Is formed. At this time, the buried layer is not limited to the oxide of Zr, but Ti,
Oxides containing at least one element selected from the group consisting of V, Nb, Hf, Ta and Zr, SiN, BN, S
at least one of iC and AlN, or a combination thereof, and the upper cladding layer 111 and the opposite conductive type n
_-Type , semi-insulating, i-type nitride semiconductor (In _x Al _y Ga
_1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦
1)) can be used. Further, as shown in FIG. 7, the ridge stripe is disposed above the second nitride semiconductor layer 12 so as to be provided in the low defect density region 12b.

Finally, the n exposed by the etching
N-electrode 121 made of Ti / Al and Ni / Au on the surface of p-side contact layer 104 and p-side contact layer 112, respectively.
A p-electrode 120 (formed over the protective film 162 provided on the ridge stripe surface as shown in FIG. 7) is formed. Next, after providing a reflective film 164 of a dielectric multilayer film composed of SiO ₂ and TiO ₂ , N
i-Ti-Au (1000-1000-8000)
Extraction (pat) electrodes 122 and 123 composed of Å) were provided, respectively. The extraction electrodes 122 and 123 electrically connected to each electrode and having a length of about 600 μm from the etched end face side serving as the resonator reflection face are used as the reflection film 16 as an insulating film.
4 is formed. At this time, the width of the active layer 108 is 2
00 μm width (width in the direction perpendicular to the resonator direction)
A dielectric multilayer film 164 made of SiO ₂ and TiO ₂ is also provided on an etching end surface (including an active layer end surface) provided when the n-side contact layer 104 is exposed, and becomes a reflection film when it is used as a resonator surface. After forming the n-electrode and the p-electrode, the substrate is divided into bars in the direction perpendicular to the stripe-shaped electrodes by the M-plane (hexagonal M-plane, {11-00}) of the nitride semiconductor. Then, the bar-shaped wafer is further divided to obtain laser devices.
At this time, the resonator length is 650 μm. At this time, when forming a bar shape, cleavage is performed in the waveguide region sandwiched between the etching end surfaces, and the obtained cleavage surface may be used as a resonator surface,
It is also possible to cleave outside the waveguide region and use the etched end face as a resonator face, or to form a pair of resonator faces with one etched end face and the other as a cleavage face. In addition, a reflection film made of a dielectric multilayer film is provided on the resonance surface of the etching end face, but a reflection film may be provided on the cavity surface of the cleavage surface after cleavage. At this time, SiO ₂ , T
iO ₂ , ZrO ₂ , ZnO, Al ₂ O ₃ , MgO, at least one member of the group consisting of polyimide,
It may be a multilayer film laminated with a thickness of λ / 4n (λ is the wavelength, n is the refractive index of the material), or may be a single layer, and may be used as a surface protective film for preventing the exposure of the cavity facet simultaneously with the reflection film. May also function. Further, as the cleavage plane of the nitride semiconductor, in addition to the M plane, an A plane {1 1 2-0} approximated to a hexagonal system can be used.

[0053] The laser device thus obtained has a threshold current density of 2.5 kA / cm ² at room temperature, the threshold voltage 4.5V, the oscillation wavelength 4
With a continuous oscillation of 05 nm and 30 mW, a laser element with a long service life exceeding 1000 hours and a high output can be obtained. Here, in the present embodiment, as described above, the second nitride semiconductor layer 1
By forming an element structure corresponding to the low defect density region 12b and the high defect density region 12a formed in 2, a high output nitride semiconductor light emitting device can be obtained. Specifically, the low defect density region 12 of the second nitride semiconductor layer 12
Since a low defect density region is formed in the ridge stripe above this region b, a current mainly flows through the active layer in the low defect density region 12b to increase the output. , And the service life can be extended.

Example 5 As in Example 4, a low-temperature growth buffer layer 10 was formed on a substrate 101 made of sapphire.
2, a first nitride semiconductor layer 11 and a second nitride semiconductor layer 12 are formed, and as shown in FIG. 8, this second nitride semiconductor layer 12 is A layer 104 is formed, and subsequently, a crack preventing layer 105 to a p-side contact layer 112 are laminated in the same manner as in the fourth embodiment. At this time, n
It is preferable to provide the buffer layer 103 between the side contact layer 104 and the crack prevention layer 105 in the same manner as in the first embodiment because pits are reduced. The resulting laser element is
A high-output, long-life laser device substantially equivalent to the fourth embodiment is obtained.

Example 6 A laser device was fabricated in the same manner as in Example 5, except that the second nitride semiconductor layer 12 was replaced with Si-doped AlGaN (Al alloy crystal ratio: 0.01). obtain. The obtained laser device is a laser device having a high output and a long life almost equivalent to that of the fifth embodiment. In this embodiment, the compositions of the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12 are set to be different from each other as GaN and AlGaN, but the crystallinity of the obtained second nitride semiconductor layer is No major change appears.

[Example 7] In Example 1, a low-temperature growth buffer layer, a first nitride semiconductor layer, and a second nitride semiconductor layer were formed on a substrate made of sapphire. As shown in FIG. 5, after forming a thick third nitride semiconductor layer 15 on the second nitride semiconductor layer 12 and performing a thickening process, as shown in FIG. The second nitride semiconductor layer 13 is grown. At this time, the first
Of the nitride semiconductor layer 14 and the second nitride semiconductor layer 13
The second formation of the second nitride semiconductor layer 13 using undoped GaN having the same composition as the first formation is performed by forming the second first nitride semiconductor layer 15 on the thick third nitride semiconductor layer 15. The layer 14 is formed under the same conditions as the first time, and is heat-treated to form a first surface and a second surface. The third nitride semiconductor layer 15 is formed by growing undoped GaN with a thickness of 100 μm using HVPE, so that the entire surface of the third nitride semiconductor layer 15 becomes 10 ⁹ / cm ^2. . Further, by forming the second nitride semiconductor layer for the second time under the same conditions as the first time, the surface of the second nitride semiconductor layer for the second time has a defect density of 5 × 10 ⁶ / cm ² . A defect density region and a high defect density region with a defect density of 10 ⁹ / cm ² are formed in stripes with a width of 6 μm and 14 μm, respectively.

A laser device shown in FIG. 7 is manufactured in the same manner as in Example 1 using the second nitride semiconductor layer 13 obtained as described above as a growth substrate. At this time, as shown in FIG. 5, a heterogeneous substrate made of sapphire, a low-temperature growth buffer layer, a first first nitride semiconductor layer 11, The nitride semiconductor layer 12 and a part of the thick third nitride semiconductor layer 15 are singulated from the nitride semiconductor substrate removed by a removal step such as polishing. It may be singulated at any stage after the formation of the structure, after the formation of the ridge stripe, and after the formation of the electrodes, or before the formation of the element structure. Here, after the electrodes are formed, a removing step is performed to singulate.

On the second nitride semiconductor layer 13 for the second time, the device structure of the buffer layer 103 to the p-side contact layer 112 is laminated in the same manner as in the fourth embodiment.
Form electrodes. Subsequently, as shown in FIG. 5C, a sapphire heterogeneous substrate 10, a low-temperature growth buffer layer (not shown), a first first nitride semiconductor layer 11, a second nitride semiconductor layer 12, And thick third nitride semiconductor layer 15
Is removed by polishing (removed area C in the figure),
A chip is obtained by cleavage of the nitride semiconductor. At this time, the laser device shown in FIG. 7 is obtained.
The substrate 101 is partially removed by the removing
This is a single substrate made of the third nitride semiconductor layer 13 having a thickness of 0 μm, the buffer layer 102 is not formed, and the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12 are both formed for the second time. It will be formed. When the wafer is divided and the chips are taken out, the same method as in the fourth embodiment may be used. However, the wafer is cleaved in a bar shape on the M-plane of the nitride semiconductor.
Since one of the resonator surfaces is a cleavage end surface and a nitride semiconductor single substrate is used for the substrate 101, the bar-shaped wafer can be further converted to the nitride semiconductor A-plane (｛11 1 when approximating a hexagonal system).
Cleave almost perpendicular to the cavity direction on the (2-0) plane, and take out the chip. As described above, when the single substrate of the nitride semiconductor is used, the cleavage plane and the easy cleavage plane of the nitride semiconductor can be used at the time of chip cutting.

In the obtained laser device, the defect density in the low defect density region is reduced as compared with the fourth embodiment, so that both the output and the device life are improved.

Example 8 A laser device having a counter electrode structure shown in FIG. 11 is manufactured. In the same manner as in Example 7, as shown in FIG. 4, a low-temperature growth buffer layer, a first first nitride semiconductor layer 11, a second nitride semiconductor layer 12, A third nitride semiconductor layer 15 of a film, a second first nitride semiconductor layer 14 and a second nitride semiconductor layer 13 are formed.
The first nitride semiconductor layer 14 and the second nitride semiconductor layer 13 of the second nitride semiconductor layer 15 (partially a single substrate 201) are each doped with an n-type impurity to have an n conductivity type. Here, Si is doped. Then, the second time of the second
A buffer layer 203 is formed on the nitride semiconductor layer 13 in the same manner as in Example 4, and a crack prevention layer 205, an n-side cladding layer 206, and an n-side
7. The active layer 208, the p-side electron confinement layer 209, the p-side light guide layer 210, the p-side cladding layer 211, and the p-side contact layer 212 are laminated. Unlike the first embodiment, the n-side contact layer is not formed, the third nitride semiconductor layer is used as the substrate 201, and at the same time, the buffer layer 20 is used as the n-side contact layer.
3 is also doped with Si as an n-type impurity. Subsequently, as in the seventh embodiment, the ridge stripe, the buried layer 262, p
After the electrode 220 is formed, as shown in FIG. 4 as a removal region C, the substrate 10, the first first nitride semiconductor layer 11,
Second nitride semiconductor layer 12, third nitride semiconductor layer 15
And a third nitride semiconductor layer 15 of about 80 μm is used as a single substrate for the substrate 201. continue,
As shown in FIG. 11, the n-electrode 2 is formed on the back side of the nitride semiconductor substrate 201, on the side opposite to the surface on which the element structure is laminated.
21 are formed, and then cleaved on the M-plane of the nitride semiconductor to form a bar shape by cleavage substantially perpendicular to the ridge stripe direction, as in Example 4, and the nitride semiconductor A perpendicular to the cleavage plane is further formed. Cleave at the surface to obtain a chip. Thereafter, Example 4
Similarly to the above, a reflective film, an insulating film, and the like are formed on the side surface (the surface not perpendicular to the waveguide) of the active layer and on the end surface of the active layer perpendicular to the waveguide, and are further electrically connected to the p-electrode and the n-electrode. A laser element is obtained by providing an extraction electrode.

In the laser device thus obtained, the electrodes are arranged to face each other, and the first nitride semiconductor layer 11 and the second nitride semiconductor layer 12, which are the underlying layers, have the conventional lateral growth. As described above, since no mask material is contained, the flow of current is not hindered and good current injection is realized. For this reason, the first nitride semiconductor layer 11 and the second
By using the nitride semiconductor layer 12 described above, the defect density can be reduced. This is particularly effective when a nitride semiconductor single substrate having dislocation defects is used as in this embodiment.

Ninth Embodiment In the same manner as in the seventh embodiment, the same buffer layer 203 as the buffer layer 103 and the n-side layers 230 as the n-side contact layers 104 to 107, the active layer 208, and the p-side layer 231. As the electron confinement layer 109 ~
The p-side contact layer 112 and the p-side contact layer 112 are stacked to form an element structure, thereby manufacturing a laser element. As shown in FIG. 9, a laser element is provided with a plurality of stripe-shaped waveguides. In the figure, the hatched area indicates the low defect density area B formed on the first surface 1 of the first nitride semiconductor layer 11. Here, FIG. 9A is a schematic cross-sectional view showing an element structure, and FIG. 9B is a schematic view showing an electrode arrangement, a p-side layer, and a ridge stripe arrangement from the top. The width of the low defect density region B is about 6 μm, and the region B is formed up to the p-side contact layer which is the uppermost layer of the element structure. Therefore, the first surface 1 formed in a stripe shape
Ridge stripes 240 are formed substantially at the center of each of the ridge stripes 240. Each ridge stripe 240 has one ridge stripe 240 disposed on one first surface 1, and as shown in FIG. The two second surfaces are sandwiched and arranged. The method of forming a plurality of waveguide regions by forming a plurality of ridge stripes is not limited to this. For example, a low defect density region B on one first surface may be used.
A plurality of ridge stripes may be arranged such that a plurality of waveguide regions are formed therein, and between two or more adjacent ridge stripes, two or more high defect density regions A on the second surface 2. (Regions not hatched in the drawing) may be provided. Therefore, a plurality of low defect density regions B are provided in at least one element, and a ridge stripe is provided so as to overlap a part, preferably all of the low defect density regions B, so that a plurality of waveguide regions are provided. That is, a plurality of structures are formed. Preferably, the region B is provided so that one waveguide region is provided in one low defect density region B.
Is to form one ridge stripe inside. By doing so, the active layer and the p-side layer 23 on the active layer are formed.
1, at least a part of a region (current region) where current flows,
Preferably, all of them are arranged so as to overlap with the low defect density region B, and a current flows selectively in a place where the crystal defect of the active layer is small, thereby driving the element. Therefore, it is possible to improve the output and the life of the element. Further, as in the present embodiment, by using a laser element having an array structure in which a plurality of waveguides are provided, high output is achieved, and a plurality of waveguide regions are selectively arranged in the low defect density region B. Further, higher output and longer life can be achieved.

As shown in FIG. 9, three ridge stripes 240 are arranged at substantially the center of the low defect density regions B arranged in a stripe shape over the second surface 2, and the n-electrode 221 is The p-electrode 220 is formed on the outer side and both sides of the ridge stripe 240 as a stripe-shaped electrode substantially parallel to the ridge stripe. The buried layer is formed on the side surface of the ridge stripe and on the exposed surface where the ridge stripe is formed, as in the seventh embodiment. Also, multiple p
The electrode 220 and the plurality of n-electrodes 221 may be electrically insulated from each other and arranged independently, or may be electrically connected and serve as a common electrode. To form a common electrode, for example, as shown in FIG. 9B, the exposed surface of the n-side contact layer 204 where the n-electrode 221 is to be formed (the area not hatched) is replaced with the p-side layer 231. The n-electrode 222 is formed so as to surround the convex region including the active region, and surrounds the outside of the active layer end face (resonator end face).
Stripe-shaped n-electrodes 222 are formed extending parallel to the waveguide region and arranged on both sides of the active layer. At this time,
The n-electrode may be arranged so as to surround four sides of the end face of the active layer. However, if an exposed surface of the n-side contact layer 203 is formed on the emission end face side, the emitted light may be blocked. The exposed surface of the n-side contact layer 203 is preferably formed. At this time, the ohmic electrode that is in ohmic connection with the n-side contact layer 203 is formed in a stripe shape, an electrode is formed almost in parallel with the waveguide, outside the active layer, and an extraction electrode (pad electrode) formed thereon. Thus, the respective electrodes may be electrically connected, or the ohmic electrodes may be electrically connected by metal wiring. To make the p-electrode 220 a common electrode, the p-electrode 220 is electrically connected to the p-electrode 220 provided on each ridge stripe over the buried layer provided on the side surface of the ridge stripe and the exposed surface of the p-side layer 231 continuous therewith. It is possible by providing a take-out electrode. Similarly to the n-electrode 222, at least one end of the ridge stripe is provided with a projection for joining each ridge at the time of forming the ridge stripe, and a p-electrode common to each ridge is provided on the surface of the p-side contact layer. Alternatively, for example, the p-side layer 331 and the p-electrode 310 shown in FIG. 10C can be used. Here, the p-side contact layer surface of each ridge stripe is
Electrodes are formed, electrically connected to them, and an extraction electrode is formed over the buried layer surface.

In the array laser device obtained in this manner, as shown in FIG. 9, each ridge stripe is selectively provided in the low defect density region B hatched in the drawing. By selectively supplying a current to the stripe-shaped waveguide region in the low defect density region B, particularly to the active layer in the low defect density region B, it is suitable for driving with a large current.
In addition, light emission and laser oscillation with high output can be performed.

[Embodiment 10] In the same manner as in Embodiment 1,
A low-temperature growth buffer layer is formed on a substrate 301 made of fire.
302, first nitride semiconductor layer 11, second nitride semiconductor
The body layer 12 is formed, and on the second nitride semiconductor layer 312,
As shown in FIG. 7A, the following LED element structure is formed.
I do. N-side contact layer 304: 4.5 × 10 Si¹⁸/ C
m³Doped GaN 2.25 μm n-side first multilayer layer 305: undoped GaN 200n
m / Si is 4.5 × 10 ¹⁸/ Cm³Doped GaN
 Multilayer of 30nm / undoped GaN 5nm
Film n-side second multilayer film 306: undoped GaN, 4 nm
First layer and undoped In_0.13Ga_0.87N, 2
nm second layer as a pair, alternately 10 layers each,
A multilayer film in which 10 pairs are stacked and a first layer is finally stacked Active layer 307: undoped GaN, having a thickness of 20 nm
Barrier layer (B) and undoped In_0.4Ga
_0.6N, well layers (W) each having a thickness of 3 nm are alternately formed.
(B) / (W) / (B)... (B)
Active multiple quantum well structure consisting of five barrier layers and four well layers
Layer p-side cladding layer 308: 1 × 10 Mg²⁰/ Cm³Do
P-type Al_0.2Ga_0.8N, 4 nm thick
3 layers, 1 × 10 Mg²⁰/ Cm³Doped In
_0.03Ga_0.97N, a fourth layer having a thickness of 2.5 nm;
, As a pair, alternately stack 5 pairs of 5 layers
-Layer contact having a superlattice structure in which a third layer is laminated on the p-side
Layer 309: 1 × 10 Mg²⁰/ Cm³Doped p
After stacking element structures of type GaN or more, in a nitrogen atmosphere,
Anneal at 700 ° C to further reduce the resistance of the p-type layer
Become Subsequently, until the n-side contact layer 304 is exposed.
Partly etched by p-side contact layer on top
309 including Ni and Au having a film thickness of 20 nm over almost the entire surface.
Optical p-electrode 310, partially bonded on p-electrode 310
The p pad electrode 311 made of Au for
μm, and the surface of the n-side contact layer 4 has W
And an n-electrode 12 containing Al to form an LED element.
This LED element has a forward current of 20 mA, and
nm pure green emission. This LED element is
Conventional first nitride semiconductor layer 11 and second nitride semiconductor layer
12 without using a 1.5 μm undoped GaN layer
Output is 20m compared to LED element formed as a ground layer
What has been saturated with W is higher than its output. This
This is on the second nitride semiconductor layer 12b in the plane of the active layer.
By introducing the low defect density region B, the luminous efficiency is improved.
It is thought to be due to the improvement.

[Embodiment 11] In the same manner as in Embodiment 10,
n-side contact layer 304 to become n-side layer 330 to n-side second
The p-side cladding layer 308 to the p-side contact layer 309 to be the contact layer 306, the active layer 307, and the p-side layer 331.
After exposing the n-side contact layer 304 by etching after forming an element structure by stacking
As shown in FIG. 7, the p-side layer is left in the low defect density region B formed on the first surface 1. Specifically, current flows through a part, preferably all, of the low defect density region B and the p-side layer so that current flows selectively through the p-side layer 331 and the active layer 307 in the low defect density region B. This is to overlap the flowing current region. At this time, a plurality of current regions in the low defect density region B are provided in the element.
As shown in (b), three are provided.

That is, similarly to the laser array element of the ninth embodiment, the structure is such that a current selectively flows through the active layer in the low defect density region B, and the high defect density region A (hatched in FIG. 10B). In this case, the active layer is removed from the active region. Here, an n-electrode is formed by providing a groove in the p-side layer 331 region at a depth at which the n-side contact layer 304 is exposed. In addition, similarly to the laser array element of FIG. Alternatively, a groove may be provided at a depth that does not reach the active layer 307 so as to exclude the high defect density region A, and a plurality of current regions may be selectively arranged in the low defect density region B. Alternatively, a structure may be employed in which a groove is formed at a depth where the n-side layer 330 is exposed, and no n-electrode is provided. Here, as shown in FIG. 10 (b), it becomes a part of the p-side layer, the active layer, and the n-side layer in one or a plurality of high defect density regions A sandwiched between the low defect density regions B. A groove is formed between the p-side layer 331 protruding in each of the low defect density regions B, and an n-electrode is formed in the groove. At this time, n
The protruding portion including the p-side layer 331 provided on the side contact layer 304 has a comb shape as shown in FIG. 10C, that is, each stripe-shaped current region provided in the low defect density region B, That is, each protruding portion of the p-side layer has a convex shape joined at least at one end, and conversely, the groove at the time of forming the protruding portion separates the protruding portion of each striped p-side layer. -It is formed so as not to separate. As described above, since the respective protrusions of the p-side layer 331 are joined without being separated from each other, the p-electrode 3 is formed on the p-side contact layer 309 on the surface thereof.
Ten common electrodes can be formed, and an electrode structure advantageous for wire bonding is formed. Further, the n-electrode 312 is also shown in FIG.
As shown in FIG. 0 (c), the use of the common electrode results in an electrode structure having the same effect. This n-electrode 312 is
At least, so as to sandwich the protruding p-side layer 331 therebetween.
Good current injection into each current region by providing opposing n-electrodes, a pair of n-electrodes on the outermost side in the figure, almost parallel to the convex portions of the stripe-shaped p-side layer Further, an n-electrode extended so as to join each electrode is formed so that the pair of n-electrodes becomes a common electrode. Here, the n-electrode is formed so as to surround three sides of the protruding portion of the p-side layer 331. In this manner, a structure in which the periphery of the p-side layer of the protruding portion is partially surrounded by the n-electrode partially omitted may be employed. Alternatively, an n-electrode that almost completely surrounds the periphery may be formed. Further, in addition to these outer n-electrodes, an n-electrode may be formed between each protruding portion of the p-side layer 331, and this is preferable because current is favorably injected into each protruding portion. Here, as shown in FIG. 10 (c), outside the protruding portion of the p-side layer 331, an outer n-electrode substantially parallel to and facing the stripe direction of the protruding portion, and a p-side layer 331, between each protruding part, an inner n-electrode also arranged substantially in parallel,
Is formed in a comb shape so as to be a common electrode, and the p-side layer 331 is formed.
And the comb shape of the n-electrode have an electrode structure arranged to face each other so that the unevenness fits.

The light emitting device thus obtained can emit light of higher output than that of the tenth embodiment. This is because, by adopting a structure in which the current region is selectively arranged in the low defect density region B, the low defect density region B can be effectively used, and the light emitting element has a suppressed output saturation.

In the ninth and eleventh embodiments, as shown in FIG. 11 (eighth embodiment), a p-electrode and an n-electrode are
It is also possible to adopt a structure in which the opposing members are positioned with respect to each other. In this case, the n-electrode formed on the back surface of the substrate 201 may have an electrode formed in a similar shape corresponding to the shape of the p-electrode, that is, the shape of the p-electrode is projected on the back surface of the substrate 201. As the shape of the n-electrode, a current may efficiently flow between the pair of positive and negative electrodes, and a part, preferably all, of the n-electrode has a shape substantially the same as that of the low defect density region B. It is preferable that the n-electrode is formed so as to cover a part, preferably almost all of the plurality of current regions, and to efficiently inject a current.

COMPARATIVE EXAMPLE 1 As shown in FIG. 6, a heterogeneous substrate 410 has a thickness of 425 μm, a diameter of 2 inches, a main surface of a C surface, and an orientation flat surface (hereinafter referred to as an orientation flat surface) of an A surface. Prepare sapphire substrate, MOCV
The wafer is set in the reaction vessel D. Next, the temperature is raised to 510 ° C., a hydrogen is used as a carrier gas, and ammonia and TMG (trimethylgallium) are used as a source gas. ), The temperature is further increased to 1050 ° C., and an underlayer 412 made of undoped GaN is grown to a thickness of 2.5 μm using TMG and ammonia as source gases.

After the formation of the underlayer 102, a selective growth layer 413a made of gallium nitride is further formed thereon.
This is also an underlayer made of gallium nitride. The selective growth layer is formed in the order shown in FIGS. After the formation of the underlayer 413a, the wafer is taken out of the reaction vessel, placed on a CVD apparatus, and a protective film 418 is formed as a mask region for selective growth on the underlayer 413a (FIG. 12A). At this time, the protective film 418 serving as a mask region is formed of a stripe-shaped SiO ₂ film perpendicular to the orientation flat surface (A surface) of the sapphire substrate with a width of 6 μm and an interval (width of the opening) of 14 μm over substantially the entire surface of the wafer. It is formed on the underlayer 413a. Then, the wafer is MOCV
D Return to the reaction vessel, temperature 1050 ° C, source gas TM
G, undoped GaN is grown to a thickness of 15 μm on the surface of the non-mask region where the protective film 418 is not provided, that is, the surface where the underlayer 413a is exposed, using G and ammonia (FIG. 6B). , (C)) and a nitride semiconductor substrate 413a having a flat surface (FIG. 6 (c)).
In the growth of the nitride semiconductor substrate, in the initial stage, the nitride semiconductor is selectively grown only in the non-mask region. However, when the nitride semiconductor is grown to a certain thickness, in addition to the growth in the thickness direction, the mask region is grown. Is grown in the lateral direction (in the plane of the substrate) toward the protective film 418, and the upper part of the mask region is blocked by the laterally grown nitride semiconductor.
A nitride semiconductor substrate 413a having a thickness of 15 μm is formed thereon. At this time, as compared with the first embodiment, the selective growth layer 413a that grows in the lateral direction is about 1
It requires a film thickness of 0 μm, which is planarized and further grown to obtain a good mirror surface to a film thickness of about 15 μm. The selective growth layer 413a thus obtained
Has a variation in the bonding position above the mask 418,
In some cases, poor bonding occurs. That is, compared to the first embodiment, a thick film needs to be grown, and the growth is also difficult to control.

[0072]

In the growth of the nitride semiconductor according to the manufacturing method of the present invention, differently from the conventional method, different growth regions on the first surface and the second surface are distributed on the surface and grown. Since the growth regions grow while being influenced by each other, it is easy to control the growth, and it is possible to obtain a nitride semiconductor surface having a smaller film thickness than the conventional one and excellent in surface morphology. In addition, by using the nitride semiconductor layer thus obtained in a growth substrate having an element structure or in an element structure, a nitride semiconductor element having excellent characteristics can be obtained. In the second nitride semiconductor layer of the present invention and the element structure laminated thereon, a low defect density region B and a high defect density region A are distributed, and the low defect density region B has By selectively disposing the current region, the waveguide region, and the active layer region, a nitride semiconductor device having excellent device characteristics can be obtained.

[0073]

[Brief description of the drawings]

FIG. 1 is a schematic sectional view illustrating a growth method according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating a growth method according to one embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view illustrating a nitride semiconductor according to one embodiment of the present invention.

FIG. 4 is a schematic sectional view illustrating a growth method according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view illustrating a growth method according to one embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view illustrating a conventional growth method.

FIG. 7 is a schematic sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention.

FIG. 8 is a schematic sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention.

FIG. 9 is a schematic sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention.

FIG. 10 is a schematic sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention.

FIG. 11 is a schematic sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention.

[Explanation of symbols]

1 1st surface, 2 2nd surface, 10 ...
Heterogeneous substrate, 11 ... first nitride semiconductor layer, 12 ...
A second nitride semiconductor layer, 13, 14 ... nitride semiconductor layer, 15 ... third nitride semiconductor layer layer, 100 ...
・ Crystal defects, 101, 201, 301 ... substrate, 10
2 ... nitride semiconductor substrate, 103, 203, 303
..Buffer layers, 104, 304... N-type contact layers, 105, 205... Crack preventing layers, 106, 2
06 ... n-type cladding layer, 107, 207 ... n-type light guide layer, 108, 208, 308 ... active layer, 1
09, 209... P-type electron confinement layer, 110, 210
... p-type light guide layer, 111, 211 ... p-type cladding layer, 112, 212 ... p-type contact layer, 12
0, 220, 310... P electrode, 121, 222, 3
12 ... n electrode, 122, 311 ... p pad electrode, 123 ... n pad electrode, 162,262 ...
Second protective film (embedded layer), 164... Insulating film, 23
0, 330... N-side layer, 231, 331.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F045 AA04 AB09 AB14 AB17 AB18 AB19 AB32 AB33 AC08 AC12 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AF02 AF03 AF04 AF06 AF09 AF13 AF20 BB12 CA10 CA12 DA51 DA53 DA54 DA55 DB02 EE14 HA16 5F073 AA11 AA13 AA45 AA51 AA74 AA77 AA83 CA07 CB05 CB07 CB20 DA05 DA35 EA29

Claims (5)

[Claims] 1. A method according to claim 1, wherein the first nitride semiconductor surface is selectively covered with a first nitride semiconductor.
Forming a surface and a second surface having a higher growth rate of the nitride semiconductor than the first surface; and after the step,
A second surface is provided on the first surface and the second surface of the first nitride semiconductor.
Growing the nitride semiconductor according to (1). 2. The method for growing a nitride semiconductor according to claim 1, wherein said first surface has larger irregularities than said second surface. 3. The step of forming the first surface and the second surface comprises selectively forming a mask on the surface of the first nitride semiconductor, and forming a mask on a non-mask region where the mask is not formed. Part 1 of the nitride semiconductor is removed by thermal decomposition,
3. The method for growing a nitride semiconductor according to claim 1, wherein the surface is formed and the mask is removed to form a second surface. 4. A nitride semiconductor device, wherein the second nitride semiconductor is used as a base layer, and an element structure having a nitride semiconductor is provided on the base layer. 5. The nitride semiconductor device according to claim 1, wherein said second nitride semiconductor is provided in an element structure having a nitride semiconductor.