JP2002278512A - Drive device for planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption equivalent to one layer of a three- electrode type planar display device. SOLUTION: A planar display device has a display panel 1, which forms a cell section 10 that has a memory function arranged in a matrix manner and electric discharge light emission function. In the device, one of the pair of electrodes 14 and 15, located on a same substrate on which discharge light emission, is conducted is commonly connected. The drive device of the flat display device is provided with a common electrode drive circuit which alternatively applies a voltage to the common electrodes and an electric power recovering circuit 60, which recovers and accumulates electric power, when the common electrode is switched from a high potential to a low potential and applies the power accumulated, when the common electrode is switched from the high potential to the low potential to the common electrode. The circuit 60 is provided with a capacitor element C3, a recovery path XVH, which has an inductance element 64 and a diode DO33 and recovers electric power and an applying path XLG, which has an inductance element 65 and a diode DO34 and applies electric power which is accumulated to the electrode 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a flat display device such as a plasma display (PDP) device and an electroluminescence display (EL) device, and more particularly, to a high-speed line sequential scanning system with low power consumption and low cost. The present invention relates to a feasible driving device for a flat panel display device.

[0002]

2. Description of the Related Art In recent years, due to the advantage of a thin shape, P
The demand for flat matrix type display devices such as DP (plasma display), LCD (liquid crystal display), and EL (electroluminescence) has been increasing. In particular, recently, the demand for color display has been increasing.

Conventionally, a flat display device, that is, a flat display device, such as a plasma display device or an electroluminescence display (EL) device, has a small depth and a large display screen. As a result, its applications are rapidly expanding and the production scale is also increasing. Such a flat display device is
In general, electric charges accumulated between electrodes are discharged and emitted under a predetermined voltage for display. The general display principle is described by taking a plasma display device as an example and its structure and operation. This will be schematically described below.

Conventionally known plasma display devices (AC-type PDPs) include a two-electrode type in which two electrodes perform selective discharge (address discharge) and sustain discharge,
There is a three-electrode type in which an address discharge is performed using a third electrode. On the other hand, in a plasma display device (PDP) for performing color display, a phosphor formed in a discharge cell is excited by ultraviolet rays generated by the discharge. There is a disadvantage that it is vulnerable to shock. In the above two-electrode type,
Since the phosphor is configured to directly hit the ions, the life of the phosphor may be shortened. In order to avoid this, in a color plasma display device,
A three-electrode structure using surface discharge is generally used.

Further, in this three-electrode type, the third electrode is formed on the substrate on which the first and second electrodes for performing the sustain discharge of the third electrode are arranged. The third electrode may be arranged on one substrate.
Further, even when the above-mentioned three types of electrodes are formed on the same substrate, there are cases where a third electrode is arranged on two electrodes for performing sustain discharge and cases where a third electrode is arranged thereunder. is there. Further, there are cases where visible light emitted from a phosphor is viewed through the phosphor and cases where reflection from the phosphor is viewed.

[0006] Since the above-mentioned respective types of plasma display devices are the same in principle, hereinafter, a first substrate provided with first and second electrodes for performing sustain discharge is described below. Separately, a specific example of a flat panel display device in which a third electrode is formed on a second substrate facing the first substrate will be described. FIG. 9 is a plan view showing an example of the configuration of a conventional plasma display (PDP) device, and FIG. 10 is a schematic sectional view of one discharge cell 10 formed in the PDP device of FIG. In the drawings, the same functional portions are denoted by the same reference numerals, and a part of the description will be omitted.

[0007] As shown in FIGS. 9 and 10, the PDP device is composed of two glass substrates 12 and 13. The first substrate 13 has a first electrode (X electrode) 14 and a second electrode (Y electrode) 15 which operate as sustain electrodes and are arranged in parallel with each other. 18 coated. On the discharge surface composed of the dielectric layer 18, a coating 21 made of a MgO (magnesium oxide) film or the like is formed as a protective film.

On the other hand, on the surface of the second substrate 12 facing the first glass substrate 13, a third electrode, that is, an electrode 16 operating as an address electrode, is provided with an X electrode 14 and a Y electrode.
It is formed so as to be orthogonal to the electrode 15. A phosphor 19 having one of red, green, and blue emission characteristics is disposed on the address electrode 16. Wall 1 formed on the same surface as the surface on which the address electrodes of second substrate 12 are arranged
The discharge space 20 is defined by 7. That is, each discharge cell 10 in the plasma display device is partitioned by the wall (barrier).

A first electrode (X electrode) 14 and a second electrode (Y electrode) 15 are arranged in parallel with each other and form a pair, and the second electrode (Y electrode) 15 , Are individually driven by individual Y electrode driving circuits 4-1 to 4-n connected to the Y electrode driving common driver circuit 3, respectively. The first electrode (X electrode) 14 And is driven by one driver circuit 5.

Address electrodes 16-1 to 16-m are arranged orthogonally to the X electrode 14 and the Y electrode 15, and the electrodes 16-1 to 16-m are connected to the address driver circuit 6 at addresses. ing. The address electrodes 16 are connected one by one to the address driver 6, and the address driver 6
Thus, an address pulse at the time of address discharge is applied to each address electrode.

The Y electrodes 15 are individually connected to Y scan drivers 4-1 to 4-n. Scan driver 4
-1 to 4-n are further connected to the Y-side common driver 3, and the pulse at the time of address discharge is applied to the scan driver 4-n.
1 to 4-n, the sustain discharge pulse and the like are generated by the Y-side common driver 33 and the Y-scan driver 4-1.
Are applied to the Y electrode 15 via .about.4-n.

On the other hand, the X electrodes 14 are commonly connected and driven over all display lines of the panel. That is, the common driver 5 on the X electrode side generates a write pulse, a sustain pulse, and the like, and applies them to each of the Y electrodes 15 simultaneously and in parallel. The common driver 5 on the X electrode side and the common driver 3 on the Y electrode side simultaneously drive the X electrode 14 and the Y electrode 15 while inverting the polarity of the voltage applied alternately, thereby executing the sustain discharge.

The above driver circuit is controlled by a control circuit (not shown), and the control circuit is controlled by a synchronization signal and a display data signal input from outside the device. FIG. 11 is a diagram illustrating a configuration of a basic driving cycle of the PDP device, and FIG. 12 is a diagram illustrating driving waveforms in the basic driving cycle. A method of driving the PDP device will be described with reference to FIGS.

The PDP device displays one display screen while rewriting it at predetermined intervals, and one display period is called one frame. One frame is, as shown in FIG.
A scan address period S-1 for setting each cell to a state corresponding to display data, a sustain discharge period S-2 for causing a cell set to emit light to perform discharge light emission, and all cells set to the same state. And a batch erase period. When performing gradation expression, it is common to divide one frame into a plurality of sub-frames having different sustain discharge periods and combine sub-frames to emit light. As shown in FIG. 11, a scan period S-1, a sustain discharge period S-2, and a batch erase period are provided. Since the subframe configuration is not directly related to the present invention, a description will be given here assuming that one frame is configured as shown in FIG.

In the scan address period, first, a scan signal is supplied from the Y electrode side scan driver circuit 4-1 to the Y electrode 15-1, and a Y address is supplied from the address driver circuit 6 to the address electrodes 16-1 to 16-m. A signal corresponding to the display data of the first line constituted by the electrode 15-1 is supplied using the address pulse AP, the cell portion 10 to be displayed is temporarily discharged, and a predetermined wall charge is generated. It is deposited inside and exhibits a memory function. Similarly, the Y-electrode-side scanning drivers 4-2, 4-3,.
Are sequentially scanned line-sequentially in this order, and the data to be displayed is written in a predetermined cell portion.

When the scan address period S-1 ends, a sustain discharge period S-2 starts. The Y electrode 15-1 to 15-n and the X electrode 14 intersect with each other by the Y electrode side common driver circuit 3 and the X electrode side common driver circuit 5 for all the cell portions 10 constituting the display panel. A predetermined voltage Ysus is simultaneously applied between the electrodes of the cell portion 10 formed in the portion, and then the same voltage application operation Xsus is performed by reversing the polarity of this voltage,
A voltage is alternately applied between the electrodes of the cell portion 10.

At this time, the display data is applied during the scanning address period, and the cell portion 1 having a predetermined wall charge is applied.
Only 0 discharges light emission repeatedly a predetermined number of times. In the conventional flat display device, the cell portion 10 that has emitted and emitted light in the immediately preceding sustain discharge period by using the Y-electrode-side common driver circuit 3 and the X-electrode-side common driver circuit 5 for all the cell portions 10. It is common to provide an initialization period for erasing remaining wall charges generated in the cell. In the initialization period, a method of erasing line-sequentially for each display line may be used, or a method of erasing all display lines at once may be used. In FIG. 11, it is shown as a batch erasing period.

As described above, in the PDP device, display is performed by accumulating electric charges in the cells in accordance with display data and applying a sustain discharge pulse between the electrodes to cause discharge light emission. The electrodes constituting each cell are opposed to each other with a dielectric material serving as a coating film or a discharge space therebetween, and constitute a capacitive element. Therefore, applying a pulse between the electrodes means changing the voltage applied to the capacitor and its polarity.

In a PDP device, a maximum of 200 V is applied between the electrodes.
It is necessary to apply a voltage of the order of magnitude as a high-frequency pulse. In particular, in a type of performing a gradation display in sub-frame display, the pulse width is several μs. In order to drive with such a high-voltage and high-frequency signal, the power consumption of the PDP device is generally large, and there is a demand for power saving. U.S. Pat. No. 4,070,663 describes EL (Electroluminescence)
In order to reduce the power consumption of a capacitive display unit such as a device, a control method for providing a capacitance of the display unit and an inductance element forming a resonance circuit is disclosed.

US Pat. No. 4,866,349 and US Pat. No. 5,081,400 disclose a sustain (sustain discharge) driver and an address driver for a PDP panel having a power recovery circuit composed of an inductance element. The above-mentioned known example discloses a two-electrode type display unit, and does not mention a three-electrode type display unit.

Japanese Patent Application Laid-Open No. Hei 7-160219 discloses that in a three-electrode display unit, a recovery path for recovering power applied when the Y electrode is switched from a high potential to a low potential is formed on the Y electrode side. A configuration is disclosed in which two inductances are provided: an inductance and an inductance that forms an application path for applying accumulated power when the Y electrode is switched from a low potential to a high potential.

FIG. 13 is a diagram showing a configuration of a conventional example in which two power recovery inductances are provided on the Y electrode side disclosed in JP-A-7-160219. Although detailed description is omitted here, the power recovery circuit can be recovered with higher efficiency by using two paths, a recovery path and an application path, and further power saving can be achieved.

[0023]

As described above, the configuration disclosed in Japanese Patent Application Laid-Open No. 7-160219 enables further power saving, but further power saving is required. SUMMARY OF THE INVENTION An object of the present invention is to further reduce the power consumption of a driving device for a three-electrode type flat display device by simply adding a simple configuration.

[0024]

According to the present invention, at least two substrates having electrodes disposed on a surface thereof are disposed at predetermined intervals so that electrode portions are orthogonally opposed to each other. A plurality of orthogonal parts are formed to form cell parts arranged in a matrix forming pixels, and the cell part has a memory function and a discharge function capable of accumulating a predetermined amount of electric charge according to a voltage applied to an electrode. It has a light-emitting function and includes an electrode formed on one of the two substrates and a pair of electrodes formed on the other, which emits discharge light, and one of the pair of electrodes is commonly used. 4 is a driving device of a flat panel display device having a display panel which is a connected common electrode.

FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, reference numeral Cp is a panel capacity,
Reference numerals 14 and 15 denote a pair of electrodes formed on one substrate and performing discharge light emission, 14 is a common electrode, and 15 is a scanning electrode. The common electrode 14 and the scanning electrode 15 correspond to an X electrode and a Y electrode, respectively. 101, 102, ...
A scan electrode driver, 60 is a power recovery circuit on the scan electrode side, and C3 is a storage capacitor. In addition,
Even if the capacitor C3 is a power supply circuit, power can be recovered similarly.

As shown, the drive circuit and the power recovery circuit on the common electrode side have two recovery paths XVH and an application path XL.
G, each of which has an inductance element 6
4 and 65 are provided. The inductance elements 64 and 65 form a resonance circuit with the panel capacitance Cp, respectively.
SW3 and SW4 constitute a drive circuit for the common electrode 14. In the conventional device having no power recovery circuit, the common electrode 14 is driven by these components. SW3 connects the recovery path XVH to the low potential terminal when the power applied to the common electrode 14 is recovered, and SW4 connects the application path XLG to the high potential terminal when the stored power is applied to the common electrode 14. I do.

SW1 and SW2 are switches corresponding to the transistors C and D in the case of one system shown in FIG. 13. SW1 is on the recovery path XVH, and SW2 is on the application path XL.
G. DO33 and DO34 are the collection route XV
Diodes provided in H and the application path XLG for blocking currents in opposite directions. DO31 and DO32 are
Diodes provided in the recovery path XVH and the application path XLG to block currents in opposite directions. However, it is not always necessary to provide them.

DO35 and DO36, DO37 and DO38
Is a reset diode in which the recovery path XVH and the application path XLG are connected to a high-potential terminal and a low-potential terminal, respectively, so as to be reverse-biased. These are SW3
And common electrode 14 by power recovery circuit in cooperation with SW4
It operates so as to eliminate the voltage difference generated between both ends of the inductance elements 64 and 65 by recovering the power from the power supply and applying the stored power to the common electrode 14.

SW1, SW2, SW3 and SW4 can be realized as field effect transistors. SW1, S
W2 is an insulated gate bipolar transistor (Insulated
Gated Bipolar Transistor (IGBT) can also be realized, in which case the efficiency and the like do not decrease even if the DO31 and DO32 are not provided. Also, the inductance elements 64 and 6
5, the inductance of the inductance element 64 is desirably larger than the inductance of the inductance element 65.

It is also desirable to provide two systems of power recovery circuits on the scanning electrode side. The scanning drive circuit for driving the scanning electrode is provided with a driving switch between the scanning electrode and the collecting path or the applying path, and a diode is provided in parallel with the driving switch. May be of a diode mixing type in which only a diode is connected and the driving switch is connected between the scanning electrode and another power supply terminal.

Here, US Pat. Nos. 4,070,663 and 4,86
No. 6,349, No. 5,081,400, one power recovery circuit
Problems in the case of a system will be briefly described. The one-system power recovery circuit is, for example, the power recovery circuit on the X electrode side of the conventional configuration shown in FIG. As shown, the circuit includes a coil 61 operating as an inductance element connected to the X electrode 14, a capacitor C3 operating as a capacitance element, and a set C of transistors connected between the coil 61 and the capacitor C3. D. Transistors C and D are functionally equivalent to SW1 and SW in FIG. 1, respectively.
Equivalent to 2. In the above-mentioned U.S. Pat. No. 4,070,663, a power supply circuit is used instead of the capacitor C3, and the power supply circuit can be similarly used in the present invention. However, in the following description, an example using the capacitor C3 will be described.

FIG. 2 is a diagram for explaining a problem of the power recovery circuit on the X electrode side shown in FIG. When the potential of the X electrode is
When applying a voltage that changes between 0 V and Vs,
A voltage of Vs / 2 is stored in the capacitor C3. X
When changing the potential of the electrode from 03 to Vs, FIG.
As shown in (1), both ends of the coil 61 are at 0V. In this state, when the transistor C is turned on, a voltage of Vs / 2 is applied from the capacitor C3 to one end of the coil 61, a current flows through the coil 61, and the potential of the X electrode at the other end of the coil 61 rises. I do. Ideally,
The potential of the X electrode rises from the potential Vs / 2 at the other end to Vs / 2 higher than the potential Vs / 2 at the other end by the back electromotive force of the coil 61. Actually, since the potential does not rise to Vs due to various losses, the transistor A is turned on when the potential rises to a level lower than Vs to some extent, and the potential is raised to Vs. Similarly, when changing the potential of the X electrode from Vs to 0 V, both ends of the coil 61 are at Vs as shown in FIG. 2B, the transistor D is turned on, and one of the coils 61 is turned on. Vs / 2. After the potential of the other end of the coil 61 becomes Vs / 2, the X electrode becomes OV due to the back electromotive force. The current is recovered by returning the current to C3. Also in this case, when the potential of the X electrode decreases to near 0V, the transistor B is turned on to reduce the voltage to 0V. That is, the potential of the X electrode changes as shown by the solid line in (3) of FIG. The dashed line shows the ideal case. An increase in the potential of the X electrode via the transistor A and a decrease in the potential of the X electrode via the transistor B result in a loss, and extra power is consumed. Therefore, it is necessary to raise the potential of the X electrode as much as possible and to lower the potential of the X electrode as much as possible.

The switching speed of the transistors C and D greatly affects the raising and lowering of the potential of the X electrode by the power recovery circuit. The higher the switching speed, the higher the potential of the X electrode can be raised or lowered. . As shown in FIGS. 2A and 2B, the transistors C and D have a parasitic capacitance. As shown in (1) of FIG. 2, before the potential of the X electrode is changed from 0 V to Vs, the potential at both ends of the coil 61 is 0 V, and the potential of the capacitor C3 is Vs / 2. C and D
A voltage of Vs / 2 is applied to the parasitic capacitance, and electric charges are accumulated. In order for the transistor C to conduct and one end of the coil 61 to be at Vs / 2, it is necessary to cancel the charges accumulated in the parasitic capacitances of the transistors C and D. Generally, the parasitic capacitances of the transistors C and D are large, and the speed of switching has been reduced in order to cancel the electric charges stored therein. For this reason, the potential of the X electrode was not sufficiently raised or lowered, resulting in a large power loss.

On the other hand, in the present invention, since the power recovery circuit is separated into two systems, that is, the recovery path XVH and the application path XLG, the parasitic capacitances of the transistors constituting the switches SW1 and SW2 are different from each other. It does not affect the switching speed, but only affects the parasitic capacitance of the transistor constituting the switch of the path. As a result, the effect of the parasitic capacitance can be reduced by half, and the switching speed improves accordingly,
The potential of the X electrode can be sufficiently raised and lowered, and power loss can be reduced.

The switching speed of the potential of the electrode causes another problem different from the above. FIG. 3 is a diagram illustrating this problem. As already explained, in the PDP device,
In the sustain discharge period, discharge is performed by alternately applying voltages of opposite polarities between the common electrode (X electrode) 14 and the scan electrode (Y electrode) 15. As shown in FIG. 3A, charges of opposite polarities are accumulated on the surfaces of the common electrode 14 and the scanning electrode 15 by the address discharge during the scanning period. The wall voltage due to these accumulated charges is defined as Vw. Here, by applying the sustain discharge voltage Vs to one of the electrodes, Vs is applied between the common electrode 14 and the scan electrode 15.
A voltage of +2 Vw is applied, and sustain discharge is performed. Since the charges on the surfaces of the common electrode 14 and the scanning electrode 15 move to the other electrodes by the sustain discharge, when the electrode to which the sustain discharge voltage Vsc is applied is switched at the time when all the charges have moved, the reverse of the above occurs. A phenomenon occurs and the charge moves in the opposite direction. By repeating this, sustain discharge is performed. In order for the sustain discharge to be repeated in the same manner, it is necessary that all the electric charges accumulated on one electrode move to the other electrode. Strength decreases.

If the switching speed of the potential of the electrode is high, the voltage of the cell (the voltage between the electrodes) reaches the threshold value Vf during the rise of the potential of the electrode, as shown in FIG. However, the discharge is not started immediately, but is started with a delay. Actually, the discharge starts when the voltage of the cell is clamped at the clamp voltage. On the other hand, if the switching speed of the potential of the electrode is low, there is a time from the time when the cell voltage reaches the threshold value Vf to the time when the voltage of the cell reaches the clamp voltage as shown in (3) of FIG. Discharge will start before the cell voltage reaches the clamp voltage. When such a discharge occurs, a problem arises in that a part of the charge stored in the electrode does not move to the other electrode, resulting in a loss. When such a discharge is repeated, wall charges decrease, causing a decrease in discharge intensity. Thus, the switching speed of the potential of the electrode is required to be high to some extent.

On the other hand, the current flowing at the time of switching the potential of the electrode is represented by the time derivative of the voltage, and the more rapid the change, the larger the flowing current. Power recovery circuit, drive circuit,
The electrode has a resistance, and the power consumption by the resistance is two times the current.
It is proportional to the power. Therefore, the higher the switching speed of the potential of the electrode, the greater the power consumption by the resistance. That is, the switching speed of the electrode potential needs to be determined in consideration of two contradictory factors.

The switching speed of the potential of the electrode is determined by various factors such as the driving capability of the transistor and the resistance of the path. The inductance element forms a resonance circuit with the panel capacitance Cp, and the resonance period is determined by the inductance value. Therefore, it is greatly affected by the inductance value of the inductance element. As in the present invention, when the power recovery circuit is composed of two paths and each has an inductance element, the switching speed can be reduced by recovering and applying power by using elements having different inductance values. It is possible to change it. For example, as shown in (4) of FIG. 3, the application of power can be performed at a high speed, and the recovery can be performed at a slower speed.

[0039]

FIG. 4 is a diagram showing a configuration of a driving device of a PDP device according to a first embodiment. This PDP device is
It is a three-electrode type PDP device shown in FIGS. 9 and 10. Therefore, this driving device also includes an address driver 6, which is the same as the conventional one, and is not shown here and the description is omitted.

In FIG. 4, reference numeral Cp denotes a panel capacitance, 14 denotes an X electrode, that is, a common electrode, and 15 denotes a common electrode.
Denotes a Y electrode, that is, a scanning electrode. The circuit part connected to the X electrode 14 is an X electrode drive circuit and its power recovery circuit, and the circuit part connected to the Y electrode 15 is a Y electrode drive circuit and its power recovery circuit. As shown in FIG. 4, the X electrode drive circuit and its power recovery circuit are composed of two paths, a recovery path XVH and an application path XLG. Collection route X
VH includes a diode D in order from the panel capacitance Cp.
O33, the coil 64, the diode DO31, and the transistor TR31 are connected, and the other controlled electrode of the transistor TR31 is connected to the capacitor C3. The diode DO33 and the diode DO31 have the panel capacitance C.
The connection is made such that the direction from p to the capacitor C3 is the forward direction. A transistor TR33 is connected between the connection between the diode DO33 and the coil 64 and the ground. The connection between the coil 64 and the diode DO31 is connected to the power supply Vs via the diode DO35,
It is connected to the ground via a diode DO36. A diode DO34, a coil 65, a diode DO32, and a transistor TR32 are connected to the application path XLG in order from the panel capacitance Cp, and the other controlled electrode of the transistor TR32 is a capacitor C3.
It is connected to the. Diode DO34 and diode D
O32 is connected such that the direction from the capacitor C3 to the panel capacitance Cp is the forward direction. Diode DO34
The transistor TR34 is connected between the power supply Vs and the connection portion of the power supply Vs. The connection between the coil 65 and the diode DO32 is connected to the power supply Vs via the diode DO37 and to the ground via the diode DO38. Transistors TR31 and TR3
2 correspond to the switches 1 and 2 of FIG. 1, respectively, and the transistors TR33 and TR34 correspond to the switches 3 and 4 of FIG. 1, respectively, and are turned on / off by a signal from a control unit (not shown). These transistors are all field effect transistors (FETs). The coils 64 and 65 realize the inductance element shown in FIG. Furthermore, diodes DO35 to DO35
Numeral 38 is for zeroing the potential difference remaining at both ends of the coil generated in the circuit in connection with the coils 64 and 65.

The Y-electrode drive circuit and its power recovery circuit are the same as the circuit called the floating type disclosed in Japanese Patent Application Laid-Open No. Hei 7-160219 shown in FIG. 13, and will be briefly described here. The drive circuit and the power recovery circuit on the Y electrode side also have a recovery path FVH and an application path FL.
G is divided into two. Reference numerals 101 and 102 are drive circuits connected to the corresponding Y electrodes, respectively.
It has a diode DO2 and a transistor TR6 connected between the Y electrode 15 and the recovery path FVH, and a diode DO3 and a transistor TR7 connected between the Y electrode 15 and the application path FLG. The transistors TR6 and TR7 are
The push-pull circuit 110 is configured. For example, if the scan pulse is a pulse that changes from Vsc to ground,
The transistor TR6 of the driving circuit connected to the Y electrode to which the scanning pulse is applied is turned off, the transistor TR7 is turned on,
The transistor TR6 of the driving circuit connected to the Y electrode except for the application of the scanning pulse is turned on, and the transistor TR7 is turned off.

Elements shown in the drawing are connected to the recovery path FVH and the application path FLG, respectively. Reference numeral 7
The portion indicated by 0 is a portion for setting the recovery path FVH to the scanning voltage Vsc and setting the application path FLG to ground during the scanning period. During the scanning period, the transistors TR8 and TR9 are turned on. Sometimes it is off. The portion indicated by reference numeral 80 is the scanning voltage Vsc remaining in the recovery path FVH when the sustain period is entered from the scanning period.
This is a leak circuit part for removing the noise. Reference numeral 90
The portion indicated by is applied during the sustain discharge period.
Is a circuit for clamping the recovery path FVH to the ground at the sustain discharge voltage Vs, and the transistors TR11 and TR12 are turned on and off alternately as described later.
The portion indicated by reference numeral 60 is a power recovery circuit.

FIG. 5 is a time chart showing the operation of the driving circuit according to the first embodiment of FIG. 4. Referring to FIG.
The operation of the circuit of FIG. In FIG. 5, signals related to the address electrodes are omitted. As shown in FIG. 5, immediately before entering the scan address period S-1, the Y electrode 1
Scan driver circuit 10 as scan driver circuit 5
At the same time as turning on the transistor TR6 constituting the transistor 1, the transistors TR8 and TR9 are also turned on. The voltage between the recovery path connected to the driver circuit for driving the Y electrode 15 and the application path FVH and FLG is Vsc
As a result, each of the Y electrodes is rapidly charged to the potential Vsc. During this time, the transistor TR on the X electrode side
34 is in the ON state, and the potential Vs is applied to the X electrode 14.
Is applied. The state where the potential Vs is applied to the X electrode 14, the collection path and the application paths FVH and FL
The state where the voltage between G is Vsc corresponds to the scan address period S
It is maintained until near the end of -1.

On the other hand, each of the Y electrodes is charged to the voltage Vsc as described above, but is first connected to one application path FLG1 connected to the driver circuit 101 for driving the first Y electrode 15-1. The pull-side transistor TR7 is turned on and the push-side transistor TR6 is turned off, thereby lowering the potential of the Y electrode to the ground. At times t1 and t2, the potential of the Y electrode 15-1 corresponds to that of the Y electrode 15-1. An address output corresponding to the display data to be performed is applied from an appropriate address driver 6 to write data. In this data writing operation, the cell section 10 on the Y electrode 15-1 selected by the address data discharges, a predetermined wall charge is generated in the corresponding cell section 10, and then the discharge occurs. The cell unit 10 stops discharging due to the wall charges of the cell unit 10 itself, and the operation of writing the address data ends. During this time, in the driver circuit for driving the other electrodes of the Y electrodes 15-2 to 15-n, the transistor TR6 on the push side is in the ON state.

Such scanning is performed by each of the Y electrodes 15-2 to 15-15.
-N for each scan address period S-
At the time T2 immediately before the end of the transistor TR1, the transistor TR8
Is turned off, and at time T3 after a predetermined time has elapsed, the leakage transistor TR10 is turned on. In this state, since the transistor TR9 is on, at time T4, the high voltage Vsc charged to the power supply lines FVH and FLG connected to the driver circuit for driving the Y electrode changes to the transistor T9.
Since the current flows from R10 to ground, the voltage between the recovery path and the application paths FVH and FLG becomes 0V. Note that the transistor TR9 is also turned off at time T4. At the same time, the transistor TR34 on the side of the X electrode 15 also
4 and the scanning address period S-1
Ends.

That is, the potential on the Y electrode side is set to 0 V, the voltages of all the Y electrodes are set to 0 V via the diode DO2, and the potential between the recovery path and the application paths FVH and FLG is also set to 0 V. , A series of scanning periods ends. At this time, the voltage Vs is applied on the X electrode side so that the discharge does not extend in the vertical direction. Next, in the sustain discharge period S-2, the cell portion 10 discharged in the scan address period has a state in which wall charges remain in the cell portion 10 to be displayed. Display is performed by alternately applying the alternating voltage and repeating the discharge only in the cell portion where the wall charges remain. When the sustain discharge is performed, the same alternating voltage is applied to all the Y electrodes at the same time.

First, at the beginning of the sustain discharge period, Y
A predetermined voltage Vs is applied to the electrode. At time T5, the transistor TR3 on the X electrode side
3 is turned on, and the X electrode is maintained at 0V. Thereafter, at time T6, the transistor TR14 provided in the power recovery circuit 60 is turned on, and a part of the power stored in the capacitor C2 is charged in the application path FLG, thereby connecting to the driver circuit for driving the Y electrode. The potential of one application path FLG increases. If the electric charge of the capacitor C2 is sufficient, the voltage of one application path FLG connected to the driver circuit for driving the Y electrode rises to a predetermined voltage Vs, but generally rises to Vs. At time T7, the transistor TR14 is turned off, and at the same time, the transistor TR12 is turned off.
Is turned on, and the voltage of the application path FLG is raised to Vs. This voltage is applied to the cell section 10 of the display panel section via the diode DO3.

At T8, at the same time as the transistor TR12 is turned off, the transistor TR33 on the X electrode side is turned off. Next, at T9, the transistor TR13 provided in the power recovery circuit 60 is turned on, and Y
A part of the voltage Vs charged in the electrode 15 is drawn into the capacitor C2 and stored therein, and the charge is
It is used for charging the next Y electrode. With this operation, the voltage of the recovery path FVH rapidly decreases, and T
At the same time as the transistor TR13 is turned off, the transistor TR11 is turned on at the same time, and the voltage of the recovery path FVH is reduced to a complete 0V state.

On the X electrode side, the transistor TR1
1 during the ON state of the transistor TR
32 is turned on, the potential of the X electrode 14 is raised through the coil 65, and the transistor TR32
Is turned off and the transistor TR34 is turned on, whereby the potential of the X electrode 14 is raised to a predetermined voltage Vs. During this time, the voltage on the Y electrode side of the cell portion 10 is maintained at 0 V at the ground potential via the diode DO2.

Next, at T13, the transistor T
R11 and the transistor TR34 are turned off at the same time. Thereafter, at T14, the transistor TR31 is turned on, the potential of the X electrode 14 falls, and a part of the electric charge stored in the cell portion 10 is charged in the capacitor C3. X
When the potential of the electrode 14 drops to some extent, the transistor TR33 turns on, and the potential of the X electrode 14 is reduced to 0V. Thus, one cycle of the sustain discharge operation is completed.

Thereafter, the above operation is repeated a predetermined number of times, and a predetermined cell portion 10 of the display panel emits light at a predetermined luminance. Note that the luminance level in the cell portion 10 is determined by the number of times the alternating voltage is applied during the sustain discharge period. When the above display operation is completed,
The wall charges of all cell portions 10 are erased by the initialization operation, and the operation of the next frame is performed.

FIG. 6 is a diagram showing the configuration of the driving device of the PDP device of the second embodiment. As is apparent from comparison with FIG. 4, the driving device of the PDP device of the second embodiment has substantially the same configuration as that of the first embodiment.
In the electrode power recovery circuit, a part of the recovery path XVH and a part of the application path XLG are shared.

The diode DO39 connected to the power supply Vs for removing the residual inductance and the diode DO40 connected to the ground are connected to a common part and can be shared. Thereby, the number of parts can be reduced. In the driving device according to the second embodiment, the transistor T which operates as a switch for switching the connection path to the capacitor C3 for storing the recovered power is provided.
R31 and TR32 are connected via diodes DO31 and DO32. Diodes DO31 and DO32
Is a forward direction in which a current flows from the transistor TR32 toward the transistor TR31, the parasitic capacitance of the transistors TR31 and TR32 is
It does not affect the switching speed when R31 changes from off to on, but does affect the switching speed when transistor TR32 changes from off to on. Therefore, the effect of reducing the influence of the parasitic capacitance to increase the switching speed and increasing the ultimate voltage when applying the recovered power to the X electrode 14 to reduce the power consumption is not sufficient. However, since two coils are provided for each path, it is possible to make the inductance value of the coil different to make the switching speed different between when the power is collected and when the power is applied.

The operation of the driving device of the PDP device of the second embodiment is the same as the operation of the first embodiment described with reference to the time chart of FIG. FIG. 7 is a diagram illustrating a configuration of a driving device of the PDP device according to the third embodiment. As is apparent from comparison with FIG. 4, the driving device of the PDP device according to the third embodiment has substantially the same configuration as the driving device of the first embodiment.
The point that the diodes DO33 and DO34 of the drive circuit on the X electrode side and the scanning voltage application circuit 70 on the Y electrode side are removed,
This is a drive circuit on the Y electrode side.

Since there are no diodes DO33 and DO34, the coils 64 and 65 are always connected. Therefore, when the voltage at the connection point with the X electrode 14 changes, the potentials at the ends of both coils change, but the diode DO3
1 and DO32, almost no current flows in the coil on the path that does not operate. Therefore, the effect is small, and the efficiency is only slightly reduced as compared with the first embodiment.

In the driving circuit on the Y electrode side, the transistor TR15 is connected between the Y electrode 15 and a power supply for supplying the scanning voltage Vsc, and the transistor TR16 is connected between the Y electrode 15 and the ground. . Diodes DO2 and DO3 are connected between the Y electrode 15 and the recovery path FVH, and between the Y electrode 15 and the application path FLG. During the address scanning period, the transistors TR15 and TR16 directly apply a scanning pulse. Therefore, the scanning voltage application circuit 70 is not required. Such a circuit is called a diode mixing system.

The operation of the driving device of the PDP device of the third embodiment is the same as the operation of the first embodiment described with reference to the time chart of FIG. In the first to third embodiments described above,
All transistors that operate as switches are MOSF
It was an ET (field effect) transistor. This is because the operation speed of the MOSFET transistor is generally higher than that of the bipolar transistor. 2. Description of the Related Art In recent years, an element having an operation speed, a peak current capacity, and the like, which are equivalent to a MOSFET transistor called an insulated gate bipolar transistor (IGBT), and having good conduction characteristics, which is a characteristic of a bipolar transistor, has been used. It has become The fourth embodiment is an example in which this insulated gate bipolar transistor is used as a switch.

FIG. 8 is a diagram showing a configuration of a driving device of the PDP device of the fourth embodiment. As is apparent from comparison with FIG. 4, the driving device of the PDP device of the third embodiment has substantially the same configuration as that of the first embodiment, except that the transistors TR31 and TR32 are replaced. Are provided with insulated gate bipolar transistors IGBT35 and IGBT36, and the diodes DO31 and DO32 are omitted. As described above, the insulated gate bipolar transistor has characteristics equivalent to or better than those required for the MOSFET transistor, and a more efficient power recovery circuit can be realized. Also, the diode DO
Even if there is no 31 and DO32, it operates as a power recovery circuit, and there is no particular problem.

[0059]

As described above, according to the present invention,
In the three-electrode type flat panel display device, since a two-path power recovery circuit capable of efficiently recovering power is provided for the X electrode of the pair of electrodes on which the sustain discharge operation is performed,
Further power saving can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram illustrating a problem of a one-path power recovery circuit.

FIG. 3 is a diagram illustrating the effect of switching speed.

FIG. 4 is a diagram illustrating a configuration of a driving device of the PDP device according to the first embodiment.

FIG. 5 is a time chart showing an operation of the PDP device by the driving device of the first embodiment.

FIG. 6 is a diagram illustrating a configuration of a driving device of a PDP device according to a second embodiment.

FIG. 7 is a diagram illustrating a configuration of a driving device of a PDP device according to a third embodiment.

FIG. 8 is a diagram illustrating a configuration of a driving device of a PDP device according to a fourth embodiment.

FIG. 9 is a plan view illustrating the outline of the configuration of a flat panel display device.

FIG. 10 is a cross-sectional view illustrating an example of a configuration of a cell portion used in one PDP device of the flat panel display device.

FIG. 11 is a diagram illustrating an example of a driving method of a flat panel display device.

FIG. 12 is a diagram illustrating an example of a driving voltage waveform for operating the flat panel display device.

FIG. 13 is a diagram showing a configuration of a conventional flat panel display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Display panel 3 ... Y electrode side common driver circuit 4, 4-1-4-n ... Y electrode driver circuit 5 ... X electrode side common driver circuit 6 ... Address driver circuit 10 ... Cell part 12, 13 ... Substrate 14 ... Common (X) electrode 15 Scanning (Y) electrode 16 Address electrode 17 Wall 18 Dielectric layer 19 Phosphor 20 Discharge space 21 MgO film 60 Power recovery circuit 70 Scanning power supply circuit 80 Leakage Switch 90: Sustain discharge power supply 101, 102... Y electrode driver 110: Push-pull driver circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) G09G 3/28 H (72) Inventor Tadatsugu Hirose 4-1-1 Kamiodanaka Nakahara-ku Kawasaki City Kanagawa Prefecture Fujitsu Limited (72) Inventor Shigehisa Tomio 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Yoshimasa Awata 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. Within Fujitsu Ltd. 5950 No. Kyushu Fujitsu Electronics Co., Ltd. (72) Inventor Akira Otsuka 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fuji F Co., Ltd. F term (reference) 5C058 AA11 AA12 BA26 BB25 5C080 AA05 BB05 DD26 DD27 FF12 HH04 JJ02 JJ03 JJ04 JJ06

Claims (1)

[Claims] An intersecting electrode disposed between two substrates (12, 13) facing each other at a predetermined interval;
A plurality of orthogonal portions formed between the electrodes are arranged in a matrix (1) to form a pixel.
0), and the cell portion is constituted by an electrode (16) formed on one of the two substrates and a pair of electrodes (14, 15) formed on the other. A driving device for a flat panel display device, wherein one of the electrodes is a common electrode (14) connected in common, wherein the common electrode (14) alternately switches between a high potential and a low potential. When the common electrode (14) is switched from a high potential to a low potential, the power applied to the common electrode is collected and stored, and when the common electrode is switched from a low potential to a high potential, the power is accumulated. A power recovery circuit for applying the recovered power to the common electrode, the power recovery circuit comprising: a capacitor (C3) for storing the recovered power; and a capacitor (C3) between the capacitor (C3) and the common electrode (14). Connected to the capacitive element C3), an inductance element (64) connected thereto, and a diode (DO33) connected between the common electrode (14) and the inductance element (64), wherein the common electrode (14) has a high potential. The common electrode (14) when switched from
Collection path (XVH) for collecting the electric power applied to the power supply
And the capacitance element (C3) in parallel with the collection path (XVH).
And an inductance element (65) connected between the common electrode (14) and the capacitance element (C3);
The common electrode (14) and the inductance element (6
And a diode (DO34) connected between the common electrode (14) and an application path (XLG) for applying the accumulated power to the common electrode (14) when the common electrode (14) is switched from a low potential to a high potential. And a driving device for the flat panel display device.