JP2003177702A - Planar display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a planar display device which carries out a stable display irrespective of the lighting state of a previous frame. <P>SOLUTION: The planar display device has a plurality of cell parts 10, and the cell part is provided with a panel having a memory function to store a prescribed amount of electric charge and a discharge light emission function according to a suitable voltage applied. The planar display device has an initialization period S1 provided in common to each display line for initializing a display screen, an address period S2 provided in common to each display line for sequentially selecting each display line for selecting the cell parts in correspondence with display data, and a sustaining discharge period S3 for carrying out the discharge light emission of each selected cell part during a predetermined period. The initialization period includes a plurality of wall electric charge adjusting periods S11 and S12 for adjusting a wall charge amounts stored in the cells, and a driving waveform in which the change of a voltage applied is delayed is applied in the wall electric charge adjusting periods. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a plasma display panel by optimally driving a display panel.
The present invention relates to a flat panel display device capable of stable image display.

[0002]

2. Description of the Related Art In recent years, PRT has been replaced by CRT due to its thinness
The demand for flat-panel type display devices such as DP (plasma display) and LCD (liquid crystal display) is increasing, but recently, the demand for color display is increasing.

Conventionally, flat display devices such as plasma display devices, that is, flat display devices have been realized with large display screens having a small depth. The scale is also increasing.

By the way, such a flat display device is generally
The electric charge accumulated between the electrodes is discharged and emitted under a predetermined voltage for display, and its general display principle will be schematically described below together with its structure and operation.

That is, a well-known plasma display device (AC PDP) uses a two-electrode type which performs selective discharge (address discharge) and sustain discharge with two electrodes, and a third electrode. There is a three-electrode type in which the address discharge is performed.

On the other hand, in a plasma display device (PDP) for color display, the phosphor formed in the discharge cell is excited by the ultraviolet rays generated by the discharge.
This phosphor has a drawback that it is vulnerable to the impact of ions, which are positive charges simultaneously generated by discharge. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened.

In order to avoid this, a color plasma display device generally uses a three-electrode structure utilizing surface discharge.

Further, also in this three-electrode type, the case where the third electrode is formed on the substrate on which the first and second electrodes for performing the sustain discharge of the third electrode are arranged and the case where it is opposed to the other case The third electrode may be arranged on one substrate.

Even when the above-mentioned three kinds of electrodes are formed on the same substrate, the third electrode is arranged on the two electrodes for sustaining discharge, and the third electrode is arranged below the two electrodes. There is a case.

Further, the visible light emitted from the phosphor is
There are cases where the light is seen through the phosphor and there are cases where the light is reflected from the phosphor.

Since the principles of the plasma display devices of the respective types described above are the same as each other, in the following, the first substrate provided with the first and second electrodes for sustaining discharge and the first substrate will be described. Separately, a specific example will be described for a flat panel display device configured by forming a third electrode on a second substrate facing the first substrate.

That is, FIG. 1 is a schematic plan view showing the outline of the configuration of the above-mentioned three-electrode type plasma display device (PDP), and FIG. 2 is formed in the plasma display device of FIG. 2 is a schematic cross-sectional view of one discharge cell 10. FIG.

That is, the plasma display device is
As can be seen from FIGS. 1 and 2, the two glass substrates 12, 1
It is composed of three. The first substrate 13 comprises a first electrode (X electrode) 14 and a second electrode (Y electrode) 15 which are arranged in parallel with each other and act as sustain electrodes, which are dielectric layers 18 It is covered with.

Further, a coating film 21 made of a MgO (magnesium oxide) film or the like is formed as a protective film on the discharge surface composed of the dielectric layer 18.

On the other hand, on the surface of the second substrate 12 which faces the first glass substrate 13, a third electrode, that is, an electrode 16 which operates as an address electrode, is provided with the sustain electrodes 14 and 1.
It is formed in a shape orthogonal to 5.

On the address electrode 16, red, green,
The discharge space 2 in which the phosphor 19 having one of the blue emission characteristics is defined by the wall portion 17 formed on the same surface as the surface of the second substrate 12 on which the address electrode is arranged
It is located within 0.

That is, each discharge cell 10 in the plasma display device is partitioned by a wall (barrier).

Further, in the plasma display device 1 in the above specific example, the first electrode (X electrode) 14
And the second electrode (Y electrode) 15 are arranged in parallel with each other to form a pair, and the second electrode (Y electrode) 15 is individually driven. One electrode (X electrode) 14 constitutes a common electrode and is driven by one driver.

FIG. 3 is a schematic block diagram showing a peripheral circuit for driving the plasma display device shown in FIGS. 1 and 2, and each address electrode 16 is provided to the address driver 31. The address driver 31 is connected and an address pulse at the time of address discharge is applied to each address electrode.

The Y electrodes 15 are individually connected to the Y scan driver 34.

The scan driver 34 is further connected to the Y-side common driver 33, and a pulse at the time of address discharge is generated from the scan driver 34, but a sustain discharge pulse or the like is generated from the Y-side common driver 33. It is applied to the Y electrode 15 via the scan driver 34.

On the other hand, the X electrodes 14 are commonly connected and taken out over all display lines of the panel in the flat display device.

That is, the common driver 32 on the X electrode side is
A write pulse, a sustain pulse, etc. are generated, and these are applied simultaneously and in parallel to each X electrode 14. These driver circuits are controlled by a control circuit, and the control circuit is controlled by a synchronizing signal and a display data signal input from the outside of the device.

That is, as is apparent from FIG. 3, the address driver 31 is connected to the display data control unit 36 provided in the control circuit 35, and the display data control unit 36.
Is a dot clock signal (CLOCK) indicating the display data and a display data signal (DATA) input from the outside, using the data of the frame memory or the like 37 provided inside the display data control unit 36, In one frame, the address data of the address electrode to be selected is output.

Further, the Y scan driver 34 is connected to a scan driver control section 39 of a panel drive control section 38 provided in the control circuit 35, and one frame (one field) of an external input. In response to the vertical synchronizing signal VSYNC which is a signal for instructing the start and the horizontal synchronizing signal HSYNC which is a signal for instructing the start of one sub-frame, the Y scan driver 34 is driven to drive the flat panel display device 1. A plurality of Y electrodes 15 are sequentially selected one by one to display one frame image.

In FIG. 3, Y-DATA output from the scan driver control unit 39 is scan data for turning on the Y scan driver bit by bit, and Y-CLOCK is the Y data. This is a transfer clock for turning on the scan driver bit by bit.

On the other hand, both the X-electrode side common driver 32 and the Y-electrode side common driver 33 in this example are connected to a common driver control section 40 provided in the control circuit 35, and the X-side common driver 32 is connected to the common driver control section 40. The electrodes 14 and the Y electrodes 15 are driven all at once while inverting the polarities of the voltages applied alternately,
The sustain discharge described above is executed.

In FIG. 3, the X-UD output from the common driver control unit 40 is the ON / OFF of the X side common driver.
X-DD output from the common driver control unit 40 in the figure.
GN to control ON / OFF of the X side common driver
It outputs D.

Similarly, the Y-UD output from the common driver control unit 40 is ON / OFF of the Y side common driver.
Vs and Vw are output to control the Y-DD output from the common driver control unit 40 in the figure.
GN to control ON / OFF of the Y side common driver
It outputs D.

Now, an example of a conventional image display driving method for a three-electrode plasma display device will be described.

That is, in the past, the line-sequential / self-erase address system and the batch write / batch erase / line-sequential address system have been generally used. An example of the display method in the latter case, that is, the case of using the collective writing / collective erasing / line sequential addressing method will be described.

According to this method, in the initializing period, the batch writing / batch erasing process is executed for all the cells of one frame, and in the subsequent address period, each line is sequentially line-sequentially processed. Lines are sequentially selected to write predetermined information to predetermined cells, and then sustain discharge is performed to all cells for a predetermined period, that is, until one frame display time ends in the sustain discharge period. In the address period, the operation of discharging and displaying only the cells in which predetermined information is written is repeated.

[0033]

By the way, the amount of wall charge is greatly affected by the state of the cell at the time of discharge light emission.
It is very difficult to make the display panel completely uniform, especially as the area increases.

In addition, at the time of initialization, there is a difference in the wall charges held between the cells that are turned on in the previous frame and the cells that are not turned on, and the electric field applied to the cells during writing (external applied electric field-internal The electric field is also different. As a result, a writing error may occur, which causes a problem of impairing stable display quality.

The present invention solves such a problem, and an object of the present invention is to realize a flat display device capable of performing stable display regardless of the lighting state in the previous frame.

[0036]

To achieve the above object, in the flat panel display device of the present invention, the initialization period is
It is divided into a plurality of wall charge adjustment periods for adjusting the amount of wall charges accumulated in the cell, and in the plurality of wall charge adjustment periods, a drive waveform in which a change in applied voltage is delayed is applied.

That is, the flat panel display device of the present invention comprises a plurality of cell portions each of which constitutes a pixel, and the cell portion has a memory function capable of accumulating a predetermined amount of electric charge in accordance with an appropriate voltage applied. In a flat panel display device having a panel having a discharge light emitting function, in order to initialize the display screen, a common initialization period is provided for each display line, and each display line is adapted. In order to execute the selection of the cell portion in the selected display line according to the display data, the address period commonly provided for each display line and the display line in each address period After the selection, each of the selected cell parts has a sustain discharge period commonly provided for each display line to discharge and emit light for a predetermined period, and the initialization period is accumulated in the cells. A plurality of wall charge adjustment periods for adjusting the amount of wall charges that are present, and a drive waveform in which a change in applied voltage is delayed is applied in the plurality of wall charge adjustment periods. .

It is preferable that the drive waveforms in the plurality of wall charge adjustment periods have their respective delay amounts of changes in applied voltage set independently of each other.

In the flat panel display device, the difference in the wall charge amount between the cells that were lit in the previous field and the cells that were not lit affected the display characteristics of each cell in the current field display. In order to prevent this, it is necessary to adjust the wall charge amount of each cell in the previous field in the initialization of the field.

According to the flat display device of the present invention, the initialization period is divided into a plurality of wall charge adjustment periods for adjusting the amount of wall charges accumulated in the cell, and the plurality of wall charge adjustment periods are included. In addition, since the wall charge amount of each cell is adjusted to the optimum amount, it is possible to perform better adjustment as compared with the related art.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a third embodiment of the present invention.
It is a figure which shows the time chart of the drive waveform in an electrode type plasma display apparatus.

As shown in FIG. 4, in the three-electrode plasma display apparatus of the first embodiment, after receiving the control signal VSYNC for starting a frame, all cells corresponding to one frame as described above are received. An initialization period S1 in which the operation of collectively initializing is performed is started. At that time, after setting the X electrode to GND, a predetermined voltage Vs is applied and a predetermined voltage Vs is applied to the Y electrode. Apply, then
A first wall charge adjustment period S11 for adjusting the amount of charges accumulated in a predetermined cell by delaying and dropping the Y electrode voltage with a predetermined time constant as shown in the figure is provided. .

In the first wall charge adjustment period S11, the wall charge amount P1 accumulated in the cell which was illuminated in the previous field is accumulated in the cell which was not illuminated in the previous field. The operation for approaching the existing wall charge amount P2 is performed.

The wall charge P2 is the amount of wall charge generated in the all-cell writing period S13 and the second wall charge adjusting period S12 described later, and the wall charge amount P1 is
The amount of wall charge generated in the cell during the sustain discharge period S3 described later is shown.

Subsequently, in the all-cell writing period S13, the voltage of the Y electrode is kept at GND, the voltage of Vs + Vw is applied to the X electrode, and predetermined information is written in all the cells. All the cells are turned on, and a predetermined amount of wall charge is uniformly generated for all the cells.

Next, in the second wall charge adjustment period S12, the voltage of the X electrode is dropped to GND and, at the same time, the Y voltage is reduced.
A predetermined voltage Vs is applied as the voltage of the electrode to invert the polarity of the applied voltage in the first wall charge adjustment period S11 described above, and the sustain discharge is instantaneously executed.

Thereafter, as shown in the figure, the Y electrode voltage is delayed with a predetermined time constant so that the amount of charges accumulated in a predetermined cell is adjusted.

That is, the second wall charge adjustment period S12
In this case, the amount of wall charges in all cells is limited so that cells not selected in the address selection period S2 do not discharge.

That is, in the plasma display device of the first embodiment, the difference in the wall charge amount between the cells that were lit in the previous field and the cells that were not lit was the difference in the field display this time. The wall charge amount of each cell in the previous field is adjusted in the initialization of the field so that the display characteristics of each cell in the field is not affected. That is, in the above-mentioned wall charge adjustment period S11, it is not necessary to completely erase the wall charges of all cells, but it is necessary to adjust the wall charges so that the predetermined wall charge amount is obtained.

Therefore, a predetermined time constant is set to cause a delay drop in the Y electrode voltage.

Next, all the cells are turned on in the all-cell writing period S13, and as a result, it becomes possible to apply substantially the same wall charge amount to all the cells.

However, the wall charge amount of each cell is not necessarily an appropriate value in many cases even by the operation in the all-cell write period.

Therefore, in the second wall charge adjustment period S12, the wall charge amounts of all the cells lighted in the previous step are erased at the same time or discharged so as to reach a predetermined same level. The previous cell is adjusted to a wall charge amount level so that discharge and light emission do not occur in the subsequent sustain discharge operation.

The drive waveforms in the plasma display device of the first embodiment have been described above, but as in the first embodiment, the first and second wall charge adjustment periods S11 and S1 are performed.
Even in the wall charge amount adjusting operation executed in 2, the wall charge amount remaining in each cell is always the optimum wall charge amount in the step of displaying the next frame. It wasn't enough. This is the first wall charge adjustment period S11 and the second wall charge adjustment period S12.
It was considered that the same cell drive circuit was used to adjust the wall charge amounts. Therefore, the wall charge amount obtained in the display operation of the previous frame and remaining in the cell could not be sufficiently adjusted to a proper value.

That is, in the first embodiment, since the drive circuits for the cells are the same, as described above, the drive circuits for the cells have different purposes and functions from each other. As long as the operation of the second wall charge adjustment periods S11 and S12 is performed by the same driving means, it is impossible to individually exhibit an appropriate adjustment function.

Therefore, even if the wall charge amount of each cell is properly controlled and used in each period, proper control is not executed in each period in which the optimum value is different, and therefore,
The optimum operating voltage varies depending on the lighting state of the previous field, resulting in a narrow voltage margin that enables stable operation.

In the second embodiment of the present invention described below,
The problem of the first embodiment is further solved, and the wall charge amount remaining in each cell in the previous frame is set to an appropriate value, and all the cells have a substantially uniform optimum predetermined amount of wall charge. (EN) A plasma display device capable of creating an optimum display state in the display drive in the next frame by making it possible to adjust.

In the second embodiment of the present invention, in the structure in which the wall charge adjustment period is divided into a plurality of sub wall charge adjustment periods having different operation time zones, each sub wall charge adjustment period is independent of the cell driving means. It is configured to be driven by. In the second embodiment, in the first wall charge adjustment period S11 and the second wall charge adjustment period S12, individually-independently driven cell driving means are used, respectively. In this period, it is possible to drive the cells according to the driving conditions set individually by the individual cell driving means, so that it is possible to prevent a large-scale all-cell write discharge and at the same time effectively avoid the misaddress. As a result, it becomes possible to greatly contribute to the longevity of the phosphor.

FIG. 5 is a block diagram showing the construction of a specific example of the cell driving means 100 used in the three-electrode type plasma display device according to the second embodiment of the present invention. 1 is an enlarged view of cell driving means 100 provided in a Y electrode driving system in the plasma display device 1 shown in the diagram.

That is, as a basic configuration of the plasma display device according to the present embodiment, as shown in FIG. 1, at least two substrates 12 having electrodes arranged on the surface thereof,
13, so that the electrode portions face each other at right angles,
Appropriate phosphors 19 are arranged adjacent to each other between the substrates 12 and 13, and a plurality of orthogonal portions formed between the electrodes form the cell portion 10 that constitutes each pixel. Therefore, in the flat panel display device 1 in which the cell portion 10 has a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function in accordance with an appropriate voltage applied to the electrode, One frame displayed on the display device 1 is composed of a plurality of sub-frames S for each scanning line.
The divided sub-frames are temporally divided into F, and each divided sub-frame is further initialized at least in the initialization period S1 in which the display screen is initialized. Address period S for executing write operation
2 and the cell portion in which the display data is written is constituted by a sustain discharge period S3 in which discharge light emission is performed for a predetermined period, and the initialization period S1 is further divided into a wall charge adjustment period and an all-cell write period S13. The wall charge adjusting period is divided into a plurality of sub wall charge adjusting periods S11 and S12 having different operation time zones, and the respective wall charge adjusting periods S11 and S12 are controlled. Is configured to be driven by cell driving means 101 and 102 which are independent of each other.

The structure according to the present embodiment can basically be adopted in any flat display device as long as it has a structure of retaining charges and exhibiting a memory function, but preferably, a plasma display device. It suffices if the display device is mainly a flat panel display device.

In the initialization period S1 according to this embodiment, the first sub-wall charge adjustment period S11, the all-cell write period S13, and the second sub-wall charge adjustment period S12 are arranged in this order. It is desirable that it is configured with.

Further, in the present embodiment, in the initialization period S1 within one sub-frame period SF, in order to initialize the display screen, predetermined data is given to each cell. It is desirable that it is the period for batch writing / erasing.

Further, in the present embodiment, it is desirable that the flat panel display device 1 uses three electrodes to drive display of an image.

In the plasma display device according to the present embodiment, as described above, each selection line, in the present embodiment, the Y electrode 15 is connected to the panel 30.
And the first sub-wall charge adjustment period S connected in series with
11 is connected to the panel 30 in series in the same manner as the first cell drive circuit 101 that drives the predetermined cell 10, and drives the predetermined cell 10 during the second sub-wall charge adjustment period. Two cell drive circuits 102 are provided.

The cell driving circuit 100 according to this embodiment will be described in detail with reference to FIG. 1. First, a plurality of cell parts 10 constituting a display panel of the plasma display device 1 will be described.
The X electrode 14 forming the common electrode is provided on the terminal portion on one side of the panel portion 30 made of
Is connected to the sustain discharge circuit (sustain circuit) 107 in the X electrode drive circuit shown in FIG.

On the other hand, a plurality of Y electrode groups 15 constituting a plurality of display lines are arranged in parallel with each other at the terminal portion on the other side of the panel portion 30, and a diode D1 and a transistor are provided for each Y electrode. Y scan driver 10 including a set of T5 and a set of diode D2 and transistor T6
Wirings 103 and 104 connected to the sustain discharge circuit (sustain circuit) 108 of the Y electrode drive circuit shown in FIG.

In the wiring 103 on one side, the write voltage power source (Vw) is the transistor T3 and the diode D.
3 and the other wiring 104 is connected to the ground power source (GND) through the transistor T4.

On the other hand, at the portion between the Y scan driver 105 and the sustain discharge circuit (sustain circuit) 108 in the wiring 103, the cell drive circuit 100 described above is provided.
Are connected, and the cell drive circuit 100 is
Through the diode D4 and the resistor R1 to the ground power supply (GN
There is provided a first cell drive circuit 101 connected to the transistor T2 connected to D), and also connected to the ground power source (GND) from the connection portion N via the diode D5 and the resistor R2. A second cell drive circuit 102 connected to the transistor T1 is provided.

The drive circuits 101 and 102 of the cell drive circuit 100 in this embodiment are the resistors R1 and R1 respectively provided in the cell drive circuits 101 and 102.
The time constant is set individually by R2 and the capacitance component (C) formed in the cell portion 10, and the transistor T1 or T2 of the cell drive circuit 101 or 102 concerned is set.
When is turned on, the electric charge accumulated in the cell unit 10 is extracted to the ground power supply (GND) according to the time constant of each drive circuit.

Therefore, the resistance value in each cell drive circuit 101, 102 is changed, and each cell drive circuit 10 is changed.
By individually controlling the gates of the transistors T1 and T2 in Nos. 1 and 102, the electric charge accumulated in the cell unit 10 is caused by one of the driving circuits 101 and 102 and according to the time constant of each driving circuit. , It is possible to adjust so that a predetermined wall charge amount is obtained.

That is, in the present embodiment, by supplying a predetermined control signal to the gates of the transistors T1 and T2, the cell drive circuit 101 or 10 respectively.
It is possible to drive 2 independently.

In this embodiment, an example in which the drive circuit is constructed by using MOSFET transistors is shown.
Needless to say, the structure is not limited to this, and any structure having a switching function can be used.

Each of the above-mentioned cell drive circuits 101
And 102 of the first sub-wall charge adjustment period S
It is arbitrary whether to drive in No. 11 and the other in the second sub-wall charge adjusting period S12, and it is necessary to set a predetermined time constant according to the order.

FIG. 6 is a waveform diagram showing a driving state when the display driving is executed by using the cell driving circuit 100 in the plasma display device according to the present embodiment.

In the figure, the driving waveforms of the address electrodes and the X electrodes are the same as those shown in FIG. 6, but the waveforms of the Y electrodes are:
The drive waveform in the first sub-wall charge adjustment period S11 is different from the drive waveform in the second sub-wall charge adjustment period S12.

This is because the wall charge amount accumulated in the cell portion is different in each period as described above, so that the wall charge amount becomes appropriate in each operation period. The result is obtained by changing the time constant of each cell drive circuit.

Further, as understood from FIG. 6, in the first sub-wall charge adjustment period S11, the control signal for driving the gate electrode of the MOSFET transistor T2 of the first cell drive circuit 101, for example, 101 is supplied. The program is set so that it is turned on, and in the second sub-wall charge adjustment period S12, the control signal for driving the gate electrode of the MOSFET transistor T1 of the second cell drive circuit, for example 102, is turned on. Thus, the display operation in this embodiment is executed.

[0079]

Since the present invention employs the above-mentioned technical structure, in the flat panel display device, a plurality of wall charges for adjusting the amount of wall charges accumulated in the cells are set in the initialization period. In the plurality of wall charge adjustment periods, the wall charge amount of each cell is adjusted to the optimum amount, so that better adjustment is possible as compared with the conventional case. As a result, the difference in the wall charge amount between the cells that were lit in the previous field and the cells that were not lit was adjusted so as not to affect the display characteristics of each cell in this field display. It Therefore, stable display is performed regardless of the lighting state in the previous frame.

Further, regardless of the lighting state of each cell portion in the previous frame, all-cell write discharge of a certain scale is possible, and writing to the adjacent cell or self-erasing caused by the large-scale discharge can be performed. Since it is possible to effectively prevent the mis-addressing and the deterioration of the phosphor, it is possible to stabilize the display state and extend the life of the flat panel display device itself.

[Brief description of drawings]

FIG. 1 is a plan view showing an outline of a configuration of a conventional flat panel display device.

FIG. 2 is a cross-sectional view showing a configuration example of a cell portion provided in a conventional flat panel display device.

FIG. 3 is a block diagram illustrating a drive system in a conventional flat panel display device.

FIG. 4 is a driving waveform diagram illustrating a driving method of the flat panel display device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a configuration of a cell driving circuit used in the flat panel display device according to the second embodiment of the present invention.

FIG. 6 is a waveform diagram showing an example of drive waveforms of respective parts in a flat panel display device using a cell drive circuit according to a second embodiment.

[Explanation of symbols]

1 ... Flat display device 2 ... Power supply circuit 3 ... Address current detection means 4… Comparison means 5 ... Address frequency control means 6, 45 ... Reference current value storage means 10 ... Cell part 12, 13 ... Substrate 14 ... X electrode 15 ... Y electrode 16 ... Address electrode 17 ... Wall 18 ... Dielectric layer 19 ... Phosphor 20 ... Discharge space 21 ... MgO film 30 ... Panel section 31 ... Address driver 32 ... X common driver 33 ... Y common driver 34 ... Y scan driver 35 ... Control circuit 36 ... Display data control unit 37 ... Frame memory 38 ... Panel drive control unit 39 ... Scan driver control unit 60 ... Common driver control unit 100 ... Cell drive circuit 101 ... First cell drive circuit 102 ... Second cell drive circuit 103, 104 ... Wiring 105 ... Y scan driver 107, 108 ... Sustain circuit

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Claims (2)

[Claims] 1. A plurality of cell parts each constituting a pixel are provided, and the cell parts have a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function according to an appropriate voltage applied. In a flat panel display device equipped with a panel that has a display panel, in order to initialize the display screen, the initialization period commonly provided for each display line and each display line are selected according to the display data. In order to perform the selection of the cell portion in the selected display line, an address period commonly provided for each display line, and each selected cell after the selection of each display line in the address period A sustain discharge period commonly provided for each display line in order to discharge light to a unit for a predetermined period, and the initialization period adjusts the amount of wall charges accumulated in the cell. for Includes a wall charge adjusting period of, said plurality of In the wall charge adjusting period, a flat display device, wherein a driving waveform obtained by delaying the change in the applied voltage is applied. 2. The flat display device according to claim 1, wherein the drive waveforms in the plurality of wall charge adjustment periods are set such that the delay amounts of changes in applied voltage are set independently of each other.