JP3370405B2 - Flat display device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a plasma display panel by optimally driving a display panel.
Ru Oh relates stable flat display device which can perform image display was.

[0002]

2. Description of the Related Art In recent years, PRT has been replaced by CRT due to its thinness.
The demand for flat-panel type display devices such as DP (plasma display) and LCD (liquid crystal display) is increasing, but recently, the demand for color display is increasing. 2. Description of the Related Art Conventionally, flat display devices such as plasma display devices, that is, flat-type display devices have been realized with large display screens with a small depth, so their applications are rapidly expanded, and the production scale is also increased. Is coming.

By the way, such a flat display device is generally
The electric charge accumulated between the electrodes is discharged and emitted under a predetermined voltage for display, and its general display principle will be schematically described below together with its structure and operation . That is, a plasma display device (AC
The type PDP includes a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes, and a three-electrode type that performs address discharge using the third electrode.

On the other hand, in a plasma display device (PDP) for color display, the phosphors formed in the discharge cells are excited by the ultraviolet rays generated by the discharge.
This phosphor has a drawback that it is vulnerable to the impact of ions, which are positive charges simultaneously generated by discharge. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened.

In order to avoid this, a color plasma display device generally uses a three-electrode structure utilizing surface discharge. Further, also in this three-electrode type, when the third electrode is formed on the substrate on which the first and second electrodes for sustaining the third electrode are arranged,
In some cases, the third electrode is arranged on another substrate that faces the third electrode.

Further, even when the above-mentioned three kinds of electrodes are formed on the same substrate, the third electrode is arranged on the two electrodes for sustaining discharge and the third electrode is arranged below the third electrode. There is a case. Furthermore, the visible light emitted from the phosphor is
There are cases where the light is seen through the phosphor and there are cases where the light is reflected from the phosphor.

Since the principles of the plasma display devices of the respective types described above are the same as each other, in the following, the first substrate provided with the first and second electrodes for sustaining discharge and the first substrate will be described. Separately, a specific example will be described for a flat panel display device configured by forming a third electrode on a second substrate facing the first substrate. That is, FIG. 3 is a schematic plan view showing an outline of the configuration of the above-mentioned three-electrode type plasma display device (PDP), and FIG.
3 is a schematic cross-sectional view of one discharge cell 10 formed in the plasma display device of FIG.

That is, the plasma display device is
As can be seen from FIGS. 3 and 4, the two glass substrates 12, 1
It is composed of three. The first substrate 13 comprises a first electrode (X electrode) 14 and a second electrode (Y electrode) 15 which are arranged in parallel with each other and act as sustain electrodes, which are dielectric layers 18 It is covered with. Furthermore, M is used as a protective film on the discharge surface composed of the dielectric layer 18.
Film 21 composed of gO (magnesium oxide) film or the like
Are formed.

On the other hand, on the surface of the second substrate 12 facing the first glass substrate 13, a third electrode, that is, an electrode 16 which operates as an address electrode, is provided with the sustain electrodes 14 and 1.
It is formed in a shape orthogonal to 5. A phosphor 19 having one of red, green, and blue emission characteristics is formed on the address electrode 16 on the same surface as the surface of the second substrate 12 on which the address electrode is arranged. It is arranged in the discharge space 20 defined by the wall portion 17 that is formed.

That is, each discharge cell 10 in the plasma display device is partitioned by a wall (barrier). In addition, in the plasma display device 1 in the above specific example, the first electrode (X electrode) 14 and the second electrode
The electrodes (Y electrodes) 15 of the second electrodes (Y electrodes) 15 are arranged in parallel with each other and form a pair.
Are individually driven, but the first electrode (X electrode) 14 constitutes a common electrode and is driven by one driver.

FIG. 5 is a schematic block diagram showing a peripheral circuit for driving the plasma display device shown in FIGS. 3 and 4, in which the address electrodes 16 are provided to the address driver 31 one by one. The address driver 31 is connected and an address pulse at the time of address discharge is applied to each address electrode. The Y electrodes 15 are individually connected to the Y scan driver 34.

The scan driver 34 is further connected to the Y-side common driver 33, and pulses for address discharge are generated from the scan driver 34, but sustain discharge pulses and the like are generated in the Y-side common driver 33. It is applied to the Y electrode 15 via the scan driver 34. On the other hand, the X electrode 14 is commonly connected and taken out over all display lines of the panel in the flat display device.

That is, the common driver 32 on the X electrode side is
Write pulse, sustain pulse, etc. are generated at the same time.
Concurrent manner be applied to the X electrode 1 4. These driver circuits are controlled by the control circuit, the control circuit is inputted from the outside of the device is controlled by a synchronizing signal and the display data signal. That is, as is apparent from FIG. 5, the address driver 31 is connected to the display data control unit 36 provided in the control circuit 35, and the display data control unit 36 receives the display data input from the outside. It should be selected within one frame from the dot clock signal (CLOCK) and the display data signal (DATA) shown, using the data of, for example, a frame memory 37 provided inside the display data control unit 36. The address data of the address electrode is output.

Further, the Y scan driver 34 is connected to a scan driver control unit 39 of a panel drive control unit 38 provided in the control circuit 35, and one frame (one field) of an external input. In response to a vertical synchronizing signal V _{SY NC} which is a signal instructing the start and a horizontal synchronizing signal H _SYNC which is a signal instructing the start of one subframe,
The Y scan driver 34 is driven to sequentially select the plurality of Y electrodes 15 in the flat panel display device 1 one by one to display one frame image.

In FIG. 5 , Y-DATA output from the scan driver control unit 39 is scan data for turning on the Y scan driver bit by bit, and Y-CLOCK is the Y data. This is a transfer clock for turning on the scan driver bit by bit. On the other hand, both the X-electrode side common driver 32 and the Y-electrode side common driver 33 in this example are connected to a common driver control section 40 provided in the control circuit 35, and the X-electrode 14 and The Y electrodes 15 are driven all at once while inverting the polarity of the voltage applied alternately, and the sustain discharge described above is executed.

In FIG. 5, the X-UD output from the common driver control unit 40 is ON / OFF of the X side common driver.
X-DD output from the common driver control unit 40 in the figure.
GN to control ON / OFF of the X side common driver
It outputs D. Similarly, the Y-UD output from the common driver control unit 40 outputs Vs and Vw in order to control ON / OFF of the Y side common driver. The Y-DD output from the control unit 40 outputs GND to control ON / OFF of the Y-side common driver.

An example of an image display driving method for the flat panel display device will be described with reference to the timing waveform diagram of FIG. 6, taking a conventional three-electrode type plasma display device as an example. That is, in the past, the line-sequential / self-erasing address system and the batch writing / collective erasing / line-sequential addressing system are generally used. An example of the display method in the case of using the batch writing / batch erasing / line sequential addressing method will be described.

That is, batch writing at the timing shown in FIG.
-It was driven by the batch erase and line sequential addressing method.
According to this method, in the initialization period S1, batch writing / batch erasing processing is executed for all cells of one frame, and in the subsequent address period S2, each line is line-sequentially. Are sequentially written to write predetermined information to predetermined cells, and then, in the sustain discharge period S3, sustain discharge is performed for all cells for a predetermined period, that is, until one frame display time ends. , In the address period S2,
The operation of discharging and displaying only the cells in which predetermined information is written is repeated.

[0019]

Where [0008], the amount of wall charges is greatly affected in the state of the cell at the time of discharge emission,
It is very difficult to make the display panel completely uniform, especially as the area increases.

In addition, at the time of initialization, there is a difference in wall charge held between cells that are lit in the previous frame and cells that are not lit, and an electric field applied to the cells at the time of writing (external applied electric field-internal The electric field is also different. As a result, a write error occurs.
There is a possibility that it may occur, which causes a problem of impairing stable display quality.

Therefore, in the above-described display method in the related art, after receiving the control signal V _SYNC for starting a frame, as described above, all cells corresponding to one frame are initially initialized. The initialization period S1 for performing the operation of changing the voltage is started. At that time, after setting the X electrode to GND, a predetermined voltage Vs is applied and a predetermined voltage Vs is applied to the Y electrode.
Was marked pressure, then, as shown the Y electrode voltage, by delaying lowered to have a predetermined time constant, the first wall charge adjusting for adjusting the amount of charge stored in the predetermined cell The period S11 is provided.

In the first wall charge adjustment period S11, the wall charge amount P 1 accumulated in the cell which was illuminated in the previous field is accumulated in the cell which was not illuminated in the previous field. The operation of approaching the wall charge amount P2 that is being performed is performed. The wall charge P 2 is the same as the all-cell write period S 13 and the second wall charge adjustment period S 1 described later.
2 is the amount of wall charges generated, and the amount of wall charges P 1 is the amount of wall charges generated in the cell during the sustain discharge period S3 described later.

Subsequently, in the all-cell write period S13, the voltage of the Y electrode is kept at GND, the voltage of Vs + Vw is applied to the X electrode, and predetermined information is written in all the cells. All the cells are turned on, and a predetermined amount of wall charge is uniformly generated for all the cells. Then
In the second wall charge adjusting period S12, and at the same time dropping the voltage of the X electrode to GND, and the voltage of the Y electrode, and sign pressurizing the predetermined voltage Vs, the first wall charge adjustment period that the The polarity of the applied voltage in S11 is reversed, and the sustain discharge is instantaneously executed.

After that, the Y electrode voltage is delayed and lowered with a predetermined time constant as shown in the figure to adjust the amount of electric charge accumulated in a predetermined cell. That is, in the second wall charge adjustment period S12, the wall charges in the cells are not discharged to all the cells so that the cells not selected in the address selection period S2 do not discharge. It limits the amount.

That is, in such a conventional flat panel display device composed of a plasma display device, the difference in the wall charge amount between the cells that were lit in the previous field and the cells that were not lit was It is necessary to adjust the wall charge amount of each cell in the previous field in the initialization of the field so that the display characteristics of each cell in the current field display are not affected.

That is, during the wall charge adjustment period S11 described above, it is not necessary to completely erase the wall charges of all cells, but it is necessary to adjust the wall charges so that a predetermined wall charge amount is obtained. Therefore, a predetermined time constant is set so that the Y electrode voltage is delayed and dropped. Next, the all-cell writing period S 1
In No. 3 , all cells are turned on, and as a result, it is possible to give substantially the same wall charge amount to all cells.

However, the wall charge amount of each cell is not necessarily an appropriate value in many cases even by the operation in the all-cell write period. Therefore, in the second wall charge adjustment period S12, the wall charges of all the cells lighted in the previous step are erased at the same time or discharged so as to reach a predetermined same level. The level of wall charge is adjusted so that discharge and light emission will not occur in the subsequent sustain discharge operation.

However, even in the wall charge amount adjusting operation executed in the first and second wall charge adjusting periods S11 and S12, the wall charge amount remaining in each cell is not always required. There was no guarantee that the optimum amount of wall charge was left in the process of displaying the next frame. Therefore, as in the conventional case, the first wall charge adjustment period S
11 and the second wall charge adjustment period S12, when the same cell drive circuit is used to adjust the wall charge amount, it is surely obtained in the display operation of the previous frame. Moreover, it was impossible to adjust the amount of wall charges remaining in the cell to an appropriate value.

That is, in the prior art, since the drive circuits of the cells are the same, as described above, the first and second drive circuits having different purposes and functions from each other are used.
As long as the same drive means is used for the operation of the wall charge adjustment periods S11 and S12, it is impossible to individually exert an appropriate adjustment function. Therefore, even if the wall charge amount of each cell is properly controlled and used in each period, proper control is not executed in each period in which the optimum value is different,
Therefore, the optimum operating voltage varies depending on the lighting state of the previous field, resulting in narrowing the voltage margin that enables stable operation.

Therefore, an object of the present invention is to solve the above conventional problems and to set the wall charge amount remaining in each cell in the previous frame to an appropriate value, and an optimum predetermined amount in which all cells are substantially uniform. It is an object of the present invention to provide a flat panel display device capable of creating an optimum display state in display driving in the next frame by adjusting so as to have the wall charge amount.

[0031]

In order to achieve the above-mentioned object, the present invention adopts the technical constitution as described below. That is, a panel having a plurality of cell portions each of which constitutes a pixel, the cell portion having a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function in accordance with an appropriate applied voltage is formed. In a provided flat display device, an initialization period for initializing a display screen, an address period for performing selection of the plurality of cell portions according to display data, and a discharge corresponding to the selection in the address period A sustain discharge period for emitting light, and a control system for controlling the initializing period by further dividing the initial period into a wall charge adjusting period and an all-cell writing period. It is divided into a plurality of sub-wall charge adjustment periods whose bands are different from each other before and after the all-cell write period, respectively.
The flat display device is characterized in that it is arranged and each sub-wall charge adjustment period is driven by independent cell driving means.

[0032]

In the flat panel display device according to the present invention, the above-mentioned technical structure is adopted in order to solve the above-mentioned problems in the prior art. In the period S11 and the second wall charge adjustment period S12,
Independently driving the cell driving means provided individually allows driving in accordance with the driving conditions individually set by the individual cell driving means in each period. At the same time, it is possible to prevent the large-scale all-cell write discharge that occurred at the same time, and to effectively avoid the misaddress, and as a result, it is possible to greatly contribute to the longevity of the phosphor.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific examples of a flat panel display device according to the present invention will be described in detail below with reference to the drawings. That is, FIG. 1 is a block diagram showing a configuration of a specific example of the cell driving means 100 used in the flat panel display device according to the present invention, and the conventional flat panel display device 1 shown in the block diagram of FIG. 3 is an enlarged view of the cell driving means 100 provided in the Y electrode driving system in FIG.

That is, as a basic configuration of the flat panel display device according to the present invention, as shown in FIG. 5, at least two substrates 12 and 13 on the surface of which electrodes are arranged, Adjacent fluorescent materials 19 are inserted between the substrates 12 and 13 so as to be orthogonal to each other and face each other, and a plurality of orthogonal portions formed between the electrodes are respectively formed. A cell portion 10 forming a pixel is formed, and the cell portion 10 has a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function according to an appropriate voltage applied to the electrode. In the flat panel display device 1, one frame displayed on the display device 1 is temporally divided and displayed in a plurality of sub-frames SF configured for each scanning line, and each divided sub-frame is displayed. And at least An initialization period S1 for initializing the display screen, an address period S2 for selecting the plurality of cell portions and performing an appropriate write operation of display data, and a cell portion in which the display data is written for a predetermined period. , together with allowed to configure in a sustain discharge period S3 for discharging light emission, has a control system for controlling the initialization period S1 was further divided into the all-cell write period S13 between the wall charge adjusting period,
And between the wall charge adjusting period, is divided into an operation time period different sub wall charge adjusting period S11 each other, S12, the cell driving means 101 and 102 independent of each other each sub wall charge adjusting period S11, S12 the A flat panel display device is shown which is characterized in that it is adapted to be driven.

The flat panel display device 1 according to the present invention is basically applicable to any flat panel display device as long as it has a structure for retaining charges and exhibiting a memory function.
Preferably, it is a flat display device mainly including a plasma display device. The initialization period S1 according to the present invention includes a first sub-wall charge adjustment period S11, an all-cell write period S13, and a second sub-wall charge adjustment period S12.
It is desirable that and are arranged in this order.

Further, in the present invention, in the initialization period S1 within one sub-frame period SF, in order to initialize the display screen, predetermined data is collectively stored in each cell. It is desirable that it is a period for writing / erasing all at once. Further, in the present invention, it is desirable that the flat panel display device 1 uses three electrodes to perform image display driving.

[0037] In the flat display apparatus according to this embodiment, as described above, their respective select lines, in the present example the Y electrode 15, it is connected in series with the panel 30 Also, during the first sub-wall charge adjustment period S11, the second sub-wall charge connected in series with the panel 30 in the same manner as the first cell driving circuit 101 that drives a predetermined cell 10. A second cell drive circuit 102 that drives a predetermined cell 10 is provided during the adjustment period.

FIG. 1 shows the cell driving circuit 100 according to the present invention.
The flat display device 1 will be described in detail with reference to FIG.
The X electrode 14 forming the common electrode is provided on one terminal portion of the panel portion 30 including the plurality of cell portions 10 forming the display plate of FIG. It is connected to the sustain discharge circuit (sustain circuit) 107 in the X electrode drive circuit.

On the other hand, a plurality of Y electrode groups 15 constituting a plurality of display lines are arranged in parallel with each other at the terminal portion on the other side of the panel portion 30, and a diode D1 and a transistor are provided for each Y electrode. Y scan driver 10 including a set of T5 and a set of diode D2 and transistor T6
Wirings 103 and 104 connected to the sustain discharge circuit (sustain circuit) 108 of the Y electrode drive circuit shown in FIG.

The write voltage power supply (Vw) of the one wiring 103 is the transistor T3 and the diode D.
3 and the other wiring 104 is connected to the ground power source (GND) through the transistor T4. On the other hand, the Y scan driver 105 and the sustain discharge circuit (sustain circuit) 10 in the wiring 103.
The cell drive circuit 100 described above is connected to a portion between 8 and a transistor T2 connected to the ground power source (GND) from the connection portion N via the diode D4 and the resistor R1. A connected first cell drive circuit 101 is provided, and a ground power source (GND) is provided from the connection portion N via a diode D5 and a resistor R2.
A second cell drive circuit 102 connected to the transistor T1 connected to is provided.

The drive circuits 101 and 102 of the cell drive circuit 100 according to the present invention have resistors R1 and R, respectively, which the cell drive circuits 101 and 102 respectively have.
2 and the capacitance component (C) formed in the cell portion 10 individually set the time constant, and the transistor T1 or T2 of the cell driving circuit 101 or 102 concerned is set.
When is turned on, the electric charge accumulated in the cell unit 10 is extracted to the ground power supply (GND) according to the time constant of each drive circuit.

Therefore, changing the resistance value in each cell drive circuit 101, 102, and each cell drive circuit 10
By individually controlling the gates of the transistors T1 and T2 in Nos. 1 and 102, the electric charge accumulated in the cell unit 10 is caused by one of the driving circuits 101 and 102 and according to the time constant of each driving circuit. , It is possible to adjust so that a predetermined wall charge amount is obtained.

That is, in the embodiment of the present invention, each cell driving circuit 101 or 102 can be driven independently by supplying a predetermined control signal to the gates of the transistors T1 and T2. Becomes In the above specific example of the present invention, an example in which a drive circuit is configured using MOSFET transistors is shown, but the present invention is not limited to such a configuration.
It goes without saying that any one having a switching function can be used.

Each of the above-mentioned cell drive circuits 101
And 102 of the first sub-wall charge adjustment period S
It is arbitrary whether to drive in No. 11 and the other in the second sub-wall charge adjusting period S12, and it is necessary to set a predetermined time constant according to the order. FIG. 2 is a waveform diagram showing a driving state when display driving is performed using the cell driving circuit 100 in the flat panel display device according to the present invention.

In the figure, the driving waveforms of the address electrodes and the X electrodes are the same as those shown in FIG. 6, but the waveforms of the Y electrodes are:
The drive waveform in the first sub-wall charge adjustment period S11 is different from the drive waveform in the second sub-wall charge adjustment period S12. As described above, this is because the wall charge amount accumulated in the cell portion is different in each period, so that each wall charge amount is appropriate in each operation period. This is due to the result of changing the time constant of the cell drive circuit.

Further, as understood from FIG. 2, in the first sub-wall charge adjusting period S11, the control signal for driving the gate electrode of the MOSFET transistor T2 of the first cell driving circuit, for example, 101 is supplied. The program is set so that it is turned on, and in the second sub-wall charge adjustment period S12, the control signal for driving the gate electrode of the MOSFET transistor T1 of the second cell drive circuit, for example 102, is turned on. Thus, the display operation in the flat panel display device of the present invention is executed.

[0047]

Since the present invention adopts the above-mentioned technical constitution, in the flat panel display device, the first sub-wall charge is set in the initializing step at the time of displaying an image. In the adjustment period S11 and the second sub-wall charge adjustment period S12,
It is possible to drive the first and second cell drive circuits individually and set the time constant in each drive circuit individually to an optimum value according to each sub-wall charge adjustment period. Therefore, the display drive can always be executed under the optimum conditions.

Further, regardless of the lighting state of each cell portion in the previous frame, all-cell write discharge of a certain scale is possible, and writing to the adjacent cell or self-erasing caused by the large-scale discharge can be performed. Since it is possible to effectively prevent the mis-addressing and the deterioration of the phosphor, it is possible to stabilize the display state and prolong the life of the flat panel display device itself.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a cell drive circuit used in a flat panel display device according to the present invention.

FIG. 2 is a waveform diagram showing an example of drive waveforms of respective parts in a flat panel display device using a cell drive circuit according to the present invention.

FIG. 3 is a plan view showing an outline of a configuration of a conventional flat panel display device.

FIG. 4 is a cross-sectional view showing a configuration example of a cell portion provided in a conventional flat panel display device.

FIG. 5 is a block diagram illustrating a drive system in a conventional flat panel display device.

FIG. 6 is a drive waveform diagram illustrating a conventional method of driving a flat panel display device.

[Explanation of symbols]

1 ... Flat display device 2 ... Power supply circuit 3 ... Address current detection means 4… Comparison means 5 ... Address frequency control means 6, 45 ... Reference current value storage means 10 ... Cell part 12, 13 ... Substrate 14 ... X electrode 15 ... Y electrode 16 ... Address electrode 17 ... Wall 18 ... Dielectric layer 19 ... Phosphor 20 ... Discharge space 21 ... MgO film 30 ... Panel section 31 ... Address driver 32 ... X common driver 33 ... Y common driver 34 ... Y scan driver 35 ... Control circuit 36 ... Display data control unit 37 ... Frame memory 38 ... Panel drive control unit 39 ... Scan driver control unit 60 ... Common driver control unit 100 ... Cell drive circuit 101 ... First cell drive circuit 102 ... Second cell drive circuit 103, 104 ... Wiring 105 ... Y scan driver 107, 108 ... Sustain circuit

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/28 G09G 3/20 611 G09G 3/288

Claims (5)

(57) [Claims] 1. A plurality of cell parts each constituting a pixel are provided, and the cell parts have a memory function capable of accumulating a predetermined amount of electric charge and a discharge light emitting function according to an appropriate voltage applied. In a flat panel display device equipped with a panel, an initialization period for initializing the display screen, an address period for selecting the plurality of cell parts according to the display data,
And a sustain discharge period for discharging and emitting light in response to selection in the address period, and further has a control system for controlling the initialization period by further dividing it into a wall charge adjustment period and an all-cell writing period. In addition, the wall charge adjustment period is divided into a plurality of sub wall charge adjustment periods having different operation time zones and arranged before and after the all-cell write period , and the respective sub wall charge adjustment periods are independent cells. A flat display device characterized by being configured to be driven by a drive means. 2. The independent cell driving means each have an appropriate resistance, and a predetermined time constant is set by the resistance and the capacitance of the panel. Flat display device. 3. The flat panel display device according to claim 1, wherein the time constants of the independent cell driving means are set independently of each other. 4. The independent cell driving means each have a switching means, and are individually driven by individually driving the switching means. Flat display device. 5. A plurality of cell parts each constituting a pixel
A certain amount of electric charge according to the appropriate voltage that is provided and applied.
It has a memory function that can store
In a method of driving a flat panel display device equipped with a panel, a display screen is initialized according to an initialization period and display data.
Address period for selecting the plurality of cell parts,
And the discharge light is emitted according to the selection in the address period.
And a sustain discharge period that allows the voltage to be applied according to the first time constant during the initialization period.
A first wall charge adjustment period for performing the first wall charge adjustment;
After performing the first wall charge adjustment, all cell writing is performed.
All cell writing period and after performing all cell writing
Voltage is applied according to the second time constant, and the second wall voltage is applied.
A second wall charge adjustment period for adjusting the load.
Driving method of flat panel display device.