JP3862720B2 - Method for driving plasma display panel and plasma display panel - Google Patents

Description

  The present invention relates to a plasma display panel driving method and a plasma display panel, and more particularly to driving a plasma display panel that realizes a high-contrast information display terminal, a flat-screen television, and the like using a high-definition, large-capacity plasma display panel. The present invention relates to a method and a plasma display panel.

  In general, a plasma display panel (hereinafter abbreviated as PDP) has a thin structure, no flicker, a large display contrast ratio, a relatively large screen, a high response speed, a self-luminous phosphor It has many features such as the ability to emit multicolor light. For this reason, in recent years, it has been widely used in the field of computer-related display devices, the field of color image display, and the like.

  Depending on the operation method, this PDP has an AC discharge type in which the electrode is coated with a dielectric and indirectly operates in an AC discharge state, and an electrode is exposed to the discharge space and operated in a DC discharge state. There are DC discharge types. Further, the AC discharge type includes a memory operation type that uses a memory function of a discharge cell as a driving method and a refresh operation type that does not use it. Note that the brightness of the PDP is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage. The refresh operation type described above is mainly used for a PDP having a small display capacity because luminance decreases as the display capacity increases.

  FIG. 19 is a cross-sectional view showing a configuration of one display cell of the AC discharge memory operation type PDP. This display cell includes two insulating substrates 1 and 2 made of glass on the back and front, and a trace electrode 5 arranged so as to overlap a transparent scanning electrode 3 and a transparent sustaining electrode 4 formed on the insulating substrate 2. 6, the data electrode 7 formed orthogonally to the scan electrode 3 and the sustain electrode 4 on the insulating substrate 1, and the space of the insulating substrates 1 and 2 from He, Ne, Xe or the like or a mixed gas thereof. A discharge gas space 8 filled with a discharge gas, partition walls 9 for securing the discharge gas space 8 and partitioning display cells, and a phosphor for converting ultraviolet rays generated by the discharge of the discharge gas into visible light 10 11, a dielectric film 12 covering the scan electrode 3 and the sustain electrode 4, a protective layer 13 made of magnesium oxide or the like for protecting the dielectric film 12 from discharge, and a dielectric film 1 covering the data electrode It is equipped with a door.

  Next, the discharge operation of the selected display cell will be described with reference to FIG. When a pulse voltage exceeding the discharge threshold is applied between the scan electrode 3 and the data electrode 7 to start discharge, positive and negative charges are caused to flow on the dielectric films 12 on both sides and correspond to the polarity of the pulse voltage. 14 is attracted to the surface to cause charge build-up. Since the equivalent internal voltage resulting from this charge accumulation, that is, the wall voltage, has a polarity opposite to that of the pulse voltage, the effective voltage inside the cell decreases as the discharge grows, and the pulse voltage becomes a constant value. Even if held, the discharge cannot be maintained, and the discharge is finally stopped. Thereafter, when a sustain pulse having a pulse voltage having the same polarity as the wall voltage is applied between the adjacent scan electrode 3 and sustain electrode 4, the wall voltage is superimposed as an effective voltage. Even if the amplitude is low, the discharge can exceed the discharge threshold. Therefore, the discharge can be maintained by continuously applying the sustain pulse between the scan electrode 3 and the sustain electrode 4. This function is the memory function described above. Further, by applying to the scan electrode 3 or the sustain electrode 4 an erase pulse which is a wide low voltage pulse or a narrow sustain pulse voltage which neutralizes the wall voltage, The sustain discharge can be stopped.

  Next, the configuration of a conventional PDP driving device will be described. FIG. 20 is a block diagram showing an example of a conventional PDP driving device. The PDP has a sustain electrode group 42 and a scan electrode group 53 parallel to each other on one surface, and a data electrode group 32 in a direction perpendicular to these electrodes on the opposite surface. A display cell 22 is formed at the position of this intersection. The sustain electrodes X correspond to the respective scan electrodes Y1, Y2, Y3,..., Yn (n is an arbitrary positive integer) and are provided close to each other, and one ends thereof are commonly connected.

  Next, the configuration of a plurality of types of driver circuits for driving the display cells 22 and a control circuit for controlling these driver circuits will be described. A data driver 31 that drives data of the data electrode group 32 for one line for the purpose of address discharge of the display cell 22 and a sustain discharge that performs a common sustain discharge for the sustain electrode group 42 for the purpose of the sustain discharge of the display cell 22. A side driver circuit 40 and a scanning side driver circuit 50 that performs a common sustain discharge for the scanning electrode group 53 are provided. As shown in FIG. 21, the sustain side driver circuit 40 and the scanning side driver circuit 50 are composed of a low impedance circuit and a high impedance circuit. Further, for the purpose of performing selective write discharge in the address period, a scan driver 55 that sequentially scans the scan electrode group 53 of the scan electrodes Y1 to Yn is provided. The scanning driver 55 performs a sustain discharge by applying a sustain pulse to its own power supply by the scanning driver circuit 50. The control circuit 61 controls all the operations of the data driver 31, the sustain side driver circuit 40, the scanning side driver circuit 50, the scanning driver 55, and the PDP 21. The main part of the control circuit 61 includes a display data control unit 62 and a drive timing control unit 63. The display data control unit 62 temporarily stores display data input from the outside into data for driving the PDP 21 and the rearranged display data string, and the scan driver 55 sequentially performs the address discharge. The data is transferred to the data driver 31 as display data DATA in accordance with the scanning. The drive timing control unit 63 converts various signals such as a dot clock input from the outside into internal control signals for driving the PDP 21, and controls each driver and driver circuit.

  Next, the drive sequence will be described. FIG. 22 is a diagram showing a state in which a plurality of subfields are formed in a conventional PDP driving apparatus. For example, the number of subfields (abbreviated as SF) formed by dividing one field having a period of 16.7 ms is set to eight. By appropriately combining these subfields and defining the driving sequence, 256 gradations can be displayed. Each subfield is divided into a scanning period in which display data is written according to the weight of the subfield and a sustain discharge period in which display data for which writing is designated is displayed. An image of one field is displayed.

  FIG. 23 is a diagram illustrating details of a subfield having a certain weight. Common sustain electrode drive waveform Wx applied to sustain electrode X, scan electrode drive waveforms Wy1 to Wyn applied to scan electrodes Y1 to Yn, and data electrode drive waveform Wdi (1 ≦ i ≦ k) applied to data electrodes D1 to Dk ). One cycle of the subfield is formed by a scanning period and a sustain discharge period, and the scanning period is formed by a preliminary discharge period and an address discharge period, and a desired video display is obtained by repeating this. The preliminary discharge period is used as necessary and may be omitted.

  The preliminary discharge period is a period for generating active particles and wall charges in the discharge gas space in order to obtain a stable address discharge in the address discharge period, and a preliminary discharge pulse for simultaneously discharging all display cells of the PDP. This comprises a preliminary discharge erasing pulse for extinguishing charges that inhibit the writing discharge and the sustain discharge among the wall charges generated by applying the preliminary discharge pulse.

  The sustain discharge period is a period in which the display cell that has performed the address discharge in the address discharge period is sustain-discharged to emit light to obtain a desired luminance.

  In the preliminary discharge period, first, a preliminary discharge pulse Pp is applied to the sustain electrode X to cause discharge in all display cells. Thereafter, a preliminary discharge erasing pulse Ppe is applied to the scan electrodes Y1 to Yn to generate an erasing discharge, and the wall charges accumulated by the preliminary discharging pulse are erased.

  Subsequently, in the write discharge period, the scan pulse Pw is applied to the scan electrodes Y1 to Yn in a line sequential manner, and the data pulse Pd is selectively applied to the data electrode Di (1 ≦ i ≦ k) corresponding to the video display data. In the cell to be displayed, a write discharge is generated to generate wall charges.

  Subsequently, in the sustain discharge period, only the display cells that have caused the address discharge continuously generate the sustain discharge by the sustain pulses Pc and Ps. After the last sustain discharge is performed by the final sustain pulse Pce, the formed wall charges are erased by the sustain discharge erase pulse Pse, the sustain discharge is stopped, and the light emission operation for one surface is completed.

  A first object of the present invention is to provide a plasma display panel capable of obtaining good image quality regardless of the amount of display load.

  First, in the conventional plasma display panel driving method, the time from the start of charge recovery to the sustain potential and the GND potential is fixed at a fixed time. Therefore, from the start of charge recovery to the sustain potential and the ground potential. When the time until clamping is set short, the gas discharge intensity is too strong, so there is a disadvantage that luminance display is saturated and a good display image cannot be obtained especially when the display load is small. When the time from the start of collection to clamping to the sustain potential and the ground potential is set to be long, the gas discharge intensity is too weak, so that there is a disadvantage that the required luminance cannot be obtained when the display load is large.

  Further, in the conventional PDP driving method, a plurality of display cells are driven in one line by the electrode pair constituted by the sustain electrode X of the sustain electrode group and the scan electrodes Y1 to Yn of the scan electrode group. In this case, the display current corresponding to the display data of each line is substantially proportional to the display data amount (load amount) in the display cell. A resistance component is distributed in each electrode, and the resistance value of the electrode increases as the electrode becomes longer. Accordingly, the resistance component of the electrode causes a voltage drop when supplying a display current. This amount of voltage drop depends on the amount of display data. Furthermore, since a stray capacitance originally exists between the electrodes, electric charges are unnecessarily accumulated by this stray capacitance, so that a voltage drop similarly occurs.

  Further, as shown in FIG. 21, the conventional sustain side driver circuit 40 and scanning side driver circuit 50 are composed of a low impedance circuit + high impedance circuit or a low impedance circuit alone, and all outputs and control signals are common. There is a fixed point in time when the low impedance circuit control signal is turned ON as shown in FIG. 24, which is an enlarged view of the A portion, which is the falling portion of the sustain pulse in FIG. In this case, since the discharge current is always supplied from the low impedance circuit, as described above, a voltage drop occurs depending on the display data amount.

  For this reason, when the amount of display data is small, the voltage drop is small. However, when the amount of display data is large, the voltage drop is also large, resulting in a difference in display luminance between lines. That is, as shown by the solid line of the luminance graph with respect to the display load amount in FIG. 8, when the display data amount is small, the luminance increases more than necessary, and when the display data amount is large, the luminance decreases. Therefore, there arises a problem that the gradation display which should be gentle should be disturbed, resulting in discontinuous luminance characteristics.

  The present invention has been made in view of the above problems, and in the plasma display driving method and driving apparatus, when the amount of display data is small, an increase in luminance can be suppressed, and when the amount of display data is large, To provide a plasma display driving method and a driving apparatus with excellent display quality capable of faithfully displaying the gradation of display data regardless of the amount of display load by preventing a decrease in luminance. With the goal.

In order to solve the above problems, an invention according to claim 1, the plasma display panel relates to a driving method, each line, each subfield, or to detect the amount of display data in units of each field, it detected the display data By controlling the switching timing of the impedance of the sustain pulse circuit within the sustain discharge period according to the amount, when the amount of display data is large, the sustain discharge is further performed from the low impedance circuit constituting the sustain pulse circuit. While the current is supplied, when the display data amount is relatively small, the sustain discharge current is supplied from the high impedance circuit constituting the sustain pulse circuit .

According to a second aspect of the present invention, a plurality of scan electrodes, a plurality of sustain electrodes paired with the scan electrodes and formed on the same plane, and a direction orthogonal to the scan electrodes and the sustain electrodes are formed. A plurality of data electrodes; a plurality of display cells formed at intersections of the scan electrodes, the sustain electrodes, and the data electrodes; a write discharge period for determining whether each display cell is turned on or off; and the write discharge period Means for detecting a display load amount in units of lines, subfields, or fields, according to a plasma display panel that is driven by being divided into sustain discharge periods in which light emission discharge is repeatedly performed based on selective discharge in according to the display load amount, the impedance control means for controlling the impedance of the sustain pulse circuit in the sustain discharge period are added, and the Wei The pulse circuit includes a high impedance circuit and a low impedance circuit, and the impedance control means controls the switching timing between the high impedance circuit and the low impedance circuit within the sustain discharge period, whereby the impedance is controlled. It is characterized by controlling .

According to a third aspect of the present invention, there is provided the plasma display panel according to the second aspect , wherein the high impedance circuit comprises a circuit for raising (falling) a sustain pulse, and the low impedance circuit comprises a sustain voltage. The circuit for clamping the sustain pulse and the circuit for maintaining the sustain voltage, and the circuit for raising (falling) the sustain pulse has a reactive power recovery means.

Claim 8

The high impedance circuit includes a circuit that raises (falls) a sustain pulse, and the low impedance circuit includes a circuit that clamps to a sustain voltage and a circuit that maintains the sustain voltage. The circuit that performs (falling) includes reactive power recovery means.

The invention's effect

  According to the plasma display panel and the driving method thereof according to the present invention, a predetermined luminance can be obtained when the display load amount is large, and luminance saturation does not occur when the display load amount is small. Therefore, good image quality can be obtained regardless of the display load amount.

  And even if the amount of display data for writing discharge changes for each line, the luminance can be corrected to reduce the luminance difference between lines, the gradation of the display data can be displayed faithfully, and the display quality is excellent. A plasma display panel driving method and a plasma display panel can be realized.

  The driving method of the plasma display according to the first exemplary embodiment of the present invention includes a sustain period for each subfield, the timing for fixing the insufficient recovery amount to the sustain potential and the timing for fixing to the GND potential from the start of the charge recovery of the sustain pulse. It is configured so as to be variable within.

  FIG. 1 shows a sustain pulse control timing chart according to the present invention. In the conventional driving method, the time from the start of charge collection to clamping to the sustain potential and the GND potential is constant, but in the present invention, the time from the start of charge collection of the sustain pulse to the fixation to the sustain potential. T and the time T until fixing to the ground potential are varied. That is, the time from the end of charge recovery to the clamp to the sustain potential or the GND potential is set to a plurality of times (ta1 ≠ ta2 ≠ ta3, tb1 ≠ tb2 ≠ tb3) within the sustain period.

  By configuring in this way, when the light emission load amount of the PDP is small and concentrates light emission, luminance saturation that occurs concentrically in the display area where the drive power is small is prevented, and when the light emission load amount is large, By changing the timing of clamping to the sustain potential or the GND potential, light emission is controlled so that the light emission luminance does not become insufficient.

  Therefore, a good display without luminance saturation is always obtained without depending on the display load amount.

  In the plasma display panel driving apparatus according to the second embodiment of the present invention, sustain electrodes X1, X2, X3,..., Xn and scan electrode group constituting the first electrode group 42 in the PDP shown in FIG. The scanning electrodes Y1, Y2, Y3,..., Yn constituting 53 form a pair for each display line and are driven independently for each display line. Then, during the writing discharge period of the scanning period, the display data amount inputted to the means for detecting the display data for writing discharge is detected for each line, and the detected amount is temporarily stored. ing. Further, when the sustain pulse is switched in the sustain discharge period, the display data detection amount DAC for performing the write discharge for each line once stored is input to the delay time control circuit, and the output is as shown in FIG. Each of the electrodes is input to a sustain side driver circuit and a scan side driver circuit for performing a sustain discharge, which is composed of a low impedance circuit 47 and a high impedance circuit 48. At this time, when the amount of display data (display load amount) is large, the delay time is shortened as shown by the dotted line in FIG. 9, and the sustain discharge current is supplied from the low impedance circuit to suppress the voltage drop. When the data amount (display load amount) is small, the display data amount (display load) is increased by increasing the delay time and supplying more sustain discharge current from the high impedance circuit as shown by the thick dotted line in FIG. Even if the amount is different for each line, the sustain discharge current is controlled to be constant for each line. Thus, even if the display data amount (display load amount) for performing the write discharge changes, the luminance can be corrected as shown by the dotted line in FIG.

Hereinafter, specific examples of the plasma display panel driving apparatus and driving method according to the present invention will be described in detail with reference to the drawings.
(First embodiment)
Example 1 FIG. 3 is a circuit diagram showing a specific example of a plasma display panel driving apparatus and driving method according to a first example of the first embodiment of the present invention, and FIG. 2 explains the operation. These figures show a method of driving a plasma display panel that emits a subfield with a predetermined gradation using n sustain pulses, and is maintained from the start of charge recovery of the sustain pulses. Plasma display characterized in that time t1 to T3, t5 to t6, t9 to t10 until fixing to potential and time t3 to t4, t7 to t8, t11 to t12 until fixing to ground potential are variable A method of driving the panel is shown.

  Further, the plasma display panel in which the time from the start of charge recovery of the sustain pulse to the time when it is fixed to the sustain potential and the time until it is fixed to the ground potential are increased in the order of the nth sustain pulse from the first sustain pulse. The driving method is shown.

  Hereinafter, the first example 1 according to the first embodiment will be described in more detail.

  FIG. 2 is a control timing chart of the sustain pulse of this example. An example is shown in which the time from the start of charge recovery to clamping to the sustain potential and the GND potential within the sustain period increases as the number of sustain pulses increases.

  In the schematic diagram showing the drive timing period in the figure, first, there is a preliminary discharge period in which all display cells of the PDP emit light at the same time to form priming particles necessary for writing, and then there is an address period indicated by hatching. . During this period, writing pulses are applied in order from the first scanning line of the PDP, and writing is performed. After writing is completed, there is a sustain period in which the written cells are simultaneously sustained and discharged. Within this sustain period, the sustain pulse is set in order from the head to the last nth in order to gradually increase the time from the start of charge collection until it is clamped to the sustain potential and GND potential, and sustain discharge is performed. A desired display image can be obtained by repeating a series of driving sequences in this manner.

  FIG. 3 shows a schematic diagram of a drive circuit for realizing the first specific example. The configuration in the figure is roughly divided into a voltage clamp unit 1, a charge recovery unit 2, and a control unit 3 that controls the switch element. The voltage clamp unit 1 includes at least a switch element S2 that fixes the output line to the sustain voltage (VS <0), a switch element S1 that fixes the output line to the GND potential, and backflow prevention diodes D1 and D2. The charge recovery unit 2 includes at least a switching element S3, S4 for supplying charge recovery / discharge current, a backflow prevention diode D3, D4 for preventing backflow of current, a recovery capacitor C for storing charge, and a recovery coil L for resonance. Composed.

  Next, the operation of this example will be described using the schematic diagram of the drive circuit shown in FIG. 3 and the timing chart of FIG. First, a charging current is supplied to the recovery capacitor C through the recovery coil L, the switch element S3, and the diode D3 during a period from when the switch element S3 is turned on by the control signal 3 output from the control circuit 3 at time t1 to t2. To do.

  Since the gas discharge of the PDP requires a delay time of several hundred nanoseconds from the voltage application, it does not discharge at the time t2 when the recovery operation ends. Next, the switch element S2 is turned on by the control signal 2 output from the control circuit 3, and the output line is clamped to the sustain voltage level through the diode D2 until the time just before the timing of time t3. The hundreds of nanoseconds described above elapses after the clamping is completed, and a PDP gas discharge is generated. Since the discharge at this time is generated after the sustain voltage is sufficiently applied, the discharge is strong and the emission luminance is high.

  Next, the switch element S4 is turned on by the control signal 4 output from the control circuit 3 at time t3, and a discharge current is supplied to the PDP display cell through the recovery capacitor C, the diode D4, the switching element S4, and the recovery coil L. . After that, the switch element S1 is turned on by the control signal 1 output from the control circuit 3 at time t4, and the output line is clamped to the GND level through the diode D1. At this time, since the sustain pulse at point A in FIG. 3 is clamped at the sustain voltage, gas discharge occurs. This discharge is also a strong discharge as described above.

  The sustain pulse is generated by repeating the above operation. In this specific example, the sustain pulse has the time from the start of the charge recovery to the sustain potential and the GND potential until the last nth order. Since it is set so as to gradually increase, the effective applied voltage when the gas discharge is generated gradually decreases, and the discharge intensity itself can be gradually decreased.

The present invention is particularly effective for a driving method (maximum load → small number of sustain pulses, minimum load → large number of sustain pulses) that controls the number of sustain pulses in the sustain period according to the light emission load amount.
(Example 2)
As a second specific example according to the first embodiment of the present invention, sustain pulse control timing diagrams are shown in FIGS. 4 and 5, and a schematic diagram of a drive circuit is shown in FIG.

  This specific example is a method that is particularly effective when driven by a driving method that controls the number of sustain pulses in the sustain period according to the light emission load, and further improves the above-described luminance saturation and luminance deficiency, The time from detecting the display load amount from the video signal, inputting the detection result to the control circuit for controlling the control of the switch element, and clamping to the sustain potential or the GND potential from the start of the charge recovery of the sustain pulse according to the detection result Is variable.

  The description overlapping with the first specific example and the content that can be easily inferred are omitted.

  FIG. 4 is a timing chart when the display load amount in the second specific example is small, that is, when the number of sustain pulses is large. In this case, a long time from the start of charge collection to clamping to the sustain potential and the GND potential is set. is doing. As a result, it is possible to drive with weakened gas discharge intensity and to suppress luminance saturation. Further, when the display load amount is large, that is, when the number of sustain pulses is small, as shown in the timing chart of FIG. 5, the time from the start of charge recovery to clamping to the sustain potential and the GND potential is set short. As a result, it is possible to drive with increased gas discharge intensity and to obtain sufficient light emission luminance. The timings shown in FIGS. 4 and 5 are shown in the case of both extremes as an example, but it goes without saying that the degree of improvement with respect to luminance saturation and luminance deficiency increases by driving with a plurality of such timing settings.

  Note that the control of each switch element according to the display load amount is performed by the arithmetic circuit 4 and the control circuit 3A in FIG. The arithmetic circuit 4 detects the load amount from the input video signal and outputs a control signal corresponding to the load amount to the control circuit 3A. The control circuit 3A outputs control signals for the switch elements S1 to S4 at a timing according to the output signal.

(Second Embodiment)
Example 1
A first example according to the second embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a block diagram showing a configuration of a first example according to the second exemplary embodiment of the present invention. In the PDP 21, the sustain electrodes X1, X2, X3,..., Xn constituting the sustain electrode group 42 and the scan electrodes Y1, Y2, Y3,. Placed in. Further, the data electrodes D1, D2, D3,..., Dk constituting the data electrode group 32 are opposed to the electrode pairs of the sustain electrodes X1, X2, X3,. And are arranged in an orthogonal state. A plurality of display cells 22 in a matrix form are formed at the intersections between such electrode pairs and data electrodes.
Further, the configuration of the sustain side driver circuit 41, the scanning side driver circuit 51, the scanning driver 55, and the data driver 31 for driving the PDP 21 and the configuration of the control circuit unit 61 for controlling these circuits will be described.

  A data driver 31 for driving data of the data electrode group 32 for one line is provided for the purpose of address discharge of the plurality of display cells 22. Further, for the purpose of sustain discharge of the display cell 22, a sustain side driver circuit 41 that performs sustain driving independently for each of the sustain electrodes X <b> 1 to Xn of the sustain electrode group 42 is provided. Further, in the scanning period in which the selective write discharge is performed, the scanning electrodes Y1 to Yn of the scanning electrode group 53 are sequentially scanned with respect to the display data for one line set in the data driver 31, and the sustain discharge period is reached. A scanning-side driver circuit 51 that performs sustain driving independently for each electrode is provided. As shown in FIG. 11, the sustain side driver circuit 41 and the scanning side driver circuit 51 are configured by a clamp circuit 45 that operates independently for each electrode and a charge recovery circuit 44 that operates in common for each electrode. A specific example of FIG. 11 is shown in FIGS.

  In the clamp circuit, a diode and a switch connected in series to the sustain voltage VS, and a diode and a switch connected in series to the ground are connected, and the voltage is switched by the switch. On the other hand, the charge recovery circuit includes a case where the panel is used as a capacitor (A) and a case where the charge is recovered using another capacitor (B).

  Further, a control circuit unit 61 is provided for controlling all operations of the plasma display panel driving device including the data driver 31, the sustain side driver circuit 41, the scanning side driver circuit 51, the scanning driver 55, and the like. The main part of the control circuit unit 61 includes a display data control unit 62 and a drive timing control unit 63 as in the conventional case. The display data control unit 62 rearranges display data input from the outside into data for driving the PDP 21 and temporarily stores the rearranged display data string, and sequentially scans the scan driver 55 during address discharge. At the same time, it is transferred to the data driver 31 as display data DATA. The drive timing control unit 63 converts various signals (not shown) such as a dot clock and a blanking signal input from the outside into an internal control signal for driving the PDP 21, and converts the data clock CLK to the data driver 31. The scan data SDATA and the scan clock SCLK are output to the scan driver, the sustain side driver switch 41 receives the sustain side clamp switch control signals 1 to n, and the sustain side power recovery switch control signal to the scan side driver circuit 51. Control is performed by outputting scanning-side clamp switch control signals 1 to n and scanning-side power recovery switch control signals.

  Further, the display data DATA output from the display data control unit 62 is also input to the display data amount detection circuit 81 that is a feature of the present invention. The display data amount detection circuit 81 detects the display data amount for performing write discharge for each line in the write discharge period of the scanning period, and outputs the detection amount DAC. The detected amount DAC is input to the delay time control circuit 91, and when the detected amount changes, as shown in FIG. 14, a delay from when the charge recovery switch control signal is turned on until the clamp switch control signal n is turned on. When the amount of display data (display load) is large by controlling the time, the delay time is shortened as shown by the dotted line, and the sustain discharge current is supplied from the low impedance clamp circuit to suppress the voltage drop. When the display data amount (display load amount) is small, the delay time is lengthened as shown by the thick dotted line, and the sustain discharge current is supplied from the high impedance charge recovery circuit to display the display data amount (display Control is performed so that the sustain discharge current is constant for each line even if the load amount is changed. As a result, even if the display data amount (display load amount) for performing write discharge changes, the luminance can be corrected as shown by the dotted line in FIG. Display can be performed faithfully, and excellent display quality can be obtained.

  Next, the drive sequence will be described. As in the prior art, FIG. 22 is a diagram showing a state in which a plurality of subfields are formed in a PDP driving apparatus. For example, the number of subfields (abbreviated as SF) formed by dividing one field having a period of 16.7 mS is set to eight. By appropriately combining these subfields and defining the driving sequence, 256 gradations can be displayed. Each subfield is divided into a scanning period in which display data is written according to the weight of the subfield and a sustain discharge period in which display data for which writing is designated is displayed. An image of one field is displayed.

  FIG. 13 is a diagram showing details of a subfield having a certain weight. Common sustain electrode drive waveforms Wx1 to Wn applied to sustain electrodes X1 to Xn, scan electrode drive waveforms Wy1 to Wyn applied to scan electrodes Y1 to Yn, and data electrode drive waveforms Wdi (1 applied to data electrodes D1 to Dk) ≦ i ≦ k). One cycle of the subfield is formed by a scanning period and a sustain discharge period, and the scanning period is formed by a preliminary discharge period and an address discharge period, and a desired video display is obtained by repeating this. The preliminary discharge period is used as necessary and may be omitted.

  The preliminary discharge period is a period for generating active particles and wall charges in the discharge gas space in order to obtain a stable address discharge in the address discharge period, and a preliminary discharge pulse Pp for simultaneously discharging all display cells of the PDP. And a pre-discharge erasing pulse Ppe for eliminating the charge that hinders the write discharge and the sustain discharge among the wall charges generated by the application of the pre-discharge pulse Pp.

  The sustain discharge period is a period in which the display cell that has performed the address discharge in the address discharge period is sustain-discharged to emit light to obtain a desired luminance.

  In the preliminary discharge period, first, the preliminary discharge pulse Pp is applied to the sustain electrodes X1 to Xn to cause discharge in all the display cells. Thereafter, the preliminary discharge erasing pulse Ppe is applied to the scan electrodes Y1 to Yn to generate an erasing discharge, and the wall charges deposited by the preliminary discharging pulse Pp are erased.

  Subsequently, in the write discharge period, the scan pulse Pw is applied to the scan electrodes Y1 to Yn in a line sequential manner, and the data pulse Pd is selectively applied to the data electrode Di (1 ≦ i ≦ k) corresponding to the video display data. In the cell to be displayed, a write discharge is generated to generate wall charges. At this time, the display data amount detection circuit 81 detects the display data amount for performing the write discharge of each line and temporarily stores it until the sustain discharge period.

  Subsequently, in the sustain discharge period, only the display cells that have caused the address discharge continuously generate the sustain discharge by the sustain pulses Pc and Ps. After the final sustain discharge is performed by the final sustain pulse Pce, the formed wall charges are erased by the sustain discharge erase pulse Pse, the sustain discharge is stopped, and the light emission operation for one surface is completed. At this time, as shown in FIG. 14, the sustain pulses Pc and Ps are generated by the charge recovery switch control signal and the clamp switch control signal n, and the detected display data amount DAC once stored is the delay time. The delay time from when the power recovery switch control signal is turned ON to when the clamp switch control signal n is turned ON is controlled for each line in accordance with the detected display data amount DAC input to the control circuit 91. Thus, even if the display data amount (display load amount) for performing write discharge changes by passing a constant sustain discharge current through each line, the luminance is corrected as shown by the dotted line in FIG. The variation in luminance can be reduced, the gradation of display data can be displayed faithfully, and excellent display quality can be obtained.

(Example 2)
FIG. 15 is a block diagram showing a configuration of a second example according to the second exemplary embodiment of the present invention. In PDP 21, sustain electrodes X1, X2, X3,..., Xn constituting sustain electrode group 42 and scan electrodes Y1, Y2, Y3,..., Yn constituting scan electrode group 53 are paired in parallel for each display line. Placed in. Further, the data electrodes D1, D2, D3,..., Dk constituting the data electrode group 32 are opposed to the electrode pairs of the sustain electrodes X1, X2, X3,..., Xn and the scan electrodes Y1, Y2, Y3,. And are arranged in an orthogonal state. A plurality of display cells 22 in a matrix form are formed at the intersections between such electrode pairs and data electrodes.
Further, the configuration of the sustain side driver circuit 43, the scanning side driver circuit 54, the scanning driver 55, and the data driver 31 for driving the PDP 21, and the configuration of the control circuit unit 61 for controlling these driver circuits and drivers will be described. To do.

  As in the conventional case, a data driver 31 that performs data driving of the data electrode group 32 for one line is provided for the purpose of address discharge of the plurality of display cells 22. Further, for the purpose of sustain discharge of the display cell 22, a sustain side driver circuit 43 that performs sustain driving independently for each of the sustain electrodes X1 to Xn of the sustain electrode group 42 is provided. Further, in the scanning period in which the selective writing discharge is performed, the scanning electrodes Y1 to Yn of the scanning electrode group 53 are sequentially scanned with respect to the display data for one line set in the data driver. A scanning side driver circuit 54 that performs sustain driving independently of the electrodes is provided. As shown in FIG. 16, the sustain side driver circuit 43 and the scanning side driver circuit 54 are configured by a clamp circuit 45 that operates independently for each electrode and a slope circuit 46 that operates in common for each electrode.

  A specific example of FIG. 16 is shown in FIG. The clamp circuit is the same as in FIG. 12, and the slope circuit has a diode, a switch, and a resistor connected in series to the sustain voltage VS, and a diode, a switch, and a resistor connected in series to the ground. It is switched by a switch.

  Further, a control circuit unit 61 is provided for controlling all the operations of the plasma display panel driving device including the data driver 31, the sustain side driver circuit 43, the scanning side driver circuit 54, the scanning driver 55, and the like. The main part of the control circuit unit 61 includes a display data control unit 62 and a drive timing control unit 63 as in the conventional case. The display data control unit 62 rearranges display data input from the outside into data for driving the PDP 21 and temporarily stores the rearranged display data string, and sequentially scans the scan driver 55 during address discharge. At the same time, it is transferred to the data driver 31 as display data DATA. The drive timing control unit 63 converts various signals (not shown) such as a dot clock and a blanking signal input from the outside into an internal control signal for driving the PDP 21, and converts the data clock CLK to the data driver 31. The scan data SDATA and the scan clock SCLK are output to the scan driver, and the sustain side driver circuit 43 scans the sustain side clamp switch control signals 1 to n and the sustain side slope forming switch signal to the scan side driver circuit 54. Control is performed by outputting side clamp switch control signals 1 to n and scanning side slope forming switch signals.

  Further, the display data DATA output from the display data control unit 62 is also input to the display data amount detection circuit 81 that is a feature of the present invention. The display data amount detection circuit 81 detects the display data amount for performing write discharge for each line in the write discharge period of the scanning period, and outputs the detection amount DAC. The detection amount DAC is input to the delay time control circuit 91. When the change in the detection amount changes, as shown in FIG. 14, the slope formation control signal is turned on until the clamp switch control signal is turned on. When the delay time is controlled and the amount of display data (display load amount) is large, the delay time is shortened as shown by the dotted line, and the sustain discharge current is supplied from the low impedance clamp circuit to reduce the voltage drop. If the display data amount (display load amount) is small, the delay time is increased as shown by the thick dotted line, and the sustain discharge current is supplied from the high impedance slope forming circuit, thereby the display data amount ( Control is performed so that the sustain discharge current is constant for each line even if the display load amount changes. As a result, even if the display data amount (display load amount) for performing write discharge changes, the luminance can be corrected as shown by the dotted line in FIG. Display can be performed faithfully, and excellent display quality can be obtained.

  Next, the drive sequence will be described. As in the prior art, FIG. 22 is a diagram showing a state in which a plurality of subfields are formed in a PDP driving apparatus. For example, the number of subfields (abbreviated as SF) formed by dividing one field having a period of 16.7 mS is set to eight. By appropriately combining these subfields and defining the driving sequence, 256 gradations can be displayed. Each subfield is divided into a scanning period in which display data is written according to the weight of the subfield and a sustain discharge period in which display data for which writing is designated is displayed. An image of one field is displayed.

  FIG. 13 is a diagram showing details of a subfield having a certain weight. Common sustain electrode drive waveforms Wx1 to Wn applied to sustain electrodes X1 to Xn, scan electrode drive waveforms Wy1 to Wyn applied to scan electrodes Y1 to Yn, and data electrode drive waveform Wdi (1 applied to data electrodes D1 to Dk) ≦ i ≦ k). One cycle of the subfield is formed by a scanning period and a sustain discharge period, and the scanning period is formed by a preliminary discharge period and an address discharge period, and a desired video display is obtained by repeating this. The preliminary discharge period is used as necessary and may be omitted.

  The preliminary discharge period is a period for generating active particles and wall charges in the discharge gas space in order to obtain a stable address discharge in the address discharge period, and a preliminary discharge pulse Pp for simultaneously discharging all display cells of the PDP. And a pre-discharge erasing pulse Ppe for eliminating the charge that hinders the write discharge and the sustain discharge among the wall charges generated by the application of the pre-discharge pulse Pp.

  The sustain discharge period is a period in which the display cell that has performed the address discharge in the address discharge period is sustain-discharged to emit light to obtain a desired luminance.

  In the preliminary discharge period, first, a preliminary discharge pulse Pp is applied to the sustain electrodes X1 to Xn to cause discharge in all display cells. Thereafter, the preliminary discharge erasing pulse Ppe is applied to the scan electrodes Y1 to Yn to generate an erasing discharge, and the wall charges deposited by the preliminary discharging pulse Pp are erased.

  Subsequently, in the write discharge period, the scan pulse Pw is applied to the scan electrodes Y1 to Yn in a line sequential manner, and the data pulse Pd is selectively applied to the data electrode Di (1 ≦ i ≦ k) corresponding to the video display data. In the cell to be displayed, a write discharge is generated to generate wall charges. At this time, the display data amount detection circuit 81 detects the display data amount for performing the write discharge of each line and temporarily stores it until the sustain discharge period.

Subsequently, in the sustain discharge period, only the display cells that have caused the address discharge continuously generate the sustain discharge by the sustain pulses Pc and Ps. After the final sustain discharge is performed by the final sustain pulse Pce, the formed wall charges are erased by the sustain discharge erase pulse Pse, the sustain discharge is stopped, and the light emission operation for one surface is completed. At this time, as shown in FIG. 8, the sustain pulses Pc and Ps are generated by the slope forming switch control signal and the clamp switch signal n, and the detected data amount DAC once stored is the delay time control circuit 91. By controlling the delay time from when the slope forming switch control signal is turned ON to when the clamp switch control signal is turned ON for each line according to the detected display data amount DAC. Even if the display data amount (display load amount) for writing discharge changes by passing a constant sustain discharge current through the line, the luminance is corrected as shown by the dotted line in FIG. The display data gradation can be displayed faithfully, and an excellent display quality can be obtained.
Example 3
In the first and second embodiments, the display data amount for performing the write discharge is detected for each line, and the impedance change point of the sustain pulse circuit is dynamically changed for each line according to the detected display data amount during the sustain discharge period. The display data amount for performing the write discharge is detected for each subfield, and the change point of the impedance of the sustain pulse circuit during the sustain discharge period is changed according to the detected display data amount. Even if the variable control is dynamically performed for each field, the same effect is obtained.

  Further, in the first and second embodiments, the display data amount for performing the write discharge for each line is detected, and the change point of the impedance of the sustain pulse circuit during the sustain discharge period is determined for each line according to the detected display data amount. The display data amount for performing the write discharge is detected for each field, and the change point of the impedance of the sustain pulse circuit during the sustain discharge period is determined according to the detected display data amount. Even if the variable control is dynamically performed for each field, the same effect is obtained.

The figure which shows the control timing of the waveform of the sustain pulse of the drive apparatus and drive method of a plasma display panel concerning this invention, and each control signal The figure which shows the control timing of the waveform of a sustain pulse explaining each operation | movement of 1st Embodiment, and each control signal The circuit diagram of the principal part of Example 1 of 1st Embodiment The figure which shows the control timing of the waveform of a sustain pulse explaining each operation | movement in Example 2 of 1st Embodiment when display load amount is small, and each control signal The figure which shows the control timing of the waveform of a sustain pulse explaining each operation | movement in Example 2 of 1st Embodiment when display load amount is large, and each control signal The circuit diagram of the principal part of Example 2 of 1st Embodiment The block diagram of the driver circuit which shows the principle of the 2nd Embodiment of this invention Luminance graph against display load Sustain pulse waveform forming diagram for explaining the principle of the second embodiment of the present invention The block diagram which shows Example 1 of the 2nd Embodiment of this invention The internal block diagram of the sustain side and scanning side driver circuit of Example 1 of the second mode for carrying out the invention Circuit diagram showing a specific example of FIG. Detailed view of subfield according to the second embodiment of the present invention 13 is an enlarged view of part A in the case of Example 1 of the second embodiment of the present invention. The block diagram which shows Example 2 of the 2nd Embodiment of this invention The internal block diagram of the sustain side and scanning side driver circuit of Example 2 of the second embodiment of the present invention Circuit diagram showing a specific example of FIG. The A section enlarged view of FIG. 13 in the case of Example 2 of the 2nd Embodiment of this invention Cross section of PDP Block diagram of a conventional PDP driving device Internal block diagram of conventional driver circuit on the sustain side and scan side The figure which shows the state which formed the several subfield Detailed view of conventional subfields FIG. 15 is an enlarged view of part A in the conventional case.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Voltage clamp part 102 ... Charge collection | recovery part 103, 103A ... Control part (control circuit)
104 ... arithmetic circuits S1-S4 ... switch elements D1-D4 ... diode C ... recovery capacitor L ... recovery coil PDP ... display cells ta1-ta3 ... sustaining ramp period tb1-tb3 ... GND clamp period 1, 2 ... insulating substrate 3 ... scanning Electrode 4 ... sustain electrode 5, 6 ... trace electrode 7 ... data electrode 8 ... discharge gas space 9 ... partition wall 10 ... visible light 11 ... phosphor 12, 14 ... dielectric film 13 ... protective layer 21 ... PDP
22 ... display cell 31 ... data driver 32 ... data electrode group 40 ... conventional sustain side driver circuit 41 ... sustain side driver circuit 42 according to the present invention ... sustain electrode group 43 ... sustain side driver circuit 44 according to the present invention ... charge recovery circuit 45 ... Clamp circuit 46 ... Slope formation circuit 47 ... Low impedance circuit 48 ... High impedance circuit 50 ... Conventional scanning side driver circuit 51 ... Scanning side driver circuit 53 according to the present invention ... Scanning electrode group 54 ... Scanning side driver circuit 55 according to the present invention ... Scanning driver 61 ... Control circuit unit 62 ... Display data control unit 63 ... Drive timing control unit 81 ... Display data amount detection circuit 91 ... Delay time control circuit DAC ... Detection amounts Y1, Y2, Y3, ... Yn ... Scanning electrode X ... Conventional sustain electrodes X1, X2, X3,... Xn, sustain electrodes D1, D2, D3,. Over data electrodes Pp ... preliminary discharge pulse Ppe ... priming discharge erasing pulse Pw ... scan pulse Pc, Ps ... sustain pulse Pce ... final sustain pulse

Claims (3)

By detecting the display data amount in units of lines, subfields, or fields, and controlling the switching timing of the impedance of the sustain pulse circuit within the sustain discharge period according to the detected display data amount, When the display data amount is large, the sustain discharge current is supplied from the low impedance circuit constituting the sustain pulse circuit. On the other hand, when the display data amount is relatively small, the sustain pulse circuit is A method for driving a plasma display panel, characterized in that a sustain discharge current is supplied from a high-impedance circuit to be configured . A plurality of scan electrodes, a plurality of sustain electrodes paired with the scan electrodes and formed on the same plane, a plurality of data electrodes formed in a direction perpendicular to the scan electrodes and the sustain electrodes, and the scan electrodes and A plurality of display cells formed at the intersections of the sustain electrodes and the data electrodes, and a repeated light emission discharge based on a write discharge period for determining whether each display cell is turned on or off, and a selective discharge in the write discharge period A plasma display panel that is driven separately from a sustain discharge period in which
Means for detecting the display load amount in units of lines, subfields or fields, and impedance control means for controlling the impedance of the sustain pulse circuit within the sustain discharge period according to the display load amount Added, and
The sustain pulse circuit comprises a high impedance circuit and a low impedance circuit, and the impedance control means controls the switching timing between the high impedance circuit and the low impedance circuit within the sustain discharge period, A plasma display panel, wherein the impedance is controlled . The high impedance circuit includes a circuit that raises (falls) a sustain pulse, and the low impedance circuit includes a circuit that clamps to a sustain voltage and a circuit that maintains the sustain voltage. 3. The plasma display panel according to claim 2 , wherein the circuit that performs (falling) includes reactive power recovery means.

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