JP2002270509A5 - - Google Patents

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Publication number
JP2002270509A5
JP2002270509A5 JP2001394184A JP2001394184A JP2002270509A5 JP 2002270509 A5 JP2002270509 A5 JP 2002270509A5 JP 2001394184 A JP2001394184 A JP 2001394184A JP 2001394184 A JP2001394184 A JP 2001394184A JP 2002270509 A5 JP2002270509 A5 JP 2002270509A5
Authority
JP
Japan
Prior art keywords
single crystal
crystal substrate
trench
semiconductor single
substrate according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001394184A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002270509A (ja
Filing date
Publication date
Priority claimed from FR0100414A external-priority patent/FR2819631B1/fr
Application filed filed Critical
Publication of JP2002270509A publication Critical patent/JP2002270509A/ja
Publication of JP2002270509A5 publication Critical patent/JP2002270509A5/ja
Pending legal-status Critical Current

Links

JP2001394184A 2001-01-12 2001-12-26 単結晶基板の製作方法およびその基板を含む集積回路 Pending JP2002270509A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0100414A FR2819631B1 (fr) 2001-01-12 2001-01-12 Procede de fabrication d'un substrat monocristallin, et circuit integre comportant un tel substrat
FR0100414 2001-01-12

Publications (2)

Publication Number Publication Date
JP2002270509A JP2002270509A (ja) 2002-09-20
JP2002270509A5 true JP2002270509A5 (enExample) 2005-07-14

Family

ID=8858764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001394184A Pending JP2002270509A (ja) 2001-01-12 2001-12-26 単結晶基板の製作方法およびその基板を含む集積回路

Country Status (5)

Country Link
US (1) US7060596B2 (enExample)
EP (1) EP1223614B1 (enExample)
JP (1) JP2002270509A (enExample)
DE (1) DE60216646T2 (enExample)
FR (1) FR2819631B1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2819632B1 (fr) * 2001-01-12 2003-09-26 St Microelectronics Sa Circuit integre comportant un dispositif analogique de stockage de charges, et procede de fabrication
US6784072B2 (en) * 2002-07-22 2004-08-31 International Business Machines Corporation Control of buried oxide in SIMOX
FR3099964B1 (fr) * 2019-08-14 2024-03-29 St Microelectronics Crolles 2 Sas Procédé de réalisation d’une électrode dans un substrat de base et dispositif électronique
CN112768509B (zh) * 2021-02-03 2022-07-08 杭州中瑞宏芯半导体有限公司 一种反向恢复时间短的frd二极管及制备方法
CN117568912B (zh) * 2023-11-21 2024-10-01 松山湖材料实验室 一种单晶复合衬底及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292365A (ja) * 1985-10-18 1987-04-27 Fuji Photo Film Co Ltd 半導体装置およびその製造方法
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
JPS62293759A (ja) * 1986-06-13 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置
US4942554A (en) * 1987-11-26 1990-07-17 Siemens Aktiengesellschaft Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same
KR100197648B1 (ko) * 1995-08-26 1999-06-15 김영환 반도체소자의 소자분리 절연막 형성방법
FR2756104B1 (fr) 1996-11-19 1999-01-29 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos
JP3502531B2 (ja) * 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
US5891763A (en) * 1997-10-22 1999-04-06 Wanlass; Frank M. Damascene pattering of SOI MOS transistors
US6001706A (en) * 1997-12-08 1999-12-14 Chartered Semiconductor Manufacturing, Ltd. Method for making improved shallow trench isolation for semiconductor integrated circuits
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
FR2819636B1 (fr) * 2001-01-12 2003-09-26 St Microelectronics Sa Circuit integre comportant un point memoire de type dram, et procede de fabrication

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