JP2002270509A - 単結晶基板の製作方法およびその基板を含む集積回路 - Google Patents

単結晶基板の製作方法およびその基板を含む集積回路

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Publication number
JP2002270509A
JP2002270509A JP2001394184A JP2001394184A JP2002270509A JP 2002270509 A JP2002270509 A JP 2002270509A JP 2001394184 A JP2001394184 A JP 2001394184A JP 2001394184 A JP2001394184 A JP 2001394184A JP 2002270509 A JP2002270509 A JP 2002270509A
Authority
JP
Japan
Prior art keywords
trench
single crystal
substrate
silicon
crystal substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001394184A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002270509A5 (https=
Inventor
Olivier Menut
オリヴィエール・メニュ
Yvon Gris
イヴォン・グリ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of JP2002270509A publication Critical patent/JP2002270509A/ja
Publication of JP2002270509A5 publication Critical patent/JP2002270509A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3248—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3458—Monocrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Landscapes

  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2001394184A 2001-01-12 2001-12-26 単結晶基板の製作方法およびその基板を含む集積回路 Pending JP2002270509A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0100414A FR2819631B1 (fr) 2001-01-12 2001-01-12 Procede de fabrication d'un substrat monocristallin, et circuit integre comportant un tel substrat
FR0100414 2001-01-12

Publications (2)

Publication Number Publication Date
JP2002270509A true JP2002270509A (ja) 2002-09-20
JP2002270509A5 JP2002270509A5 (https=) 2005-07-14

Family

ID=8858764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001394184A Pending JP2002270509A (ja) 2001-01-12 2001-12-26 単結晶基板の製作方法およびその基板を含む集積回路

Country Status (5)

Country Link
US (1) US7060596B2 (https=)
EP (1) EP1223614B1 (https=)
JP (1) JP2002270509A (https=)
DE (1) DE60216646T2 (https=)
FR (1) FR2819631B1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2819632B1 (fr) * 2001-01-12 2003-09-26 St Microelectronics Sa Circuit integre comportant un dispositif analogique de stockage de charges, et procede de fabrication
US6784072B2 (en) * 2002-07-22 2004-08-31 International Business Machines Corporation Control of buried oxide in SIMOX
FR3099964B1 (fr) * 2019-08-14 2024-03-29 St Microelectronics Crolles 2 Sas Procédé de réalisation d’une électrode dans un substrat de base et dispositif électronique
CN112768509B (zh) * 2021-02-03 2022-07-08 杭州中瑞宏芯半导体有限公司 一种反向恢复时间短的frd二极管及制备方法
CN117568912B (zh) * 2023-11-21 2024-10-01 松山湖材料实验室 一种单晶复合衬底及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292365A (ja) * 1985-10-18 1987-04-27 Fuji Photo Film Co Ltd 半導体装置およびその製造方法
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
JPS62293759A (ja) * 1986-06-13 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置
US4942554A (en) * 1987-11-26 1990-07-17 Siemens Aktiengesellschaft Three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising trench capacitor and method for manufacturing same
KR100197648B1 (ko) * 1995-08-26 1999-06-15 김영환 반도체소자의 소자분리 절연막 형성방법
FR2756104B1 (fr) 1996-11-19 1999-01-29 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos
JP3502531B2 (ja) * 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
US5891763A (en) * 1997-10-22 1999-04-06 Wanlass; Frank M. Damascene pattering of SOI MOS transistors
US6001706A (en) * 1997-12-08 1999-12-14 Chartered Semiconductor Manufacturing, Ltd. Method for making improved shallow trench isolation for semiconductor integrated circuits
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
FR2819636B1 (fr) * 2001-01-12 2003-09-26 St Microelectronics Sa Circuit integre comportant un point memoire de type dram, et procede de fabrication

Also Published As

Publication number Publication date
DE60216646D1 (de) 2007-01-25
US7060596B2 (en) 2006-06-13
FR2819631B1 (fr) 2003-04-04
EP1223614A1 (fr) 2002-07-17
US20020094678A1 (en) 2002-07-18
DE60216646T2 (de) 2007-10-11
EP1223614B1 (fr) 2006-12-13
FR2819631A1 (fr) 2002-07-19

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