JP2002261703A - Sampling converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome the problem that, in a sampling converter, samples having no error periodically generate among sampling data after sampling conversion and are conspicuous. SOLUTION: There is provided a means for setting sampling points after sampling conversion, so that they differ from the sampling points before the sampling conversion and all the sampling points, and an error occurs in all the sampling points and emergency of the samples having no error is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to sampling converter for converting a digital signal having a first sampling frequency f _alpha into a digital signal having a second sampling frequency f _beta.

[0002]

BACKGROUND OF THE INVENTION When converting a digital signal having a first sampling frequency f _alpha into a digital signal having a second sampling frequency f _beta, performed in the following manner in the conventional technique.

In order to minimize the error in the sampling conversion, for each period of the greatest common frequency of the sampling frequency f _alpha and the sampling frequency f _beta, using sampling data before sampling conversion as sampling data after sampling conversion as it is. For data that cannot be used as is, a and b are data before sampling conversion at two points adjacent in the horizontal direction, and c and d are time differences from desired sampling data (data after conversion) to a and b, respectively. The data after sampling conversion is obtained by performing an arithmetic process such as a × d + b × c) / (c + d). It should be noted that not only two points adjacent in the horizontal direction but also two points adjacent in the vertical direction and a plurality of peripheral data in the horizontal and vertical directions are used.

[0004]

In the above-described sampling conversion processing, no error occurs in the sampling data before sampling conversion as it is as sampling data after sampling conversion. But,
An error occurs in the other sampling data because the arithmetic processing is performed. For this reason, in the sampling signal after the sampling conversion, sampling data having no error in the sampling signal including the error periodically appears. In other words, a signal in which noise-less data periodically exists in a noisy signal. Such signals are less preferred. An object of the present invention is to provide a sampling conversion device in which sampling data after sampling conversion has an error as evenly as possible.

[0005]

[Means for Solving the Problems] To solve the problems,
The sampling conversion device of the present invention is provided with a means for providing a sampling point by the second sampling clock that does not temporally overlap with a sampling point by the first sampling clock when performing the sampling conversion. That is, the second sampling point is delayed so that the sampling point by the first sampling clock and the sampling point by the second sampling clock are different. With this configuration, it is possible to prevent sampling data having no error from appearing periodically in the sampling signal after sampling conversion, and to make all sampling data after sampling conversion vary within a certain range. Can be. Therefore, it is possible to reduce the unevenness of the error as a whole.

Further, in order to more surely reduce the unevenness of errors appearing in each sampled data after sampling conversion, the minimum time difference between sampling points before and after sampling conversion is maximized. To maximize the minimum time difference, the minimum time difference T _d between sampling points before and after sampling conversion
And the operating frequency f _alpha and 0.5 times the period T _gamma minimum common multiple frequency f _gamma operating frequency f _beta of the second sampling clock of the first sampling clock. That is, T
_d is obtained by equation (1).

[0007]

[Number 1] _{T d = 0.5 / LCM (f} α, f β) ... (1) _{where, LCM (f α, f β} ) the operation of the operating frequency f _alpha and a second sampling clock of the first sampling clock It represents the least common multiple of the frequency f _β. Minimum time difference T _d shown in equation (1)
Is used, the minimum time difference _Td can be maximized. Thereby, the minimum error of each sampled data after the sampling conversion becomes the maximum. For this reason, it is possible to more reliably make the sampling data after error-free sampling conversion inconspicuous, and to more reliably reduce the unevenness of the error appearing in each sampling data after the sampling conversion.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, errors in sampling data will be described with reference to FIGS. As shown in FIG. 2A, when the sampling points before the sampling conversion are used as they are for the sampling data after the sampling conversion, the sampling data without any error is included in the signal after the sampling conversion as shown in FIG. 2B. Appears periodically. Therefore, sampling data having no error is conspicuous, and error unevenness increases. FIG. 2 (b)
| E (t) | indicates the absolute value of the error of the sampling data at the sampling point t after the sampling conversion. On the other hand, if all the sampling data before and after the sampling conversion is shifted as shown in FIG.
As shown in (b), all the sampling data after the sampling conversion has an error. Since the error varies within a certain range, the sampling data after sampling conversion without error is not conspicuous as a whole, and the unevenness of the error is reduced. Further, the minimum time difference between the sampling points before and after the sampling conversion is maximized by setting the minimum time difference between the sampling points before and after the sampling conversion to 0.5 times the cycle of the least common multiple frequency of the sampling frequency before and after the sampling conversion. In addition, sampling data without errors can be more reliably made inconspicuous, and unevenness in errors can be more reliably reduced.

Next, FIG. 1 shows a block diagram of a sampling converter which is an embodiment of means for shifting sampling points by the first and second sampling clocks. Figure 1
Is the sampling signal S _I (f _α ) sampled by the first sampling clock operating at the frequency f _α
Is a sampling conversion device for performing a sampling conversion on a sampling signal S _o (f _β ) sampled by a second sampling clock operating at a frequency f _β . The sampling conversion device of FIG. 1 performs a calculation for obtaining sampling data at each sampling point by a second sampling clock, and outputs the sampling data obtained by the calculation unit 110 with a second sampling clock. And a clock generator 130 for generating first and second sampling clocks.
The clock generation unit provides the generated first sampling clock and second sampling clock to the calculation unit 110 and the storage unit 120.

First, the clock generator 130 will be described. The clock generation unit 130 generates a second sampling clock that does not have the same sampling point as the sampling point by the first sampling clock.
There are various methods for generating such a second sampling clock, but the following two will be described as examples. It goes without saying that the present invention can be applied even if a method other than these two examples is used.

As a first specific means of the clock generation unit 130, a method of inputting a first sampling clock and generating a second sampling clock using a PLL will be described with reference to FIG. FIG. 4 shows a configuration diagram of the clock generation unit 130 using a PLL. The first sampling clock is input to the frequency divider 450. The frequency divider 450 divides the frequency of the first sampling clock to a common divisor of the frequencies of the first and second sampling clocks. on the other hand,
The voltage controlled oscillator 440 generates a clock whose operating frequency is equal to the second sampling clock. Divider 451
Divides the output clock of the voltage controlled oscillator 440 to a frequency equal to the operating frequency of the output clock from the frequency divider 450. Two clocks having the same operating frequency and divided by the frequency dividers 450 and 451 are input to the phase comparator 410, the low-pass filter 420, and the amplifier 430, and the output is input to the voltage-controlled oscillator 440 as a control signal. Voltage controlled oscillator 440
Is used as a second sampling clock. The minimum time difference _Td between the sampling points by the first and second sampling clocks can be controlled by adjusting the gain of the PLL. The gain of the PLL can be controlled by adjusting the gain of the amplifier 430 or the like. The sampling points by the first and second sampling clocks are all different.
By adjusting the gain of the PLL, it is possible to prevent data having no error from appearing periodically in the sampling data after the sampling conversion. Further, the minimum time difference _Td between the sampling points of the first and second sampling clocks at this time is set to a time 0.5 times the cycle of the least common frequency of the operating frequencies of the first and second sampling clocks. By doing so, the minimum time difference _Td between the sampling points by the first and second sampling clocks can be maximized. Although the present embodiment has been described using an exclusive OR circuit as a phase comparator, there is no essential difference even if a phase comparator having another configuration is used. In this embodiment, the amplifier 430 is used for adjusting the gain of the PLL.
30 can be configured.

As a second specific example of the clock generator 130, a clock whose operating frequency is a common multiple of the operating frequencies of the first and second sampling clocks is input, and this is divided into first and second clocks. And a method of generating the second sampling clock. FIG. 5 shows a configuration example of the clock generation unit 130 using this method. First, the clock generator 1
To 30 is input a clock whose operating frequency is a common multiple of the operating frequencies of the first and second sampling clocks. This is divided by a frequency divider 510 into a clock having an operating frequency equal to the operating frequency of the first sampling clock.
This output is used as a first sampling clock.
The frequency divider 511 divides the input clock into a clock having an operation frequency equal to the operation frequency of the second sampling clock. The clock output from the frequency divider 511 is delayed by the delay unit 520, and the output is used as a second sampling clock. FIG. 6 shows a configuration example of the delay unit 520. The delay unit shown in FIG. 6 has a variable delay amount. The input signals are sequentially delayed by buffers 610, 611, 612, 613. On the other hand, only one of the switches 620, 621, 622, 623 is turned on, and the other switches are turned off.
The amount of delay can be preset depending on which switch is turned on. When configuring the delay unit 520, the delay amount does not have to be variable, and a delay unit having a variable delay amount or a configuration other than the delay unit configuration shown in FIG. 6 can be used. Further, even when the minimum time difference _Td between the sampling points by the desired first and second sampling clocks can be obtained from the difference between the delay amounts of the frequency dividers 510 and 511, a configuration that does not require a delay device is used. Good. By providing the delay unit 520 with a preset value that is the minimum time difference _Td between the sampling points of the first and second sampling clocks such that all the sampling points of the first and second sampling clocks are always different, the sampling conversion is performed. It is possible to prevent data having no error from appearing periodically in subsequent sampling data. Further, the minimum time difference _Td between the sampling points by the first and second sampling clocks is
By setting the time to be 0.5 times the cycle of the least common frequency of the operating frequencies of the first and second sampling clocks,
The minimum time difference _Td between the sampling points by the first and second sampling clocks can be maximized.

Next, the calculation unit 110 will be described. In the calculation unit 110, the second
The sampling data corresponding to the sampling point by the sampling clock is calculated.

According to the first and second sampling clocks,
Time difference T between sampling points _dIs the first sump
Ring clock operating frequency f_αAnd the second sampling
Clock operating frequency f_βLeast common frequency of f_γPeriod T
_γCan be maximized when the time is 0.5 times as large as
For example, the operating frequency f of the first sampling clock _α=
32KHz, operating frequency f of the second sampling clock_β= 4
For 8KHz, least common multiple frequency f_γ= 96KHz, the first
And the sampling point by the second sampling clock
Minimum time difference T between_d= 5.2 μs.

Next, a description will be given of a sampling conversion apparatus which performs sampling conversion with the minimum time difference T _d = 5.2 μs between the sampling points by the first and second sampling clocks. Here, as an example, the sampling conversion formula is
Equation (2) shows the window function W (t) in equation (2) in equation (3). (3)
The waveform represented by the equation is shown in FIG. Here, S _o (t) in the equation (2) is sampling data at the sampling point t by the second sampling clock, and t ₀ , t ₁ , t ₂ ,. They are arranged in order. Δt in the equation (3) and FIG. 7 is a time difference from the sampling point by the second sampling clock to the sampling point by the first sampling clock. T _α is the period of the first sampling clock.

[0016]

(Equation 2)

(Equation 3) The window function according to equation (3) shown here is a linear, three-tap function. FIG. 8 shows a configuration example of the calculation unit 110 using the window function shown in the equation (3). When f _α = 32 KHz, f _β = 48 KHz, and T _d = 5.2 μs, the sampling data at the sampling point by the second sampling clock is 0.833 _I (t
_i-1 ) + 0.167S _I (t _i ), 0.167S _I (t _i-1 ) + 0.833S _I (t _i ), 0.500S _I
(t _i-1 ) + 0.500S _I (t _i ). However, S _I
(t) is the sampling data at the sampling point t by the first sampling clock, and i is an arbitrary integer of 1 or more. Therefore, the calculation unit 110 shown in FIG.
These three are calculated and output for each sampling point by the first sampling clock. Although three calculation solutions are output for each sampling point based on the first sampling clock, some of the solutions are not used. Therefore, the configuration example of the calculation unit 110 illustrated in FIG. 8 assumes that the storage unit 120 has a function of classifying only the solution to be used. However, it goes without saying that the present invention can be applied to other configurations such as the configuration of the calculation unit 110 that outputs only the solution to be used.

As another example of the window function for constructing a sampling conversion device in which the minimum time difference T _d between the sampling points by the first and second sampling clocks is 5.2 μs, the fourth order b Indicates the -spline function. FIG. 9 shows the window function of equation (4).

[0018]

(Equation 4) The window function in equation (4) is a 5-tap function. FIG. 10 shows a configuration example of the calculation unit 110 using the equation (4) as a window function. f _α = 32KHz,
When f _β = 48 KHz and T _d = 5.2 μs, in the sampling conversion using the equation (4) as a window function, the sampling data at the sampling point by the second sampling clock is 0.010S.
_I (t _i-3 ) + 0.664S _I (t _i-2 ) + 0.262S _I (t _i-1 ) + 0.001S _I (t _i ),
0.001S _I (t _i-3 ) + 0.262S _I (t _i-2 ) + 0.664S _I (t _i-1 ) + 0.010S
_I (t _i ), 0.021S _I (t _i-3 ) + 0.479S _I (t _i-2 ) + 0.479S _I (t _i-1 ) +
0.021S _I (t _i ). Therefore, FIG.
In the example of the configuration of the calculation unit 110, these three calculations are performed, and the solution is output. The calculation unit shown in FIG.
Like the configuration example of the calculation unit 110 shown in FIG. 8, the configuration example of 110 also assumes that only the solution to be used is separated in the storage unit 120. Needless to say, the present invention can be applied to other configurations such as the configuration of the calculation unit 110.

Although two types of window functions are shown here as a method of configuring the calculation unit 110, it goes without saying that the calculation unit 110 can be configured by other methods and the present invention can be applied. .

The storage unit 120 is used to convert the operation clock from the first sampling clock to the second sampling clock. That is, the sampling data calculated by the calculation unit 110 operating with the first sampling clock is temporarily stored in a memory or the like, and read out with the second sampling clock.

The calculation unit shown in FIGS.
FIG. 11 shows a configuration example of the storage unit 120 corresponding to 110. In FIGS. 8 and 10, three values are output at each sampling point by the first sampling clock. However, not all of these three values are used as sampling data, but which of the three values output from the calculation unit 110 corresponds to the sampling data to be obtained differs for each sampling point by the first sampling clock. Further, at one sampling point by the first sampling clock, two of the three values output from the calculation unit 110 are output.
One may be necessary sampling data. Therefore, a memory is provided for each of the three outputs from the calculation unit 110, and only necessary data is stored in the memory by the memory control unit 1020. When reading, the second sampling clock is used, and for each sampling point based on the second sampling clock, data is output from only one of the three memories. Which memory to read from depends on the memory controller 1020. It should be noted that the storage unit 120 can be configured other than the configuration example of the storage unit 120 shown in FIG. 11, such as a configuration without using a memory, and that the present invention can be applied.

[0022]

According to the sampling conversion apparatus of the present invention, the means for setting the sampling point by the first sampling clock and the sampling point by the second sampling clock to be different when performing the sampling conversion is provided. It is possible to prevent the appearance of data having no error periodically in the sampled data after the sampling conversion, and reduce unevenness of the error.

When performing sampling conversion, the first
If the time difference between the closest point of the sampling point of the sampling clock of the second sampling clock and the closest point of the sampling point of the second sampling clock is 0.5 times the period of the least common frequency of the operating frequencies of the first and second sampling clocks, The minimum time difference between the sampling point by the first sampling clock and the sampling point by the second sampling clock can be maximized, the sampling data after the error-free sampling conversion can be made less noticeable, and The unevenness of the error appearing in each sampling data can be reduced more reliably.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a sampling conversion device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of a sampling conversion according to a conventional technique and an explanatory diagram thereof.

3A and 3B are a waveform diagram and an explanatory diagram of a sampling conversion according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a clock generation unit of the sampling conversion device according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a clock generation unit of the sampling conversion device according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a delay unit in a clock generation unit of the sampling conversion device according to the embodiment of the present invention.

FIG. 7 is a waveform diagram of a window function used for sampling conversion according to the embodiment of the present invention.

FIG. 8 is a configuration diagram of a calculation unit of the sampling conversion device according to the embodiment of the present invention.

FIG. 9 is a waveform diagram of a window function used for sampling conversion according to the embodiment of the present invention.

FIG. 10 is a configuration diagram of a calculation unit of the sampling conversion device according to the embodiment of the present invention.

FIG. 11 is a configuration diagram of a storage unit of the sampling conversion device according to the embodiment of the present invention.

[Explanation of symbols]

 110 calculation unit 120 storage unit 130 clock generation unit 200 analog signal before sampling 410 phase comparator 420 low-pass filter 430 amplifier 440 voltage-controlled oscillator 450,451 frequency divider 510,511 frequency divider 520 Delay device 610,611,612,613… Buffer 620,621,622,623… Switch 810,811,812… Multiplier 820,821,822… Adder 830,831,832… Flip-flop 1010,1011,1012,1013,1014,1015… Multiplier 1020,1021,1022… Adder 1030,1031,1032,1033, 1034,1035 ... Flip-flop 1040,1041,1042,1043,1044,1045 ... Flip-flop 1050,1051,1052 ... Flip-flop 1110,1111,1112 ... Memory 1120 ... Memory controller 1130 ... OR circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C082 AA01 BC03 CA21 CA85 DA76 MM10 5K041 AA04 EE01 HH40 JJ11 JJ18 JJ21 JJ24 JJ31 JJ32 5K047 AA01 GG02 MM46 MM50 MM53 MM55 MM63

Claims (7)

[Claims] 1. A sampling conversion device for converting a digital signal based on a first sampling clock into a digital signal based on a second sampling clock, wherein the sampling point based on the second sampling clock is the sampling point based on the first sampling clock. A sampling conversion device provided with clock generation means for generating a second sampling clock differently from the above. 2. A sampling conversion device for converting digital data based on a first sampling clock into digital data based on a second sampling clock, wherein a sampling point based on the second sampling clock is converted from the digital data based on the first sampling clock. Calculating means for calculating the sampling data in the storage means, storing the sampling data output from the calculating means, and outputting the sampling data with the second sampling clock; And a clock generating means for generating the second sampling clock so as to be different from the sampling point by the sampling clock, and providing the calculating means and the storage means with the second sampling clock. Grayed conversion device. 3. The clock generating means includes: first frequency dividing means for dividing the input first sampling clock to a frequency which is the greatest common divisor of the first and second sampling clocks; Voltage-controlled oscillating means for generating a clock having an operating frequency equal to the second sampling clock; and an output clock of the voltage-controlled oscillating means up to a clock having an operating frequency equal to the sampling clock output from the first frequency dividing means. Second frequency dividing means for dividing the frequency, phase comparing means to which the clocks output from the first frequency dividing means and the second frequency dividing means are inputted, and a signal outputted from the phase comparing means Signal converting means for converting the control signal into a control signal and outputting the control signal to the voltage controlled oscillating means, wherein the second sampling clock is generated by the output of the signal converting means. Sampling conversion apparatus according to claim 1 or 2, characterized in. 4. A first frequency dividing means to which a clock having a frequency which is the greatest common divisor of the first and second sampling clocks is inputted, and which divides the frequency to the same frequency as the first sampling clock, 1 and a clock having a frequency which is the greatest common divisor of the second sampling clock is input, and the second frequency dividing means divides the frequency to the same frequency as the second sampling clock; and an output from the second frequency dividing means. 3. The sampling converter according to claim 1, further comprising: delay means for delaying the delayed clock and using the delayed clock as a second sampling clock. 5. The clock generating means according to claim 1, wherein a minimum time difference between a sampling point based on the second sampling clock and a sampling point based on the first sampling clock is a minimum common difference between the frequencies of the first and second sampling clocks. The sampling converter according to claim 1, wherein the first and second sampling clocks having a time that is 0.5 times the cycle of the double frequency are generated. 6. A sampling converter for converting a digital signal based on a first sampling clock into a digital signal based on a second sampling clock, wherein the sampling points based on the second sampling clock are:
A sampling conversion device comprising means for shifting a sampling point by a second sampling clock so as to be different from a sampling point by a first sampling clock. 7. A sampling converter for converting a digital signal based on a first sampling clock into a digital signal based on a second sampling clock, wherein a sampling point based on the second sampling clock and a sampling point based on the first sampling clock are used. Wherein the minimum time difference is 0.5 times the cycle of the least common multiple frequency of the first and second sampling clocks.