JPS5831643A - Standard signal generator - Google Patents

Abstract

PURPOSE:To generate a standard signal as a digital signal directly, by reading out the content of a corresponding address stored in a storage device in synchronizing with an external signal and performing the operation processing, through the command of a switch circuit designating frequency, level and waveform. CONSTITUTION:A storage circuit 10 selects a minimum frequency fe to be generated so that a quotient of a sampling frequency fs divided by the fe is an integer, and as to the standard signal waveform transmitted, the sampling values equal to this quotient are stored as digital values. A storage circuit 11 stores a multiplier for level conversion of a digital signal to a separate address at each level conversion. A readout output of an address designated at the circuit 1 is multiplied 17 with the readout output of the circuit 10 to form a phase-locked loop including a voltage controlling oscillator 23 operated in synchronizing with a synchronizing signal given externally. The readout operation of the circuit 10 and the multiplication operation of the circuit 17 are controlled with a clock generating circuit 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal generator that generates a standard signal as a digital coded signal. In particular, Digital Communication Line Test 1+ relates to a device suitable for maintenance use, which can be synchronized with an externally applied signal and which generates a standard signal of any level and frequency.

In a conventional digital standard signal generator of this type, as illustrated in FIG. Digital POM by 3
It is sent to the output terminal 4 as a signal. A synchronizing signal is applied to the input terminal 5. When it becomes necessary to change the level or frequency of the digital PON 1 depending on the purpose of use, the change is made by operating the analog signal oscillator 1, which is the signal generation source.

In this analog signal oscillator 1, the initial set value is likely to fluctuate due to temperature changes or changes in temperature, and furthermore, adjustment is extremely difficult, requiring a huge number of adjustment steps during manufacturing.

In addition, in digital communication systems, information is arranged on the time axis, so external devices connected to the line of sight for measurement or maintenance must be synchronized with each other in terms of time. Since the conversion time required for digital linear encoding is long, there is a drawback that the frequency at which the digital signal can be synchronized with an external clock is limited.

The present invention improves on this and aims to provide an apparatus that directly generates a standard signal as a digital signal instead of converting it into an analog signal tube digital signal. The present invention has no level or frequency changes due to temperature changes or aging, can always generate accurate standard signals in synchronization with external inputs, requires almost no calibration to adjust the device, and The object of the present invention is to provide a device capable of generating high frequency signals.

The present invention stores nine values encoded according to the frequency, level, and waveform of a digital signal at a predetermined address in a storage circuit, and receives a command from a switch circuit that specifies the frequency, level, and waveform. It is characterized by reading out the contents of the address in synchronization with an external signal and performing arithmetic processing on the read output.

Next, a detailed explanation will be given using embodiment drawings.

FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention. Each of the memory circuits 10 has a basic waveform (here, a sine wave).
The amplitude sampled values of are digitized and written in advance. Further, constants specifying levels are written in the memory circuit 11K in advance. This level can be externally controlled (specified by the switch circuit 12K). The switch circuit 13#i is a switch that is also controlled externally to specify the frequency, and its output is controlled by the adder circuit 14, the comparator circuit 15, The holding circuit 16 converts the signal into an addressing signal and applies it to the storage circuit 10.

The digital signal string read out from the memory circuit 10 is operated by the multiplier circuit 17 with the constant read out from the memory n1llll, and converted into a POM signal by the encoder circuit 18 and sent to the output terminal 4.
Sent from The signal is also converted into an analog signal by the D/DC conversion circuit 19K, and sent out as an analog output from the output terminal 21 via the low-frequency pan path 20.

The signal applied to the input terminal 5 is, for example, a synchronization signal obtained from a communication line 6, and the signal at the input terminal 5 is processed by a so-called phase synchronization circuit consisting of a phase comparator circuit 22, a voltage controlled oscillation circuit 23, and a frequency dividing circuit 24. A desired clock signal synchronized with is generated and supplied to the D/DC conversion circuit 19 and the code circuit 18. This signal is further processed by a clock extraction circuit 26 and a shift circuit 27 to generate a synchronization signal necessary for the storage circuit 10 and the multiplication circuit 17.

First, the initial settings of the device configured as described above will be explained.

In the storage circuit 10, an analog signal is sampled in advance at equal time intervals, the sampled value, that is, the amplitude value is digitized into a linear code, and a good signal is stored as data. Now, let us assume that the lowest signal frequency to be generated is f・, and the sampling frequency is f−, then select f・ so that “/l” is an integer.The number of sample values equal to this “/l” is selected. The data is stored in this memory circuit 10 as data. This”/1@uf@
This is the number of samples when one period of is sampled by 8.

Next, the frequency and level of the digital signal are set and designated using the frequency designation switch circuit 13 and the level value/designation switch circuit 12, respectively.

With this initial setting, when the frequency and level of the digital signal are specified by the switch circuits 12 and 13, the specified value for the frequency enters one input of the adder circuit 14, passes through the comparator circuit 15, and is held. It is temporarily stored in the circuit 16. This output is fed back to the other input of the adder circuit 14 again. Therefore, the adder circuit 14 is connected to the switch circuit 13
The specified value and the output value of the holding circuit 16 are added and outputted to the comparison circuit 15.

15 comparison circuits, the output value of the addition circuit 14, and a pre-stored fixed sample value fII/1. When the comparison value is greater than or equal to the sample value, a value obtained by subtracting this sample value from the output value is output, and when the comparison value is less than or equal to the sample value, the output value is output as is.

The holding circuit 16 receives nine control clock signals in synchronization with the sampling period from a synchronous calculation clock generation circuit composed of a phase comparison circuit 22, a voltage controlled oscillation circuit 23, a frequency division circuit 24, a click extraction circuit 26, and a shift circuit 27. It receives the signal as needed, temporarily stores the output value of the comparison circuit 15 for each signal, and sends the output to the storage circuit 10. Memory circuit 1
0 receives the output of the holding circuit 16 and immediately stores its contents.

The contents stored in the storage circuit 10 in this manner are standard digital signals, and a control clock signal is received from the shift circuit 27 in synchronization with this sampling period every sampling period, and upon reception, the storage circuit 10 Reading is performed from.

In this way, the reading of the memory circuit 10 is performed step by step.
When done cyclically, a low frequency (f) signal is output,
If we take that step, then f-th 2f,, St,, ---・-, if f,, --・-,
A signal with a frequency of – is output. In this case, the highest frequency of occurrence is limited by the sampling theorem to f8/2.

In the case of generating an analog signal, the digital signal output from the storage circuit 10 is input to the multiplication circuit 17 and set to a predetermined level, and then converted to an analog signal by the DMU conversion circuit 19 to generate a low-frequency P wave. The signal is outputted via the device 20.

When it is desired to change the frequency, the designated value is changed using the frequency designating switch circuit 13.

Next, a description will be given of changing the level of a digital signal in the present invention. In the above-described initial setting, when a level value is designated by the level value designating switch circuit 12, the storage circuit 11 for storing level conversion coefficients selects an address where data corresponding to the designation is stored. At address #i in this memory circuit 110, a constant corresponding to the level, that is, data necessary to determine the level of the digital signal is stored in advance. The constant at the address specified by the switch circuit 12 is read and output to the multiplication circuit 17.

At this time, as described above, the frequency specified by the frequency specification switch circuit 13, that is, the digital signal, is already processed in the multiplication circuit 17 by the addition circuit 14, the comparison circuit 15, the holding circuit 16, the storage circuit 10, etc. , are input from this memory circuit 10.

Therefore, the multiplication circuit 17 receives a control clock signal synchronized with the sampling period of the synchronous operation clock generation circuit and the sampling period, and upon receiving the control clock signal, multiplies the input value from the storage circuit 10 by the constant. , output as a specified level.

Now, if the input value is am and this constant is ORed, the output value of the multiplication circuit 17 will be as X Owl. in this case.

If an ≧ 1, then amplification 0R (if it is 1, it will be attenuation, and the constant is set in advance by 20 log, .0R (
(IB), it becomes possible to change the signal level in dBlv[. The digital signal #iDm conversion circuit 191 of the specified level thus outputted is inputted to the POM code circuit 18tj.

The DM conversion circuit 19 receives the frame pulse signal from the branch circuit 16, converts the input signal into an analog signal, and outputs this analog signal via the low-frequency p-wave converter 2G. POM
The code circuit 18 receives the POM bit clock from the branch circuit 16 and outputs a digital signal.

Next, the synchronization required when using the device of the present invention in a digital communication system will be explained. In the digital communication system, since information is transmitted on the time axis, it is necessary for connected external devices to operate in mutual synchronization with each other in terms of time. In other words, the digital processing must be performed within one sampling period, and the control clock signal must also be synchronized with the synchronization signal input from the terminal 5.

Therefore, in the O device of the present invention, as shown in the second ffiK,
Adopts an omniscient O phase-locked circuit (PIJ TJ, loop method). That is, the phase comparator circuit 22, the voltage controlled oscillator circuit 23, and the frequency divider circuit 24 are connected in series, the 10th output of the frequency divider circuit 24 is feedback-connected to one output of the phase comparator circuit 22, and the phase comparison circuit 24 is connected in series. The other input of circuit 22 is provided with an external synchronization signal. Furthermore, as the positive and third outputs of the 1 frequency divider circuit 24, the signal output terminal 31 and the '1' output terminal of the frame pulse signal synchronized with the sampling period, respectively.
A clock output terminal 32 of the M-bit clock is provided.

When the input terminal SK external synchronization signal, that is, the digital overconfidence type PGM clock signal f@x, is input, the input signal is combined with the feedback signal from the frequency divider circuit 24 and the phase comparator circuit 22.
The phase comparison is performed by the voltage control generator 11111.
Enter 128. As a result, the voltage controlled oscillator circuit 23 acts to synchronize with the synchronizing signal t@xK, and oscillates at the frequency f.
The output is output to the frequency dividing circuit 24.

The division circuit 24 is a 1/M frequency divider (M=integer), and outputs a frame pulse signal and a 70 Mbit clock to a signal output terminal 31 and a clock output terminal 32, respectively. This frame pulse signal #i1 period clock extraction circuit 26 enters one input, and the H-f*xvrM divided clock that has already arrived at the other input causes the 1 period clock extraction circuit 26 to output M/ A pulse corresponding to one period of the clock Nfex is extracted from the rising edge of the frame pulse signal and is applied to the shift circuit 27.

The shift circuit 27 shifts the input value at the frequency /Hf@x and outputs a control clock signal for control. This control clock signal has M/N f·! on 111 cycles. The clock is composed of a /M clock having one pulse temporally shifted with a period of 1, and is used as a clock signal for controlling sequentially in time within the full cycle.

The frame pulse signal itDM of the terminal 31 is used for controlling the DTM conversion circuit 19. The control signal sent from the shift circuit 27 is sent to the holding circuit 16, the storage circuit 10. It is used for controlling the multiplication circuit 170. t, terminal 32
P (1M bit clock is used as a clock signal for controlling the POM code circuit 18.

As described above, according to the present invention, there is provided a standard signal generating device that can generate a digital signal directly rather than generating an analog signal and converting the signal into a digital signal. According to the present invention, the frequency is determined in synchronization with the clock of the given system, so it does not fluctuate due to temperature changes or aging. Furthermore, since the level is determined by calculation using digital values, it will not gradually fluctuate during use. Waveforms that are stored in advance can be selected from various standard waveforms, including sine waves, resulting in a device that does not require adjustment during calibration. Also,
Regarding signals in the high frequency range, there are no limitations in principle, depending on the performance of the digital circuits used.

The device of the present invention is useful when used as a maintenance test device for digital communication lines.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a conventional device. FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention. 5.--Synchronization signal input terminal, io-.. (first) storage circuit, 11-. (second) storage circuit, 22.--phase comparison circuit, 23-.. voltage controlled oscillation circuit. Naotaka Ide, Patent Attorney and Patent Issuer Representative

Claims (1)

[Claims] (1) The standard signal waveform to be transmitted is selected such that the quotient of the sampling frequency divided by the lowest generated frequency is an integer (and the first signal waveform is selected to be transmitted in such a way that the quotient of the sampling frequency divided by the lowest generated frequency is an integer). a second memory circuit in which a multiplier for performing level conversion of a digital signal is stored at a different address for each level conversion amount; A multiplication circuit that multiplies the readout output of a designated address of the storage circuit, and a phase synchronization circuit that operates in synchronization with an externally applied synchronization signal; a readout operation of the first storage circuit and a multiplication operation of the multiplication circuit. The standard signal generator II is equipped with a circuit that generates the clock signal and the signal that controls the clock.