JP2002232269A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a consumption current at the time when the frequency of a clock signal is low in a clock generation circuit. SOLUTION: When a clock selection circuit 30 selects a clock signal CLKA of a high frequency, the clock signal CLKA is supplied at high speed to each circuit block by enhancing the performance of a clock driver circuit 40. When the selection circuit 30 switches the clock signal CLKA of a high frequency to a clock signal CLKB of a low frequency, a consumption current is reduced by lowering the drive capability of the driver circuit 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for switching and outputting a plurality of clocks having different frequencies.

[0002]

2. Description of the Related Art A microcomputer is a CR oscillator,
It operates based on a basic clock generated from a crystal oscillator, a ceramic filter, or the like. This basic clock is driven by a clock driver and supplied to each circuit block. Here, the clock driver is configured to be able to switch between, for example, one of a high-frequency first clock and a low-frequency second clock in accordance with the operation speed of the microcomputer.

In this case, the driving capability of the clock driver is set so as to supply a basic clock to each circuit block at a high speed corresponding to the maximum operating speed of the microcomputer.

[0004]

By the way, when the driving capability of the clock driver is increased, the current consumption increases accordingly. However, according to such a configuration, the current consumption increases even when the basic clock is switched from the high frequency first clock to the low frequency second clock, and the current consumption of the microcomputer as a whole increases. There was a drawback of doing it.

On the other hand, in order to supplement the driving capability of the clock driver, another clock is provided at an appropriate position on a clock line for transmitting a basic clock to each circuit block (for example, a clock supply point to each circuit block). A driver may be involved. By doing so, it is possible to reduce the size of the clock driver of the clock source and reduce the current consumption. However, the interposition of the clock driver causes a delay of the basic clock, which may cause a malfunction of the circuit block.

An object of the present invention is to reduce the current consumption of a clock driver when a low-frequency clock is selected. In particular, in a microcomputer, the current consumption when the operation speed is low is reduced. That is.

[0007]

A clock generation circuit according to the present invention comprises: a clock selection circuit for selectively outputting any one of a plurality of clock signals having different frequencies in accordance with a switching signal; A clock driver circuit to which a clock signal selected by a clock selection circuit is applied and whose drive capability can be switched according to the switching signal.

When a high-frequency clock signal is selected, the clock signal can be supplied to each circuit block at high speed by increasing the capability of the clock driver. When a clock signal is switched from a high-frequency clock signal to a low-frequency clock signal by the clock selection circuit, the current consumption can be reduced by reducing the driving capability of the clock driver circuit according to the frequency. Become.

A clock selection circuit for selectively outputting any one of a plurality of clock signals having different frequencies according to the first switching signal, and a clock signal selected by the clock selection circuit And a clock driver circuit whose drive capability can be switched in response to a second switching signal, wherein the clock signal is selectively output based on the first and second switching signals. The timing and the switching timing of the drive capability of the clock driver circuit can be adjusted.

For example, when switching from a high-frequency clock signal to a low-frequency clock signal, the first
A second switching signal is output a predetermined time after the switching signal is output. Thus, after switching from the high frequency clock signal to the low frequency clock signal, the drive capability of the clock driver circuit is switched low.

Therefore, the current consumption of the clock driver circuit when a low-frequency clock is selected can be reduced, and the driving capability of the clock driver circuit is switched to a low value before the switching of the clock signal, resulting in insufficient driving capability. There is no danger of occurrence.

Conversely, when switching from a low-frequency clock signal to a high-frequency clock signal, the first switching signal is output a predetermined time after the second switching signal is output. Thus, after the drive capability of the clock driver circuit is switched to a high level, the clock signal is switched from a low-frequency clock signal to a high-frequency clock signal. There is no danger that the driving capability of the clock driver circuit will be insufficient.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a clock generation circuit according to an embodiment of the present invention will be described with reference to FIGS.

In FIG. 1, a clock signal (first clock signal CLKA) output from an oscillator 10 for generating a source oscillation clock signal is frequency-divided by a frequency divider 20 to have a lower frequency than the first clock signal CLKA. A second clock signal CLKB is generated. As the oscillator 10, a CR oscillator, a crystal oscillator, a ceramic filter, or the like can be used.

The clock selection circuit 30 receives the first and second clock signals CLKA and CLKB in response to the clock switching signal Sig1.
Select and output either one. The clock selection circuit 30 can be constituted by, for example, a multiplexer. Thus, when the clock switching signal Sig1 is “L (low level)”, the first clock signal CLKA is selected, and when the clock switching signal Sig1 is “H (high level)”, the second clock signal CLKB is selected. Is selected.

The clock driver circuit 40 is a circuit for driving the clock signal selected by the clock selection circuit 30, and is configured so that the driving capability can be switched by the clock switching signal Sig1.

Specifically, the clock driver circuit 40
Is composed of a clocked inverter 41 (first inverter) and an inverter 42 (second inverter) to which the output of the clock selection circuit 30 is applied. The outputs of the clocked inverter 41 and the inverter 42 are commonly connected. The clocked inverter 41 is configured by connecting P-channel MOS transistors M1 and M2 and N-channel MOS transistors M3 and M4 in cascade. The inverter 42 is configured by connecting a P-channel MOS transistor M5 and an N-channel MOS transistor M6 in cascade.

When the clock switching signal Sig1 is "L", the clocked inverter 41 functions as an inverter because M1 and M4 are turned on. However, when the clock switching signal Sig1 is "H", the clocked inverter 41 functions as an inverter. Since M1 and M4 are turned off, their outputs become high impedance. On the other hand, the inverter 42 always operates regardless of the clock switching signal Sig1.

Therefore, according to the clock generation circuit 100 having the above-described configuration, when the clock switching signal Sig1 is "L", the first clock signal CLKA having a high frequency is selected by the clock selection circuit 30. Are supplied to the clock driver circuit 40. When both the clocked inverter 41 and the inverter 42 operate, sufficient driving capability can be obtained. Then, when the clock switching signal Sig1 is switched to “H” and the second clock signal CLKB having a low frequency is selected by the clock selection circuit 30, only the inverter 42 operates to drive the clock driver circuit 40. The ability is switched low. Since clocked inverter 41 does not operate, current consumption can be reduced accordingly.

As shown in FIG. 2, the first clock signal CLKA is generated by the first oscillator 11 having a high frequency, and the second clock signal CLKB is generated by the second oscillator 12 having a low frequency. May be created. When the second clock signal CLKB is selected by the clock selection circuit 30, the operation of the high-frequency first oscillator 11 is stopped, so that the current consumption of the oscillator can also be reduced. is there.

Next, a second embodiment will be described with reference to FIG. In this embodiment, a first switching signal Sig1 for controlling the clock selection circuit 30 and a second control signal Sig2 for switching the driving capability of the clock driver circuit 40 are separated from each other, so that the first and second clock signals are switched. The timing for selectively outputting CLKA and CLKB and the timing for switching the drive capability of the clock driver circuit 40 can be adjusted. Other configurations are the same as those of the first embodiment.

The operation will be described with reference to FIG. First
When the switching signal Sig1 changes from “L” to “H”, the clock selecting circuit 30 switches the high frequency first clock signal CLKA to the low frequency second clock signal CLKB accordingly.

After a predetermined time, the second switching signal Sig2 changes from "L" to "H". As a result, the drive capability of the clock driver circuit 40 is switched to a lower level. Therefore, the low frequency second clock signal CLKB
When the clock signal is selected, the current consumption of the clock driver circuit 40 can be reduced, and before the clock signal is switched, the drive capability of the clock driver circuit 40 is switched to a low level.

Conversely, the low frequency second clock signal CL
When switching from KB to the first clock signal CLKA having a higher frequency, first, the second switching signal Sig2 changes from “H” to “L”, and the driving capability of the clock driver circuit 40 is switched to a higher level.

After a predetermined time, the first switching signal Sig1 changes from "H" to "L". As a result, since the first clock signal CLKA having a high frequency is switched after the drive capability of the clock driver circuit 40 is switched to a high level, there is no possibility that the drive capability of the clock driver circuit 40 becomes insufficient.

Further, in the circuit of the second embodiment, the first clock signal CL is used similarly to the configuration shown in FIG.
KA may be created by the first oscillator 11 having a high frequency, and the second clock signal CLKB may be created by the second oscillator 12 having a low frequency. Then, the first clock signal having a high frequency is output by the clock selection circuit 30.
When the frequency is switched from CLKA to the second clock signal CLKB having a lower frequency, the oscillating operation of the first oscillator 11 having a higher frequency is stopped, and current consumption can be reduced.

Although the case where two clock signals are switched in the first and second embodiments has been described,
The present invention is not limited to this, and can be applied to a case where any one of two or more clock signals is selected. When the clock generation circuit 100 having the above-described configuration is built in a microcomputer and supplied as its basic clock, the first switching signal Sig1 and the second
The switching signal Sig2 can be generated using a command of a microcomputer.

Next, an example of application of the clock generation circuit of the present invention to a microcomputer will be described with reference to FIG. The clock signal from the clock generation circuit 100 is (the first clock signal CLKA or the second clock signal CL
KB) transmitted on the clock line 110 as a basic clock.

In the microcomputer 200, the clock line 110 includes a display drive circuit such as an LCD, a peripheral circuit 101 such as a serial interface circuit, an internal circuit 102 such as a timer and an AD converter, and a CPU 10.
3, wiring is provided throughout the microcomputer chip to supply a basic clock to many circuit blocks such as the ROM 104.

The clock line 110 is formed of a metal wiring such as an Al wiring, and is wired without intervening a plurality of other clock driver circuits (such as an inverter) in the middle. This is to prevent clock skew from occurring due to the intervening clock driver circuit. As a result, the clock line 110
Has a considerably large stray capacitance. Therefore, it is necessary to set the drive capability of the clock driver circuit 40 high so as to correspond to the maximum operation speed of the microcomputer 200.

Therefore, when the operating speed of the microcomputer 200 is high (for example, when the first clock signal CLKA is used as a basic clock), the driving capability of the clock driver circuit 40 is increased, and the operating speed of the microcomputer 200 is increased. Is slower, the clock driver circuit 40 can be switched to lower the drive capability. Therefore, an optimal drive capability can be obtained according to the operation speed of the microcomputer, and the clock driver circuit 40 when the operation speed is low can be obtained.
Current consumption can be reduced.

[0032]

According to the clock generation circuit of the present invention, the drive capability of the clock driver circuit can be switched according to the frequency of the clock signal, so that a suitable drive capability can be obtained according to the frequency of the clock. In addition, current consumption when the frequency of the clock signal is low can be reduced.

Further, since the timing for switching the clock signal and the timing for switching the driving capability of the clock driver circuit can be adjusted, it is possible to prevent the clock driver circuit from temporarily lacking the driving capability when switching the clock signal. Is done.

In particular, the present invention is particularly suitable as a basic clock generation circuit for a microcomputer.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a clock generation circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of the clock generation circuit according to the second embodiment of the present invention.

FIG. 5 is a diagram illustrating an application example of a clock generation circuit of the present invention to a microcomputer.

[Explanation of symbols]

Reference Signs List 10 oscillator 20 frequency divider 30 clock selection circuit 40 clock driver circuit 41 clocked inverter (first inverter) 42 inverter (second inverter) 100 clock generation circuit 101 peripheral circuit 102 internal circuit 103 CPU 104 ROM 110 clock line 200 microcomputer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/0175 H03K 19/00 101F F-term (Reference) 5B011 DC06 LL11 LL13 5B079 AA07 BA02 BA03 BC01 DD08 5J055 AX08 AX12 AX54 AX65 BX03 CX27 DX22 DX56 DX72 DX83 EX07 EX21 EY21 EZ00 EZ07 EZ28 EZ39 FX12 FX17 FX35 GX01 5J056 AA05 BB12 BB17 CC00 CC16 DD13 DD29 EE11 FF01 FF07 KK00

Claims (5)

[Claims] 1. A clock selection circuit for selectively outputting one of a plurality of clock signals having different frequencies according to a switching signal, and a clock signal selected by the clock selection circuit is applied. Along with
A clock driver circuit whose drive capability can be switched according to the switching signal. 2. A clock selection circuit for selectively outputting one of a plurality of clock signals having different frequencies according to a first switching signal, and a clock signal selected by the clock selection circuit And a clock driver circuit whose drive capability can be switched in response to a second switching signal, wherein the clock signal is selectively output based on the first and second switching signals. A clock generation circuit, wherein a timing and a timing for switching between the driving capabilities of the clock driver circuit can be adjusted. 3. The clock driver circuit includes a first inverter and a second inverter to which a clock signal selected by the clock selection circuit is applied, wherein the first inverter is connected to the second switching circuit. 3. The clock generation circuit according to claim 2, wherein the clock generation circuit is a clocked inverter whose output has a high impedance according to a signal. 4. A clock line for transmitting a clock signal output from the clock driver circuit, wherein the clock signal is built in the microcomputer on the clock line without intervening another clock driver circuit. 4. The clock generating circuit according to claim 3, wherein the clock is transmitted to the plurality of circuit blocks as a basic clock. 5. The clock generation circuit according to claim 3, wherein the first and second switching signals are generated by a command of a microcomputer.