JP2004129198A - Jitter generating circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a jitter generating circuit which adds exact jitter and reduce radiated noise effectively. <P>SOLUTION: The jitter generating circuit 3 is provided with an inverter circuit 6, a hysteresis inverter circuit 7, and a switching circuit 8 which selectively connects either of the inverter circuits 6, 7 to an output terminal 3c. Threshold voltage is changed by a connecting location of the switching circuit 8, and an output clock signal CLKOUT to which jitter is added is output from the output terminal 3c. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a jitter generation circuit that adds a jitter to a signal such as a clock signal and outputs the signal, and a semiconductor device including the jitter generation circuit.
[0002]
2. Description of the Related Art In recent years, higher integration and higher frequencies have been achieved in semiconductor devices (LSIs), and accordingly, generation of noise due to EMI (electromagnetic interference) has become a problem. As a countermeasure against the noise, an apparatus has been proposed in which a jitter (fluctuation in a time axis direction) is added to a clock signal for operating a CPU and its peripheral circuits to thereby disperse a noise peak. There is a demand for a technology that can realize a circuit for adding the jitter at low cost and can generate an accurate jitter according to the signal frequency.
[0003]
[Prior art]
2. Description of the Related Art It is known that a CPU and its peripheral circuits constituting a semiconductor device operate in synchronization with a clock signal and emit noise by a drive current during circuit operation. In particular, when a clock signal of a semiconductor device has a high frequency, radiated noise having a very large peak is generated at the frequency of the clock signal, which causes a problem of circuit malfunction due to the noise.
[0004]
Patent Literature 1 and Patent Literature 2 disclose techniques for modulating the phase of a clock signal, that is, giving jitter to the clock signal to reduce radiation noise due to a clock frequency spreading effect. I have.
[0005]
The device disclosed in Patent Document 1 includes a plurality of delay circuits connected in series, and a multiplexer connected to the output of each delay circuit via a tap. The clock signal input from each delay circuit to the multiplexer via a tap is a signal delayed in phase with respect to the reference phase. By controlling the multiplexer, any one of the phase-delayed signals is selectively provided. Is output to
[0006]
The device of Patent Document 2 includes a digital-to-analog converter (DAC), a voltage-controlled oscillator (VCO) that changes an oscillation frequency according to a change in the input of the DAC, and the like. The VCO includes an analog switch, and the impedance of the analog switch changes by changing the gate voltage of the analog switch by the DAC. As a result, jitter is added to the reference clock signal.
[0007]
Conventionally, a semiconductor device 71 as shown in FIG. 14 has been put to practical use. Specifically, in the semiconductor device 71, the clock signal CLK is input to the jitter generation circuit 72, and jitter is added to the clock signal CLK. Then, the jitter-added clock signal GCLK1 is supplied from the jitter generation circuit 72 to the CPU 73 and peripheral circuits (for example, a serial IO 74, a RAM 75, a counter 76, a timer 77, and a parallel IO 78).
[0008]
Further, Patent Literature 3 discloses a technique for reducing radiation noise by supplying a clock signal having a different duty ratio to each of a plurality of divided internal logic circuits in a semiconductor device.
[0009]
[Patent Document 1]
JP-A-7-202652
[Patent Document 2]
JP-A-9-98152
[Patent Document 3]
JP-A-11-110067
[0010]
[Problems to be solved by the invention]
Incidentally, a general semiconductor device is designed to be operable at different clock frequencies within a predetermined range. However, in the device of Patent Document 1, since a fixed delay time is set according to the delay circuit, if the clock frequency is changed, it is not possible to add an accurate jitter corresponding to the frequency. Further, the device requires a multiplexer and a circuit for controlling the multiplexer in addition to the delay circuit, so that the circuit logic becomes complicated. The device disclosed in Patent Document 2 also requires a DCO and a peripheral circuit (DAC) for changing the oscillation frequency thereof, thus causing a problem that the circuit scale is increased.
[0011]
In the semiconductor device 71 shown in FIG. 14, a clock signal GCLK to which jitter is added is supplied to the entire system such as the CPU 73 and peripheral circuits, and the system is operated based on the clock signal GCLK including uniform jitter. . In the semiconductor device 71, since a severe circuit (CPU 73, serial IO 74, etc.) is included in the timing, an optimum jitter for reducing radiation noise can be added to the clock signal CLK in consideration of a malfunction of the circuit. Can not.
[0012]
Further, in the case of supplying clock signals having different duty ratios as in the device of Patent Document 3, the range in which the EMI spectrum can be dispersed is narrow, and the effect of noise reduction cannot be sufficiently obtained.
[0013]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a jitter generation circuit and a semiconductor device capable of effectively reducing radiation noise by adding accurate jitter.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, the inversion timing of the output level is changed with respect to the timing of a fixed interval according to the cycle of the reference input signal by switching the threshold voltage of the circuit. You. As a result, an output signal obtained by adding jitter to the reference input signal is output. According to this configuration, it is possible to add jitter to the reference input signal with a simple circuit configuration as compared with the related art. When the frequency of the reference input signal changes, the jitter of the output signal changes according to the frequency of the reference input signal.
[0015]
According to the second aspect of the present invention, the switch circuit includes a hysteresis inverter circuit having hysteresis characteristics, an inverter circuit having no hysteresis characteristics, and a switch circuit provided between the output terminal and each inverter circuit. Thereby, the inverter circuit connected to the output terminal is switched. As a result, the threshold voltage is switched, and it becomes possible to generate jitter in the output signal.
[0016]
According to the third aspect of the present invention, the hysteresis inverter circuit includes a plurality of transistors. A transistor provided for providing hysteresis in the hysteresis inverter circuit is disconnected from the inverter circuit by a switch. As a result, the threshold voltage is switched, and it becomes possible to generate jitter in the output signal.
[0017]
According to the fourth aspect, a plurality of gate circuits having different threshold voltages are connected in parallel, and one of the gate circuits is selectively connected to the output terminal by the switch circuit. As a result, the threshold voltage is switched, and it becomes possible to generate jitter in the output signal.
[0018]
According to the fifth aspect of the present invention, an output signal to which jitter has been added is output by the jitter generation circuit, and the internal circuit is operated based on the output signal. Is reduced.
[0019]
According to the sixth and seventh aspects of the present invention, there are provided a jitter generation circuit for adding jitter to a clock signal, and first and second internal circuits. The first internal circuit whose operation timing is strict is supplied with a clock signal that is an input signal of the jitter generation circuit, that is, an accurate clock signal before adding jitter. Further, a clock signal to which jitter has been added by the jitter generation circuit is supplied to the second internal circuit having a margin for operation timing. In this case, the first internal circuit whose operation timing is strict can be operated at higher speed. Further, a large jitter can be added to the clock signal to the second internal circuit, which has a margin for the operation timing, and the radiation noise is effectively reduced. Therefore, it is possible to achieve both high-speed circuit operation and low radiation noise.
[0020]
According to the invention described in claim 8, the frequency division circuit divides the frequency of the first clock signal for operating the first internal circuit, and the frequency of the second clock signal having a lower frequency than that of the first clock signal is reduced. Generated. Then, the second clock signal is input to the jitter generation circuit, and jitter is added to the second clock signal. In this case, since the second clock signal has a lower frequency than the first clock signal, larger jitter can be added and radiation noise is effectively reduced.
[0021]
According to the ninth aspect of the present invention, a plurality of jitter generation circuits are provided, and the amount of jitter added to the clock signal is made different so that clock signals having different amounts of jitter can be selectively used according to the operation speed of the internal circuit. Becomes possible. By doing so, the ratio of the second internal circuit that operates based on the clock signal to which jitter has been added can be increased, and radiation noise can be more effectively reduced.
[0022]
According to the tenth aspect, since the amount of jitter added to the clock signal is adjusted according to the operation state of the internal circuit, radiation noise is reduced more effectively.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a first embodiment in which the present invention is embodied in a semiconductor device will be described with reference to the drawings.
[0024]
As shown in FIG. 1, the semiconductor device 1 includes a clock generation circuit 2, a jitter generation circuit 3, a selection signal generation circuit 4, and an internal circuit 5. The clock generation circuit 2 generates and outputs an input clock signal CLKIN as a reference input signal based on an oscillation signal from a crystal oscillator. In the present embodiment, the input clock signal CLKIN output from the clock generation circuit 2 changes in a substantially sinusoidal manner at a constant period T as shown in FIG.
[0025]
A jitter generation circuit 3 is provided between the clock generation circuit 2 and the internal circuit 5, and the jitter generation circuit 3 generates a jitter (fluctuation in the time axis direction) with respect to the input clock signal CLKIN from the clock generation circuit 2. ) To the internal circuit 5.
[0026]
The internal circuit 5 includes a well-known CPU 5a and its peripheral circuit 5b (for example, a RAM, a ROM, an input / output circuit, etc.), and operates based on an output clock signal CLKOUT from the jitter generation circuit 3.
[0027]
The selection signal generation circuit 4 includes a flip-flop circuit (not shown), generates a selection signal VTSEL based on an input clock signal CLKIN from the clock generation circuit 2, and outputs the selection signal VTSEL to the jitter generation circuit 3. As shown in FIG. 2, the voltage level of the selection signal VTSEL is H level or L level at a timing corresponding to the cycle T of the input clock signal CLKIN (specifically, at a timing when the level of the input clock signal CLKIN becomes the maximum value). Change to a level.
[0028]
The jitter generation circuit 3 of the present embodiment includes a normal inverter circuit 6 having no hysteresis characteristics, a hysteresis inverter circuit 7 having hysteresis characteristics, and a switch circuit 8. The jitter generation circuit 3 has a first input terminal 3a for inputting an input clock signal CLKIN from the clock generation circuit 2, a second input terminal 3b for inputting a selection signal VTSEL from the selection signal generation circuit 4, and an output clock signal. An output terminal 3c for outputting CLKOUT is provided.
[0029]
In the jitter generation circuit 3, an inverter circuit 6 and a hysteresis inverter circuit 7 are connected to a first input terminal 3a, and an input clock signal CLKIN is input to each of the inverter circuits 6 and 7. The inverter circuit 6 and the hysteresis inverter circuit 7 are connected to the output terminal 3c via the switch circuit 8.
[0030]
The threshold voltage of the hysteresis inverter circuit 7 (threshold voltage) is higher than the threshold voltage of the inverter circuit 6 when the output is switched from H level (first level) to L level (second level). When switching from the H level to the L level, the voltage is lower than the threshold voltage of the inverter circuit 6.
[0031]
In FIG. 2, the output of the inverter circuit 6 changes from H level to L level when the input clock signal CLKIN becomes higher than the voltage value VH1, and changes to L level when the input clock signal CLKIN becomes lower than the voltage value VL1. To H level. On the other hand, the output of the hysteresis inverter circuit 7 changes from H level to L level when the input clock signal CLKIN becomes higher than the voltage value VH2, and changes from L level when the input clock signal CLKIN becomes lower than the voltage value VL2. It changes to H level. The relationship between the voltage values is VH2>VH1>VL1> VL2.
[0032]
The switch circuit 8 connects either the inverter circuit 6 or the hysteresis inverter circuit 7 to the output terminal 3c according to the voltage level of the selection signal VTSEL. Specifically, the switch circuit 8 connects the inverter circuit 6 and the output terminal 3c when the selection signal VTSEL is at the H level, and connects the hysteresis inverter circuit 7 and the output terminal 3c when the selection signal VTSEL is at the L level. Connect.
[0033]
Therefore, in the jitter generation circuit 3, as shown in FIG. 2, the output clock signal CLKOUT changes to H level or L level according to the input clock signal CLKIN. Specifically, before time t1, the selection signal VTSEL is at the H level, and the inverter circuit 6 is connected to the output terminal 3c via the switch circuit 8. Therefore, at time t1 when the voltage level of input clock signal CLKIN becomes higher than voltage value VH1, output clock signal CLKOUT changes from H level to L level.
[0034]
Thereafter, the selection signal VTSEL becomes L level, and the hysteresis inverter circuit 7 is connected to the output terminal 3c via the switch circuit 8, so that the input clock signal CLKIN is output at time t2 when the voltage level becomes lower than the voltage value VL2. Clock signal CLKOUT changes from L level to H level. At the subsequent time t3, when the voltage level of input clock signal CLKIN becomes higher than voltage value VH2, output clock signal CLKOUT changes from H level to L level.
[0035]
Between time t3 and time t4, the selection signal VTSEL becomes H level, and the inverter circuit 6 is connected to the output terminal 3c via the switch circuit 8, so that the voltage level of the input clock signal CLKIN is higher than the voltage value VL1. At time t4 when the output clock signal CLKOUT becomes low, the output clock signal CLKOUT changes from the L level to the H level. At time t5, similarly to time t1, when the voltage level of input clock signal CLKIN is higher than voltage value VH1, output clock signal CLKOUT changes from H level to L level. At time t6, when the voltage level of input clock signal CLKIN becomes lower than voltage value VL2, output clock signal CLKOUT changes from L level to H level.
[0036]
That is, the output clock signal CLKOUT of the jitter generation circuit 3 becomes L level during the period T1 from time t1 to t2, and becomes H level during the period T2 from time t2 to t3. In addition, the level becomes L level during a period T3 between times t3 and t4, becomes H level during a period T4 between times t4 and t5, and becomes L level during a period T5 between times t5 and t6. The period T1 is longer than the period T2, and the period T2 is longer than the period T3 (T1>T2> T3). Further, the period T4 is equal to the period T2, and the period T5 is equal to the period T1.
[0037]
As described above, in the jitter generation circuit 3 of the present embodiment, the connection position of the switch circuit 8 is switched based on the selection signal VTSEL, and one of the inverter circuits 6 and 7 having different threshold voltages is connected to the output terminal 3c. Connected. As a result, the threshold voltage of the jitter generating circuit 3 is changed, and the inversion timing of the output level changes with respect to the timing at a fixed interval according to the cycle T of the input clock signal CLKIN. As a result, an output clock signal CLKOUT to which jitter has been added is output from the jitter generation circuit 3.
[0038]
As described above, according to the above embodiment, the following effects can be obtained.
(1) The jitter generation circuit 3 includes an inverter circuit 6, a hysteresis inverter circuit 7, and a switch circuit 8. In this case, jitter can be added with a simple circuit configuration as compared with the related art. Further, when the frequency of the input clock signal CLKIN is changed due to the application of the semiconductor device 1 or the like, the jitter of the output clock signal CLKOUT changes according to the frequency, and the ratio of the jitter to the input clock signal CLKIN is kept substantially constant. it can. Therefore, radiation noise of the semiconductor device 1 can be effectively reduced.
[0039]
(2) Since the jitter generation circuit 3 can be configured with a simple circuit, the manufacturing cost of the semiconductor device 1 can be reduced.
(3) The selection signal generation circuit 4 generates the selection signal VTSEL based on the input clock signal CLKIN from the clock generation circuit 2, and switches the connection position of the switch circuit 8 according to the selection signal VTSEL. This makes it possible to generate an accurate selection signal VTSEL according to the input clock signal CLKIN. Further, the selection signal generation circuit 4 has a relatively simple circuit configuration using a flip-flop circuit, and is therefore practically preferable.
[0040]
(2nd Embodiment)
Hereinafter, a second embodiment of the present invention will be described. The semiconductor device of the present embodiment includes a jitter generation circuit 11 shown in FIG. 3 instead of the jitter generation circuit 3 of the first embodiment. Note that the clock generation circuit 2, the selection signal generation circuit 4, and the internal circuit 5 constituting the semiconductor device are the same as those in the first embodiment, and thus detailed description thereof will be omitted.
[0041]
As shown in FIG. 3, the jitter generation circuit 11 has a first input terminal 11a for inputting an input clock signal CLKIN from the clock generation circuit 2, and a second input for inputting a selection signal VTSEL from the selection signal generation circuit 4. A terminal 11b and an output terminal 11c for outputting the output clock signal CLKOUT are provided.
[0042]
The jitter generation circuit 11 includes P-channel MOS transistors TP1 to TP4 and N-channel MOS transistors TN1 to TN4. In the jitter generation circuit 11, P-channel MOS transistors TP1 and TP2 and N-channel MOS transistors TN1 and TN2 are connected in series between a power supply Vcc and a ground GND. Each gate terminal of these transistors TP1, TP2, TN1, TN2 is connected to the first input terminal 11a, and the input clock signal CLKIN is input to each gate terminal. The connection between the transistors TP1 and TP2 is connected to ground GND via a P-channel MOS transistor TP3 and an N-channel MOS transistor TN4. The connection between the transistors TN1 and TN2 is connected to the power supply Vcc via an N-channel MOS transistor TN3 and a P-channel MOS transistor TP4.
[0043]
The gate terminal of the transistor TP3 is connected to the gate terminal of the transistor TN3, and the connection is connected between the transistor TP2 and the transistor TN1 and to the output terminal 11c. The gate terminals of the transistor TN4 and the transistor TP4 are connected to the second input terminal 11b, and the selection signal VTSEL generated by the selection signal generation circuit 4 is input to these gate terminals.
[0044]
In the jitter generation circuit 11, a circuit excluding the transistors TP3, TP4, TN3, and TN4, that is, a circuit including the transistors TP1, TP2, TN1, and TN2 functions as a normal inverter circuit. In the jitter generating circuit 11, when the transistor TN4 is omitted and the transistor TP3 is connected to the ground GND, and the transistor TP4 is omitted and the transistor TN3 is connected to the power supply Vcc, the circuit functions as a hysteresis inverter circuit. The transistor TP3 and the transistor TN3 are transistors for providing a hysteresis characteristic to the inverter circuit constituted by the transistors TP1, TP2, TN1, and TN2. The transistors TN4 and TP4 serve as switches for disconnecting the transistors TP3 and TN3 from the inverter circuit.
[0045]
In the jitter generation circuit 11, when the selection signal VTSEL is at the H level and the transistor TN4 is turned on, the threshold voltage for changing the output clock signal CLKOUT from the L level to the H level decreases. On the other hand, when the selection signal VTSEL is at the L level and the transistor TP4 is turned on, the threshold voltage for changing the output clock signal CLKOUT from the H level to the L level increases.
[0046]
More specifically, when an H-level selection signal VTSEL is input to the jitter generation circuit 11, the transistor TN4 turns on and the transistor TP4 turns off. In this state, when the voltage level of the input clock signal CLKIN is high and the output terminal 11c (the output clock signal CLKOUT) is at the L level, the transistor TP3 is turned on. Therefore, the threshold voltage for changing the output terminal 11c from the L level to the H level is lower than the threshold voltage of the inverter circuit including the transistors TP1, TP2, TN1, and TN2. When the voltage level of the input clock signal CLKIN is low and the output terminal 11c is at the H level, the transistor TP3 turns off. At this time, since the transistor TP4 is off, the power supply Vcc is not supplied to the transistor TN3, and the transistor TN3 is disconnected from the inverter circuit. Therefore, the threshold voltage for changing output terminal 11c from H level to L level is equal to the threshold voltage of the inverter circuit including transistors TP1, TP2, TN1, and TN2.
[0047]
On the other hand, when the L-level selection signal VTSEL is input to the jitter generation circuit 11, the transistor TN4 turns off and the transistor TP4 turns on. In this state, the threshold voltage for changing output terminal 11c from H level to L level is higher than the threshold voltage of the inverter circuit including transistors TP1, TP2, TN1, and TN2. The threshold voltage for changing output terminal 11c from the L level to the H level is equal to the threshold voltage of the inverter circuit including transistors TP1, TP2, TN1, and TN2.
[0048]
Accordingly, in the jitter generation circuit 11, as shown in FIG. 4, when the selection signal VTSEL is at the H level, when the input clock signal CLKIN becomes higher than the voltage value VH1 (time t11, t15), the output clock signal CLKOUT becomes It changes from H level to L level. When the selection signal VTSEL is at the H level and the input clock signal CLKIN becomes lower than the voltage value VL2 (time t14), the output clock signal CLKOUT changes from the L level to the H level.
[0049]
On the other hand, when the selection signal VTSEL is at the L level and the input clock signal CLKIN becomes higher than the voltage value VH2 (time t13), the output clock signal CLKOUT changes from the H level to the L level. Further, when the selection signal VTSEL is at the L level and the input clock signal CLKIN becomes lower than the voltage value VL1 (time t12, t16), the output clock signal CLKOUT changes from the L level to the H level.
[0050]
That is, the output clock signal CLKOUT of the jitter generation circuit 11 becomes L level during the period T11 from time t11 to t12, and becomes H level during the period T12 from time t12 to t13. In addition, the level becomes L level during a period T13 from time t13 to t14, becomes H level during a period T14 from time t14 to t15, and becomes L level during a period T15 from time t15 to t16. Here, the period T11 is equal to the period T13 and the period T15, and is shorter than the period T12 (T11 = T13 = T15 <T12). Further, the period T14 is also shorter than the period T11 (T11> T14).
[0051]
As described above, also in the jitter generation circuit 11 of the present embodiment, since the threshold voltage is changed in accordance with the selection signal VTSEL, the output level is changed with respect to the timing at a constant interval corresponding to the cycle T of the input clock signal CLKIN. Change timing. As a result, an output clock signal CLKOUT to which jitter has been added is output.
[0052]
As described above, according to the above embodiment, the following effects can be obtained.
(1) The jitter generation circuit 11 includes MOS transistors TP1 to TP4 and TN1 to TN4. In this case, jitter can be added with a simple circuit configuration as compared with the related art. Further, when the frequency of the input clock signal CLKIN is changed, the jitter of the output clock signal CLKOUT changes according to the frequency, so that the radiation noise of the semiconductor device 1 can be effectively reduced.
[0053]
The first and second embodiments can be modified as follows.
-Instead of the jitter generation circuits 3 and 11 of the first and second embodiments, a jitter generation circuit 21 shown in FIG. 5 or a jitter generation circuit 31 shown in FIG. 6 may be used.
[0054]
More specifically, the jitter generation circuit 21 of FIG. 5 includes a normal NAND circuit 22 having no hysteresis characteristics, a NAND circuit 23 having hysteresis characteristics, and an inverter circuit 24. The jitter generation circuit 21 includes a first input terminal 21a for inputting an input clock signal CLKIN, a second input terminal 21b for inputting a control signal CNTL, and an output terminal 21c for outputting an output clock signal CLKOUT. . The first input terminal 21a is connected to one input terminal of the NAND circuit 22 and the NAND circuit 23, and the second input terminal 21b is connected to the other input terminal of the NAND circuit 22 and via the inverter circuit 24 It is connected to the other input terminal of the NAND circuit 23. The NAND circuit 22 and the NAND circuit 23 are connected to the output terminal 21c.
[0055]
Also in the jitter generation circuit 21, the threshold voltage is changed according to the voltage level of the control signal CNTL as in the above embodiments, and the output clock signal CLKOUT to which jitter has been added can be output. .
[0056]
6 includes a first inverter circuit 32 including a P-channel MOS transistor TP5 and an N-channel MOS transistor TN5, a second inverter circuit 33 including a P-channel MOS transistor TP6 and an N-channel MOS transistor TN6, and a switch. The circuit 34 is provided. The jitter generation circuit 31 has a first input terminal 31a for inputting an input clock signal CLKIN from the clock generation circuit 2, a second input terminal 31b for inputting a selection signal VTSEL from the selection signal generation circuit 4, and an output terminal. An output terminal 31c for outputting a clock signal CLKOUT is provided. First and second inverter circuits 32 and 33 are connected to the first input terminal 31a, and each of the circuits 32 and 33 is connected to an output terminal 31c via a switch circuit 34. The switch circuit 34 connects one of the first and second inverter circuits 32 and 33 to the output terminal 31c according to the voltage level of the selection signal VTSEL.
[0057]
In the jitter generation circuit 31, the threshold voltage Vth1 of the first inverter circuit 32 is set to be lower than the threshold voltage Vth2 of the second inverter circuit 33. Specifically, in the first inverter circuit 32, the driving capability of the transistor TP5 is smaller than the driving capability of the transistor TN5, and in the second inverter circuit 33, the driving capability of the transistor TP6 is larger than the driving capability of the transistor TN6. I have. The driving capability of each of the transistors TP5, TP6, TN5, TN6 is adjusted by changing the gate length.
[0058]
Also in the jitter generation circuit 31, the threshold voltage is changed according to the voltage level of the selection signal VTSEL, as in the above embodiments, and the output clock signal CLKOUT to which jitter has been added can be output. .
[0059]
The jitter generating circuit 31 is a circuit in which two inverter circuits 32 and 33 having different threshold voltages are connected in parallel. However, a jitter generating circuit in which three or more inverter circuits having different threshold voltages are connected in parallel is used. You may comprise. Also in this case, a switch circuit is provided between the output terminal and each inverter circuit, and the switch circuit selectively connects any one of the inverter circuits to the output terminal.
[0060]
When the clock signal generated by the clock generation circuit 2 has a rectangular waveform, the CR circuit 41 including the capacitor C and the resistor R is connected to the clock generation circuit 2 and the jitter generation circuit 3, as shown in FIG. 11, 21 and 31. In this way, the clock signal CLK having a rectangular waveform passes through the CR circuit 41 and smoothly changes to a sine waveform. As a result, in the jitter generation circuits 3, 11, 21, and 31, it becomes possible to add appropriate jitter according to the clock signal CLK.
[0061]
In the above embodiments, the present invention is applied to a clock signal for operating the internal circuit 5 (the CPU 5a and its peripheral circuit 5b). However, the present invention is applied to, for example, a synchronization signal used in data communication. May be.
[0062]
(Third embodiment)
FIG. 8 is a configuration diagram illustrating a semiconductor device 51 according to the third embodiment.
The semiconductor device 51 includes a jitter generation circuit 52, a CPU 53, a serial interface (serial IO) 54, a RAM 55, a counter 56, a timer 57, and a parallel interface (parallel IO) 58.
[0063]
Among the circuits included in the semiconductor device 51, the CPU 53, the serial IO 54, and the RAM 55 are circuits (first internal circuits) with strict operation timing, and the counter 56, the timer 57, and the parallel IO 58 have relatively margin for operation timing. (A second internal circuit).
[0064]
In the semiconductor device 51, an external clock signal CLK is input to the jitter generation circuit 52, the CPU 53, the serial IO 54, and the RAM 55. The jitter generation circuit 52 adds a jitter to the clock signal CLK, and supplies the clock signal GCLK with the jitter added to the counter 56, the timer 57, and the parallel IO 58. As the jitter generation circuit 52, the jitter generation circuits 3, 11, 21, 31 of the above embodiments may be used, or a general jitter generation circuit may be used.
[0065]
In the semiconductor device 51, a clock signal serving as an input signal of the jitter generation circuit, that is, an accurate clock signal CLK without adding jitter is supplied to the first internal circuit (CPU 53, serial IO 54, RAM 55) whose operation timing is strict. Each circuit 53, 54, 55 can be operated at high speed.
[0066]
Further, the clock signal GCLK to which the jitter has been added by the jitter generation circuit 52 is supplied to the second internal circuit (the counter 56, the timer 57, and the parallel IO 58) having an operation timing margin. When the entire system is operated by the clock signal GCLK to which jitter is added as in the conventional semiconductor device 71 shown in FIG. 14, the amount of jitter that can be added to the clock signal CLK is set only within a relatively narrow range. I can't. On the other hand, in the present embodiment, the clock signal GCLK to which jitter is added is supplied only to the circuit having an operation timing margin, so that a larger jitter can be added to the clock signal GCLK. Radiation noise can be effectively reduced.
[0067]
As described above, in the semiconductor device 51 of the present embodiment, it is possible to achieve both high-speed circuit operation and low radiation noise.
(Fourth embodiment)
FIG. 9 is a configuration diagram illustrating a semiconductor device 61 according to the fourth embodiment. In the present embodiment, the same components as those in the third embodiment are denoted by the same reference numerals in the drawings. The following description focuses on differences from the third embodiment.
[0068]
That is, the semiconductor device 61 includes frequency dividing circuits 62 and 63 in addition to the circuits (jitter generating circuit 52, CPU 53, serial IO 54, RAM 55, counter 56, timer 57, parallel IO 58) of the third embodiment.
[0069]
In the semiconductor device 61, an external clock signal CLK is input to a frequency dividing circuit 62. The frequency dividing circuit 62 divides the frequency of the clock signal CLK by a predetermined frequency division ratio and outputs a clock signal CLK1 having a lower frequency than the clock signal CLK. The clock signal CLK1 output from the frequency dividing circuit 62 is input to the jitter generating circuit 52. The jitter generation circuit 52 adds jitter to the clock signal CLK1 from the frequency dividing circuit 62 and supplies the clock signal GCLK1 to the counter 56, the timer 57, and the frequency dividing circuit 63.
[0070]
The frequency dividing circuit 63 divides the frequency of the clock signal GCLK1 by a predetermined frequency dividing ratio and outputs a clock signal GCLK2 having a lower frequency than the clock signal GCLK1. The clock signal GCLK2 is input to the parallel IO 58.
[0071]
The CPU 53, the serial IO 54, and the RAM 55 in the semiconductor device 61 operate at high speed based on a clock signal CLK input from the outside. The counter 56 and the timer 57 operate at a low speed based on the clock signal GCLK1 to which the jitter is added. Further, the parallel IO 58 operates at a lower speed than the counter 56 and the timer 57 based on the clock signal GCLK2.
[0072]
That is, in the present embodiment, the second internal circuit (the counter 56, the timer 57, and the parallel IO 58) is a circuit whose operation speed is lower than that of the first internal circuit (the CPU 53, the serial IO 54, and the RAM 55). Jitter is added to the clock signals GCLK1 and GCLK2 for operation. In this case, since the clock signals GCLK1 and GCLK2 have a lower frequency than the clock signal CLK, larger jitter can be added. Therefore, radiation noise of the semiconductor device 61 can be effectively reduced.
[0073]
(Fifth embodiment)
FIG. 10 is a configuration diagram illustrating a semiconductor device 65 according to the fifth embodiment. In the figure, the same components as those of the above-described fourth embodiment are denoted by the same reference numerals. The following description focuses on the differences from the fourth embodiment.
[0074]
The semiconductor device 65 of this embodiment includes two jitter generation circuits 52 and 66, and is configured to vary the amount of jitter added to a clock signal according to the operation speed of an internal circuit.
[0075]
Specifically, in the semiconductor device 65, the clock signal CLK1 output from the frequency dividing circuit 62 is input to the frequency dividing circuit 63. The frequency dividing circuit 63 divides the frequency of the clock signal CLK1 by a predetermined frequency division ratio and outputs a clock signal CLK2 having a lower frequency than the clock signal CLK1.
[0076]
The jitter generating circuit 52 adds jitter to the clock signal CLK1 from the frequency dividing circuit 62 and supplies the clock signal GCLK1 to the counter 56 and the timer 57. On the other hand, the jitter generating circuit 66 adds a jitter to the clock signal CLK2 from the frequency dividing circuit 63 and supplies the clock signal GCLK2 to the parallel IO. Here, the jitter generation circuit 66 adds a larger jitter than the jitter generation circuit 52.
[0077]
According to the semiconductor device 65, it is possible to add accurate jitter corresponding to the operation speed of the internal circuit to the clock signals CLK1 and CLK2. Further, in this case, it is possible to increase the ratio of internal circuits that operate based on the clock signals GCLK1 and GCLK2 to which jitter has been added. Therefore, radiation noise of the semiconductor device 65 can be reduced more effectively.
[0078]
Each of the above embodiments can be modified as follows.
The jitter generation circuits 52, 66 of the semiconductor devices 51, 61, 65 may have a function of adjusting the amount of jitter according to the operation state of the internal circuit.
[0079]
Specifically, a case where the jitter generating circuit 52 of the third embodiment is provided with a function of adjusting the amount of jitter will be described below.
As shown in FIG. 11, the jitter generation circuit 52 in the semiconductor device 51a includes a first generation unit 52a and a second generation unit 52b, and based on a mode signal MODE output from the CPU 53, each of the generation units 52a and 52b Is activated. In the jitter generation circuit 52, when the first generation section 52a is activated, a small jitter is added to the clock signal CLK, and when the second generation section 52b is activated, a large jitter is added to the clock signal CLK. It has become.
[0080]
The operation modes of the semiconductor device 51a include various operation modes such as a test mode, a sleep mode, a high-speed operation mode, and a low-speed operation mode. The CPU 53 determines the current operation mode and outputs a mode signal MODE according to the operation mode. For example, when the operation mode of the semiconductor device 51a shifts from the high-speed operation mode to the low-speed operation mode, the mode signal MODE output from the CPU 53 is inverted from H level to L level. Then, based on the mode signal MODE, the first generator 52a of the jitter generator 52 is deactivated and the second generator 52b is activated. As a result, a large jitter is added to the clock signal CLK.
[0081]
As described above, by adjusting the amount of jitter according to the operation state of the semiconductor device 51a, the radiation noise of the semiconductor device 51a can be effectively reduced. Further, when the semiconductor device 51a is tested, the test can be easily performed by switching the amount of jitter based on the test mode signal.
[0082]
As in the semiconductor device 51b shown in FIG. 12, the jitter amount may be adjusted according to the power supply voltage. That is, the semiconductor device 51b is provided with a power supply voltage monitoring circuit 59 for monitoring the power supply voltage supplied to each circuit such as the CPU 53, and a control signal CON corresponding to the power supply voltage level is output from the power supply voltage monitoring circuit 59. Is output. One of the generators 52a and 52b is activated based on the control signal CON.
[0083]
For example, when the power supply voltage falls below a predetermined value, control signal CON is inverted from L level to H level. Then, based on the control signal CON, the first generator 52a of the jitter generator 52 is activated and the second generator 52b is deactivated. As a result, a small jitter is added to the clock signal CLK. That is, when the semiconductor device 51b operates in the low voltage state, the amount of jitter added to the clock signal CLK is reduced, and when the semiconductor device 51b operates in the high voltage state, the amount of jitter added to the clock signal CLK is increased. .
[0084]
When the semiconductor device 51b is in a low voltage state, radiation noise is reduced, and the operating speed margin of the circuit is reduced. Therefore, a circuit malfunction can be prevented by reducing the amount of jitter. On the other hand, when the semiconductor device 51b is in the high voltage state, the radiation noise increases, and the operating speed margin of the circuit increases. Therefore, by increasing the amount of jitter, radiation noise can be effectively reduced.
[0085]
Further, in the semiconductor devices 51a and 51b, a detection circuit for detecting the frequency of the clock signal CLK may be provided, and the jitter amount may be adjusted based on the detection result. Further, in the semiconductor devices 51a and 51b, the jitter amount may be adjusted based on information on the power supply voltage acquired by the CPU 53 and the like.
[0086]
The jitter generation circuit 52 of the semiconductor devices 51a and 51b includes two generation units 52a and 52b and switches the amount of jitter added to the clock signal CLK in two stages. A configuration may be provided in which the amount of jitter is switched in multiple stages. Further, a jitter generation circuit that can adjust an arbitrary amount of jitter according to a setting signal input from the outside has been put to practical use. When the jitter generation circuit is used, the amount of jitter may be adjusted by a setting signal corresponding to each operation mode.
[0087]
The semiconductor device 65 of the fifth embodiment includes two jitter generation circuits 52 and 66, and each of the jitter generation circuits 52 and 66 applies different jitters to accurate clock signals CLK1 and CLK2 to which no jitter is added. This is a configuration to be added, but is not limited to this. For example, as in a semiconductor device 65a shown in FIG. 13, the second jitter generation circuit 66a may further add jitter to a clock signal to which the first jitter generation circuit 52 has added jitter. That is, the second jitter generating circuit 66a in the semiconductor device 65a functions as a jitter increasing circuit that increases the amount of jitter of the clock signal.
[0088]
According to the semiconductor device 65a, the circuit size of the second jitter generating circuit 66a can be reduced as compared with the semiconductor device 65 that independently generates jitter. Further, the amount of jitter of the clock signal GCLK1 for operating the counter 56 and the timer 57 and the amount of jitter of the clock signal GCLK2 for operating the parallel IO 58 can be reliably made different.
[0089]
In the semiconductor devices 65 and 65a, two jitter generating circuits 52 and 66 are provided, but three or more jitter generating circuits may be provided.
The above various embodiments are summarized as follows.
(Supplementary Note 1) A jitter generation circuit that inputs a reference input signal whose voltage level changes at a constant cycle, adds jitter to the reference input signal, and outputs the signal.
A circuit for changing an output to a first level or a second level in accordance with the reference input signal, wherein the circuit is formed so as to be capable of switching a threshold voltage, and by switching the threshold voltage, jitter is reduced. A jitter generation circuit for outputting an added output signal.
(Supplementary Note 2) A hysteresis inverter circuit having hysteresis characteristics,
An inverter circuit without hysteresis characteristics;
A switch circuit provided between an output terminal for outputting the output signal and each of the inverter circuits;
2. The jitter generation circuit according to claim 1, further comprising: switching an inverter circuit connected to the output terminal by the switch circuit.
(Supplementary Note 3) A hysteresis inverter circuit including a plurality of transistors;
A switch for disconnecting a transistor provided for providing hysteresis in the hysteresis inverter circuit from the inverter circuit;
2. The jitter generation circuit according to claim 1, further comprising:
(Supplementary Note 4) A plurality of gate circuits having different threshold voltages are connected in parallel,
A switch circuit provided between an output terminal for outputting the output signal and each of the gate circuits selectively connects any one of the gate circuits to the output terminal. 3. The jitter generation circuit according to claim 1, wherein
(Supplementary Note 5) A semiconductor device comprising: the jitter generation circuit according to any one of Supplementary notes 1 to 4; and an internal circuit that operates based on an output signal output from the jitter generation circuit.
(Supplementary Note 6) A clock generation circuit that generates a clock signal as the reference input signal, and a clock signal that is provided between the clock generation circuit and the jitter generation circuit and that changes the clock signal that changes in a rectangular waveform into a sine waveform. 6. The semiconductor device according to supplementary note 5, comprising:
(Supplementary Note 7) A clock generation circuit that generates a clock signal as the reference input signal, and a selection signal generation circuit that generates a selection signal based on the reference input signal generated by the clock signal generation circuit, The semiconductor device according to claim 5, wherein the threshold voltage is switched by a selection signal.
(Supplementary Note 8) The jitter generation circuit according to any one of Supplementary Notes 1 to 4,
A first internal circuit to which a clock signal serving as an input signal to the jitter generation circuit is supplied;
A second internal circuit to which a clock signal to which jitter is added in the jitter generation circuit is supplied, wherein the second internal circuit has a margin of operation timing more than the first internal circuit;
A semiconductor device comprising:
(Supplementary Note 9) A jitter generation circuit that inputs a clock signal, adds jitter to the clock signal, and outputs the jitter signal.
A first internal circuit to which a clock signal serving as an input signal to the jitter generation circuit is supplied;
A second internal circuit to which a clock signal to which jitter is added in the jitter generation circuit is supplied, wherein the second internal circuit has a margin of operation timing more than the first internal circuit;
A semiconductor device comprising:
(Supplementary Note 10) The frequency of the first clock signal for operating the first internal circuit is divided, a second clock signal having a lower frequency than the first clock signal is generated, and the second clock signal is input to the jitter generation circuit. 10. The semiconductor device according to supplementary note 8 or 9, further comprising a peripheral circuit.
(Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 8 to 10, wherein a plurality of the jitter generation circuits are provided, and the amount of jitter added to a clock signal is varied in each of the jitter generation circuits.
(Supplementary note 12) The semiconductor device according to any one of Supplementary notes 8 to 11, wherein the jitter generation circuit has a function of adjusting an amount of jitter added to a clock signal according to an operation state of an internal circuit.
(Supplementary note 13) The semiconductor device according to supplementary note 12, wherein the amount of jitter of the jitter generation circuit is adjusted according to a power supply voltage to the internal circuit.
(Supplementary note 14) The semiconductor device according to supplementary note 12, wherein a jitter amount of the jitter generating circuit is adjusted according to an operation speed of the internal circuit.
(Supplementary Note 15) A supplementary note 11 characterized by comprising a first jitter generating circuit for adding jitter to the clock signal, and a second jitter generating circuit for further adding jitter to the clock signal to which the jitter is added. 3. The semiconductor device according to claim 1.
(Supplementary Note 16) A first jitter generating circuit, and a second jitter generating circuit to which a clock signal having a lower frequency than the first jitter generating circuit is input, wherein the second jitter generating circuit includes the first jitter generating circuit. 12. The semiconductor device according to supplementary note 11, wherein a jitter larger than that of the circuit is added.
[0090]
【The invention's effect】
As described in detail above, according to the present invention, radiation noise of a semiconductor device can be effectively reduced by adding accurate jitter.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a semiconductor device according to a first embodiment.
FIG. 2 is an operation waveform diagram of the jitter generation circuit of the embodiment.
FIG. 3 is a circuit diagram illustrating a jitter generation circuit according to a second embodiment.
FIG. 4 is an operation waveform diagram of the jitter generation circuit of the embodiment.
FIG. 5 is a circuit diagram showing another example of a jitter generation circuit.
FIG. 6 is a circuit diagram showing another example of a jitter generation circuit.
FIG. 7 is a circuit diagram showing a CR circuit.
FIG. 8 is a configuration diagram illustrating a semiconductor device according to a third embodiment.
FIG. 9 is a configuration diagram illustrating a semiconductor device according to a fourth embodiment.
FIG. 10 is a configuration diagram illustrating a semiconductor device according to a fifth embodiment.
FIG. 11 is a configuration diagram illustrating another example of a semiconductor device.
FIG. 12 is a configuration diagram illustrating another example of a semiconductor device.
FIG. 13 is a configuration diagram illustrating another example of a semiconductor device.
FIG. 14 is a configuration diagram showing a conventional semiconductor device.
[Explanation of symbols]
1,51,51a, 51b, 61,65,65a Semiconductor device
3,11,21,31,52,66,66a Jitter generation circuit
3c, 11c, 21c, 31c output terminal
5 Internal circuit
6. Inverter circuit as gate circuit
7. Hysteresis inverter circuit as gate circuit
8 Switch circuit
22, 23 NAND circuit as gate circuit
32,33 Inverter circuit as gate circuit
34 switch circuit
62, 63 frequency divider circuit
CLK, CLK1, CLK2 clock signal
CLKIN Input clock signal as reference input signal
CLKOUT Output clock signal as output signal
GCLK, GCLK1, GCLK2 clock signal
TN1 to TN4 N-channel MOS transistors
TP1 to TP4 P-channel MOS transistor

Claims (10)

A jitter generation circuit that inputs a reference input signal whose voltage level changes at a constant cycle, adds jitter to the reference input signal, and outputs the signal.
A circuit for changing an output to a first level or a second level in accordance with the reference input signal, wherein the circuit is formed so as to be capable of switching a threshold voltage, and by switching the threshold voltage, jitter is reduced. A jitter generation circuit for outputting an added output signal. A hysteresis inverter circuit having hysteresis characteristics,
An inverter circuit without hysteresis characteristics;
A switch circuit provided between an output terminal for outputting the output signal and each of the inverter circuits, wherein an inverter circuit connected to the output terminal is switched by the switch circuit. 2. The jitter generation circuit according to 1. A hysteresis inverter circuit composed of a plurality of transistors;
2. The jitter generation circuit according to claim 1, further comprising a switch for disconnecting a transistor provided for providing the hysteresis in the hysteresis inverter circuit from the inverter circuit. Connect multiple gate circuits with different threshold voltages in parallel,
A switch circuit provided between an output terminal for outputting the output signal and each of the gate circuits selectively connects any one of the gate circuits to the output terminal. The jitter generation circuit according to claim 1. A semiconductor device comprising: the jitter generation circuit according to claim 1; and an internal circuit that operates based on an output signal output from the jitter generation circuit. A jitter generation circuit according to any one of claims 1 to 4,
A first internal circuit to which a clock signal serving as an input signal to the jitter generation circuit is supplied;
A semiconductor device, comprising: a circuit having more operation timing margin than the first internal circuit; and a second internal circuit to which a clock signal to which jitter is added in the jitter generation circuit is supplied. A jitter generation circuit that inputs a clock signal, adds jitter to the clock signal, and outputs the jitter signal;
A first internal circuit to which a clock signal serving as an input signal to the jitter generation circuit is supplied;
A semiconductor device, comprising: a circuit having more operation timing margin than the first internal circuit; and a second internal circuit to which a clock signal to which jitter is added in the jitter generation circuit is supplied. A frequency divider that divides a first clock signal for operating the first internal circuit, generates a second clock signal having a lower frequency than the first clock signal, and inputs the second clock signal to the jitter generation circuit; The semiconductor device according to claim 6, wherein: 9. The semiconductor device according to claim 6, wherein a plurality of said jitter generation circuits are provided, and the amount of jitter added to a clock signal in each of said jitter generation circuits is made different. 10. The semiconductor device according to claim 6, wherein said jitter generation circuit has a function of adjusting an amount of jitter added to a clock signal according to an operation state of an internal circuit.

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