JP2002217327A - Package for containing semiconductor element and its manufacturing method - Google Patents

Package for containing semiconductor element and its manufacturing method

Info

Publication number
JP2002217327A
JP2002217327A JP2001008916A JP2001008916A JP2002217327A JP 2002217327 A JP2002217327 A JP 2002217327A JP 2001008916 A JP2001008916 A JP 2001008916A JP 2001008916 A JP2001008916 A JP 2001008916A JP 2002217327 A JP2002217327 A JP 2002217327A
Authority
JP
Japan
Prior art keywords
hole
semiconductor element
conductor
thermosetting resin
grounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001008916A
Other languages
Japanese (ja)
Inventor
Kenichi Omura
健一 大村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001008916A priority Critical patent/JP2002217327A/en
Publication of JP2002217327A publication Critical patent/JP2002217327A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a package for containing a semiconductor element in which thermosetting resin does not adhere unnecessarily to a wiring conductor and the electrode of a semiconductor element can be electrically connected with the wiring conductor surely and rigidly. SOLUTION: The package for containing a semiconductor element comprises an insulating plate 4 having a substantially square central through hole 4a for containing a semiconductor element, a plurality of wiring conductors 5 formed from the periphery of the through hole 4a in the upper surface of the insulating plate 4 to the outer circumferential part, an earth or power supply conductor 6 formed substantially entirely on the lower surface of the insulating plate 4, an insulation layer 12 of thermosetting resin formed on the lower surface of the earth or power supply conductor 6, and a metallic heat dissipation plate 2 bonded to the lower surface of the insulation layer 12 through a bonding layer 15 to close the through hole 4a wherein the insulation layer 12 has inner edge spaced apart by 0.05-2 mm from the opening of the through hole 4a to the outer circumferential side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体集積回路素
子等の半導体素子を収容するための半導体素子収納用パ
ッケージおよびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for accommodating a semiconductor device such as a semiconductor integrated circuit device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、MPU等の半導体素子を収容する
ための半導体素子収納用パッケージは、例えば図4に断
面図で示すように、中央部に半導体素子20を収容するた
めの段状の貫通穴21aを有する配線基板21と、この配線
基板21の下面に貫通穴21aを塞ぐように接合層23を介し
て接合され、上面中央部に半導体素子20が搭載される搭
載部22aを有する銅等の金属材料から成る放熱板22とか
ら主に構成されている。
2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element such as an MPU has a stepped through hole for accommodating a semiconductor element 20 at a central portion as shown in a sectional view of FIG. A wiring board 21 having a hole 21a, and a lower surface of the wiring board 21 which is bonded to the lower surface of the wiring board 21 via a bonding layer 23 so as to cover the through hole 21a, and which has a mounting portion 22a in the center of the upper surface where the semiconductor element 20 is mounted. And a radiator plate 22 made of a metallic material.

【0003】この従来の半導体素子収納用パッケージに
おいては、配線基板21は、例えばガラスクロスにエポキ
シ樹脂等の熱硬化性樹脂を含浸させて成る二枚の絶縁板
24・25を同じくガラスクロスにエポキシ樹脂等の熱硬化
性樹脂を含浸させて成る接着層26を介して積層して成
り、絶縁板24には、その中央部に半導体素子20よりも若
干大きな貫通穴24aが形成されているとともにその上面
の貫通穴24a周辺から外周部にかけて複数の配線導体27
およびその下面の略全面に接地または電源用導体28が被
着されており、絶縁板25には、その中央部に貫通穴24a
よりも大きな貫通穴25aが形成されているとともに上面
に外部接続用導体29が被着されている。そして、これら
の絶縁板24・25および接着層26の外周部には、複数の貫
通孔30が設けられており、貫通孔30の内壁には配線導体
27や接地または電源用導体28と外部接続用導体29とを電
気的に接続する貫通導体31が被着されている。さらに、
接地または電源用導体28の下面には配線基板21と放熱板
22との接合を強固なものとするためにエポキシ樹脂から
成る絶縁層32が被着されており、この絶縁層32に放熱板
22がガラスクロスにエポキシ樹脂等の熱硬化性樹脂を含
浸させて成る接合層23を介して接合されている。
In this conventional package for housing a semiconductor element, the wiring board 21 is made of two insulating plates made of glass cloth impregnated with a thermosetting resin such as an epoxy resin.
24 and 25 are also laminated via an adhesive layer 26 made of glass cloth impregnated with a thermosetting resin such as an epoxy resin. A hole 24a is formed and a plurality of wiring conductors 27 extend from the periphery of the through hole 24a on the upper surface to the outer peripheral portion.
A grounding or power supply conductor 28 is attached to substantially the entire lower surface thereof, and the insulating plate 25 has a through hole 24a at the center thereof.
A larger through hole 25a is formed, and an external connection conductor 29 is attached to the upper surface. A plurality of through holes 30 are provided in the outer peripheral portions of the insulating plates 24 and 25 and the adhesive layer 26.
27 and a through conductor 31 for electrically connecting the grounding or power supply conductor 28 to the external connection conductor 29 are provided. further,
The wiring board 21 and the heat sink
An insulating layer 32 made of epoxy resin is adhered to make the connection with the bonding layer 22 strong.
22 is joined via a joining layer 23 made of glass cloth impregnated with a thermosetting resin such as an epoxy resin.

【0004】そして、この従来の半導体素子収納用パッ
ケージによれば、放熱板22の搭載部22aに半導体素子20
を搭載するとともにこの半導体素子20の各電極を配線導
体27にボンディングワイヤ33等の電気的接続手段を介し
て電気的に接続し、しかる後、外部接続用導体29に半田
ボール等から成る外部接続用部材34を接合するとともに
貫通穴21a内へ図示しない封止用樹脂をポッティングし
て半導体素子20を気密に封止することにより製品として
の半導体装置となる。
According to this conventional semiconductor device housing package, the semiconductor device 20 is mounted on the mounting portion 22a of the heat sink 22.
And electrically connecting each electrode of the semiconductor element 20 to the wiring conductor 27 via an electrical connection means such as a bonding wire 33, and then externally connecting the external connection conductor 29 with a solder ball or the like. The semiconductor element 20 is hermetically sealed by joining the sealing member 34 and potting a sealing resin (not shown) into the through hole 21a to hermetically seal the semiconductor element 20.

【0005】なお、このような半導体素子収納用パッケ
ージの配線基板21は、次に述べる方法により製作されて
いた。
The wiring board 21 of such a package for housing semiconductor elements has been manufactured by the following method.

【0006】先ず、図5(a)に断面図で示すように、
上面に配線導体27用の金属層27Aが被着され、下面の全
面に接地または電源用導体28用の金属層28Aが被着され
た絶縁板24Aと、上面に外部接続用導体29用の金属層29
Aが被着され、中央部に貫通穴25aを有する絶縁板25A
と、中央部に貫通穴25aと実質的に同じ大きさの貫通穴
を有する接着層26Aとを準備する。
First, as shown in a sectional view of FIG.
An insulating plate 24A having a metal layer 27A for the wiring conductor 27 attached on the upper surface and a metal layer 28A for the grounding or power supply conductor 28 on the entire lower surface, and a metal for the external connection conductor 29 on the upper surface. Tier 29
A is attached and an insulating plate 25A having a through hole 25a in the center.
And an adhesive layer 26A having a through hole substantially the same size as the through hole 25a at the center.

【0007】このとき、絶縁板24A・25Aは、ガラスク
ロスにエポキシ樹脂等の熱硬化性樹脂を含浸させて成
り、その熱硬化性樹脂は熱硬化されている。また、金属
層27A・28A・29Aは所定のパターンにエッチング加工
されており、絶縁板24A・25Aに含有される熱硬化性樹
脂により絶縁板24A・25Aに固着されている。他方、接
着層26Aは、ガラスクロスにエポキシ樹脂等の熱硬化性
樹脂を含浸させて成り、その熱硬化性樹脂は未硬化の状
態である。
At this time, the insulating plates 24A and 25A are formed by impregnating a glass cloth with a thermosetting resin such as an epoxy resin, and the thermosetting resin is thermoset. The metal layers 27A, 28A, 29A are etched into a predetermined pattern, and are fixed to the insulating plates 24A, 25A by a thermosetting resin contained in the insulating plates 24A, 25A. On the other hand, the adhesive layer 26A is formed by impregnating a glass cloth with a thermosetting resin such as an epoxy resin, and the thermosetting resin is in an uncured state.

【0008】次に、図5(b)に断面図で示すように、
絶縁板24Aと25Aとを間に接着層26Aを挟んで積層する
とともに接着層26Aの熱硬化性樹脂を熱硬化させて、絶
縁板24Aと25Aとが接着層26Aにより接合された配線基
板21用の積層体21Aを得る。
Next, as shown in the sectional view of FIG.
The insulating plates 24A and 25A are laminated with the adhesive layer 26A interposed therebetween, and the thermosetting resin of the adhesive layer 26A is thermoset, so that the insulating plates 24A and 25A are joined by the adhesive layer 26A. Is obtained.

【0009】次に、図5(c)に断面図で示すように、
積層体21Aの中央部に半導体素子を収容するための貫通
穴24aおよび外周部に複数の貫通孔30を切削加工により
形成するとともに貫通孔30内壁に無電解めっきおよび電
解めっき法により貫通導体31を被着形成し、外部接続用
導体29とこれに対応する配線導体27および接地または電
源用導体28とをそれぞれ電気的に接続する。
Next, as shown in the sectional view of FIG.
A through hole 24a for accommodating a semiconductor element in the center of the laminate 21A and a plurality of through holes 30 in the outer peripheral portion are formed by cutting, and a through conductor 31 is formed on the inner wall of the through hole 30 by electroless plating and electrolytic plating. The external connection conductor 29 is electrically connected to the wiring conductor 27 and the grounding or power supply conductor 28 corresponding thereto.

【0010】最後に、図5(d)に断面図で示すよう
に、接地または電源用導体28が被着された絶縁板24の下
面の全面に絶縁層32用の未硬化の熱硬化性樹脂ペースト
を塗布するとともにこれを熱硬化させて配線基板21を得
る。
Finally, as shown in the sectional view of FIG. 5D, an uncured thermosetting resin for the insulating layer 32 is formed on the entire lower surface of the insulating plate 24 on which the grounding or power supply conductor 28 is attached. The wiring board 21 is obtained by applying the paste and thermally curing the paste.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージによると、貫通穴24a
が形成された絶縁板24の、接地または電源用導体28が被
着された下面全面に絶縁層32が被着形成されていること
から、この絶縁層32用の未硬化の熱硬化性樹脂を熱硬化
させる際に、絶縁層32用の熱硬化性樹脂の一部が硬化時
の流動化により貫通穴24aの内壁を毛管現象により伝っ
て配線導体27の上面まで達することがあり、そのように
配線導体27の上面に熱硬化性樹脂が付着した場合、半導
体素子20の各電極を配線導体27にボンディングワイヤ33
等の電気的接続手段を介して電気的に確実に接続するこ
とができなくなってしまうという問題点を有していた。
なお、貫通穴24aの内壁は、切削加工により形成されて
おり、そのため表面粗さが粗いことから流動化した樹脂
が毛管現象により伝いやすい状態となっている。
However, according to this conventional package for housing a semiconductor element, the through hole 24a
Since the insulating layer 32 is formed on the entire lower surface of the insulating plate 24 on which the grounding or power supply conductor 28 is formed, the uncured thermosetting resin for the insulating layer 32 is used. At the time of thermosetting, a part of the thermosetting resin for the insulating layer 32 may reach the upper surface of the wiring conductor 27 by flowing through the inner wall of the through hole 24a by capillary action due to fluidization at the time of hardening. When the thermosetting resin adheres to the upper surface of the wiring conductor 27, each electrode of the semiconductor element 20 is connected to the wiring conductor 27 by a bonding wire 33.
However, there is a problem that it is not possible to reliably connect electrically via the electrical connection means such as the above.
The inner wall of the through hole 24a is formed by cutting, and the surface roughness is so rough that the fluidized resin is easily transmitted by capillary action.

【0012】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、配線導体の表面に不要
な熱硬化性樹脂が付着するようなことがなく、半導体素
子の各電極を対応する配線導体に電気的に確実に接続す
ることができる半導体素子収納用パッケージおよびその
製造方法を提供することにある。
The present invention has been devised in view of such a conventional problem, and an object of the present invention is to prevent unnecessary thermosetting resin from adhering to the surface of a wiring conductor, and to provide a semiconductor device having various components. An object of the present invention is to provide a package for housing a semiconductor element and a method of manufacturing the same, which can reliably and electrically connect electrodes to corresponding wiring conductors.

【0013】[0013]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、中央部に半導体素子収納用の略四角形
の貫通穴を有する絶縁板と、この絶縁板の上面の貫通穴
周辺から外周部にかけて被着された複数の配線導体と、
この絶縁板の下面の略全面に被着された接地または電源
用導体と、この接地または電源用導体の下面に被着され
た熱硬化性樹脂から成る絶縁層と、この絶縁層の下面に
半導体素子収納用の貫通穴を塞ぐようにして接合層を介
して接合された金属製の放熱板とを具備して成る半導体
素子収納用パッケージであって、接地または電源用導体
の下面に被着された絶縁層は、その内縁が半導体素子収
納用の貫通穴の開口よりも0.05〜2mm外周側に位置す
ることを特徴とするものである。
According to the present invention, there is provided a package for accommodating a semiconductor element, comprising: an insulating plate having a substantially rectangular through hole for accommodating a semiconductor element in a central portion; A plurality of wiring conductors applied to
A grounding or power supply conductor attached to substantially the entire lower surface of the insulating plate, an insulating layer made of a thermosetting resin applied to the lower surface of the grounding or power supply conductor, and a semiconductor on the lower surface of the insulating layer. A semiconductor device housing package comprising: a metal heat radiating plate joined via a joining layer so as to close the element housing through hole, and is attached to a lower surface of a grounding or power supply conductor. The insulating layer is characterized in that its inner edge is located on the outer peripheral side of 0.05 to 2 mm from the opening of the through hole for accommodating the semiconductor element.

【0014】また、本発明の半導体素子収納用パッケー
ジの製造方法は、上面に配線導体用の金属層および下面
に接地または電源用導体用の金属層が被着され、中央部
に半導体素子収納用の貫通穴が形成された絶縁板を準備
する工程と、この接地または電源用導体の下面に未硬化
の熱硬化性樹脂ペーストをその内縁が半導体素子収納用
の貫通穴の開口よりも0.05〜2mm外周側に位置するよ
うに塗布した後に硬化させて絶縁層を被着させる工程
と、この絶縁層の下面に金属製の放熱板を半導体素子収
納用の貫通穴を塞ぐようにして接合層を介して接合する
工程とを具備することを特徴とするものである。
Further, in the method of manufacturing a package for housing a semiconductor element according to the present invention, a metal layer for a wiring conductor is coated on an upper surface and a metal layer for a ground or power supply conductor is coated on a lower surface, and a semiconductor element storage layer is formed at a center portion. Preparing an insulating plate having through holes formed therein, and applying an uncured thermosetting resin paste to the lower surface of the grounding or power supply conductor, the inner edge of which is 0.05 to 2 mm wider than the opening of the through hole for accommodating the semiconductor element. A step of applying the insulating layer by applying it so as to be located on the outer peripheral side, and applying an insulating layer, and a metal radiating plate on a lower surface of the insulating layer via a bonding layer so as to cover the through hole for housing the semiconductor element. And joining.

【0015】本発明の半導体素子収納用パッケージによ
れば、接地または電源用導体の下面に被着された絶縁層
は、その内縁が半導体素子収納用の貫通穴の開口よりも
0.05〜2mm外周側に位置することから、絶縁層用の熱
硬化性樹脂を熱硬化させる際に流動化した熱硬化性樹脂
が半導体素子収納用の貫通穴まで到達しにくい。
According to the package for accommodating a semiconductor element of the present invention, the insulating layer applied to the lower surface of the grounding or power supply conductor has an inner edge which is larger than the opening of the through hole for accommodating the semiconductor element.
Since it is located on the outer peripheral side of 0.05 to 2 mm, the thermosetting resin fluidized when the thermosetting resin for the insulating layer is thermoset hardly reaches the through hole for housing the semiconductor element.

【0016】本発明の半導体素子収納用パッケージの製
造方法によれば、接地または電源用導体の下面に未硬化
の熱硬化性樹脂ペーストをその内縁が半導体素子収納用
の貫通穴の開口よりも0.05〜2mm外周側に位置するよ
うに塗布した後に硬化させて絶縁層を被着させ、この絶
縁層の下面に金属製の放熱板を半導体素子収納用の貫通
穴を塞ぐようにして接合層を介して接合することから、
絶縁層用の熱硬化性樹脂ペーストを硬化させる際に流動
化した熱硬化性樹脂が半導体素子収納用の貫通穴まで到
達しにくい。
According to the method of manufacturing a package for accommodating a semiconductor element of the present invention, the uncured thermosetting resin paste is applied to the lower surface of the conductor for grounding or power supply so that the inner edge of the paste is 0.05 mm wider than the opening of the through hole for accommodating the semiconductor element. After being applied so as to be located on the outer peripheral side of about 2 mm, the coating is cured and an insulating layer is applied, and a metal heat sink is provided on the lower surface of the insulating layer via a bonding layer so as to cover the through hole for housing the semiconductor element. To join
When the thermosetting resin paste for the insulating layer is cured, the fluidized thermosetting resin hardly reaches the through hole for housing the semiconductor element.

【0017】[0017]

【発明の実施の形態】次に、本発明の半導体素子収納用
パッケージを添付の図面に基づいて説明する。図1は、
本発明の半導体素子収納用パッケージの実施形態の一例
を示す断面図である。図中、1は配線基板、2は放熱板
であり、主としてこれらで半導体素子3を収容するため
の本発明の半導体素子収納用パッケージが構成されてい
る。なお、本例では、中央部に半導体素子3を収容する
空所を形成するための貫通穴4aを有するとともに上面
に配線導体5および下面に接地または電源用導体6が被
着された絶縁板4と、中央部に貫通穴4aより大きい貫
通穴7aを有するとともに上面に外部接続用導体8が被
着された絶縁板7とを接着層9を介して接着して配線基
板1を形成した例を示している。また、この配線基板1
の外周部には複数の貫通孔10が形成されており、貫通孔
10の内壁には貫通導体11が被着されている。またさら
に、接地または電源用導体6の下面には絶縁層12が被着
されている。なお、接地または電源用導体6は、半導体
素子3の接地電極または電源電極のどちらがこの接地ま
たは電源用導体6に電気的に接続されるかにより接地用
導体として機能したり、電源用導体として機能したりす
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device housing package according to the present invention will be described with reference to the accompanying drawings. FIG.
It is sectional drawing which shows an example of embodiment of the package for semiconductor element accommodation of this invention. In the figure, 1 is a wiring board, 2 is a heat sink, and these mainly constitute a semiconductor element housing package of the present invention for housing the semiconductor element 3. In this example, the insulating plate 4 has a through hole 4a for forming a cavity for accommodating the semiconductor element 3 in the center, and a wiring conductor 5 on the upper surface and a grounding or power supply conductor 6 on the lower surface. An example in which a wiring board 1 is formed by bonding an insulating plate 7 having a through hole 7a larger than the through hole 4a at the center and having an external connection conductor 8 attached to the upper surface thereof through an adhesive layer 9 at the center portion. Is shown. In addition, this wiring board 1
A plurality of through holes 10 are formed in the outer peripheral portion of the
A through conductor 11 is adhered to the inner wall of 10. Further, an insulating layer 12 is provided on the lower surface of the grounding or power supply conductor 6. The grounding or power supply conductor 6 functions as a grounding conductor or a power supply conductor depending on which of the ground electrode or the power supply electrode of the semiconductor element 3 is electrically connected to the grounding or power supply conductor 6. Or

【0018】配線基板1を構成する絶縁板4や7は、例
えばガラス繊維やアラミド繊維のクロスにエポキシ樹脂
やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含
浸させて成る略四角枠状であり、配線導体5・接地また
は電源用導体6や外部接続用導体8の支持体として機能
するとともに貫通穴4a・7a内に半導体素子3を収容
するための空所を形成する。
The insulating plates 4 and 7 constituting the wiring board 1 are in a substantially rectangular frame shape obtained by impregnating a cloth of glass fiber or aramid fiber with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The wiring conductor 5 functions as a support for the grounding or power supply conductor 6 and the external connection conductor 8, and forms a space for accommodating the semiconductor element 3 in the through holes 4 a and 7 a.

【0019】また、これらの絶縁板4・7を接着する接
着層9は、同じくガラス繊維やアラミド繊維のクロスに
エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬
化性樹脂を含浸させて成り、絶縁板4と7とを接着する
接着部材として機能する。
The adhesive layer 9 for bonding the insulating plates 4 and 7 is also made by impregnating a cloth of glass fiber or aramid fiber with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. It functions as an adhesive member for adhering 4 and 7.

【0020】絶縁板4の上面に被着された配線導体5
は、銅箔等の金属から成り、貫通穴4aの開口近傍から
外周部にかけて複数の帯状パターンに被着形成されてい
る。この配線導体5は、パッケージ内に収容される半導
体素子3の各電極を外部電気回路に電気的に接続するた
めの導電路の一部として機能し、その貫通穴4a近傍部
位には半導体素子3の各電極がボンディングワイヤ13を
介して接合され、その外周部は貫通導体11に接続されて
いる。
The wiring conductor 5 attached to the upper surface of the insulating plate 4
Is formed of a metal such as copper foil, and is formed in a plurality of band-shaped patterns from the vicinity of the opening of the through hole 4a to the outer peripheral portion. The wiring conductor 5 functions as a part of a conductive path for electrically connecting each electrode of the semiconductor element 3 housed in the package to an external electric circuit. Are connected via bonding wires 13, and the outer peripheral portions thereof are connected to the through conductors 11.

【0021】また、絶縁板4の下面に被着された接地ま
たは電源用導体6は、銅箔等の金属から成り、絶縁板4
の下面の略全面に被着形成されている。この接地または
電源用導体6は、半導体素子3に接地または電源電位を
供給するとともに配線導体5の特性インピーダンスを所
定の値に調整する機能を有し、貫通導体11に電気的に接
続されている。
The grounding or power supply conductor 6 attached to the lower surface of the insulating plate 4 is made of metal such as copper foil.
Is formed on substantially the entire lower surface of the substrate. The ground or power supply conductor 6 has a function of supplying a ground or power supply potential to the semiconductor element 3 and adjusting the characteristic impedance of the wiring conductor 5 to a predetermined value, and is electrically connected to the through conductor 11. .

【0022】なお、接地または電源用導体6の内縁を絶
縁板4の貫通穴4aの開口よりも0.1〜5mm外周側に
位置して設けておくと、後述するように絶縁板4に貫通
穴4aを加工する際に接地または電源用導体6にバリが
発生することがなく、それによりパッケージ内部に半導
体素子3を収容した際に、接地または電源用導体6と半
導体素子3とが接触することが有効に防止され、その結
果、半導体素子3と接地または電源用導体6との間の不
要な電気的短絡や電気的絶縁性の低下を防止して半導体
素子3を正常に作動させることができる。したがって、
接地または電源用導体6は、その内縁を貫通穴4aの開
口よりも0.1〜5mm程度外周側に位置して設けること
が好ましい。なお、接地または電源用導体6の内縁と貫
通穴4aの開口との距離が0.1mmよりも短いと、貫通
穴4aを加工する際に接地または電源用導体6にバリが
発生する危険性が大きくなる傾向にあり、他方、接地ま
たは電源用導体6の内縁と貫通穴4aの開口との距離が
5mmよりも長い場合には、接地または電源用導体6を
十分な面積で確保できなくなり半導体素子3に十分に安
定した接地または電源電位を供給することができなくな
るとともに配線導体5の特性インピーダンスを所定の値
に調整することが困難となる傾向がある。
If the inner edge of the grounding or power supply conductor 6 is provided 0.1 to 5 mm outside the opening of the through hole 4a of the insulating plate 4, the through hole 4a is formed in the insulating plate 4 as described later. No burrs are generated on the grounding or power supply conductor 6 when processing the semiconductor device, and when the semiconductor element 3 is accommodated inside the package, the grounding or power supply conductor 6 may come into contact with the semiconductor element 3. As a result, it is possible to prevent the semiconductor element 3 from being unnecessarily short-circuited between the semiconductor element 3 and the conductor 6 for grounding or the power supply, and to prevent the electric insulation from being deteriorated. Therefore,
It is preferable that the grounding or power supply conductor 6 be provided with its inner edge located on the outer peripheral side of about 0.1 to 5 mm from the opening of the through hole 4a. If the distance between the inner edge of the grounding or power supply conductor 6 and the opening of the through hole 4a is shorter than 0.1 mm, there is a large risk that the grounding or power supply conductor 6 will have burrs when the through hole 4a is processed. On the other hand, if the distance between the inner edge of the grounding or power supply conductor 6 and the opening of the through hole 4a is longer than 5 mm, the grounding or power supply conductor 6 cannot be secured with a sufficient area, and the semiconductor element 3 Therefore, it is difficult to supply a sufficiently stable ground or power supply potential, and it is difficult to adjust the characteristic impedance of the wiring conductor 5 to a predetermined value.

【0023】また、絶縁板7の上面に被着された外部接
続用導体8は、外部電気回路との接続用導体として機能
し、貫通導体11に電気的に接続するようにして形成され
ている。そして、この外部接続用導体8には、半田ボー
ル等からなる外部接続用部材14が取着される。
The external connection conductor 8 attached to the upper surface of the insulating plate 7 functions as a connection conductor with an external electric circuit and is formed so as to be electrically connected to the through conductor 11. . An external connection member 14 made of a solder ball or the like is attached to the external connection conductor 8.

【0024】なお、配線導体5および外部接続用導体8
は、通常、5〜50μm程度の厚みである。高速の信号を
伝達させるという観点からは5μm以上の厚みが好まし
く、配線導体5や外部接続用導体8を寸法精度良く加工
するためには50μm以下の厚みとしておくことが好まし
い。また、これらの配線導体5および外部接続用導体8
の露出する表面には、通常であれば1〜30μm程度の厚
みのニッケルめっき層および0.1〜3μm程度の厚みの
金めっき層が無電解めっき法や電解めっき法により順次
被着されている。それにより、配線導体5および外部接
続用導体8の酸化腐食を有効に防止することができると
ともに配線導体5とボンディングワイヤ13との電気的接
続および外部接続用導体8と外部接続用部材14との電気
的接続を良好となすことができる。
The wiring conductor 5 and the external connection conductor 8
Has a thickness of usually about 5 to 50 μm. The thickness is preferably 5 μm or more from the viewpoint of transmitting a high-speed signal, and is preferably 50 μm or less in order to process the wiring conductor 5 and the external connection conductor 8 with high dimensional accuracy. The wiring conductor 5 and the external connection conductor 8
Usually, a nickel plating layer having a thickness of about 1 to 30 μm and a gold plating layer having a thickness of about 0.1 to 3 μm are sequentially applied to the exposed surface by electroless plating or electrolytic plating. Thereby, oxidation corrosion of the wiring conductor 5 and the external connection conductor 8 can be effectively prevented, and the electrical connection between the wiring conductor 5 and the bonding wire 13 and the connection between the external connection conductor 8 and the external connection member 14 can be prevented. Good electrical connection can be achieved.

【0025】また、貫通孔10の内壁に被着された貫通導
体11は配線導体5や接地または電源用導体6と外部接続
用導体8とを電気的に接続させる接続導体として機能
し、配線基板1の上面から下面にかけて穿孔された多数
の貫通孔10の内壁に厚みが4〜50μm程度の銅めっき層
を無電解めっき法や電解めっき法を採用して被着するこ
とにより形成されている。なお、貫通導体11の厚みが4
μm未満では、配線導体5や接地または電源用導体6と
外部接続用導体8とを電気的に良好に接続することが困
難となる傾向にあり、他方、50μmを超えると、そのよ
うな厚みの貫通導体11を形成するために長時間を要し、
パッケージを製造する効率が極めて低いものとなる傾向
にある。
The through conductor 11 attached to the inner wall of the through hole 10 functions as a connection conductor for electrically connecting the wiring conductor 5, the grounding or power supply conductor 6, and the external connection conductor 8 to the wiring board. 1 is formed by applying a copper plating layer having a thickness of about 4 to 50 μm to the inner wall of a large number of through holes 10 formed from the upper surface to the lower surface by using an electroless plating method or an electrolytic plating method. The thickness of the through conductor 11 is 4
When the thickness is less than μm, it tends to be difficult to electrically connect the wiring conductor 5 or the grounding or power supply conductor 6 to the external connection conductor 8 satisfactorily. It takes a long time to form the through conductor 11,
The efficiency of manufacturing packages tends to be very low.

【0026】さらに、この接地または電源用導体6の下
面にはエポキシ樹脂等の熱硬化性樹脂から成る絶縁層12
が被着形成されている。絶縁層12は、配線基板1に放熱
板2を強固に接合させるための接合用下地部材として機
能し、この絶縁層12の下面に放熱板2が接合層15を介し
て接合されることにより配線基板1と放熱板2とが接合
されている。この絶縁層12にはシリカ等の無機絶縁物粉
末から成るフィラーを5〜50重量%程度含有させてもよ
い。フィラーを含有させることにより絶縁層12の熱膨張
係数を調整することができるとともに、絶縁層12の耐熱
性等を向上させることができる。このような絶縁層12
は、未硬化のエポキシ樹脂等の熱硬化性樹脂ペーストを
接地または電源用導体6の下面に枠状に塗布した後、こ
れを熱硬化させることにより形成される。
Further, an insulating layer 12 made of a thermosetting resin such as an epoxy resin is formed on the lower surface of the grounding or power supply conductor 6.
Are formed. The insulating layer 12 functions as a joining base member for firmly joining the heat radiating plate 2 to the wiring board 1, and the heat radiating plate 2 is joined to the lower surface of the insulating layer 12 via the joining layer 15 so that the wiring is formed. The substrate 1 and the heat sink 2 are joined. The insulating layer 12 may contain about 5 to 50% by weight of a filler made of an inorganic insulating powder such as silica. By including a filler, the thermal expansion coefficient of the insulating layer 12 can be adjusted, and the heat resistance and the like of the insulating layer 12 can be improved. Such an insulating layer 12
Is formed by applying a thermosetting resin paste such as an uncured epoxy resin on the lower surface of the grounding or power supply conductor 6 in a frame shape, and then thermosetting the paste.

【0027】ところで、本発明の半導体素子収容パッケ
ージにおいては、絶縁層12は、その内縁が貫通穴4aの
開口より0.05〜2mm外周側に位置するように形成され
ている。そして、そのことが重要である。絶縁層12は、
その内縁が貫通穴4aの開口より0.05〜2mm外周側に
位置するように形成されていることから、この絶縁層12
を形成する際に、流動化した絶縁層12用の熱硬化性樹脂
の一部が貫通穴4aに到達することが有効に防止され
る。したがって、配線導体5に絶縁層12による不要な熱
硬化性樹脂が付着するようなことはなく、半導体素子3
の各電極を配線導体5にボンディングワイヤ13等の電気
的接続手段を介して確実かつ強固に接続することができ
る。
By the way, in the semiconductor element housing package of the present invention, the insulating layer 12 is formed such that the inner edge thereof is located 0.05 to 2 mm on the outer peripheral side of the opening of the through hole 4a. And that is important. The insulating layer 12
Since the inner edge is formed so as to be positioned 0.05 to 2 mm on the outer peripheral side from the opening of the through hole 4a, the insulating layer 12
When forming the layer, a part of the fluidized thermosetting resin for the insulating layer 12 is effectively prevented from reaching the through hole 4a. Therefore, unnecessary thermosetting resin due to the insulating layer 12 does not adhere to the wiring conductor 5, and the semiconductor element 3
These electrodes can be reliably and firmly connected to the wiring conductor 5 via an electrical connection means such as a bonding wire 13.

【0028】なお、絶縁層12は、その内縁から貫通穴4
aの開口までの距離が0.05mm未満の場合、絶縁層12を
形成する際に、流動化した絶縁層12用の熱硬化性樹脂の
一部が貫通穴4aに到達して、これが貫通穴4a内壁を
伝って配線導体5に付着してしまう危険性が大きなもの
となり、他方、2mmを超えると、配線基板1と放熱板
2とを隙間なく良好に接合することが困難となる傾向に
ある。したがって、絶縁層12の内縁から貫通穴4a開口
までの距離は0.05〜2mmの範囲に特定される。
The insulating layer 12 is formed such that the inner edge of the insulating layer 12
When the distance to the opening a is less than 0.05 mm, when the insulating layer 12 is formed, a part of the fluidized thermosetting resin for the insulating layer 12 reaches the through hole 4a, and this is the through hole 4a. There is a large danger that it will adhere to the wiring conductor 5 along the inner wall. On the other hand, if it exceeds 2 mm, it tends to be difficult to satisfactorily join the wiring board 1 and the heat sink 2 without gaps. Therefore, the distance from the inner edge of the insulating layer 12 to the opening of the through hole 4a is specified in the range of 0.05 to 2 mm.

【0029】さらに、図2に配線基板1の下面図で示す
ように、絶縁層12の内縁から貫通穴4aまでの距離を貫
通穴4aの各角部に対応した位置で広いものとしておく
と、絶縁層12を形成する際に流動化した絶縁層12用の熱
硬化性樹脂が貫通穴4aに到達するのをより効果的に防
止することができる。貫通穴4aの角部では流動化した
絶縁層12用の熱硬化性樹脂が集合しやすく、またその内
壁を流動化した熱硬化性樹脂が伝いやすいので絶縁層12
の内縁から貫通穴4aまでの距離を貫通穴4aの各角部
に対応した位置で広いものとしておくことが効果的であ
る。したがって、絶縁層15は、その内縁から貫通穴4a
の開口までの距離を貫通穴4aの各角部に対応した位置
で広いものとしておくことが好ましい。
Further, as shown in the bottom view of the wiring board 1 in FIG. 2, if the distance from the inner edge of the insulating layer 12 to the through hole 4a is wide at a position corresponding to each corner of the through hole 4a, When the insulating layer 12 is formed, the fluidized thermosetting resin for the insulating layer 12 can be more effectively prevented from reaching the through hole 4a. At the corners of the through holes 4a, the fluidized thermosetting resin for the insulating layer 12 is likely to collect, and the fluidized thermosetting resin is easily transmitted to the inner wall.
It is effective to increase the distance from the inner edge to the through hole 4a at a position corresponding to each corner of the through hole 4a. Therefore, the insulating layer 15 is formed from the inner edge thereof through the through hole 4a.
It is preferable to make the distance to the opening wide at a position corresponding to each corner of the through hole 4a.

【0030】さらに、絶縁層12が接地または電源用導体
6の内縁側の側面を0.01mm以上の厚みで覆うように形
成しておくと、接地または電源用導体6と半導体素子3
との間の電気的絶縁の確保が確実となる。したがって、
絶縁層12は、接地または電源用導体6の内周側の側面を
0.01mm以上の厚みで覆うように形成しておくことが好
ましい。
Further, if the insulating layer 12 is formed so as to cover the side surface on the inner edge side of the grounding or power supply conductor 6 with a thickness of 0.01 mm or more, the grounding or power supply conductor 6 and the semiconductor element 3 are formed.
And electrical insulation between them is ensured. Therefore,
The insulating layer 12 is provided on the inner side surface of the conductor 6 for grounding or power supply.
It is preferable to form it so as to cover it with a thickness of 0.01 mm or more.

【0031】他方、配線基板1の下面に接合層15を介し
て接合された放熱板2は、銅等の熱伝導性に優れる金属
から成り、貫通穴4aを塞ぐようにして接合されてい
る。この放熱板2は、半導体素子3を支持するための支
持体として機能するとともに半導体素子3が作動時に発
生する熱を外部に良好に放熱するための放熱部材として
機能し、その上面中央部に半導体素子3を搭載するため
の搭載部2aを有している。そして、この搭載部2aに
半導体素子3がエポキシ樹脂等の接着剤を介して接着固
定される。
On the other hand, the heat radiating plate 2 joined to the lower surface of the wiring board 1 via the joining layer 15 is made of a metal having excellent thermal conductivity such as copper and is joined so as to close the through hole 4a. The heat radiating plate 2 functions as a support for supporting the semiconductor element 3 and also as a heat radiating member for radiating heat generated during operation of the semiconductor element 3 to the outside. It has a mounting portion 2a for mounting the element 3. Then, the semiconductor element 3 is bonded and fixed to the mounting portion 2a via an adhesive such as an epoxy resin.

【0032】このような放熱板2は、例えば銅から成る
板材を打ち抜き金型により所定の形状に打ち抜くことに
よって形成すればよい。なお、放熱板2の表面にニッケ
ルや金等の耐食性の良好な金属をめっき法により1〜20
μmの厚みに被着させておくと、放熱板2の酸化腐食を
有効に防止することができる。さらに、放熱板2と接合
層15との接合力向上のために、放熱板2表面に黒化処理
やブラスト処理を施し、その表面に中心線平均粗さRa
が0.2〜3μm程度となるような凹凸を形成してもよ
い。
Such a heat radiating plate 2 may be formed by punching a plate made of, for example, copper into a predetermined shape using a punching die. A metal having good corrosion resistance, such as nickel or gold, is plated on the surface of the heat sink 2 by plating.
If it is applied to a thickness of μm, oxidation corrosion of the heat sink 2 can be effectively prevented. Further, in order to improve the bonding strength between the heat sink 2 and the bonding layer 15, the surface of the heat sink 2 is subjected to a blackening treatment or a blast treatment, and the surface thereof has a center line average roughness Ra.
May be formed to be about 0.2 to 3 μm.

【0033】また、配線基板1と放熱板2とを接合する
接合層15は、例えばガラスクロスにエポキシ樹脂等の熱
硬化性樹脂を含浸させて成る略四角枠状であり、このよ
うな構成により接合面にボイドが発生せず接合強度が大
きく密着性に優れている。このような接合層15は、例え
ばガラスクロスに未硬化のエポキシ樹脂を含浸させたシ
ートを打ち抜き金型等を用いて絶縁板4と略同一の形状
に打ち抜き、これを配線基板1と放熱板2との間に挟ん
で上下から加圧しながら熱硬化させることにより配線基
板1と放熱板2とを強固に接合する。このとき、接合層
15用のシートをその内縁が貫通穴4aの開口から0.1〜
1mm外周側に位置するように打ち抜いておくと、配線
基板1と放熱板2とを接合層15を介して接合する際に、
接合層15に含有される熱硬化性樹脂の一部が貫通穴4a
内壁を伝って配線導体5に付着するのを有効に防止する
ことができるとともに、配線基板1と放熱板2との間に
隙間を形成することなく両者を強固に接合することがで
きる。したがって、接合層15用のシートは、その内縁が
貫通穴4aの開口から0.1〜1mm外周側に位置するよ
うに打ち抜くことが好ましい。
The bonding layer 15 for bonding the wiring board 1 and the heat radiating plate 2 has a substantially rectangular frame shape made by impregnating a thermosetting resin such as an epoxy resin into a glass cloth. No voids are generated on the joint surface, the joint strength is large, and the adhesion is excellent. Such a bonding layer 15 is formed, for example, by punching a sheet of glass cloth impregnated with an uncured epoxy resin into a shape substantially the same as that of the insulating plate 4 using a punching die or the like. The wiring board 1 and the heat radiating plate 2 are firmly joined by being thermally cured while pressing from above and below. At this time, the bonding layer
The inner edge of the sheet for 15 is 0.1 to 0.1 mm from the opening of the through hole 4a.
If it is punched out so as to be located on the outer peripheral side of 1 mm, when the wiring board 1 and the heat sink 2 are joined via the joining layer 15,
Part of the thermosetting resin contained in the bonding layer 15 is formed in the through hole 4a.
It is possible to effectively prevent the adhesive from being attached to the wiring conductor 5 along the inner wall, and it is possible to firmly join the wiring board 1 and the heat sink 2 without forming a gap between them. Therefore, it is preferable to punch the sheet for the bonding layer 15 so that the inner edge thereof is located 0.1 to 1 mm on the outer peripheral side from the opening of the through hole 4a.

【0034】かくして、本発明の半導体素子収納用パッ
ケージによれば、放熱板2の搭載部2aに半導体素子3
を搭載するとともに、この半導体素子3の各電極と配線
導体5とをボンディングワイヤ13を介して電気的に接続
し、しかる後、貫通穴4a・5a内へ封止用樹脂をポッ
ティングして樹脂封止を行なうことにより半導体装置と
なる。
Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 3 is mounted on the mounting portion 2a of the heat sink 2.
And electrically connect each electrode of the semiconductor element 3 to the wiring conductor 5 via a bonding wire 13. Thereafter, potting a sealing resin into the through holes 4a and 5a to seal the resin. By stopping, a semiconductor device is obtained.

【0035】なお、このような半導体素子収納用パッケ
ージにおいては、必要に応じて配線基板1上に外部接続
用導体8の外周部を覆うソルダーレジスト層16を設けて
もよい。このようなソルダーレジスト層16は、例えばシ
リカ等の絶縁性フィラーを含有させたエポキシ樹脂等の
熱硬化性樹脂から成り、外部接続用導体8上に半田ボー
ル等の外部接続用部材14を被着する際の外部接続用部材
14の不要な濡れ広がりを制御するダムの作用をする。こ
のようなソルダーレジスト層16は、未硬化の感光性を有
する熱硬化性樹脂ペーストを外部接続用導体8が形成さ
れた絶縁板7の上面にスクリーン印刷法を採用して塗布
するとともに従来公知のフォトリソグラフィ−により所
定のパターンにエッチングした後、熱硬化させることに
より形成することができる。
In such a semiconductor device housing package, a solder resist layer 16 covering the outer peripheral portion of the external connection conductor 8 may be provided on the wiring board 1 if necessary. Such a solder resist layer 16 is made of, for example, a thermosetting resin such as an epoxy resin containing an insulating filler such as silica, and is provided with an external connection member 14 such as a solder ball on the external connection conductor 8. For external connection when connecting
Acts as a dam that controls the spread of 14 unwanted wets. Such a solder resist layer 16 is formed by applying an uncured photosensitive thermosetting resin paste to the upper surface of the insulating plate 7 on which the external connection conductors 8 are formed by using a screen printing method and a conventionally known solder resist layer. After etching into a predetermined pattern by photolithography, it can be formed by heat curing.

【0036】次に、上述の半導体素子収納用パッケージ
を製造する本発明の製造方法について説明する。
Next, a description will be given of a manufacturing method of the present invention for manufacturing the above-described semiconductor element housing package.

【0037】まず、図3(a)に断面図で示すように、
絶縁板4用の絶縁板4Aと絶縁板7用の絶縁板7Aと接
着層9用の未硬化の接着シート9Aとを準備する。この
とき、絶縁板4Aの上面には配線導体5用の金属層5A
を、絶縁板4Aの下面には接地または電源用導体6用の
金属層6Aを、絶縁板7Aの上面には外部接続用導体8
用の金属層8Aを貫通孔10が形成される領域を含めて所
定のパターンに被着形成しておく。また、絶縁板7Aの
中央部には貫通穴7aを形成しておく。
First, as shown in the sectional view of FIG.
An insulating plate 4A for the insulating plate 4, an insulating plate 7A for the insulating plate 7, and an uncured adhesive sheet 9A for the adhesive layer 9 are prepared. At this time, the metal layer 5A for the wiring conductor 5 is formed on the upper surface of the insulating plate 4A.
A metal layer 6A for the grounding or power supply conductor 6 on the lower surface of the insulating plate 4A, and an external connection conductor 8 on the upper surface of the insulating plate 7A.
Metal layer 8A is formed in a predetermined pattern including a region where the through hole 10 is formed. A through hole 7a is formed in the center of the insulating plate 7A.

【0038】このような絶縁板4Aおよび7Aは、例え
ばガラスクロスに未硬化のエポキシ樹脂等の熱硬化性樹
脂を含浸させてなるシートを得るとともに、これを熱硬
化させることによって形成され、貫通穴7aは、硬化し
た絶縁板7Aに切削加工を施すことにより形成される。
また、配線導体5・接地または電源用導体6や外部接続
用導体8用の金属層5A・6A・8Aは、絶縁板4A・
7A用のシートの上面や下面の全面に銅箔を貼着してお
くとともに絶縁板4A・7A用のシートを硬化させた
後、これらの銅箔を公知のフォトリソグラフィー技術を
採用して所定のパターンにエッチングすることによって
形成される。また、未硬化の接着シート9Aは、ガラス
クロスに未硬化のエポキシ樹脂等の熱硬化性樹脂を含浸
させて成るシートを打ち抜き金型により所定の枠状に打
ち抜くことによって形成される。
The insulating plates 4A and 7A are formed by, for example, obtaining a sheet in which a glass cloth is impregnated with a thermosetting resin such as an uncured epoxy resin and thermosetting the sheet to form a through hole. 7a is formed by cutting the cured insulating plate 7A.
The metal layers 5A, 6A, and 8A for the wiring conductor 5, the grounding or power supply conductor 6, and the external connection conductor 8 are made of an insulating plate 4A.
After the copper foil is stuck on the entire upper and lower surfaces of the sheet for 7A and the sheet for insulating plates 4A and 7A is cured, these copper foils are subjected to a predetermined photolithography technique. It is formed by etching into a pattern. The uncured adhesive sheet 9A is formed by punching a sheet formed by impregnating a glass cloth with an uncured thermosetting resin such as an epoxy resin into a predetermined frame shape using a punching die.

【0039】次に、図3(b)に断面図で示すように、
絶縁板4Aと絶縁板7Aとを間に未硬化の接着シート9
Aを挟んで積層するとともに、これらを例えば積層プレ
ス機を用いて、真空度が4kPa以下、温度が180〜200
℃の範囲、圧力が2〜4MPaの範囲の条件で90〜120
分間加圧加熱することにより接着シート9Aを熱硬化さ
せて絶縁板4Aと絶縁板7Aとを接着シート9Aを介し
て接着して成る配線基板1用の積層体1Aを得る。
Next, as shown in the sectional view of FIG.
Uncured adhesive sheet 9 between insulating plate 4A and insulating plate 7A
A and sandwich them, and using a laminating press, for example, the degree of vacuum is 4 kPa or less, the temperature is 180 to 200
90 ° C to 120 ° C under the condition of a temperature range of 2 to 4 MPa.
The adhesive sheet 9A is thermally cured by applying pressure and heating for one minute to obtain a laminate 1A for the wiring board 1 formed by bonding the insulating plate 4A and the insulating plate 7A via the adhesive sheet 9A.

【0040】次に、図3(c)に断面図で示すように、
積層体1Aの中央部に半導体素子を収容するための貫通
穴4aおよび外周部に複数の貫通孔10をルーター加工や
ドリル加工等の切削加工により形成するとともに、貫通
孔10の内壁に無電解めっき法や電解めっき法により銅か
ら成る貫通導体11を被着形成して外部接続用導体8とこ
れに対応する配線導体5および接地または電源用導体6
とをそれぞれ電気的に接続する。
Next, as shown in the sectional view of FIG.
A through-hole 4a for accommodating a semiconductor element in the center of the laminated body 1A and a plurality of through-holes 10 in the outer periphery are formed by cutting such as router processing and drilling, and electroless plating is performed on the inner wall of the through-hole 10. Conductor 11 made of copper is formed on the conductor 8 for external connection, the corresponding wiring conductor 5 and the conductor 6 for grounding or power supply by the method or the electrolytic plating method.
Are electrically connected to each other.

【0041】このとき、接地または電源用導体6をその
内縁が貫通穴4aの開口よりも0.1〜5mm程度外周側
に位置するように設けておくと、絶縁板4Aに貫通穴4
aを切削加工により形成する際に接地または電源用導体
6の内縁にバリが発生することを有効に防止することが
できる。そして、その結果、パッケージの内部に収容す
る半導体素子と接地または電源用導体6とが接触するこ
とがないパッケージを提供することができる。したがっ
て、接地または電源用導体6は、その内縁が貫通穴4a
の開口よりも0.1〜5mm程度外周側に位置するように
設けておくことが好ましい。
At this time, if the grounding or power supply conductor 6 is provided so that its inner edge is located on the outer peripheral side by about 0.1 to 5 mm from the opening of the through hole 4a, the through hole 4 is formed in the insulating plate 4A.
When forming a by cutting, it is possible to effectively prevent burrs from being generated on the inner edge of the grounding or power supply conductor 6. As a result, it is possible to provide a package in which the semiconductor element housed inside the package does not come into contact with the ground or power supply conductor 6. Therefore, the inner edge of the grounding or power supply conductor 6 has a through hole 4a.
It is preferable to provide it so that it is located on the outer peripheral side of about 0.1 to 5 mm from the opening.

【0042】次に、図3(d)に断面図で示すように、
積層体1Aの下面に絶縁層12用の未硬化の熱硬化性樹脂
ペースト12Aをスクリーン印刷法を採用して印刷塗布し
た後、これを熱硬化させて接地または電源用導体6の下
面に絶縁層12が被着された配線基板1を得る。
Next, as shown in the sectional view of FIG.
An uncured thermosetting resin paste 12A for the insulating layer 12 is printed and applied on the lower surface of the laminate 1A by using a screen printing method, and then thermally cured to form an insulating layer on the lower surface of the grounding or power supply conductor 6. The wiring substrate 1 on which the substrate 12 is adhered is obtained.

【0043】なお、本発明の製造方法においては、熱硬
化性樹脂ペースト12Aをその内縁が貫通穴4aの開口か
ら0.05〜2mm外周側に位置するように印刷塗布してい
る。そして、そのことが重要である。このように、熱硬
化性樹脂ペースト12Aをその内縁が貫通穴4aの開口か
ら0.05〜2mm外周側に位置するように印刷塗布するこ
とから、この熱硬化性樹脂ペースト12Aを熱硬化させて
絶縁層12とする際に、流動化した熱硬化性樹脂ペースト
12Aの一部が貫通穴4aに到達することが有効に防止さ
れる。したがって、熱硬化性樹脂ペースト12Aの一部が
貫通穴4a内壁を伝って配線導体5に付着することはな
く、その結果、半導体素子3の各電極と配線導体5とを
ボンディングワイヤ13を介して確実かつ強固に電気的に
接続することが可能な半導体素子収納用パッケージを提
供することができる。
In the manufacturing method of the present invention, the thermosetting resin paste 12A is applied by printing so that the inner edge thereof is located 0.05 to 2 mm on the outer peripheral side from the opening of the through hole 4a. And that is important. As described above, since the thermosetting resin paste 12A is printed and applied so that the inner edge thereof is positioned 0.05 to 2 mm on the outer peripheral side from the opening of the through hole 4a, the thermosetting resin paste 12A is thermoset to form an insulating layer. Thermosetting resin paste fluidized when setting to 12
Part of the 12A is effectively prevented from reaching the through hole 4a. Therefore, a portion of the thermosetting resin paste 12A does not adhere to the wiring conductor 5 along the inner wall of the through hole 4a, and as a result, each electrode of the semiconductor element 3 and the wiring conductor 5 are connected via the bonding wire 13. It is possible to provide a package for housing a semiconductor element which can be reliably and firmly electrically connected.

【0044】なお、熱硬化性樹脂ペースト12Aの内縁か
ら貫通穴4a開口までの距離が0.05mm未満であると、
熱硬化性樹脂ペースト12Aを熱硬化させて絶縁層12とす
る際に、流動化した熱硬化性樹脂ペースト12Aの一部が
貫通穴4aに到達して、これが貫通穴4a内壁を伝って
配線導体5に付着する危険性が大きなものとなり、他
方、2mmを超えると、配線基板1の下面に放熱板2を
接合層15を介して接合する際に、配線基板1と放熱板2
とを隙間なく強固に接合することが困難となる傾向にあ
る。したがって、熱硬化性樹脂ペースト12Aの内縁から
貫通穴4aの開口までの距離は0.05〜2mmの範囲に特
定される。
If the distance from the inner edge of the thermosetting resin paste 12A to the opening of the through hole 4a is less than 0.05 mm,
When the thermosetting resin paste 12A is heat-cured to form the insulating layer 12, a part of the fluidized thermosetting resin paste 12A reaches the through hole 4a, which travels along the inner wall of the through hole 4a to form a wiring conductor. When the thickness exceeds 2 mm, when the heat sink 2 is bonded to the lower surface of the wiring board 1 via the bonding layer 15, the wiring board 1
And it tends to be difficult to join them firmly without gaps. Therefore, the distance from the inner edge of the thermosetting resin paste 12A to the opening of the through hole 4a is specified in the range of 0.05 to 2 mm.

【0045】さらに、図2に配線基板1の下面図で示し
たように、熱硬化性樹脂ペースト12A内縁から貫通穴4
aの開口までの距離を貫通穴4aの各角部に対応する部
位で広いものとしておくと、熱硬化性樹脂ペースト12A
を熱硬化させて絶縁層12とする際に、流動化した熱硬化
性樹脂ペースト12Aの一部が貫通穴4aに到達するのを
より有効に防止することが可能となる。したがって、熱
硬化性樹脂ペースト12Aの内縁から貫通穴4aの開口ま
での距離は、貫通穴4aの各角部に対応する部位で広い
ものとしておくことが好ましい。
Further, as shown in the bottom view of the wiring board 1 in FIG.
If the distance to the opening a is set to be large at the portion corresponding to each corner of the through hole 4a, the thermosetting resin paste 12A
When the insulating layer 12 is formed by heat-curing, a part of the fluidized thermosetting resin paste 12A can be more effectively prevented from reaching the through hole 4a. Therefore, it is preferable that the distance from the inner edge of the thermosetting resin paste 12A to the opening of the through hole 4a is wide at a portion corresponding to each corner of the through hole 4a.

【0046】またさらに、このような絶縁層12が接地ま
たは電源用導体6の内縁側の側面を覆うようにしておく
と、絶縁層12が接地または電源用導体6の内縁側の側面
を覆うことにより、接地または電源用導体6と半導体素
子3との間の不要な電気的短絡や電気絶縁性の低下を有
効に防止することができる。したがって、絶縁層12は、
接地または電源用導体6の内縁側の側面を覆うように形
成しておくことが好ましい。
Further, if such an insulating layer 12 covers the side surface on the inner edge side of the grounding or power supply conductor 6, the insulating layer 12 covers the inner side surface of the grounding or power supply conductor 6. Thereby, unnecessary electrical short-circuiting between the ground or power supply conductor 6 and the semiconductor element 3 and a decrease in electrical insulation can be effectively prevented. Therefore, the insulating layer 12
It is preferable that the grounding or power supply conductor 6 be formed so as to cover the side surface on the inner edge side.

【0047】そして最後に、配線基板1の下面に放熱板
2を接合層15を介して接合することにより図1に示した
ような本発明の半導体素子収納用パッケージが完成す
る。なお、配線基板1と放熱板2との接合は、ガラスク
ロスに未硬化のエポキシ樹脂等を含浸させた接合層15用
のシートを間に挟んで配線基板1と放熱板2とを積層
し、これらを上下から0.3〜0.5MPaの圧力を印加しな
がら150〜200℃の温度で60〜120分間程度の時間加熱し
て接合層15用のシートを熱硬化させることにより行なわ
れる。
Finally, the heat sink 2 is bonded to the lower surface of the wiring board 1 via the bonding layer 15 to complete the semiconductor device housing package of the present invention as shown in FIG. Note that the wiring board 1 and the heat sink 2 are joined by sandwiching a sheet for the bonding layer 15 in which glass cloth is impregnated with an uncured epoxy resin or the like, and the wiring board 1 and the heat sink 2 are laminated. These are heated at a temperature of 150 to 200 ° C. for about 60 to 120 minutes while applying a pressure of 0.3 to 0.5 MPa from above and below to thermally cure the sheet for the bonding layer 15.

【0048】なお、この例で貫通穴4aを絶縁板4Aと
絶縁板7Aとを接着した後に形成したのは、両者を接着
層9を介して接着する際に大きな反りが発生するのを防
止するためであり、絶縁板4A・7Aの厚みが十分に厚
くて反りの発生の危険性が小さい場合等には、絶縁板4
Aと7Aとを接着する前に貫通穴4aを形成しておいて
もよい。
In this example, the formation of the through-hole 4a after bonding the insulating plate 4A and the insulating plate 7A prevents the occurrence of a large warp when bonding the two via the bonding layer 9. If the thickness of the insulating plates 4A and 7A is sufficiently large to reduce the risk of warpage, the insulating plate 4A
Before bonding A and 7A, the through-hole 4a may be formed.

【0049】さらに、本発明の製造方法においては、必
要に応じて配線基板1上に外部接続用導体8の外周部を
覆うソルダーレジスト層16を形成してもよい。このよう
なソルダーレジスト層16を設けることにより外部接続用
導体8上に半田ボール等の外部接続用部材14を接合した
際に半田ボール等の不要な濡れ広がりを防止することが
できる。このようなソルダーレジスト層16は、例えばシ
リカ等のフィラーを含有するエポキシ樹脂等の熱硬化性
樹脂から形成すればよく、シリカ等のフィラーを含有す
る未硬化の感光性を有する熱硬化性樹脂ペーストを外部
接続用導体8を含む絶縁板7上の略全面にスクリーン印
刷法等を採用して印刷塗布した後、これを公知のフォト
リソグラフィー技術を採用して所定のパターンにエッチ
ングし、最後にこれを130〜180℃で約1時間程度加熱し
て硬化させることによって形成すればよい。
Further, in the manufacturing method of the present invention, a solder resist layer 16 covering the outer peripheral portion of the external connection conductor 8 may be formed on the wiring board 1 if necessary. By providing such a solder resist layer 16, when the external connection member 14 such as a solder ball is joined to the external connection conductor 8, unnecessary spreading of the solder ball or the like can be prevented. Such a solder resist layer 16 may be formed of, for example, a thermosetting resin such as an epoxy resin containing a filler such as silica, and an uncured photosensitive thermosetting resin paste containing a filler such as silica. Is applied over substantially the entire surface of the insulating plate 7 including the external connection conductors 8 by using a screen printing method or the like, and then is etched into a predetermined pattern by using a known photolithography technique. May be formed by heating at 130 to 180 ° C. for about 1 hour to cure.

【0050】かくして、本発明の半導体素子収納用パッ
ケージの製造方法によれば、配線導体5に不要な熱硬化
性樹脂の付着がなく、内部に収容する半導体素子3と配
線導体5とをボンディングワイヤ13等を介して確実かつ
強固に接続することが可能な半導体素子収納用パッケー
ジを提供することができる。
Thus, according to the method of manufacturing a package for accommodating a semiconductor element of the present invention, unnecessary thermosetting resin does not adhere to the wiring conductor 5, and the semiconductor element 3 and the wiring conductor 5 housed inside are bonded to each other by a bonding wire. It is possible to provide a semiconductor element housing package that can be securely and firmly connected via the 13 or the like.

【0051】なお、本発明は上述の実施形態例に限定さ
れるものではなく、本発明の要旨を逸脱しない範囲であ
れば種々の変更は可能である。例えば、上述の実施の形
態例では、2枚の絶縁板5・7を接着した配線基板1を
例に示したが、1枚の絶縁板の上面に配線導体と外部接
続用導体とを一体的に形成するとともに下面に接地また
は電源用導体を形成して成る配線基板や、3枚以上の絶
縁板を積層して成る配線基板を用いたものであってもよ
い。また、上述の実施の形態例における貫通穴4a・5
aを、打ち抜き金型を用いたパンチングにより、あるい
はレーザ加工機により形成してもよい。さらに、貫通孔
10の加工をレーザ加工機を用いて行ってもよい。
It should be noted that the present invention is not limited to the above embodiment, and various changes can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the wiring board 1 in which the two insulating plates 5 and 7 are bonded is shown as an example, but the wiring conductor and the external connection conductor are integrally formed on the upper surface of one insulating plate. And a wiring board formed by laminating three or more insulating plates, or a wiring board having a grounding or power supply conductor formed on the lower surface. Also, the through holes 4a and 5a in the above-described embodiment example.
a may be formed by punching using a punching die or by a laser processing machine. In addition, through holes
The processing of 10 may be performed using a laser processing machine.

【0052】[0052]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、接地または電源用導体の下面に被着された絶縁
層は、その内縁が半導体素子収納用の貫通穴の開口より
も0.05〜2mm外周側に位置することから、絶縁層用の
熱硬化性樹脂を熱硬化させる際に流動化した熱硬化性樹
脂が半導体素子収納用の貫通穴の内壁まで到達しにく
い。したがって、絶縁層用の熱硬化性樹脂が貫通穴の内
壁を伝って配線導体に付着するようなことはなく、その
結果、半導体素子の各電極と配線導体とをボンディング
ワイヤ等の電気的接続手段を介して確実かつ強固に電気
的に接続させることができる。
According to the semiconductor device housing package of the present invention, the insulating layer applied to the lower surface of the grounding or power supply conductor has an inner edge 0.05 to 2 mm larger than the opening of the semiconductor element housing through hole. Since the thermosetting resin is located on the outer peripheral side, the thermosetting resin fluidized when thermosetting the thermosetting resin for the insulating layer hardly reaches the inner wall of the through hole for housing the semiconductor element. Therefore, the thermosetting resin for the insulating layer does not adhere to the wiring conductor along the inner wall of the through hole, and as a result, each electrode of the semiconductor element and the wiring conductor are electrically connected to each other by an electrical connection means such as a bonding wire. And the electrical connection can be made surely and firmly.

【0053】また、本発明の半導体素子収納用パッケー
ジの製造方法によれば、接地または電源用導体の下面に
未硬化の熱硬化性樹脂ペーストをその内縁が半導体素子
収納用の貫通穴の開口よりも0.05〜2mm外周側に位置
するように塗布した後に硬化させて絶縁層を被着させ、
この絶縁層の下面に金属製の放熱板を半導体素子収納用
の貫通穴を塞ぐようにして接着層を介して接着すること
から、熱硬化性樹脂ペーストを硬化させる際に流動化す
る熱硬化性樹脂が半導体素子収納用の貫通穴まで到達し
にくい。したがって、絶縁層用の熱硬化性樹脂が貫通穴
の内壁を伝って配線導体に付着するようなことはなく、
その結果、半導体素子の各電極と配線導体とをボンディ
ングワイヤ等の電気的接続手段を介して確実かつ強固に
電気的に接続させることが可能な半導体素子収納用パッ
ケージを提供することができる。
According to the method of manufacturing a package for accommodating a semiconductor element of the present invention, the uncured thermosetting resin paste is applied to the lower surface of the conductor for grounding or power supply, the inner edge of which is formed through the opening of the through hole for accommodating the semiconductor element. Also applied so as to be located on the outer peripheral side of 0.05 to 2 mm, cured and applied with an insulating layer,
A heat sink made of metal is adhered to the lower surface of this insulating layer via an adhesive layer so as to close the through hole for housing the semiconductor element, so that the thermosetting resin paste is fluidized when the thermosetting resin paste is cured. It is difficult for the resin to reach the through hole for housing the semiconductor element. Therefore, the thermosetting resin for the insulating layer does not travel along the inner wall of the through hole and adhere to the wiring conductor.
As a result, it is possible to provide a semiconductor element housing package capable of securely and firmly electrically connecting each electrode of the semiconductor element and the wiring conductor via an electric connection means such as a bonding wire.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの実施の
形態の一例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor element storage package according to the present invention.

【図2】図1に示す半導体素子収納用パッケージにおけ
る配線基板1の下面図である。
FIG. 2 is a bottom view of the wiring board 1 in the semiconductor device housing package shown in FIG.

【図3】(a)〜(d)は、図1に示す半導体素子収納
用パッケージの配線基板1の製造方法を説明するための
工程毎の断面図である。
3 (a) to 3 (d) are cross-sectional views for explaining steps of a method for manufacturing the wiring board 1 of the package for housing semiconductor elements shown in FIG. 1;

【図4】従来の半導体素子収納用パッケージの例を示す
断面図である。
FIG. 4 is a cross-sectional view illustrating an example of a conventional semiconductor element storage package.

【図5】(a)〜(d)は、図4に示す従来の半導体素
子収納用パッケージの配線基板21の製造方法を説明する
ための工程毎の断面図である。
5 (a) to 5 (d) are cross-sectional views for each process for explaining a method of manufacturing the wiring board 21 of the conventional package for housing semiconductor elements shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・・・配線基板 2・・・・・・・放熱板 3・・・・・・・半導体素子 4、7・・・・・絶縁板 4a、7a・・・・・半導体素子を収容するための貫通穴 5・・・・・・・配線導体 6・・・・・・・接地または電源用導体 12・・・・・・・絶縁層 15・・・・・・・接合層 1 ... wiring board 2 ... heatsink 3 ... semiconductor element 4, 7 ... insulating plate 4a, 7a ... semiconductor element Through hole for accommodating 5... Wiring conductor 6... Grounding or power supply conductor 12... Insulating layer 15... Joining layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H01L 23/12 E J 23/14 R ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/12 EJ 23/14 R

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 中央部に半導体素子収納用の略四角形の
貫通穴を有する絶縁板と、該絶縁板の上面の前記貫通穴
周辺から外周部にかけて被着された複数の配線導体と、
前記絶縁板の下面の略全面に被着された接地または電源
用導体と、該接地または電源用導体の下面に被着された
熱硬化性樹脂から成る絶縁層と、前記絶縁層の下面に前
記貫通穴を塞ぐようにして接合層を介して接合された金
属製の放熱板とを具備して成る半導体素子収納用パッケ
ージであって、前記絶縁層は、その内縁が前記貫通穴の
開口よりも0.05〜2mm外周側に位置することを特
徴とする半導体素子収納用パッケージ。
An insulating plate having a substantially rectangular through hole for accommodating a semiconductor element in a central portion; and a plurality of wiring conductors attached from a periphery of the through hole to an outer peripheral portion on an upper surface of the insulating plate.
A grounding or power conductor attached to substantially the entire lower surface of the insulating plate; an insulating layer made of a thermosetting resin applied to the lower surface of the grounding or power conductor; A semiconductor device housing package comprising: a metal heat radiating plate joined via a joining layer so as to close the through hole, wherein an inner edge of the insulating layer is larger than an opening of the through hole. A package for accommodating a semiconductor element, which is located on an outer peripheral side of 0.05 to 2 mm.
【請求項2】 前記貫通穴の開口から前記絶縁層の内縁
までの距離が前記貫通穴の各角部に対応する部位で広く
なっていることを特徴とする請求項1記載の半導体素子
収納用パッケージ。
2. The semiconductor element storage device according to claim 1, wherein a distance from an opening of the through hole to an inner edge of the insulating layer is wide at a portion corresponding to each corner of the through hole. package.
【請求項3】 上面に配線導体用の金属層および下面に
接地または電源用の金属層が被着され、中央部に半導体
素子収納用の貫通穴が形成された絶縁板を準備する工程
と、前記接地または電源用導体の下面に未硬化の熱硬化
性樹脂ペーストをその内縁が前記貫通穴の開口よりも
0.05〜2mm外周側に位置するように塗布した後に
硬化させて熱硬化性樹脂から成る絶縁層を被着させる工
程と、前記絶縁層の下面に金属製の放熱板を前記貫通穴
を塞ぐようにして接合層を介して接合する工程とを具備
することを特徴とする半導体素子収納用パッケージの製
造方法。
3. A step of preparing an insulating plate having a metal layer for a wiring conductor on the upper surface, a metal layer for grounding or a power supply on the lower surface, and a through hole for accommodating a semiconductor element formed in a central portion. An uncured thermosetting resin paste is applied to the lower surface of the grounding or power supply conductor so that the inner edge thereof is positioned 0.05 to 2 mm on the outer peripheral side of the opening of the through hole, and then cured to be cured. A semiconductor element comprising the steps of: attaching an insulating layer consisting of: and bonding a metal heat sink to a lower surface of the insulating layer via a bonding layer so as to cover the through hole. Manufacturing method of storage package.
【請求項4】 前記貫通穴の開口から前記熱硬化性樹脂
ペーストの内縁までの距離を前記貫通穴の各角部に対応
する部位で広く形成することを特徴とする請求項3記載
の半導体素子収納用パッケージの製造方法。
4. The semiconductor device according to claim 3, wherein a distance from an opening of the through hole to an inner edge of the thermosetting resin paste is formed wider at a portion corresponding to each corner of the through hole. Manufacturing method of storage package.
JP2001008916A 2001-01-17 2001-01-17 Package for containing semiconductor element and its manufacturing method Pending JP2002217327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001008916A JP2002217327A (en) 2001-01-17 2001-01-17 Package for containing semiconductor element and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001008916A JP2002217327A (en) 2001-01-17 2001-01-17 Package for containing semiconductor element and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002217327A true JP2002217327A (en) 2002-08-02

Family

ID=18876473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001008916A Pending JP2002217327A (en) 2001-01-17 2001-01-17 Package for containing semiconductor element and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002217327A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011253891A (en) * 2010-06-01 2011-12-15 Jtekt Corp Method of manufacturing multilayer circuit board
JP2012209590A (en) * 2012-07-17 2012-10-25 Shinko Electric Ind Co Ltd Electronic component mounting multilayer wiring board and manufacturing method of the same
JP2017117833A (en) * 2015-12-21 2017-06-29 京セラ株式会社 Wiring board and electronic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011253891A (en) * 2010-06-01 2011-12-15 Jtekt Corp Method of manufacturing multilayer circuit board
JP2012209590A (en) * 2012-07-17 2012-10-25 Shinko Electric Ind Co Ltd Electronic component mounting multilayer wiring board and manufacturing method of the same
JP2017117833A (en) * 2015-12-21 2017-06-29 京セラ株式会社 Wiring board and electronic apparatus

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