JP2002204157A - Counter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that in a binary counter, counter operation by a rapid clock is unstable as affected by a delay time caused by operation, thus requiring a large-sized circuit in a shift counter for obtaining a large count value. SOLUTION: A plurality of shift registers 1 to 4 are provided. Passage of count up enable is blocked by a logical product gate 10 by using a value of an uppermost bit of the shift register 1 of the forefront stage as a shift operation enable signal and only at the time of enable, and count up enable is input to a shift register of the next stage. Consequently, since a shift counter of each stage shows each digit of a count value, circuit scale is reduced. Furthermore, since each shift counter just shifts a value in a shift register, a delay time does not matter and rapid operation can be ensured stably.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a counter circuit, and more particularly to a counter circuit using a shift register.

[0002]

2. Description of the Related Art Conventionally, this kind of counter circuit is generally configured in a binary format, for example, as shown in FIG. This conventional binary counter circuit (hereinafter, referred to as a “binary counter”) includes a buffer, an exclusive OR, and a flip-flop (hereinafter, “F
F ”) are connected in cascade. The figure shows an 8-bit binary counter.

When a count-up enable is input from the left end in the drawing, an exclusive OR (EXOR) of the value stored in the FF and the count-up enable is performed, and the result is stored in the FF. At the same time, FF
Becomes an enable signal of the buffer, and when the enable signal is 1, the count-up enable is passed to the next stage. The value output from each stage FF is an 8-bit binary value, which is the output of the counter circuit.

[0004] A counter circuit configured in a shift format as disclosed in JP-A-60-20638 is also known. This shift type counter circuit (hereinafter referred to as a “shift counter”) has an FF as shown in FIG.
Are constituted by shift registers connected in cascade,
The output of the most significant bit of the FF is input to the least significant bit, and the output of each bit, that is, the output of the shift register is converted into a binary value by an encoder.

When the counter circuit is reset, "1" is set to only the least significant bit in the shift register, and "0" is set to the other bits. Thereafter, when a count-up enable is input, the shift-up is sequentially performed in synchronization with the clock timing. Therefore, the encoder converts the value into a binary value according to the position of “1”. In FIG. 5, 256 FFs are connected in cascade to obtain an 8-bit binary value.

[0006]

As described above, there are two types of counter circuits, a binary counter and a shift counter, for constructing a counter circuit.

However, since the binary counter has a small circuit configuration, it is possible to create a small-sized counter. However, the value of each bit is determined by the logical product of all lower bits and the value of the bit itself. Is obtained by an exclusive OR operation of Therefore, as the countable value increases, the bit length of the counter increases, so that the higher-order bits increase the amount of calculation, and the delay time increases accordingly. As a result, when the counter is operated by the high-speed clock, the operation becomes unstable due to the influence of the delay time.

On the other hand, the shift counter can operate without going through an operation like a binary counter, so that there is no problem of delay. However, when the bit length of the counter is increased, the circuit is increased and the counter is enlarged. was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a counter circuit capable of ensuring stable operation even with a high-speed clock and minimizing the circuit scale.

A further object of the present invention is to provide an irregular counter circuit capable of arbitrarily changing a carry value for each digit in order to enable more flexible counting operation.

[0011]

In order to achieve the above object, the present invention provides a counter which is constituted by a shift register to which a plurality of bits are connected, and which sequentially shifts up a set value when a count-up enable is inputted. The circuit has a plurality of the shift registers, uses the value of the most significant bit of the shift register as a shift operation enable signal, and inputs a count-up enable to the next-stage shift register only when the shift operation enable signal is enabled. It shall be.

In this case, an arbitrary bit is set to a different value from the other bits in the shift register. More practically, only the least significant bit is set to 1 and a reset signal is input to the shift register. It is desirable to set a value.

[0013] Further, it is provided that there is provided a buffer for passing the count-up enable when the shift operation enable signal is enabled, and an encoder for converting the output of the shift register into a binary value.

Further, in order to cope with various situations, the one or more shift registers and the one or more binary counters are mixed, and the shift register and the binary counter are provided for each stage. Can be set to any number of bits.

[0015]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a counter circuit according to the present invention. The counter circuit is composed of a plurality of FFs, and sequentially shifts up a value held by a count-up enable input, and inputs the value of the most significant bit to a restart bit. Shift registers 1 to 4 for output as shift operation enable signals, encoders 5 to 8 for inputting the values of the respective FFs of the shift registers 1 to 4 as code values and converting them into binary values, Buffers 10 to 13 are AND gates for passing the count-up enable to the next-stage shift register when the value of the upper bit, that is, the shift operation enable signal is enabled.

In this embodiment, the 8-bit shift counter has a four-stage configuration. Therefore, the values of 0 to 8 are obtained from the shift counters of each stage, and the values are formed in four stages, so that the whole counter circuit can obtain a 4-digit count value in the octal system. In other words, the number of bits of the shift counter of each stage means the number system, and the number of stages means the number of digits.

Next, the operation of the first embodiment will be described.

As an initial setting before the operation is performed, a reset signal is input to each of the shift registers 1 to 4 and a value set in the shift register is loaded into “10000000” (the leftmost bit is the least significant bit, and the rightmost is the most significant bit). Bits).
That is, 1 is set to the least significant bit, and 0 is set to all other bits. At this time, all the shift registers 1 to 4 are "
10000000 ", so encoder 5
8 inputs this as a code value and outputs a binary value of “000”. Since the most significant bit signal of the output data signals of the shift registers 1 to 4 is "0", the buffers 10 to 13 are not enabled, and the count-up enable cannot pass through the buffers 10 to 13.

When the count-up enable is input, the shift register operates in synchronism with a clock that arrives at regular intervals as described below.

With the first clock, the shift register 1 shifts the held value by one to the subsequent stage and at the same time feeds back the value of the most significant bit to the least significant bit, so that it becomes "01000000". The encoder 5 inputs the value of the shift register 1 as a code value, converts the code value into a binary value, and outputs “001”.

Note that the shift register 1 before the clock is input
4 are all "0", that is, the shift operation enable signal is "0".
Since 13 is not enabled, the count-up enable is not input to the next-stage shift counter. Therefore, a binary value of “000” is output from the encoders 6 to 8 as in the initial state.

Therefore, the counter value of the entire counter circuit indicates "1" in octal.

Next, with the second clock, the shift register 1 shifts the held value by one to the subsequent stage and at the same time feeds back the value of the most significant bit to the least significant bit, so that the value becomes "00100000". The encoder 5 inputs the value of the shift register 1 as a code value, converts the value into a binary value, and outputs "010".

Note that the shift register 1 before the clock is input
4 are all "0", that is, the shift operation enable signal is "0".
Since 13 is not enabled, the count-up enable is not input to the next-stage shift counter. Therefore, a binary value of “000” is output from the encoders 6 to 8 as in the initial state.

Therefore, the counter value of the entire counter circuit indicates octal "2".

Similarly, when the operation is repeated up to the seventh clock, "00000001" is stored in the shift register 1.

Next, by the eighth clock, the shift register 1 shifts the held value by one to the subsequent stage and simultaneously feeds back the value of the most significant bit to the least significant bit, so that the value becomes "10000000". The encoder 5 inputs the value of the shift register 1 as a code value, converts it into a binary value, and outputs "000".

At this time, the value of the most significant bit of the shift register 1 before the clock is input is "1", that is, the shift operation enable signal is "1".
0 is enabled, passes through the count-up enable, and is input to the second-stage shift counter.

When the count-up enable is input to the second-stage shift counter, the shift register 2 shifts the held value by one to the subsequent stage and feeds back the value of the most significant bit to the least significant bit.
The encoder 5 inputs the value of the shift register 2 as a code value, converts it into a binary value, and outputs "001".

Note that the shift register 2 before the clock is input
4 are all “0”, that is, the shift operation enable signal is “0”.
Since 13 is not enabled, the count-up enable is not input to the next-stage shift counter. Therefore,
A binary value of “000” is output from the encoders 7 and 8 as in the initial state.

Therefore, the counter value of the entire counter circuit indicates octal "10", and the digit increases by one.

Similarly, while the count-up enable is input, the shift operation is sequentially performed by the clock input.
When the value held by the first-stage shift register 1 makes one cycle, the value held by the second-stage shift register 2 is shifted up, so that the clock is octal 100 times (10 times).
(64 times in hexadecimal), the value held in the second-stage shift register 2 makes one cycle, and the count-up enable passes through the buffer 11 and is input to the third-stage shift counter. . In this way, the count-up / carry is sequentially repeated to the third and fourth stages, and in the configuration of the first embodiment, 10,000 can be counted in octal.

Here, considering an element that causes a maximum delay time for counting 10000 in octal, only buffers 10 to 12 and eight FFs in the shift register (one FF instead of all shift registers) Only one shift register), so that there is no practically problematic delay.

In the first embodiment, the number of bits of the shift register in each stage is equal. However, if it is desired to change the count number for each digit for design reasons or the like, the number of bits of the shift register is appropriately changed. It can be made by changing it. Further, in the first embodiment, all the stages are constituted by shift counters. However, the shift counter and the binary counter can be appropriately mixed for each stage for reasons such as design.

FIG. 2 shows these cases as a second embodiment. In the figure, the first, third and fourth stages are shift counters, while the second stage is a binary counter 25. Also,
The first and fourth stages are shift counters that output a 3-bit binary value as in FIG. 1, but the third stage is a shift counter that outputs a 2-bit binary value, and the second stage is a 4-bit binary value. It is a binary counter that outputs a value.

Therefore, the first and fourth stage shift counters have the same configuration as that of FIG. 1, but the shift register 15 in the third stage shift counter has a 4-bit configuration.
The encoder 18 is configured to input 4-bit data as a code value and output a 2-bit binary value.

The second-stage binary counter is a counter which can output a 4-bit binary value by forming the binary counter shown in the prior art into a 4-row configuration. When all FFs become "1", the next-stage binary counter becomes the next stage. The carry signal is output to the shift counter, that is, the buffer 22 is enabled.

Next, the operation will be described. Basically, as in the embodiment of FIG. 1, when the count-up enable 20 is input, the count-up enable 20 is held in the shift register 14 in synchronization with a clock arriving at a fixed interval. Are sequentially shifted to the subsequent stage, and the encoder 17 inputs the value of the shift register 14 as a code value, converts this to a binary value,
1, 2,... 7 "are sequentially output.

Next, when the shift operation enable signal from the shift register 14 becomes "1" and the count-up enable passes through the buffer 21 and is input to the second-stage binary counter 25, as shown in the prior art, , The exclusive OR and the FF, the binary value is sequentially counted up, and the binary counter 25 sequentially outputs the count value as “1, 2,... F”. In this embodiment, since this embodiment is constituted by a 4-bit binary counter, this binary value represents a value represented by a hexadecimal number.

At this time, since the buffers 22 and 23 have not been enabled, the count-up enable has not yet been input to the third and fourth shift counters, and their respective count values remain "0". . Therefore, “0” is set by the time the binary counter 25 makes one cycle.
The count value of F7 "is output. As described above," F "in the second digit is a value expressed in hexadecimal, and" 7 "in the first digit is a value expressed in octal.

Furthermore, all the FFs of the binary counter 25 are "
When the value becomes "1", "1" is input to the buffer 22 as a shift operation enable signal. Therefore, the count-up enable passes through the buffer 22 and is input to the third-stage shift counter.

The third-stage shift counter counts using the 4-bit shift register 15 and outputs a 2-bit binary value by the encoder 18. Therefore, the third digit is a quaternary number "0-3". The count value is output.

As described above, in the whole counter, "0 to 73F
A count value of 7 "can be output. Note that the fourth digit" 7 "is an octal number, the third digit" 3 "is a quaternary number, the second digit" F "is a hexadecimal number, and the first digit "7" is a value represented by an octal number.

[0044]

As described above, according to the present invention, a plurality of shift registers are provided, and a shift register is provided for each digit of the count value. Is eliminated, and even when it is desired to obtain a large count value, it becomes possible with a small-scale circuit configuration.

Further, since the circuit configuration is simple and no operation is required, a malfunction due to a delay time, which is a problem in the conventional binary counter, due to a delay time in a high-speed clock is prevented, and a stable operation is possible.

Further, according to the present invention, since the shift counter and the binary counter can be freely combined, it is possible to select each digit according to the characteristics of the shift counter and the binary counter for each digit for reasons such as design. Become.

Each shift counter and binary counter can appropriately change the number of bits.
For design reasons or the like, it is possible to make a selection according to the value to be counted for each digit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment according to the present invention.

FIG. 2 is a diagram showing a second embodiment according to the present invention.

FIG. 3 is a diagram showing a conventional binary counter.

FIG. 4 is a diagram showing a conventional shift counter.

[Explanation of symbols]

 1-4 shift register 5-8 encoder 9 count-up enable 10-13 buffer

Claims (8)

[Claims] 1. A counter circuit comprising a shift register to which a plurality of bits are connected and sequentially shifting up a set value when a count-up enable is input, comprising: a plurality of said shift registers; The value of the most significant bit of
A counter circuit wherein a count-up enable is input to a shift register of the next stage only when the shift operation enable signal is enabled. 2. The counter circuit according to claim 1, wherein an arbitrary bit is set to a value different from other bits in the shift register. 3. The counter circuit according to claim 1, wherein only the least significant bit is set to 1 in the shift register. 4. The counter circuit according to claim 2, wherein a value is set in the shift register in response to input of a reset signal. 5. The counter circuit according to claim 1, further comprising a buffer for passing the count-up enable when the shift operation enable signal is enabled. 6. The counter circuit according to claim 1, further comprising an encoder for converting an output of said shift register into a binary value. 7. The one or more shift registers,
7. The counter circuit according to claim 1, wherein one or two or more binary counters are mixed. 8. The counter circuit according to claim 1, wherein the shift register and the binary counter can set an arbitrary number of bits for each stage.