JP2020048183A - Gray code counter - Google Patents

Abstract

To reduce a variation in gray code output timing between circuit blocks.SOLUTION: The gray code counter includes a plurality of circuit blocks (11, 12, 13) for outputting gray codes (D1, D2, D3). The circuit blocks include: a gray code generation circuit for generating the gray codes by receiving clock signals (CK0, CK1, CK2) input thereinto; and a clock signal generation circuit for generating a clock signal to be input to the circuit block at the next stage. A gray code counter (1) for outputting a gray code (D0) obtained by integrating the gray codes output from the circuit blocks respectively is provided.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a gray code counter that generates a gray code from a clock signal.

  Patent Document 1 discloses a gray code counter that includes a plurality of circuit blocks each generating a gray code, integrates the gray codes from the plurality of circuit blocks, and outputs a multi-bit gray code.

JP-A-6-53818 (released on February 25, 1994)

  In the cited document 1, when the number of the plurality of circuit blocks is increased in order to increase the maximum number of bits that can be counted, the power consumption increases monotonously according to the increased number of the circuit blocks. There is.

  (1) One embodiment of the present invention includes a plurality of circuit blocks including a gray code generation circuit that generates a gray code based on an input clock signal, and a gray code output from each of the plurality of circuit blocks. A gray code counter for outputting a gray code, wherein at least one of the plurality of circuit blocks generates a clock signal to be input to the next circuit block based on an input clock signal Gray code counter with generation circuit.

  (2) In addition, in one embodiment of the present invention, in addition to the configuration of the above (1), each of the circuit blocks has a minimum value based on a clock signal input thereto, where n is an integer of 2 or more. An n-bit gray code that periodically fluctuates up to a maximum value is output, and at least one of the circuit blocks outputs a clock signal having a period of 2 n times the clock signal input thereto to the next stage. A gray code counter input to the circuit block.

  (3) In one embodiment of the present invention, in addition to the configuration of the above (2), m is an integer of 2 or more and m circuit blocks are provided, and the first to m-th circuit blocks are provided. A gray code counter that sequentially integrates gray codes from the block and outputs an n × m bit gray code.

  (4) Further, in one embodiment of the present invention, in addition to the configuration of any one of the above (1) to (3), a gray code from all the circuit blocks is input to the first-stage circuit block. Gray code counter including a synchronization circuit that synchronizes based on a clock signal.

  (5) In addition, in one embodiment of the present invention, in addition to the configuration of any one of the above (1) to (3), at least one of the circuit blocks in the second and subsequent stages includes the circuit block up to the preceding stage. Synchronization for synchronizing the gray code from the circuit block, the gray code output by itself, and the clock signal input to the next-stage circuit block based on the clock signal input to the first-stage circuit block Gray code counter with each circuit.

  (6) In one embodiment of the present invention, in addition to the configuration of the above (5), the synchronous circuit is output in a gray code from the circuit block up to the previous stage and in the circuit block including itself. Gray code counter that generates a gray code integrated with a gray code.

  (7) In addition, in one embodiment of the present invention, in addition to the configuration of (5) or (6), a gray code output by itself with respect to a clock signal input from the previous circuit block, A delay circuit for generating a delay equivalent to the delay of the clock signal input to the circuit block into a gray code input from the preceding circuit block, a delay Gray code delayed by the delay circuit, and an output in itself. Further comprising one or more flip-flop circuits for synchronizing the gray code to be inputted and a clock signal inputted to the next-stage circuit block based on a clock signal inputted to the first-stage circuit block, The signal input to the last-stage flip-flop circuit is delayed with respect to the clock signal input to the first-stage circuit block. There Gray code counter being reduced.

  According to one embodiment of the present invention, a Gray code counter in which an increase in power consumption due to an increase in circuit blocks is reduced can be provided.

FIG. 2 is a block diagram of a gray code counter according to the first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a circuit block according to the first embodiment of the present invention. It is a block diagram of a Gray code counter concerning Embodiment 2 of the present invention. It is a block diagram of a Gray code counter concerning Embodiment 3 of the present invention. It is a block diagram of a Gray code generation part concerning Embodiment 4 of the present invention.

[Embodiment 1]
In this specification, a reference numeral given to a signal line of a circuit in each drawing indicates a signal applied to the signal line. In some cases, some signal lines in each drawing are omitted, such as a signal line to which a reset signal RST0 described later is applied. Note that among the signal lines of the circuits in each drawing, a signal having only one bit of information is applied to a signal line indicated by a thin line, and a signal having information of a plurality of bits is applied to a signal line indicated by a thick line. Applied.
(Outline of gray code counter configuration)
FIG. 1 is a block diagram of a gray code counter 1 according to the present embodiment. The gray code counter 1 according to the present embodiment outputs a gray code corresponding to the number of clocks of the clock signal based on the input clock signal. In this embodiment, the clock signal input to the gray code counter 1 is an input clock signal CK0, and the gray code output from the gray code counter 1 is an output gray code D0.

  The gray code counter 1 includes a plurality of circuit blocks. In the present embodiment, as an example, the gray code counter 1 includes three circuit blocks 11, 12, and 13. Hereinafter, in this specification, the circuit block 11 will be described unless otherwise specified, and it is assumed that the same configuration can be applied to other circuit blocks.

  The circuit block 11 includes a reset signal input unit RST, a clock signal input unit CKR, a clock signal output unit CKG, and a gray code output unit DG.

  The input clock signal CK0 input to the gray code counter 1 is input to the clock signal input unit CKR of the circuit block 11. The circuit block 11 outputs the clock signal CK1 from the clock signal output unit CKG and the gray code D1 from the gray code output unit DG based on the input clock signal CK0. A detailed method of generating the clock signal CK1 and the gray code D1 will be described later.

  The clock signal CK1 is input to the clock signal input unit CKR of the next-stage circuit block 12. In the circuit blocks after the circuit block 12, the clock signal input from the clock signal input unit CKR, the clock signal from the clock signal output unit CKG, and the gray code from the gray code output unit DG, Output in the same way.

The gray code counter 1 may input the reset signal RST0 to the reset signal input unit RST of each circuit block. In the circuit block to which the reset signal RST0 has been input, the bit value of the output signal in the circuit block may be reset.
(First stage Gray code bit and clock signal)
The gray code D1 and the clock signal CK1 output from the circuit block 11 in the present embodiment will be described in detail with reference to Table 1 below. Table 1 is a table showing the gray code D1 and the clock signal CK1 output from the circuit block 11, together with changes in the input clock signal CK0.

  In this embodiment, the states of the signals are represented by bit values, where a high signal is 1 and a low signal is 0. The input clock signal CK0 is a 1-bit signal that alternates between 1 and 0 as a bit value, and the count increases by 1 when the bit value of the input clock signal CK0 changes from 0 to 1. And In the present embodiment, each circuit block outputs a 2-bit Gray code.

  The column of “count” in Table 1 shows the number of counts counted in accordance with the change of the input clock signal CK0 in decimal notation. The columns “D10” and “D11” in Table 1 show the bit values of the gray code bits D10 and D11, which are the 0th and 1st digits of the gray code output by the circuit block 11. “CK1” in Table 1 indicates a bit value of the clock signal CK1 output from the circuit block 11 and input to the circuit block 12.

  In the present embodiment, each circuit block outputs a gray code that periodically varies from a minimum value to a maximum value based on an input clock signal. Therefore, in the circuit block 11, as shown in Table 1, the gray code increases sequentially from 0 to 3 from 0 to 3, and decreases from 3 to 0 from 4 to 7. . In the subsequent counting, the circuit block 11 outputs the gray code at the same cycle.

Further, assuming that the number of bits of the Gray code output from the circuit block is n, which is an integer of 2 or more, the circuit block according to the present embodiment has a cycle of 2 n times as large as the input clock signal. Outputs a clock signal. For example, the number of bits of the Gray code output from the circuit block 11 is 2 bits. Therefore, in the circuit block 11, a clock signal CK1 having a period twice as large as that of the input clock signal CK0, that is, a quadruple period, is output from the circuit block 11. For this reason, the bit value of the clock signal CK1 is as shown in the column of “CK1” in Table 1.
(Outline of circuit block configuration)
An example of a specific circuit of the circuit block 11 that generates such a gray code D1 and the clock signal CK1 is shown in an equivalent circuit diagram of FIG. Note that the negation signals obtained by inverting the bit values of the gray code bits D10 and D11 and the clock signal CK1 are referred to as negation gray code bits D10B and D11B and the negation clock signal CK1B, respectively.

  The circuit block 11 includes a gray code generation circuit 20 and a clock signal generation circuit 21 as shown in FIG. The gray code generation circuit 20 includes a flip-flop circuit 31, a flip-flop circuit 32, and a logic circuit 40. The clock signal generation circuit 21 includes a flip-flop circuit 33.

  The logic circuit 40 includes NAND circuits 41, 42, 43, and 44. By inputting the negative gray code bit D10B and the gray code bit D11 to the NAND circuit 41, the output signal NS1 is obtained from the NAND circuit 41. By inputting the gray code bit D11 and the negative clock signal CK1B to the NAND circuit 42, the output signal NS2 is obtained from the NAND circuit 42. By inputting the gray code bit D10, the negative gray code bit D11B, and the clock signal CK1 to the NAND circuit 43, the output signal NS3 is obtained from the NAND circuit 43. By inputting the output signal NS1, the output signal NS2, and the output signal NS3 to the NAND circuit 44, the output signal NS4 is obtained from the NAND circuit 44.

  Each of the flip-flop circuits 31, 32, and 33 is a D-type flip-flop circuit that outputs and holds an input signal in synchronization with a rising edge of a clock. Each of the flip-flop circuits 31, 32, and 33 includes a signal input section D, a signal output section Q, a negative signal output section QB, a clock signal input section CKR, and a reset signal input section RST.

  In the flip-flop circuits 31, 32, and 33, the clock signal input unit CKR receives a clock signal input to its own circuit block. In the present embodiment, the input clock signal CK0 input to the circuit block 11 is input to the clock signal input unit CKR of each flip-flop circuit. Similarly, the reset signal RST0 may be input to the reset signal input unit RST of each flip-flop circuit.

  The clock signal input to the next-stage circuit block is input to the signal input unit D of the flip-flop circuit 31. In the present embodiment, the clock signal CK1 input to the circuit block 12 is input to the signal input unit D of the flip-flop circuit 31. As a result, the gray code bit D10 is output from the signal output unit Q of the flip-flop circuit 31, and the negative gray code bit D10B is similarly output from the negative signal output unit QB of the flip-flop circuit 31.

  The output signal of the logic circuit 40 is input to the signal input section D of the flip-flop circuit 32. In the present embodiment, the output signal NS4 output from the logic circuit 40 is input. As a result, the gray code bit D11 is output from the signal output section Q of the flip-flop circuit 32, and the negative gray code bit D11B is similarly output from the negative signal output section QB of the flip-flop circuit 32.

  The negative gray code bit D10B is input to the signal input unit D of the flip-flop circuit 33. As a result, the clock signal CK1 is output from the signal output section Q of the flip-flop circuit 33, and similarly, the negative clock signal CK1B is output from the negative signal output section QB of the flip-flop circuit 31.

  The gray code D1 is obtained by integrating the gray code bit D10 generated as described above as the 0th digit and the gray code bit D11 as the first digit. Therefore, the gray code generation circuit 20 generates the gray code D1, and the clock signal generation circuit 21 generates the clock signal CK1. Therefore, the gray code D1 and the clock signal CK1 are output from the circuit block 11.

The specific circuit configuration of the circuit block 11 that generates the gray code D1 having the values shown in Table 1 and the clock signal CK1 can be obtained using a state transition diagram, a Carnot diagram, or the like. Further, in the present embodiment, an example in which the circuit block 11 outputs the 2-bit gray code D1 has been described, but the circuit block 11 may output a gray code of more bits than this. Also in this case, the circuit block 11 can be designed by a general method using a state transition diagram, a Carnot diagram, or the like.
(Second stage circuit block)
In the present embodiment, the circuit block 12 has the same configuration as the circuit block 11. Here, the clock signal CK1 input to the circuit block 12 has a cycle four times as long as the input clock signal CK0. Therefore, the gray code D2 and the clock signal CK2 output from the circuit block 12 have a cycle four times as long as the gray code D1 and the clock signal CK1 output from the circuit block 11.

  The signals output from the circuit blocks 11 and 12 are shown in Table 2 below.

  In Table 2, illustration of the state of each signal at the timing when the input clock signal CK0 takes a value of 0 is omitted. The columns “D20” and “D21” in Table 1 show the bit values of the gray code bits D20 and D21, which are the 0th and 1st digits of the gray code output by the circuit block 12. “CK2” in Table 1 indicates a bit value of the clock signal CK2 output from the circuit block 12 and input to the circuit block 13.

Here, it is assumed that the gray code bits D10, D11, D20, and D21 are regarded as the 0th to third digits, respectively, and are integrated as a 4-bit gray code. In this case, as can be seen from Table 2, the 4-bit Gray code sequentially increases from 0 to 15 from count 0 to 15, and the 4-bit Gray code decreases from 15 to 0 from count 16 to 31. ing. Also in the subsequent counting, the circuit blocks 11 and 12 output the gray code at the same cycle.
(The third and subsequent circuit blocks)
Further, in the present embodiment, the circuit block 13 has the same configuration as the circuit blocks 11 and 12. The circuit block 12 inputs a clock signal CK2 having a cycle four times that of the clock signal CK1 to the circuit block 13. Here, the gray code bits D30 and D31, which are the 0th and 1st digits of the Gray code output by the circuit block 13, are regarded as the 4th and 5th digits, respectively, and are integrated with the above 4-bit Gray code. I do. As a result, a total of 6-bit output gray code D0 obtained by integrating the 2-bit gray codes D1, D2, and D3 from the circuit blocks 11, 12, and 13, respectively, can be obtained. Thus, the gray code counter 1 generates an output gray code D0 from the input clock signal CK0.

If the output gray code D0 is counted up to the maximum value of the output gray code D0 that can be output by the gray code counter 1, then the output gray code D0 is counted down from the maximum value. However, actually, before the output gray code D0 is counted up to the maximum value of the output gray code D0, the output gray code D0 is reset at a stage where the gray code counter 1 has counted up to a required count number. You may. The reset may be realized by inputting a reset signal RST0 to each circuit block.
(Effect of gray code counter)
In the present embodiment, each circuit block operates based on a clock signal having a cycle of 2 n times the clock signal input to the preceding circuit block. Therefore, the driving cycle of the transistor of the logic circuit included in each circuit block is longer than that of the preceding circuit block.

  In general, most of the power consumption of a synchronous logic circuit including a COMS transistor depends on a current flowing through the transistor when the transistor in the logic circuit is turned on or off in response to a change in a clock signal applied to the logic circuit. caused by. That is, when the period in which the transistor of the logic circuit is driven is increased, the power consumed by the logic circuit per unit time is reduced.

  That is, in each circuit block in the present embodiment, the power consumed for a certain period of time is lower than the power consumed in the preceding circuit block. Therefore, even if the number of circuit blocks is increased to configure a multi-bit gray code counter, the gray code counter 1 capable of reducing an increase in power consumption can be realized.

  In the present embodiment, the clock signal from the preceding circuit block is input to the circuit blocks 12 and 13 which are the second and subsequent circuit blocks. However, the present invention is not limited to this, and in the present embodiment, it is sufficient that the clock signal from the preceding circuit block is input to at least one of the second and subsequent circuit blocks. Thus, the gray code counter 1 has an effect of reducing the above-described increase in power consumption.

  In the present embodiment, each circuit block outputs an n-bit Gray code that periodically fluctuates from a minimum value to a maximum value based on a clock signal input thereto. Further, in the present embodiment, each circuit block outputs a clock signal having a cycle of 2 n times the clock signal input thereto to the next circuit block. Thus, the gray code counter 1 according to the present embodiment can be configured with a relatively simple circuit configuration.

  In the present embodiment, the gray code counter 1 includes a plurality of circuit blocks described above. For example, the number of circuit blocks included in the gray code counter 1 is m, which is an integer of 2 or more. As a result, the gray code counter 1 can integrate the gray codes from the circuit blocks from the first stage to the m-th stage in order and output an n × m-bit gray code.

  In the present embodiment, a circuit block that generates n bits can be configured by a simpler logic circuit than a circuit block that directly outputs a multi-bit Gray code output as the entire Gray code counter 1. The output of the entire Gray code counter 1 is configured as a repetition of a circuit block that outputs an n-bit Gray code. Therefore, even when configuring the gray code counter 1 that generates a gray code having a larger number of bits, the gray code counter 1 can be easily configured by connecting circuit blocks having the same configuration as necessary. It is possible.

[Embodiment 2]
(Synchronous circuit)
FIG. 3 is a block diagram of the gray code counter 2 according to the present embodiment. The configuration of the gray code counter 2 is different from that of the gray code counter 1 according to the previous embodiment only in that the gray code counter 2 further includes a synchronization circuit 51.

  The synchronization circuit 51 includes gray code input sections DR1, DR2, and DR3, a gray code output section DG, a clock signal input section CKR, and a reset signal input section RST.

  The gray code D1 from the circuit block 11 is input to the gray code input unit DR1. Similarly, the gray codes D2 and D3 from the circuit blocks 12 and 13 are input to the gray code input units DR2 and DR3, respectively. The input clock signal CK0 input to the gray code counter 2 is input to the clock signal input unit CKR. The operation of the synchronization circuit 51 may be reset by inputting the reset signal RST0 to the reset signal input unit RST.

  The gray codes D1, D2, and D3 input to the gray code inputs DR1, DR2, and DR3, respectively, are synchronized based on the input clock signal CK0 input to the clock signal input CKR. The synchronized gray codes D1, D2, and D3 are integrated and output from the gray code output unit DG as an output gray code D0. The output gray code D0 is output from the gray code counter 2.

  By the way, in each circuit block, the output timing of the output gray code with respect to the input clock signal is determined by the output delay in the circuit block. In the present embodiment, for example, the output delay of the gray code D1 from the circuit block 11 with respect to the input clock signal CK0 is TD. In this case, the output delay of the gray code D2 from the circuit block 12 with respect to the input clock signal CK0 is twice TD in consideration of the output delay in the circuit block 11. Similarly, the output delay of the gray code D3 from the circuit block 13 with respect to the input clock signal CK0 is three times TD.

  In the present embodiment, the output delay of the gray code with respect to the input clock signal CK0 in each circuit block can be made uniform among the circuit blocks. This makes it possible to realize the gray code counter 2 that outputs a gray code in which the difference in the output timing of the gray code between the circuit blocks is further reduced.

  The synchronization may be performed based on the input clock signal CK0. For example, the synchronization may be performed based on a signal obtained by uniformly delaying the input clock signal CK0 by a predetermined time. In the present embodiment, the configuration in which the synchronization circuit 51 includes the three gray code input units DR1, DR2, and DR3 has been described as an example, but the configuration is not limited thereto. The gray code input section of the synchronization circuit 51 can be changed according to the number of circuit blocks included in the gray code counter 2.

[Embodiment 3]
(Other synchronization circuits)
FIG. 4 is a block diagram of the gray code counter 3 according to the present embodiment. The configuration of the gray code counter 3 is different from that of the gray code counter 2 according to the previous embodiment only in that synchronization circuits 52 and 53 are provided instead of the synchronization circuit 51.

  The synchronization circuits 52 and 53 include Gray code input sections DR1 and DR2, a Gray code output section DG, clock signal input sections CKR1 and CKR2, and a clock signal output section CKG. The synchronization circuits 52 and 53 may have the same configuration as the synchronization circuit 51 except for the numbers of the gray code input units and the clock signal input units and the presence / absence of the reset signal input unit RST.

  In the synchronization circuit 52, the gray code D1 from the circuit block 11 is input to the gray code input section DR1. On the other hand, the gray code D2 generated in the circuit block 12 is input to the gray code input unit DR2. The clock signal CK2 generated in the circuit block 12 is input to the clock signal input unit CKR1. On the other hand, the input clock signal CK0 input to the gray code counter 2 is input to the clock signal input unit CKR2.

  The gray codes D1 and D2 input to the gray code input units DR1 and DR2, respectively, and the clock signal CK2 input to the clock signal input unit CKR1 are synchronized based on the input clock signal CK0 input to CKR2. You. The synchronized gray codes D1 and D2 are integrated and output from the gray code output section DG as a gray code D4. The gray code D4 is input to the synchronization circuit 53. The synchronized clock signal CK2 is output from the clock signal output unit CKG, and is input to the clock signal input unit CKR of the circuit block 13.

  The synchronization circuit 53 also synchronizes the gray codes D4 and D3 and the clock signal CK3 based on the input clock signal CK0. The synchronized gray codes D4 and D3 are integrated and output from the gray code output unit DG as an output gray code D0. The output gray code D0 is output from the gray code counter 3.

  In the present embodiment, the output delay of the gray code with respect to the input clock signal CK0 in each circuit block described above can be made uniform for each circuit block. Thus, a gray code counter 3 that outputs a gray code with further reduced differences in gray code output timing between each circuit block can be realized.

  In the present embodiment, the second and subsequent circuit blocks 12 and 13 include synchronization circuits 52 and 53, respectively. However, the present invention is not limited to this, and in the present embodiment, it is sufficient that at least one of the second and subsequent circuit blocks includes a synchronization circuit. Thereby, the gray code counter 3 has an effect of reducing the difference in the output timing of the gray code described above.

  In the present embodiment, for each synchronous circuit, a gray code is generated by integrating a gray code from a circuit block up to the preceding stage and a gray code output from a circuit block provided therein. As a result, it is possible to reduce the difference in output timing between the gray codes from the circuit blocks up to the previous stage and the gray code output from the circuit block including the gray code, as compared with the case where the gray codes are divided and generated.

[Embodiment 4]
(Outline of configuration of Gray code generator with delay circuit)
FIG. 5 is a block diagram of the gray code generation unit 60 according to the present embodiment. The gray code counter according to the present embodiment is different from the gray code counter 3 of the previous embodiment in that instead of any circuit block and a synchronous circuit corresponding to the circuit block, a gray code generation shown in FIG. The configuration is different only in including the unit 60. In the following, a description will be given of a configuration in which the Gray code counter 3 includes a Gray code generation unit 60 instead of the circuit block 12 and the synchronization circuit 52 as an example.

  As shown in FIG. 5A, the gray code generator 60 includes a circuit block 12, a synchronization circuit 54, and a delay circuit 61. The circuit block 12 has the same configuration as the circuit block 12 described above. The synchronization circuit 54 includes flip-flop circuits 34 and 35 and a delay circuit 62.

  Also in the present embodiment, the clock signal CK1 output from the preceding circuit block 11 is input to the clock signal input unit CKR of the circuit block 12. Thereby, the circuit block 12 outputs the gray code D2 from the gray code output unit DG. Here, in the present embodiment, the circuit block 12 outputs an intermediate clock signal CKM that is not input to the next-stage circuit block, instead of the clock signal CK2, as the clock signal output from the clock signal output unit CKG.

  In the present embodiment, the gray code D1 output from the preceding circuit block 11 is input to the delay circuit 61. The delay circuit 61 is a delay circuit that gives a delay corresponding to the delay amount of the gray code D2 with respect to the gray code D1 to the input signal. For this reason, the delay circuit 61 generates a delayed Gray code DD, which is a signal obtained by adding a delay corresponding to the delay of the Gray code D2 to the Gray code D1. Therefore, the synchronization deviation between the delayed gray code DD and the gray code D2 is reduced.

  The delay gray code DD output from the delay circuit 61 is integrated not only with the gray code D2 output from the circuit block 12, but also with the intermediate clock signal CKM to become an integrated signal RS1. The integrated signal RS1 is input to the signal input section D of the flip-flop circuit 34. The input clock signal CK0 delayed by the delay circuit 62 is input to the clock signal input unit CKR of the flip-flop circuit 34. The delay circuit 62 has the same configuration as the delay circuit 61, and gives a delay equivalent to the delay amount of the gray code D2 with respect to the gray code D1 to the input signal.

  Here, the flip-flop circuit 34 has a configuration in which the same number of D-type flip-flop circuits as the number of data input to the signal input unit D are arranged in parallel. Specifically, when the gray code generation unit 60 generates an n-bit gray code and the circuit block included in the gray code generation unit 60 is an n-th circuit block, the flip-flop circuit 34 outputs m × n + 1 A D-type flip-flop circuit is provided in parallel. In the present embodiment, the flip-flop circuit 34 includes 2 × 2 + 1 = 5 D-type flip-flop circuits in parallel.

  The signals input to the signal input unit D of the flip-flop circuit 34 are input to the signal input units of the D-type flip-flop circuit included in the flip-flop circuit 34, respectively. The clock signal input section of the D-type flip-flop circuit receives the input clock signal CK0 delayed by the delay circuit 62.

  The data output from the signal output unit of the D-type flip-flop circuit is integrated as an integrated signal RS2 and output from the signal output unit Q of the flip-flop circuit 34. As described above, the integrated signal RS2 is synchronized with the input clock signal CK0 delayed by the delay circuit 62.

  Next, the integrated signal RS2 is input to the signal input unit D of the flip-flop circuit 35. The flip-flop circuit 35 is the last-stage flip-flop circuit among the flip-flop circuits included in the gray code generation unit 60, and has the same configuration as the flip-flop circuit 34. The input clock signal CK0 is directly input to the clock signal input unit CKR of the flip-flop circuit 35 without passing through a delay circuit. As described above, the signal output from the signal output section Q of the flip-flop circuit 35 is synchronized with the non-delayed input clock signal CK0.

  Finally, the signal output from the signal output unit Q of the flip-flop circuit 35 is divided into a gray code D4 and a clock signal CK2, and output from the gray code generation unit 60. Thereafter, the clock signal CK2 may be input to the circuit block 13, and the gray code D4 may be input to the synchronization circuit 53.

  Further, the gray code counter according to the present embodiment may further include a new gray code generation unit having the same configuration as the gray code generation unit 60, instead of the circuit block 13 and the synchronization circuit 53. Further, the gray code D4 and the clock signal CK2 output from the gray code generation unit 60 may be input to the above-described new gray code generation unit.

  In the present embodiment, in the flip-flop circuits 34 and 35, the synchronization shift between the integrated signal and the clock signal input to each flip-flop circuit is reduced. Therefore, the delay of the gray code D4 and the clock signal CK2 with respect to the input clock signal CK0 can be further reduced. In the present embodiment, the signal input to the last-stage flip-flop circuit only needs to have a reduced delay with respect to the input clock signal CK0. It suffices if the circuit 34 or 35 is provided.

  In the present embodiment, the gray code generation unit 60 including the delay circuit 61 outside the synchronization circuit 54 has been described as an example. However, the present invention is not limited to this, and the gray code generation unit 60 may include a synchronization circuit 55 having a delay circuit 61 instead of the synchronization circuit 54 as shown in FIG.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

1-3 Gray code counter 11-13 Circuit block 20 Gray code generation circuit 21 Clock signal generation circuit 31-35 Flip-flop circuit 51-55 Synchronization circuit 60 Gray code generation unit 61, 62 Delay circuit CK0 Input clock signal CK1-3 Clock Signal D0 Output gray code D1-4 Gray code

Claims (7)

A gray code counter including a plurality of circuit blocks each including a gray code generation circuit that generates a gray code based on an input clock signal, and outputting a gray code obtained by integrating gray codes output from each of the plurality of circuit blocks And
A gray code counter, wherein at least one of the plurality of circuit blocks includes a clock signal generation circuit that generates a clock signal to be input to the next circuit block based on an input clock signal.   Each of the circuit blocks outputs an n-bit Gray code that periodically fluctuates from a minimum value to a maximum value based on a clock signal input thereto, where n is an integer of 2 or more. 2. The gray code counter according to claim 1, wherein at least one of the gray code counters inputs a clock signal having a cycle of 2 n times the clock signal input thereto to the next circuit block.   Claims wherein m is an integer of 2 or more, m circuit blocks are provided, and Gray codes from the first to m-th circuit blocks are sequentially integrated to output an n × m-bit Gray code. Item 3. A gray code counter according to item 2.   4. The gray code counter according to claim 1, further comprising a synchronization circuit that synchronizes Gray codes from all of the circuit blocks based on a clock signal input to the first circuit block. 5. .   At least one of the circuit blocks in the second and subsequent stages has a gray code from the circuit blocks up to the previous stage, a gray code output by itself, and a clock signal to be input to the next-stage circuit block. The gray code counter according to any one of claims 1 to 3, further comprising a synchronization circuit that synchronizes the first and second circuit blocks based on a clock signal input to the first-stage circuit block.   6. The gray code counter according to claim 5, wherein the synchronization circuit generates a gray code obtained by integrating a gray code output from the circuit block up to the previous stage and a gray code output from the circuit block provided therein. For a clock signal input from the preceding circuit block, a gray code output by itself, and a delay equivalent to the delay of the clock signal input to the next circuit block, are input from the previous circuit block. A delay circuit to generate a gray code,
The delay Gray code delayed by the delay circuit, the Gray code output by itself, and the clock signal input to the next-stage circuit block are determined based on the clock signal input to the first-stage circuit block. And one or more flip-flop circuits that are synchronized.
6. The gray code counter according to claim 5, wherein a delay of the signal input to the flip-flop circuit of the last stage is reduced with respect to a clock signal input to the circuit block of the first stage.

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