JP2002203905A5 - - Google Patents

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Publication number
JP2002203905A5
JP2002203905A5 JP2000401524A JP2000401524A JP2002203905A5 JP 2002203905 A5 JP2002203905 A5 JP 2002203905A5 JP 2000401524 A JP2000401524 A JP 2000401524A JP 2000401524 A JP2000401524 A JP 2000401524A JP 2002203905 A5 JP2002203905 A5 JP 2002203905A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000401524A
Other versions
JP2002203905A (ja
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Publication date
Application filed filed Critical
Priority to JP2000401524A priority Critical patent/JP2002203905A/ja
Priority claimed from JP2000401524A external-priority patent/JP2002203905A/ja
Priority to US09/900,026 priority patent/US6484303B2/en
Publication of JP2002203905A publication Critical patent/JP2002203905A/ja
Publication of JP2002203905A5 publication Critical patent/JP2002203905A5/ja
Pending legal-status Critical Current

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JP2000401524A 2000-12-28 2000-12-28 レイアウト設計装置、レイアウト設計方法および半導体装置 Pending JP2002203905A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000401524A JP2002203905A (ja) 2000-12-28 2000-12-28 レイアウト設計装置、レイアウト設計方法および半導体装置
US09/900,026 US6484303B2 (en) 2000-12-28 2001-07-09 Apparatus for layout designing of semiconductor device, method of layout designing, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000401524A JP2002203905A (ja) 2000-12-28 2000-12-28 レイアウト設計装置、レイアウト設計方法および半導体装置

Publications (2)

Publication Number Publication Date
JP2002203905A JP2002203905A (ja) 2002-07-19
JP2002203905A5 true JP2002203905A5 (ja) 2008-02-14

Family

ID=18865946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000401524A Pending JP2002203905A (ja) 2000-12-28 2000-12-28 レイアウト設計装置、レイアウト設計方法および半導体装置

Country Status (2)

Country Link
US (1) US6484303B2 (ja)
JP (1) JP2002203905A (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3479052B2 (ja) * 2001-04-23 2003-12-15 沖電気工業株式会社 半導体装置のダミー配置判定方法
US7269818B2 (en) * 2005-01-06 2007-09-11 International Business Machines Corporation Circuit element function matching despite auto-generated dummy shapes
US7343570B2 (en) * 2005-11-02 2008-03-11 International Business Machines Corporation Methods, systems, and media to improve manufacturability of semiconductor devices
KR100730077B1 (ko) * 2005-11-25 2007-06-19 삼성전기주식회사 이미지센서 모듈과 카메라모듈 패키지
KR100755667B1 (ko) * 2006-02-13 2007-09-05 삼성전자주식회사 패턴 밀도가 조절된 반도체 소자의 패턴 데이터 형성방법
KR100817064B1 (ko) * 2006-10-02 2008-03-27 삼성전자주식회사 미세패턴을 형성하기 위한 마스크 및 그 형성방법
KR20080096215A (ko) * 2007-04-27 2008-10-30 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US7763398B2 (en) * 2007-05-02 2010-07-27 Dongbu Hitek Co., Ltd. Layout method for mask
KR100837567B1 (ko) * 2007-05-10 2008-06-11 동부일렉트로닉스 주식회사 마스크의 설계방법
US8225255B2 (en) * 2008-05-21 2012-07-17 International Business Machines Corporation Placement and optimization of process dummy cells
JP4947064B2 (ja) * 2009-01-09 2012-06-06 セイコーエプソン株式会社 半導体装置の製造方法
CN103886150A (zh) * 2014-03-20 2014-06-25 上海华力微电子有限公司 一种冗余图形的填充方法
CN114464613A (zh) * 2020-11-09 2022-05-10 长鑫存储技术有限公司 集成电路的布图方法及布图装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463638A (en) * 1992-05-11 1995-10-31 Jtag Technologies B.V. Control device for interface control between a test machine and multi-channel electronic circuitry, in particular according to boundary test standard
JPH09293721A (ja) 1995-12-15 1997-11-11 Lsi Logic Corp 集積回路構造の処理のためにパターンデザインを改善するための方法
JPH1027796A (ja) * 1996-07-11 1998-01-27 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6218631B1 (en) * 1998-05-13 2001-04-17 International Business Machines Corporation Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk
JP4786006B2 (ja) * 1999-06-08 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置の設計方法および半導体装置の製造方法
JP2001351984A (ja) * 2000-06-08 2001-12-21 Mitsubishi Electric Corp ダミーパターンのレイアウト決定方法、それを用いた半導体装置およびその製造方法
JP4350886B2 (ja) * 2000-12-07 2009-10-21 富士通マイクロエレクトロニクス株式会社 ダミーパターンの配置方法、半導体装置を製造する方法及びｃａｄシステム

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