JP2002198396A - Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device - Google Patents

Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device

Info

Publication number
JP2002198396A
JP2002198396A JP2000395120A JP2000395120A JP2002198396A JP 2002198396 A JP2002198396 A JP 2002198396A JP 2000395120 A JP2000395120 A JP 2000395120A JP 2000395120 A JP2000395120 A JP 2000395120A JP 2002198396 A JP2002198396 A JP 2002198396A
Authority
JP
Japan
Prior art keywords
side electrode
semiconductor device
circuit board
thermosetting resin
resin material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000395120A
Other languages
Japanese (ja)
Inventor
Takahiko Yagi
能彦 八木
Michio Yoshino
道朗 吉野
Kojiro Nakamura
浩二郎 中村
Hiroyuki Otani
博之 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000395120A priority Critical patent/JP2002198396A/en
Publication of JP2002198396A publication Critical patent/JP2002198396A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a method for manufacturing the semiconductor device, and a circuit board for the semiconductor device, which improve connection reliability between a semiconductor component and an object for circuit formation. SOLUTION: A coating specific area 141 is formed, to be coated with a thermosetting resin material 140 which hardens at a preheating temperature lower than a main heating temperature for connecting a mounting board side electrode 107 and a circuit board side electrode 121 with a solder 130. Therefore, when the solder is molten, the thermosetting resin compound 140 has hardened. This prevents a warpage or the like of a semiconductor element mounting board 101 and a semiconductor device circuit board 120 and a connection failure between the mounting board side electrode and the circuit board side electrode, to improve connection reliability.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体部品が回路
形成体へ例えばフリップチップ装着されてなる半導体装
置の製造方法、該製造方法にて製造された半導体装置、
及び該半導体装置用回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor component is mounted, for example, by flip chip mounting on a circuit forming body, a semiconductor device manufactured by the manufacturing method,
And a circuit board for the semiconductor device.

【0002】[0002]

【従来の技術】近年、情報携帯機器等に代表されるよう
に機器の小型、軽量化が要求されている。これを実現さ
せる方法として、リードのない半導体部品であるチップ
サイズパッケージ(CSP)が使われている。このよう
なCSPの回路基板上へ接合する従来の接合方法につい
て図を参照しながら以下に説明する。まず図16に示す
ように、回路基板12の電極13とメタルマスク21の
貫通孔21aとを位置合わせして、回路基板12上にメ
タルマスク21を載置する。そしてメタルマスク21上
をスキージ31にてスキージングすることで、図17に
示すように、上記貫通孔21aを通して回路基板12の
電極13上にクリーム半田41を印刷する。次に図18
に示すように、半導体素子11を取り付けたCSP15
の電極14を回路基板12上の電極13に対向させかつ
位置合わせして、回路基板12上にCSP15を実装す
る。これにて、回路基板12の電極13上のクリーム半
田41とCSP15の電極14とが接触する。次に、こ
のようにして作製された半導体装置16を最高220℃
〜230℃程度まで加熱して、クリーム半田41を溶融
させて、回路基板12の電極13とCSP15の電極1
4とを半田で接合させ、電気的接続をとる。
2. Description of the Related Art In recent years, devices such as portable information devices have been required to be smaller and lighter. As a method for realizing this, a chip size package (CSP), which is a semiconductor component without leads, is used. A conventional bonding method for bonding such a CSP onto a circuit board will be described below with reference to the drawings. First, as shown in FIG. 16, the metal mask 21 is mounted on the circuit board 12 by aligning the electrodes 13 of the circuit board 12 with the through holes 21 a of the metal mask 21. Then, by squeezing the metal mask 21 with a squeegee 31, cream solder 41 is printed on the electrodes 13 of the circuit board 12 through the through holes 21a as shown in FIG. Next, FIG.
As shown in FIG.
The CSP 15 is mounted on the circuit board 12 with the electrode 14 facing the electrode 13 on the circuit board 12 and aligned. Thereby, the cream solder 41 on the electrode 13 of the circuit board 12 and the electrode 14 of the CSP 15 come into contact with each other. Next, the semiconductor device 16 manufactured as described above is heated up to 220 ° C.
Is heated to about 230 ° C. to melt the cream solder 41, and the electrode 13 of the circuit board 12 and the electrode 1 of the CSP 15
And 4 are joined by solder to make an electrical connection.

【0003】[0003]

【発明が解決しようとする課題】上述のように、回路基
板12の電極13とCSP15の電極14とを接合する
ため、従来、上記半導体装置16を最高230℃で、2
00℃以上を30秒間、加熱して上記半田を溶融してい
る。しかしながら上記加熱後、高温から降温するときに
回路基板12及びCSP15が反った場合、上記半田が
溶融状態であるため、上記電極13と電極14との間の
ギャップが変化してしまう。よって上記反り量が大きい
ときには、図19に示すように、電極13と電極14と
の間の導通が取れないオープン不良を引き起こす場合も
あり、接合信頼性の低下を引き起こす。又、回路基板1
2とCSP15との熱膨張係数の差によって電極13と
電極14との接合部に熱歪みが発生し、該接合部にクラ
ックが入るという問題もある。本発明はこのような問題
点を解決するためになされたもので、半導体部品と回路
形成体との間の接合信頼性を高めた、半導体装置、該半
導体装置の製造方法、及び上記半導体装置における回路
基板を提供することを目的とする。
As described above, in order to join the electrode 13 of the circuit board 12 and the electrode 14 of the CSP 15, the semiconductor device 16 has been conventionally heated at 230 ° C.
The solder is melted by heating at 00 ° C. or higher for 30 seconds. However, if the circuit board 12 and the CSP 15 warp when the temperature is lowered from a high temperature after the heating, the gap between the electrodes 13 and 14 changes because the solder is in a molten state. Therefore, when the amount of warpage is large, as shown in FIG. 19, an open failure in which conduction between the electrode 13 and the electrode 14 cannot be obtained may be caused, which causes a reduction in bonding reliability. Circuit board 1
There is also a problem that a thermal expansion is generated at a joint between the electrode 13 and the electrode 14 due to a difference in thermal expansion coefficient between the CSP 15 and the CSP 15, and a crack is formed at the joint. The present invention has been made in order to solve such a problem, and has improved a bonding reliability between a semiconductor component and a circuit forming body, a semiconductor device, a method of manufacturing the semiconductor device, and a semiconductor device. It is an object to provide a circuit board.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明は以下のように構成する。即ち、本発明の第
1態様における半導体装置は、半導体素子を取り付けた
半導体素子取付用基板の取付用基板側電極と、該半導体
素子取付用基板に対向して配置される半導体装置用回路
基板の回路基板側電極とを対向させかつ半田を介して接
合し形成される半導体装置であって、上記取付用基板側
電極と回路基板側電極とを上記半田を介して接合させる
際の本加熱温度よりも低い予備加熱温度にて硬化する絶
縁性の熱硬化型樹脂材が塗布されかつ塗布後の上記熱硬
化型樹脂材の広がりを抑制する塗布専用領域を、上記取
付用基板側電極を形成した取付用基板側電極形成面及び
上記回路基板側電極を形成した回路基板側電極形成面の
少なくとも一方に形成したことを特徴とする。
In order to achieve the above object, the present invention is configured as follows. That is, the semiconductor device according to the first aspect of the present invention includes a mounting substrate-side electrode of a semiconductor element mounting substrate on which a semiconductor element is mounted, and a semiconductor device circuit board disposed to face the semiconductor element mounting substrate. A semiconductor device formed by opposing a circuit board side electrode and bonding via a solder, wherein the heating temperature at the time of bonding the mounting board side electrode and the circuit board side electrode via the solder is Insulating thermosetting resin material that cures at a low preheating temperature is also applied, and a dedicated application area that suppresses the spread of the thermosetting resin material after application is mounted on the mounting substrate-side electrode. The electrode is formed on at least one of the substrate-side electrode forming surface and the circuit-board-side electrode forming surface on which the circuit-board-side electrode is formed.

【0005】上記塗布専用領域は、上記取付用基板側電
極形成面及び上記回路基板側電極形成面の中央部又は周
縁部に配置されてもよい。
[0005] The coating-only area may be arranged at a central portion or a peripheral portion of the mounting substrate-side electrode formation surface and the circuit board-side electrode formation surface.

【0006】上記塗布専用領域は、上記取付用基板側電
極形成面及び上記回路基板側電極形成面に形成された配
線のランドであってもよい。
The coating-only area may be a land of wiring formed on the mounting-substrate-side electrode formation surface and the circuit-board-side electrode formation surface.

【0007】上記塗布専用領域は、上記取付用基板側電
極形成面及び上記回路基板側電極形成面に複数配置され
てもよい。
[0007] A plurality of the application-dedicated regions may be arranged on the mounting-substrate-side electrode formation surface and the circuit-board-side electrode formation surface.

【0008】上記塗布専用領域は、四角形又は円形形状
にてなってもよい。
[0008] The coating-only area may have a square or circular shape.

【0009】上記塗布専用領域は、上記取付用基板側電
極形成面及び上記回路基板側電極形成面における配線に
て囲まれていてもよい。
The dedicated application region may be surrounded by wiring on the mounting substrate-side electrode formation surface and the circuit board-side electrode formation surface.

【0010】さらに、本発明の第2態様の半導体装置用
回路基板は、半導体素子を取り付けた半導体素子取付用
基板の取付用基板側電極に対向して配置される回路基板
側電極を有し、かつ上記半導体素子取付用基板に対向し
て配置され、かつ上記取付用基板側電極に半田を介して
上記回路基板側電極が接合される半導体装置用回路基板
であって、上記取付用基板側電極と回路基板側電極とを
上記半田を介して接合させる際の本加熱温度よりも低い
予備加熱温度にて硬化する絶縁性の熱硬化型樹脂材が塗
布されかつ塗布後の上記熱硬化型樹脂材の広がりを抑制
する塗布専用領域を上記回路基板側電極が形成される回
路基板側電極形成面に備えたことを特徴とする。
Further, a circuit board for a semiconductor device according to a second aspect of the present invention has a circuit board side electrode arranged opposite to a mounting board side electrode of a semiconductor element mounting board on which a semiconductor element is mounted, A circuit board for a semiconductor device, wherein the circuit board-side electrode is bonded to the mounting-substrate-side electrode via solder and is disposed opposite to the semiconductor-element-mounting substrate; And an insulating thermosetting resin material that is cured at a preheating temperature lower than the main heating temperature at the time of joining the substrate and the circuit board side electrode via the solder is applied, and the thermosetting resin material after application is applied. A coating-only area for suppressing the spread of the circuit board-side electrode is provided on the circuit board-side electrode formation surface on which the circuit board-side electrode is formed.

【0011】さらに本発明の第3態様の半導体装置製造
方法は、半導体素子を取り付けた半導体素子取付用基板
の取付用基板側電極が形成される取付用基板側電極形成
面、及び上記半導体素子取付用基板に対向して配置され
る半導体装置用回路基板の回路基板側電極が形成される
回路基板側電極形成面の少なくとも一方に形成した塗布
専用領域に絶縁性の熱硬化型樹脂材を塗布し、上記絶縁
性熱硬化型樹脂材の塗布後、上記取付用基板側電極と上
記回路基板側電極とを半田を介して接合するとき、本加
熱温度よりも低い予備加熱温度に上記絶縁性熱硬化型樹
脂材を加熱して硬化させ、上記絶縁性熱硬化型樹脂材の
硬化後、本加熱して上記取付用基板側電極と上記回路基
板側電極との間の上記半田を溶融させて上記取付用基板
側電極と上記回路基板側電極とを接合する、ことを特徴
とする。
Further, in the method of manufacturing a semiconductor device according to a third aspect of the present invention, there is provided a semiconductor device mounting substrate on which a semiconductor element is mounted. An insulating thermosetting resin material is applied to an application-only area formed on at least one of the circuit board side electrode formation surfaces on which the circuit board side electrodes of the semiconductor device circuit board arranged opposite to the circuit board are formed. After the application of the insulating thermosetting resin material, when the mounting substrate side electrode and the circuit board side electrode are joined via solder, the insulating thermosetting is performed at a preheating temperature lower than the main heating temperature. The mold resin material is cured by heating, and after the insulating thermosetting resin material is cured, the main heating is performed to melt the solder between the mounting board side electrode and the circuit board side electrode, thereby mounting the mold. Substrate side electrode and the above circuit Bonding the plate-side electrode, characterized in that.

【0012】[0012]

【発明の実施の形態】本発明の実施形態における、半導
体装置、該半導体装置の製造方法、及び上記半導体装置
における回路基板について、図を参照しながら以下に説
明する。尚、各図において同じ構成部分については同じ
符号を付している。又、本実施形態における半導体装置
は、上述した従来の半導体装置と同様に、半導体素子を
取り付けた半導体部品を、回路形成体に装着して形成さ
れる構造を例に採る。上記半導体部品として本実施形態
ではCSP(チップサイズパッケージ)を例に採り、図
13から図15には、上記CSPの形態例を図示してい
る。又、上記回路形成体とは、樹脂基板、紙−フェノー
ル基板、セラミック基板、ガラス・エポキシ(ガラエ
ポ)基板、フィルム基板等の回路基板、単層基板若しく
は多層基板などの回路基板、部品、筐体、又は、フレー
ム等、回路が形成されている対象物を意味する。尚、本
実施形態では、上記回路形成体として半導体装置用回路
基板を例に採る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device, a method of manufacturing the semiconductor device, and a circuit board in the semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals. Further, the semiconductor device according to the present embodiment employs, as an example, a structure in which a semiconductor component to which a semiconductor element is attached is mounted on a circuit forming body, similarly to the above-described conventional semiconductor device. In this embodiment, a CSP (chip size package) is taken as an example of the semiconductor component, and FIGS. 13 to 15 show examples of the CSP. Further, the above-mentioned circuit-formed body includes a circuit board such as a resin board, a paper-phenol board, a ceramic board, a glass epoxy (glass epoxy) board, a film board, a circuit board such as a single-layer board or a multilayer board, a component, and a housing. Or an object on which a circuit is formed, such as a frame. In the present embodiment, a circuit board for a semiconductor device is taken as an example of the circuit forming body.

【0013】図13に示すCSP108は、半導体素子
取付用基板101の半導体素子装着面101aに装着さ
れた半導体素子103の電極104と、上記半導体素子
装着面101aに形成されている接続用電極102とを
金線105にて電気的に接続したタイプであり、半導体
素子装着面101aに対向する対向面101bに形成さ
れている取付用基板側電極107と、上記接続用電極1
02とは電気的に接続されている。尚、上記対向面10
1bは、取付用基板側電極形成面に相当する。又、半導
体素子装着面101aに装着された半導体素子103
は、絶縁性の熱硬化型樹脂106にて封止されている。
図14に示すCSP109は、半導体素子103の電極
104と、上記接続用電極102とを直接に接合した、
即ち半導体素子103を半導体素子取付用基板101に
フリップチップ実装してなるタイプである。尚、半導体
素子103と上記半導体素子装着面101aとの隙間
は、樹脂材にて封止されている。図15に示すCSP1
10は、いわゆるリアルCSPと呼ばれるタイプであ
り、半導体素子103上にポリイミド層112を積層
し、該ポリイミド層112上に形成した取付用基板側電
極107と、半導体素子103の電極104とを、ポリ
イミド層112内の銅配線111にて電気的に接続して
いる。よって、該CSP110では、上記ポリイミド層
112が上記半導体素子取付用基板101に相当する。
A CSP 108 shown in FIG. 13 includes an electrode 104 of a semiconductor element 103 mounted on a semiconductor element mounting surface 101a of a semiconductor element mounting substrate 101, and a connection electrode 102 formed on the semiconductor element mounting surface 101a. Are electrically connected to each other by a gold wire 105, and the mounting substrate-side electrode 107 formed on the opposing surface 101b opposing the semiconductor element mounting surface 101a, and the connection electrode 1
02 is electrically connected. The facing surface 10
1b corresponds to the mounting substrate-side electrode forming surface. Also, the semiconductor element 103 mounted on the semiconductor element mounting surface 101a
Are sealed with an insulating thermosetting resin 106.
The CSP 109 illustrated in FIG. 14 directly joins the electrode 104 of the semiconductor element 103 and the connection electrode 102,
That is, the semiconductor element 103 is flip-chip mounted on the semiconductor element mounting substrate 101. The gap between the semiconductor element 103 and the semiconductor element mounting surface 101a is sealed with a resin material. CSP1 shown in FIG.
Reference numeral 10 denotes a type called a so-called real CSP, in which a polyimide layer 112 is laminated on the semiconductor element 103, and the mounting substrate side electrode 107 formed on the polyimide layer 112 and the electrode 104 of the semiconductor element 103 are formed by polyimide. They are electrically connected by the copper wiring 111 in the layer 112. Therefore, in the CSP 110, the polyimide layer 112 corresponds to the semiconductor element mounting substrate 101.

【0014】本実施形態における半導体装置について説
明する。図1に示すように、本実施形態の半導体装置1
70は、上記CSP108〜110(代表してCSP1
08を例に採る場合もある)のいずれかに備わる上記半
導体素子取付用基板101の上記取付用基板側電極10
7と、該半導体素子取付用基板101に対向して配置さ
れる半導体装置用回路基板120の回路基板側電極12
1とを対向させかつ半田130を介して接合し形成さ
れ、さらに半導体素子取付用基板101と半導体装置用
回路基板120とを絶縁性の熱硬化型樹脂材140にて
固定している。熱硬化型樹脂材140は、エポキシ系樹
脂やシリコーン系樹脂等でもよく、熱硬化型樹脂材や紫
外線硬化樹脂等の、硬化する絶縁性樹脂材であればよ
く、又、本実施形態では液状である。熱硬化型樹脂材1
40は、例えば50μm〜1mmの厚みでφ0.5〜φ
5mmの寸法を有する例えばシート状であってもよい。
The semiconductor device according to the present embodiment will be described. As shown in FIG. 1, a semiconductor device 1 of the present embodiment
70 is the CSP 108 to 110 (typically, CSP 1
08 may be taken as an example). The mounting substrate side electrode 10 of the semiconductor element mounting substrate 101 provided in any one of
7 and a circuit board-side electrode 12 of a circuit board 120 for a semiconductor device, which is disposed to face the semiconductor element mounting board 101.
The semiconductor device mounting substrate 101 and the semiconductor device circuit substrate 120 are fixed with an insulating thermosetting resin material 140. The thermosetting resin material 140 may be an epoxy resin, a silicone resin, or the like, and may be any insulating resin material that can be cured, such as a thermosetting resin material or an ultraviolet curable resin. is there. Thermosetting resin material 1
40 has a thickness of, for example, 50 μm to 1 mm and φ0.5 to φ
For example, it may be a sheet having a dimension of 5 mm.

【0015】上記熱硬化型樹脂材140は、上記半導体
装置用回路基板120において上記回路基板側電極12
1を形成している電極形成面120a、及び上記半導体
素子取付用基板101において上記取付用基板側電極1
07を形成している上記対向面101bの少なくとも一
方に、独立して設けられた塗布専用領域141上に塗布
される。尚、図2及び図3は、半導体装置用回路基板1
20の電極形成面120aに塗布専用領域141を設け
た場合を図示している。上記塗布専用領域141は、上
記熱硬化型樹脂材140の塗布後、該熱硬化型樹脂材1
40が当該塗布専用領域141を超えて外側に広がるの
を抑制する領域であり、各基板上への配線電極の形成工
程にて形成した上記配線電極と同一材料、例えば銅、金
等にて、又はレジスト材やシルク材料にて形成される。
又、塗布専用領域141の形成場所は、図2に示すよう
に、半導体装置用回路基板120及び半導体素子取付用
基板101の例えば中央部分120bであって上記回路
基板側電極121及び配線122と干渉しない場所であ
る。このように、半導体装置用回路基板120に設けた
塗布専用領域141が電極で形成されているため、熱硬
化型樹脂材140は基材表面よりぬれやすいので、塗布
専用領域141外への広がりを抑制することができる。
The thermosetting resin material 140 is provided on the circuit board side electrode 12 of the semiconductor device circuit board 120.
1 on the electrode forming surface 120a and the mounting substrate side electrode 1 on the semiconductor element mounting substrate 101.
07 is applied to at least one of the above-mentioned opposing surfaces 101b on an application-only area 141 provided independently. 2 and 3 show the circuit board 1 for a semiconductor device.
The figure shows a case where a coating-only area 141 is provided on the electrode forming surface 120a of No. 20. After the application of the thermosetting resin material 140, the thermosetting resin material 1
Reference numeral 40 denotes a region that suppresses outward spreading beyond the coating-only region 141, and is made of the same material as the wiring electrodes formed in the process of forming the wiring electrodes on each substrate, such as copper or gold. Alternatively, it is formed of a resist material or a silk material.
As shown in FIG. 2, the formation area of the application-only area 141 is, for example, a central portion 120 b of the semiconductor device circuit board 120 and the semiconductor element mounting board 101, and interferes with the circuit board side electrode 121 and the wiring 122. Not a place. As described above, since the coating-only area 141 provided on the semiconductor device circuit board 120 is formed of the electrode, the thermosetting resin material 140 is more easily wetted than the base material surface. Can be suppressed.

【0016】次に当該半導体装置170の製造方法につ
いて、図6〜図8を参照して説明する。まずステップ1
として、図6に示すように、従来と同様にメタルマスク
を用いて、上記半導体装置用回路基板120の上記回路
基板側電極121上にクリーム半田130を塗布する。
尚、該クリーム半田130の代わりに、導電性接着剤を
塗布することもできる。次のステップ2では、図7に示
すように、上記塗布専用領域141上にディスペンサー
190等を用いて絶縁性の熱硬化型樹脂材140を供給
する。供給された熱硬化型樹脂材140は、塗布専用領
域141の全領域を覆うように広がる。尚、ディスペン
サー190等は、制御装置191にて動作制御されてい
る。次のステップ3では、図8に示すように、上記回路
基板側電極121に、上記半導体素子取付用基板101
の上記取付用基板側電極107を位置合わせして、上記
クリーム半田130もしくは導電性接着剤にて電気的接
続を図るとともに、上記熱硬化型樹脂材140にて半導
体装置用回路基板120と半導体素子取付用基板101
との接着を図る。次のステップ4では、ステップ3にて
作製された貼り合わされた半導体装置用回路基板120
及び半導体素子取付用基板101がリフロー炉等、又は
硬化炉等に搬入されて、クリーム半田130内の半田が
溶融する温度又は上記導電性接着剤が硬化する本加熱温
度まで本加熱される。尚、上記半田が溶融する上記本加
熱温度は、最高約220℃〜230℃であり、上記導電
性接着剤が硬化する上記本加熱温度は、約150℃であ
る。
Next, a method of manufacturing the semiconductor device 170 will be described with reference to FIGS. First step 1
As shown in FIG. 6, a cream solder 130 is applied on the circuit board-side electrode 121 of the semiconductor device circuit board 120 using a metal mask as in the related art.
Note that, instead of the cream solder 130, a conductive adhesive may be applied. In the next step 2, as shown in FIG. 7, an insulating thermosetting resin material 140 is supplied onto the coating-only area 141 using a dispenser 190 or the like. The supplied thermosetting resin material 140 spreads so as to cover the entire area of the application-only area 141. The operation of the dispenser 190 and the like is controlled by the control device 191. In the next step 3, as shown in FIG. 8, the semiconductor element mounting substrate 101 is attached to the circuit board side electrode 121.
The mounting substrate-side electrode 107 is positioned and electrically connected with the cream solder 130 or a conductive adhesive, and the thermosetting resin material 140 is used to connect the semiconductor device circuit board 120 and the semiconductor element. Mounting substrate 101
Adhesion with In the next step 4, the bonded semiconductor device circuit board 120 produced in step 3 is bonded.
Then, the substrate 101 for mounting a semiconductor element is carried into a reflow oven or the like or a curing oven or the like, and is finally heated to a temperature at which the solder in the cream solder 130 melts or a main heating temperature at which the conductive adhesive is cured. The main heating temperature at which the solder melts is at most about 220 ° C. to 230 ° C., and the main heating temperature at which the conductive adhesive cures is about 150 ° C.

【0017】一方、熱硬化型樹脂材140の硬化温度で
ある予備加熱温度は、150℃であるので、上記本加熱
温度よりも低い。よって、リフロー動作における最高温
度時点やその後の冷却時点のように、クリーム半田13
0が溶融し、又は上記導電性接着剤が硬化する上記本加
熱温度では、熱硬化型樹脂材140は硬化を完了してお
り、半導体装置用回路基板120と半導体素子取付用基
板101とは固定された状態になっている。よって、ク
リーム半田130が溶融状態で接合部のギャップを一定
に保持できない状態となっても、熱硬化型樹脂材140
にて上記ギャップを一定に保持し、CSP108〜11
0、半導体装置用回路基板120の反りを抑制すること
ができる。したがって、CSP108〜110における
上記取付用基板側電極107と、上記半導体装置用回路
基板120の上記回路基板側電極121との接合部分に
クラックや、電気的接続不良が発生するのを防止でき
る。よって、上記取付用基板側電極107と、上記回路
基板側電極121との接合の信頼性を従来に比べて向上
させることができる。尚、クリーム半田130が溶融し
て固化し若しくは上記導電性接着剤が硬化し、及び熱硬
化型樹脂材140の硬化することで、図9に示すよう
に、半導体装置170が完成する。又、上記塗布専用領
域141は、その全領域を上記配線電極と同一材料、又
はレジスト材やシルク材料にて形成しており、上記全領
域上に上記熱硬化型樹脂材140を塗布することから、
熱硬化型樹脂材140の広がりを抑制することができ
る。例えば、塗布専用領域141の全領域を銅にて形成
することで、熱硬化型樹脂材140は、上記銅に沿って
広がるため、塗布専用領域141以外への熱硬化型樹脂
材140の広がりを防止できる。又、後述するように、
熱硬化型樹脂材140の塗布領域の周辺を例えば銅にて
囲むことで該囲みを超えて熱硬化型樹脂材140が広が
るのを防止することができる。
On the other hand, the preheating temperature which is the curing temperature of the thermosetting resin material 140 is 150 ° C., which is lower than the main heating temperature. Accordingly, the cream solder 13 may be used as in the case of the highest temperature in the reflow operation or the subsequent cooling.
At the main heating temperature at which 0 melts or the conductive adhesive is cured, the thermosetting resin material 140 has been completely cured, and the semiconductor device circuit board 120 and the semiconductor element mounting board 101 are fixed. It is in the state that was done. Accordingly, even when the cream solder 130 is in a molten state and the gap of the joint cannot be kept constant, the thermosetting resin material 140
CSP108 ~ 11
0, the warpage of the semiconductor device circuit board 120 can be suppressed. Therefore, it is possible to prevent cracks and poor electrical connection from occurring at the joint portions between the mounting substrate-side electrodes 107 in the CSPs 108 to 110 and the circuit board-side electrodes 121 of the semiconductor device circuit board 120. Therefore, the reliability of the connection between the mounting substrate-side electrode 107 and the circuit board-side electrode 121 can be improved as compared with the related art. The semiconductor device 170 is completed as shown in FIG. 9 by melting and solidifying the cream solder 130 or curing the conductive adhesive and curing the thermosetting resin material 140. The entire area of the application-only area 141 is formed of the same material as that of the wiring electrodes, or a resist material or a silk material, and the thermosetting resin material 140 is applied over the entire area. ,
The spread of the thermosetting resin material 140 can be suppressed. For example, since the entire region of the application-only region 141 is formed of copper, the thermosetting resin material 140 spreads along the copper, so that the expansion of the thermosetting resin material 140 to regions other than the application-only region 141 is increased. Can be prevented. Also, as described below,
By surrounding the periphery of the application region of the thermosetting resin material 140 with, for example, copper, it is possible to prevent the thermosetting resin material 140 from spreading beyond the surrounding.

【0018】上述した半導体装置170では、図2に示
すように、上記中央部分120bの一箇所に塗布専用領
域141を形成している。しかしながら、図4に示す半
導体装置171のように、上記中央部分120bに、上
記配線122を用いて複数の塗布専用領域141を形成
することもできる。このように複数の塗布専用領域14
1を設け、これらのそれぞれに上記熱硬化型樹脂材14
0を塗布して上記半導体素子取付用基板101と上記半
導体装置用回路基板120とを接合することで、接合後
において熱硬化型樹脂材140に作用する応力を各熱硬
化型樹脂材140に分散させることができる。よって、
半導体素子取付用基板101、つまり半導体素子103
に作用する応力を小さくすることができる。
In the above-described semiconductor device 170, as shown in FIG. 2, a coating-only area 141 is formed at one position of the central portion 120b. However, as in the case of the semiconductor device 171 shown in FIG. 4, a plurality of application-only regions 141 can be formed in the central portion 120b by using the wiring 122. As described above, the plurality of application-only areas 14
1 and each of these is provided with the thermosetting resin material 14.
0 is applied and the semiconductor element mounting substrate 101 and the semiconductor device circuit board 120 are joined to each other, so that the stress acting on the thermosetting resin material 140 after joining is dispersed to each thermosetting resin material 140. Can be done. Therefore,
The semiconductor element mounting substrate 101, that is, the semiconductor element 103
Can be reduced.

【0019】又、図5に示す半導体装置172のよう
に、半導体装置用回路基板120及び半導体素子取付用
基板101の少なくとも一方における周縁部120c、
特に四隅に、それぞれ一若しくは複数個ずつ、基板に形
成されている例えば配線やレジスト等を用いて上記塗布
専用領域141を形成することもできる。このように基
板の周縁部120c、特に四隅に塗布専用領域141を
設けることで、最も応力が作用するCSP108〜11
0の角に相当する四隅部分について、上記応力を分散さ
せることができ、半導体素子取付用基板101、つまり
半導体素子103に作用する応力を小さくすることがで
きる。又、塗布専用領域141を上述の中央部分120
bに設ける場合に比べて、上記半導体装置用回路基板1
20をより広範囲にて支持するので、半導体装置用回路
基板120の反りを抑制することもできる。
Further, as in a semiconductor device 172 shown in FIG. 5, a peripheral portion 120c of at least one of the semiconductor device circuit board 120 and the semiconductor element mounting board 101 is provided.
In particular, the coating-only area 141 can be formed at each of the four corners by using, for example, a wiring, a resist, or the like formed on the substrate, one or more each. By providing the coating-only regions 141 at the peripheral portion 120c of the substrate, particularly at the four corners, the CSPs 108 to 11 where the most stress acts are provided.
The stress can be dispersed at the four corners corresponding to the zero angle, and the stress acting on the semiconductor element mounting substrate 101, that is, the semiconductor element 103 can be reduced. In addition, the application-only area 141 is connected to the central
b, the circuit board 1 for a semiconductor device
Since the substrate 20 is supported in a wider range, the warpage of the semiconductor device circuit board 120 can be suppressed.

【0020】さらに又、上記半導体装置170〜172
において、図10に示すように上記半導体素子取付用基
板101と上記半導体装置用回路基板120との隙間
に、液状の熱硬化型樹脂材180を注入し、硬化して、
上記取付用基板側電極107と上記回路基板側電極12
1との接合部の周辺を封止してもよい。これにより半導
体素子取付用基板101と半導体装置用回路基板120
との隙間、特に上記接合部周辺の耐湿性を向上させるこ
とができ、及び耐熱信頼性を向上させることができる。
Further, the semiconductor devices 170 to 172
In FIG. 10, a liquid thermosetting resin material 180 is injected into a gap between the semiconductor element mounting board 101 and the semiconductor device circuit board 120, and is cured.
The mounting board side electrode 107 and the circuit board side electrode 12
The periphery of the joint with the first member may be sealed. Thereby, the semiconductor element mounting substrate 101 and the semiconductor device circuit substrate 120
, In particular, the moisture resistance in the vicinity of the joint, and the heat resistance can be improved.

【0021】又、上記半導体装置170〜172の内例
えば半導体装置170を例に採ると、図2に示すよう
に、塗布専用領域141の平面形状は円形である。しか
しながら、その形状は特に限定されるものではなく、図
11に示すように、例えば楕円、ひし形等の形状であっ
てもよい。このような形状にすることで、液状の熱硬化
型樹脂材180が塗布されるCSP108〜110の一
側面115に対して、流線型形状とみなせる楕円やひし
形等の形状であるため、CSP108〜110と半導体
装置用回路基板120との隙間に液状の熱硬化型樹脂材
180が毛細管現象で例えば矢印116方向に進入して
いくとき、CSP108〜110の中心部に設けられて
いる塗布専用領域142に沿って流れ、塗布専用領域1
41の後部に流れのよどみ箇所、つまり流れのない箇所
が発生せず、気泡が発生しないため、信頼性の高い接合
が得られる。
When the semiconductor device 170 of the semiconductor devices 170 to 172 is taken as an example, as shown in FIG. 2, the planar shape of the application-only region 141 is circular. However, the shape is not particularly limited, and may be, for example, an ellipse, a diamond, or the like, as shown in FIG. With such a shape, the CSPs 108 to 110 have a shape such as an ellipse or a diamond that can be regarded as a streamlined shape with respect to one side surface 115 of the CSPs 108 to 110 to which the liquid thermosetting resin material 180 is applied. When the liquid thermosetting resin material 180 enters the gap with the semiconductor device circuit board 120 by capillary action, for example, in the direction of arrow 116, the liquid thermosetting resin material 180 extends along the application-only area 142 provided at the center of the CSPs 108 to 110. Flow, coating only area 1
Since no stagnation portion of the flow, that is, a portion where there is no flow, does not occur at the rear portion of 41, and no bubble is generated, a highly reliable bonding can be obtained.

【0022】さらに又、上記塗布専用領域の形状を図1
2に示すような例えばドーナツ状とすることもできる。
即ち、塗布専用領域143では、その周縁部143bの
みを上記配線用の材料にて形成し、その中央部分143
aに上記熱硬化型樹脂材140が塗布される。尚、周縁
部143bの高さは、基板上の配線の高さと同じでよ
い。該構成によれば、熱硬化型樹脂材140は上述のよ
うに上記配線用材料に沿って広がるため、上記周縁部1
43bが障壁となり、塗布された熱硬化型樹脂材140
が時間経過や熱の影響により上記中央部分143aから
外へ漏れ出ることはなく、塗布専用領域143の周囲に
配置されている接合部の電極121を汚すことがない。
よって、さらに信頼性の高い接合を行なうことができ
る。
Further, the shape of the above-mentioned coating-only area is shown in FIG.
For example, a donut shape as shown in FIG.
That is, in the application-only region 143, only the peripheral portion 143b is formed of the wiring material, and the central portion 143b is formed.
The thermosetting resin material 140 is applied to a. Note that the height of the peripheral portion 143b may be the same as the height of the wiring on the substrate. According to this configuration, since the thermosetting resin material 140 spreads along the wiring material as described above, the peripheral portion 1
43b is a barrier, and the applied thermosetting resin material 140
Does not leak out from the central portion 143a due to the passage of time or the influence of heat, and does not contaminate the electrode 121 of the joint disposed around the coating-only area 143.
Therefore, more reliable bonding can be performed.

【0023】[0023]

【発明の効果】以上詳述したように本発明の第1態様の
半導体装置、第2態様の半導体装置用回路基板、及び第
3態様の半導体装置製造方法によれば、塗布専用領域を
設け、取付用基板側電極と回路基板側電極とを半田を介
して接合するときの本加熱温度よりも低い予備加熱温度
にて硬化する熱硬化型樹脂材を上記塗布専用領域に塗布
するようにした。よって、上記半田が溶融状態にあると
きには、上記熱硬化型樹脂材は既に硬化しており、上記
取付用基板側電極が備わる半導体素子取付用基板と上記
回路基板側電極が備わる半導体装置用回路基板とは上記
熱硬化型樹脂材にて固定されている。したがって、上記
半導体素子取付用基板及び上記半導体装置用回路基板の
反り等の発生を抑えることができ、上記取付用基板側電
極と上記回路基板側電極との接合部にクラック等が生じ
たり、接合不良が生じるのを防止でき、上記接合部の接
合信頼性を高めることができる。
As described above in detail, according to the semiconductor device of the first aspect, the circuit board for a semiconductor device of the second aspect, and the method of manufacturing a semiconductor device of the third aspect of the present invention, a coating-only area is provided. A thermosetting resin material that cures at a preheating temperature lower than the main heating temperature when the mounting substrate-side electrode and the circuit board-side electrode are joined via solder is applied to the dedicated application region. Therefore, when the solder is in a molten state, the thermosetting resin material is already cured, and the semiconductor device mounting board provided with the mounting board side electrode and the semiconductor device circuit board provided with the circuit board side electrode are provided. Is fixed by the thermosetting resin material. Therefore, it is possible to suppress the occurrence of warpage or the like of the semiconductor element mounting substrate and the semiconductor device circuit substrate, and to cause cracks or the like at the bonding portion between the mounting substrate side electrode and the circuit substrate side electrode. The occurrence of defects can be prevented, and the joint reliability of the joint can be improved.

【0024】又、上記取付用基板側電極を形成した取付
用基板側電極形成面、及び上記回路基板側電極を形成し
た回路基板側電極形成面の、特に周縁部に上記塗布専用
領域を配置し上記熱硬化型樹脂材を塗布することで、上
記半導体素子取付用基板及び上記半導体装置用回路基板
に作用する応力を分散することができ、半導体素子へ作
用する応力を削減することができる。さらに又、複数の
塗布専用領域を設けて上記熱硬化型樹脂材を塗布するこ
とでも、上記応力の分散を図ることができる。
In addition, the coating-dedicated area is arranged on the mounting-substrate-side electrode forming surface on which the mounting-substrate-side electrode is formed, and on the circuit-board-side electrode forming surface on which the circuit-board-side electrode is formed, particularly at the peripheral edge. By applying the thermosetting resin material, the stress acting on the semiconductor element mounting substrate and the semiconductor device circuit board can be dispersed, and the stress acting on the semiconductor element can be reduced. Further, the stress can be dispersed by providing a plurality of application-dedicated regions and applying the thermosetting resin material.

【0025】又、上記塗布専用領域を配線のランドを使
用することで、上記塗布専用領域を形成するための工程
を設ける必要が無く、製造工程上有利である。
Further, by using the land of the wiring for the coating-only area, there is no need to provide a step for forming the coating-only area, which is advantageous in the manufacturing process.

【0026】又、上記塗布専用領域を円形状又は四角形
状とし上記熱硬化型樹脂材を塗布することで、上記半導
体素子取付用基板及び上記半導体装置用回路基板との隙
間に封止用樹脂が進入していくとき、上記熱硬化型樹脂
材の後部によどみが発生せず、気泡の発生を抑制するこ
とができる。よって、より高い接合信頼性を得ることが
できる。
[0026] Further, by forming the application-only area in a circular or square shape and applying the thermosetting resin material, a sealing resin is provided in a gap between the semiconductor element mounting substrate and the semiconductor device circuit substrate. When entering, stagnation does not occur at the rear of the thermosetting resin material, and generation of bubbles can be suppressed. Therefore, higher joining reliability can be obtained.

【0027】又、周縁部のみを配線材料にて取り囲んだ
形状にて上記塗布専用領域を形成することで、上記熱硬
化型樹脂材は上記周縁部から外へ漏れ出すことを防止で
きる。よって、上記熱硬化型樹脂材が接合部の電極に流
れ広がって汚染することを防止でき、接続信頼性をより
高めることができる。
Further, by forming the coating-only area in a shape in which only the peripheral portion is surrounded by the wiring material, it is possible to prevent the thermosetting resin material from leaking out from the peripheral portion. Therefore, it is possible to prevent the thermosetting resin material from flowing and spreading to the electrode at the joint portion and to contaminate it, and it is possible to further improve connection reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施形態の半導体装置の側面図であ
る。
FIG. 1 is a side view of a semiconductor device according to an embodiment of the present invention.

【図2】 図1に示す半導体装置を構成する半導体装置
用回路基板の平面図である。
FIG. 2 is a plan view of a circuit board for a semiconductor device constituting the semiconductor device shown in FIG. 1;

【図3】 図2に示す半導体装置用回路基板の側面図で
ある。
FIG. 3 is a side view of the semiconductor device circuit board shown in FIG. 2;

【図4】 図1に示す半導体装置の変形例における側面
図である。
FIG. 4 is a side view of a modification of the semiconductor device shown in FIG. 1;

【図5】 図1に示す半導体装置の他の変形例における
側面図である。
FIG. 5 is a side view of another modification of the semiconductor device shown in FIG. 1;

【図6】 図1に示す半導体装置の製造方法を説明する
ための図である。
FIG. 6 is a diagram for explaining the method for manufacturing the semiconductor device shown in FIG.

【図7】 図1に示す半導体装置の製造方法を説明する
ための図である。
FIG. 7 is a view illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1;

【図8】 図1に示す半導体装置の製造方法を説明する
ための図である。
FIG. 8 is a view illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1;

【図9】 図1に示す半導体装置の製造方法を説明する
ための図である。
FIG. 9 is a view illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1;

【図10】 図1に示す半導体装置の別の変形例におけ
る側面図である。
FIG. 10 is a side view of another modified example of the semiconductor device shown in FIG. 1;

【図11】 図2に示す半導体装置用回路基板の変形例
における平面図である。
FIG. 11 is a plan view of a modification of the circuit board for a semiconductor device shown in FIG. 2;

【図12】 図2に示す半導体装置用回路基板のさらに
他の変形例における平面図である。
FIG. 12 is a plan view of still another modification of the circuit board for a semiconductor device shown in FIG. 2;

【図13】 CSPの形態を一例を示す図である。FIG. 13 is a diagram illustrating an example of a form of a CSP.

【図14】 CSPの形態を他の例を示す図である。FIG. 14 is a diagram showing another example of the form of the CSP.

【図15】 CSPの形態をさらに別の例を示す図であ
る。
FIG. 15 is a diagram showing still another example of the form of the CSP.

【図16】 従来の半導体装置を作製する工程を説明す
るための図である。
FIG. 16 is a view illustrating a step of manufacturing a conventional semiconductor device.

【図17】 従来の半導体装置を作製する工程を説明す
るための図である。
FIG. 17 is a diagram illustrating a step of manufacturing a conventional semiconductor device.

【図18】 従来の半導体装置を作製する工程を説明す
るための図である。
FIG. 18 is a view illustrating a step of manufacturing a conventional semiconductor device.

【図19】 従来の半導体装置において接合部にて接触
不良が発生した状態を示す図である。
FIG. 19 is a diagram showing a state in which a contact failure has occurred at a junction in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

101…半導体素子取付用基板、101b…取付用基板
側電極形成面、103…半導体素子、107…取付用基
板側電極、120…半導体装置用回路基板、120a…
電極形成面、120b…中央部、120c…周縁部、1
21…回路基板側電極、140…熱硬化型樹脂材、14
1…塗布専用領域、170〜172…半導体装置。
101: semiconductor element mounting substrate, 101b: mounting substrate side electrode forming surface, 103: semiconductor element, 107: mounting substrate side electrode, 120: semiconductor device circuit board, 120a ...
Electrode forming surface, 120b central part, 120c peripheral part, 1
21: Circuit board side electrode, 140: Thermosetting resin material, 14
1 ... Area dedicated to application, 170-172 ... Semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 浩二郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 大谷 博之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E319 AA03 AB05 AB10 AC02 AC04 AC20 BB05 BB11 BB20 CC33 CC61 CC70 CD45 GG11 5F044 LL11 RR18 RR19 5F061 AA01 BA04 CA05 CB02 CB12 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kojiro Nakamura 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroyuki Otani 1006 Kadoma Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co. Terms (reference) 5E319 AA03 AB05 AB10 AC02 AC04 AC20 BB05 BB11 BB20 CC33 CC61 CC70 CD45 GG11 5F044 LL11 RR18 RR19 5F061 AA01 BA04 CA05 CB02 CB12

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子(103)を取り付けた半導
体素子取付用基板(101)の取付用基板側電極(10
7)と、該半導体素子取付用基板に対向して配置される
半導体装置用回路基板(120)の回路基板側電極(1
21)とを対向させかつ半田を介して接合し形成される
半導体装置であって、 上記取付用基板側電極と回路基板側電極とを上記半田を
介して接合させる際の本加熱温度よりも低い予備加熱温
度にて硬化する絶縁性の熱硬化型樹脂材(140)が塗
布されかつ塗布後の上記熱硬化型樹脂材の広がりを抑制
する塗布専用領域(141)を、上記取付用基板側電極
を形成した取付用基板側電極形成面(101b)及び上
記回路基板側電極を形成した回路基板側電極形成面(1
20a)の少なくとも一方に形成したことを特徴とする
半導体装置。
An electrode (10) on a mounting substrate side of a semiconductor device mounting substrate (101) on which a semiconductor device (103) is mounted.
7) and a circuit board-side electrode (1) of the semiconductor device circuit board (120) arranged to face the semiconductor element mounting board.
21) is formed by opposing and bonding via a solder, which is lower than the main heating temperature when the mounting substrate side electrode and the circuit board side electrode are bonded via the solder. An application-only area (141) to which an insulating thermosetting resin material (140) that is cured at a preheating temperature is applied and that suppresses the spread of the thermosetting resin material after application is formed by the mounting substrate-side electrode. The mounting substrate-side electrode formation surface (101b) on which is formed the circuit board-side electrode formation surface (1
20a) A semiconductor device formed on at least one of them.
【請求項2】 上記塗布専用領域は、上記取付用基板側
電極形成面及び上記回路基板側電極形成面の中央部(1
20b)又は周縁部(120c)に配置される、請求項
1記載の半導体装置。
2. The coating-dedicated area is provided at a central portion (1) of the mounting substrate-side electrode formation surface and the circuit board-side electrode formation surface.
2. The semiconductor device according to claim 1, wherein the semiconductor device is arranged on the periphery (120 b).
【請求項3】 上記塗布専用領域は、上記取付用基板側
電極形成面及び上記回路基板側電極形成面に形成された
配線のランドである、請求項1又は2記載の半導体装
置。
3. The semiconductor device according to claim 1, wherein the coating-only area is a land of wiring formed on the mounting-substrate-side electrode forming surface and the circuit-board-side electrode forming surface.
【請求項4】 上記塗布専用領域は、上記取付用基板側
電極形成面及び上記回路基板側電極形成面に複数配置さ
れる、請求項1から3のいずれかに記載の半導体装置。
4. The semiconductor device according to claim 1, wherein a plurality of the application-dedicated regions are arranged on the mounting-substrate-side electrode formation surface and the circuit-board-side electrode formation surface.
【請求項5】 上記塗布専用領域は、四角形又は円形形
状にてなる、請求項1から4のいずれかに記載の半導体
装置。
5. The semiconductor device according to claim 1, wherein the dedicated application region has a rectangular shape or a circular shape.
【請求項6】 上記塗布専用領域は、上記取付用基板側
電極形成面及び上記回路基板側電極形成面における配線
にて囲まれている、請求項1、2、4、5のいずれかに
記載の半導体装置。
6. The circuit according to claim 1, wherein the coating-only area is surrounded by wiring on the mounting-substrate-side electrode formation surface and the circuit-board-side electrode formation surface. Semiconductor device.
【請求項7】 半導体素子(103)を取り付けた半導
体素子取付用基板(101)の取付用基板側電極(10
7)に対向して配置される回路基板側電極(121)を
有し、かつ上記半導体素子取付用基板に対向して配置さ
れ、かつ上記取付用基板側電極に半田を介して上記回路
基板側電極が接合される半導体装置用回路基板(12
0)であって、 上記取付用基板側電極と回路基板側電極とを上記半田を
介して接合させる際の本加熱温度よりも低い予備加熱温
度にて硬化する絶縁性の熱硬化型樹脂材(140)が塗
布されかつ塗布後の上記熱硬化型樹脂材の広がりを抑制
する塗布専用領域(141)を上記回路基板側電極が形
成される回路基板側電極形成面(120a)に備えたこ
とを特徴とする半導体装置用回路基板。
7. A mounting substrate side electrode (10) of a semiconductor device mounting substrate (101) to which a semiconductor device (103) is mounted.
7) a circuit board side electrode (121) arranged opposite to the semiconductor element mounting board, and arranged opposite to the semiconductor element mounting board, and the circuit board side electrode being soldered to the mounting board side electrode; Circuit board for semiconductor device (12
0), wherein an insulating thermosetting resin material that is cured at a preheating temperature lower than the main heating temperature when the mounting substrate side electrode and the circuit board side electrode are joined via the solder. 140) is provided on the circuit board-side electrode formation surface (120a) on which the circuit board-side electrode is formed, and a dedicated application area (141) on which the thermosetting resin material is spread after application is suppressed. A circuit board for a semiconductor device.
【請求項8】 半導体素子(103)を取り付けた半導
体素子取付用基板(101)の取付用基板側電極(10
7)が形成される取付用基板側電極形成面(101
b)、及び上記半導体素子取付用基板に対向して配置さ
れる半導体装置用回路基板(120)の回路基板側電極
(121)が形成される回路基板側電極形成面(120
a)の少なくとも一方に形成した塗布専用領域(14
1)に絶縁性の熱硬化型樹脂材(140)を塗布し、 上記絶縁性熱硬化型樹脂材の塗布後、上記取付用基板側
電極と上記回路基板側電極とを半田を介して接合すると
き、本加熱温度よりも低い予備加熱温度に上記絶縁性熱
硬化型樹脂材を加熱して硬化させ、 上記絶縁性熱硬化型樹脂材の硬化後、本加熱して上記取
付用基板側電極と上記回路基板側電極との間の上記半田
を溶融させて上記取付用基板側電極と上記回路基板側電
極とを接合する、ことを特徴とする半導体装置製造方
法。
8. A mounting substrate side electrode (10) of a semiconductor device mounting substrate (101) on which a semiconductor device (103) is mounted.
7) The mounting substrate-side electrode forming surface (101) on which the
b) and the circuit board side electrode formation surface (120) on which the circuit board side electrode (121) of the semiconductor device circuit board (120) arranged opposite to the semiconductor element mounting board is formed.
a) dedicated application region (14) formed on at least one of
1) An insulating thermosetting resin material (140) is applied, and after the insulating thermosetting resin material is applied, the mounting board side electrode and the circuit board side electrode are joined via solder. When the insulating thermosetting resin material is heated and cured at a preheating temperature lower than the main heating temperature, and after the insulating thermosetting resin material is cured, the main heating is performed and the mounting substrate side electrode and A method of manufacturing a semiconductor device, comprising melting the solder between the circuit board side electrode and joining the mounting board side electrode and the circuit board side electrode.
JP2000395120A 2000-12-26 2000-12-26 Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device Pending JP2002198396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000395120A JP2002198396A (en) 2000-12-26 2000-12-26 Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000395120A JP2002198396A (en) 2000-12-26 2000-12-26 Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device

Publications (1)

Publication Number Publication Date
JP2002198396A true JP2002198396A (en) 2002-07-12

Family

ID=18860637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000395120A Pending JP2002198396A (en) 2000-12-26 2000-12-26 Semiconductor device, method for manufacturing semiconductor device, and circuit board for semiconductor device

Country Status (1)

Country Link
JP (1) JP2002198396A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013080758A (en) * 2011-10-03 2013-05-02 Panasonic Corp Semiconductor element mounting method
CN109413886A (en) * 2017-08-17 2019-03-01 富士电机株式会社 The manufacturing method and welding auxiliary tool of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013080758A (en) * 2011-10-03 2013-05-02 Panasonic Corp Semiconductor element mounting method
CN109413886A (en) * 2017-08-17 2019-03-01 富士电机株式会社 The manufacturing method and welding auxiliary tool of semiconductor device
CN109413886B (en) * 2017-08-17 2023-11-21 富士电机株式会社 Method for manufacturing semiconductor device and soldering auxiliary tool

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