JP2002190523A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine pattern multilevel metallization, while making the top of an air gap lower than the upper surface of a plug and preventing formation of voids in the plug. SOLUTION: After a lower plug 105 has been embedded in a first interlayer insulation film 103 on a first conductive film 102, a resist pattern for forming a lower layer interconnection is formed on the first interlayer insulation film 103. The first conductive film 102 is then patterned, using the resist pattern and the lower plug 105 to form a lower layer interconnection 102A. Subsequently, a second interlayer insulation film 107 and a third interlayer insulation film 108 are deposited sequentially to form an air gap 109 in a space between interconnections of the lower layer interconnection 120A, followed by deposition of a fourth interlayer insulation film 110. Thereafter, an upper plug 113 for connection with the lower plug 105 is formed, at least in the fourth interlayer insulation film 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring and a method of manufacturing the same, and more particularly, to a structure of a plug for connecting a lower wiring having an air gap in a space between wirings to an upper wiring and a method of forming the plug. About.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated and higher in performance, wiring inside semiconductor devices has become finer and more multilayered. On the other hand, miniaturization and multilayering of wirings increase the capacitance between wirings, thereby adversely affecting the operation speed of the semiconductor device. Therefore, there is a demand for a method of miniaturizing or multi-layering wiring while reducing the capacitance between wirings.

In order to reduce the capacitance between wirings, an insulating material having a small relative dielectric constant may be used as an interlayer insulating film. However, in order to further reduce the capacitance between wirings, a space between wirings (adjacent to each other) is required. An air gap may be formed in a region between a pair of wirings).

A paper by T. Ueda et al. ((1) A Novel Air)
Gap Integration Scheme for Multi-level Interconnec
ts using Self-aligned Via Plugs: 1998 Symposium on
VLSI Technology Digest of Technical Papers, P.46, 1
998., (2) Integration of 3Level Air Gap Interconnec
t for Sub-quater Micron CMOS: 1999 Symposium onVLSI
Technology Digest of Technical Papers, P.111, 199
9.) and the like, specifically, a method of forming a multilayer wiring having an air gap will be described with reference to the drawings.

FIGS. 8 (a) to 8 (c) and FIGS. 9 (a) to 9 (c)
10 (a) to 10 (c) are cross-sectional views showing respective steps of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 8A, a base insulating film 11 made of silicon oxide and a film thickness 600 nm made of an aluminum alloy are formed on a semiconductor substrate 10 made of silicon.
m first conductive film 12 and a 1500 nm-thick first interlayer insulating film 13 made of silicon oxide are sequentially deposited.
After that, a mask pattern 14 having an opening in a plug formation region is formed on the first interlayer insulating film 13.

Next, the first interlayer insulating film 13 is etched using the mask pattern 14 to obtain a structure shown in FIG.
As shown in (b), the aperture 4 reaching the first conductive film 12
After forming the connection hole 15 of about 00 nm, the mask pattern 14 is removed.

Next, a second conductive film made of tungsten is formed over the entire surface of the first interlayer insulating film 13 including the connection hole 15 by using a vapor deposition method or the like so that the connection hole 15 is completely filled. 8 is removed by polishing the second conductive film outside the connection hole 15 using a CMP method.
As shown in (c), a plug 16 connected to the first conductive film 12 is formed.

Next, as shown in FIG. 9A, the first interlayer insulating film 13 is etched back so as to have a film thickness of about 300 to 600 nm, and the upper part of the plug 16 is first etched. From the upper surface of the interlayer insulating film 13. As a result, the air gap 20 formed in a later step (FIG. 10)
(See (a)).

Next, as shown in FIG. 9B, a resist pattern 17 is formed on the first interlayer insulating film 13 so as to cover the lower wiring formation region.

Next, as shown in FIG. 9C, the first interlayer insulating film 13 and the first conductive film 12 are sequentially etched by using the resist pattern 17 and the plug 16 as a mask, so that the first Plug 16
Is formed to be connected to the lower wiring 12A.

In the step shown in FIG. 9C, after forming the lower wiring 12A, the resist pattern 17 and the plug 1 are formed.
6 is used as a mask to etch the underlying insulating film 11 so that the lower wiring 1 on the surface of the underlying insulating film 11 is removed.
The lower side of the space between the wirings of 2A is removed by about 300 nm.

Next, after removing the resist pattern 17, as shown in FIG. 10A, the entire surface of the semiconductor substrate 10 is subjected to a plasma CVD method using a silane gas and a nitrous oxide gas by a plasma CVD method. A second interlayer insulating film 18 having a thickness of about 200 to 500 nm made of silicon oxide having a high directivity and a low coverage is deposited, and subsequently, a film made of silicon oxide having a good filling performance is formed by high-density plasma CVD. A third interlayer insulating film 19 having a thickness of about 1000 nm is deposited. Thereby, the air gap 20 is formed in the space between the lower wirings 12A.

Next, as shown in FIG.
The second interlayer insulating film 18 and the third interlayer insulating film 19 are polished by using a method until the plug 16 is exposed to the second interlayer insulating film 18 and the third interlayer insulating film 19. Are flattened so as to be flush with the upper surface of the plug 16.

Next, as shown in FIG. 10C, the planarized second and third interlayer insulating films 18 and 19 are formed.
Is formed on the upper layer so as to be connected to the plug 16, thereby completing a two-layer wiring structure.

As described above, in the conventional method of manufacturing a semiconductor device, the lower wiring 12A and the upper wiring 21
Is formed prior to the lower wiring 12A, and the first conductive film 12 is patterned using the plug 16 as a mask to form the lower wiring 12A.
For this reason, it is possible to prevent the displacement between the plug 16 and the lower layer wiring 12A, thereby improving the reliability of the multilayer wiring.

[0017]

However, in the conventional method of manufacturing a semiconductor device, the position of the top of the air gap 20 formed in the inter-wiring space of the lower wiring 12A is reduced, as shown in FIG. As shown in (1), the first interlayer insulating film 13 is etched back so that the upper portion of the plug 16 protrudes from the upper surface of the first interlayer insulating film 13. Therefore, as shown in FIG. 9B, the resist pattern 17 is formed on a base having irregularities. As a result, the precision of the pattern exposure is reduced and the resist pattern 17 is deformed, or the formed resist pattern 17 is partially collapsed. It becomes difficult to miniaturize the wiring 12A, that is, the multilayer wiring.

On the other hand, if the upper part of the plug 16 is not protruded from the upper surface of the first interlayer insulating film 13, the top of the air gap 20 may reach the same height as the upper surface of the plug 16. In that case, the second interlayer insulating film 1
10 and the third interlayer insulating film 19 (FIG. 10)
(Refer to (b)), the air gap 2 is formed on the upper surface of the planarized second interlayer insulating film 18 or third interlayer insulating film 19.
0, an opening is formed, and a conductive film serving as the upper wiring 21 enters the opening. As a result, formation failure such as disconnection of the upper layer wiring 21 occurs, and the reliability of the multilayer wiring is reduced.

By the way, with the miniaturization of semiconductor devices,
In many cases, plugs that connect a lower wiring and an upper wiring are arranged close to each other.

FIG. 11 is a view for explaining a problem that arises when a pair of plugs for connecting a lower wiring and an upper wiring are formed by using a conventional method for manufacturing a semiconductor device.

FIG. 11 is different from FIG. 10B showing one step of a conventional method of manufacturing a semiconductor device, in that the lower wiring 12A and the upper wiring 21 (see FIG. 10C) are connected. , The adjacent plug 22 adjacent to the plug 16 is formed, and the air gap 20 is also formed in a space between the plug 16 and the adjacent plug 22 (hereinafter, referred to as an inter-plug space). is there. At this time,
As the distance between the plug 16 and the adjacent plug 22 becomes smaller, the aspect ratio of the space between the plugs becomes higher.
It becomes difficult to embed the second interlayer insulating film 18 or the third interlayer insulating film 19 in the space between the plugs, and the position of the top of the air gap 20 formed in the space between the plugs becomes high. For this reason, as shown in FIG. 11, in the polishing step for the second interlayer insulating film 18 and the third interlayer insulating film 19, the planarized second interlayer insulating film 18 or the third interlayer insulating film 19 is formed. An opening 20a is formed in the air gap 20 on the upper surface, and the upper wiring 2 is formed in the opening 20a.
There is a possibility that the conductive film that becomes 1 may enter. In this case, the upper layer wiring 21 (see FIG. 10B) may have a formation defect such as a step break, the lower layer wirings 12A may be short-circuited, or the plug 16 and the adjacent plug 22 may be short-circuited. The reliability of the wiring is reduced.

In the conventional method of manufacturing a semiconductor device, the first conductive film 12 and the like are etched using the plug 16 as a mask (see FIG. 9C), or the plug 16 is exposed. Up to the second interlayer insulating film 18
Alternatively, polishing is performed on the third interlayer insulating film 19 (FIG. 1).
0 (b)), the height of the plug 16 decreases during the manufacturing process. Therefore, in order to make the final height of the plug 16 equal to the predetermined value, the plug 16 is formed in the connection hole 15 provided in the first interlayer insulating film 13 (see FIG. 8C It is necessary to give a margin to the height of the plug 16 in (1)). That is, it is necessary to form a connection hole 15 having a high aspect ratio in the first interlayer insulating film 13 and embed a conductive film to be a plug 16 (hereinafter referred to as a plug-forming conductive film) in the connection hole 15.

However, as the aspect ratio of the connection hole 15 increases, it becomes more difficult to embed the plug-forming conductive film in the connection hole 15, and as a result, as shown in FIG. 12 (corresponding to FIG. 8C). The plug 16 formed in the connection hole 15
There is a possibility that a void 16a remains inside the plug 16 and a plug formation defect such that the electrical resistance of the plug 16 increases. This plug formation defect tends to occur easily due to a decrease in plug diameter due to miniaturization of multilayer wiring.

Further, an etch-back process for the first interlayer insulating film 13 (see FIG. 9A), the first conductive film 12
The upper portion of the plug 16 is etched or polished by an etching process (see FIG. 9C) for the same or the like and a polishing process (see FIG. 10B) for the third interlayer insulating film 19 and the like. Therefore, FIG. 13 (FIG. 10B)
As shown in FIG.
There is a possibility that an opening may be formed in the hole. When an opening is formed in the void 16a, a problem arises in that a conductive film serving as the upper wiring 21 enters the opening and a formation defect such as a step break occurs in the upper wiring 21. Alternatively, there is a problem that abrasive grains used in a polishing step for the third interlayer insulating film 19 and the like flow into the voids 16a, that is, the plugs 16 and remain therein, thereby deteriorating electromigration resistance of the plugs 16 and the like. In other words, there arises a problem that the reliability of the multilayer wiring is reduced.

In view of the above, the present invention is intended to reduce the top of the air gap below the upper surface of the plug, to make the multilayer wiring finer, and to prevent the formation of voids inside the plug. The purpose is to do.

[0026]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: depositing a first conductive film on a semiconductor substrate; and forming a lower interlayer insulating film on the first conductive film. After that, a step of forming a first opening reaching the first conductive film by selectively etching the lower interlayer insulating film, and embedding a second conductive film in the first opening. Accordingly, a step of forming a lower plug connected to the first conductive film, and forming a mask pattern on the lower interlayer insulating film, and then using the mask pattern and the lower plug as a mask, form the lower interlayer insulating film and the first conductive film. A step of sequentially etching the film to form a lower wiring formed of the first conductive film and connected to the lower plug; and forming an upper interlayer insulating film on the semiconductor substrate and forming air in a space between the lower wirings. A gap is formed Forming a second opening that reaches the lower plug by selectively etching the upper interlayer insulating film; and embedding a third conductive film in the second opening. Forming an upper plug connected to the lower plug, and forming an upper wiring on the upper interlayer insulating film so as to be connected to the upper plug.

According to the method of manufacturing a semiconductor device of the present invention,
After embedding a lower plug in a lower interlayer insulating film formed on a first conductive film on a semiconductor substrate, a first plug is formed using a mask pattern and a lower plug formed on the lower interlayer insulating film.
Is patterned to form a lower wiring. Thereafter, an upper interlayer insulating film is formed so as to form an air gap in a space between the lower wires, and then an upper plug connected to the lower plug is formed in the upper interlayer insulating film. Therefore, the top of the air gap can be lower than the upper surface of the upper interlayer insulating film, that is, the upper surface of the upper plug.
In order to control the position of the top of the air gap, it is not necessary to etch back the lower interlayer insulating film in which the lower plug is embedded so that the lower plug protrudes. Therefore, a mask pattern for forming the lower wiring can be formed on the lower interlayer insulating film having no unevenness, so that the mask pattern can be miniaturized, whereby the lower wiring, that is, the multilayer wiring can be miniaturized.

According to the method of manufacturing a semiconductor device of the present invention, even when the plugs for connecting the lower wiring and the upper wiring are arranged close to each other, the upper plug constituting each plug is formed on the upper interlayer insulating film. Since the plugs are embedded, an air gap is not formed even in a region between upper plugs constituting each plug. Therefore, since the top of the air gap can be lower than the upper surface of each upper plug,
Since an opening is not formed in the air gap on the upper surface of the upper interlayer insulating film, it is possible to prevent defective formation of the upper layer wiring and the like.

Further, according to the method of manufacturing a semiconductor device of the present invention, the plug for connecting the lower wiring and the upper wiring is divided into the lower plug and the upper plug, and the conductive film is embedded in different openings, ie, the connection holes. It forms by doing. For this reason, since the aspect ratio of each connection hole can be reduced, a conductive film can be sufficiently buried in each connection hole, thereby preventing voids from being formed inside each of the lower plug and the upper plug. Can be prevented. Therefore, it is possible to easily realize a plug having a sufficient height while preventing an increase in electric resistance of the plug constituted by the lower plug and the upper plug. Also, even if the surface of the plug is etched or polished during the manufacturing process, an opening is not formed in the void inside the plug, so that formation defects such as disconnection in the upper layer wiring are prevented. It is possible to prevent the generation of polishing plugs or the intrusion of polishing abrasive grains into the plug to degrade the electromigration resistance of the plug.

In the method of manufacturing a semiconductor device according to the present invention,
The step of forming the lower plug preferably includes a step of flattening the upper surface of the lower interlayer insulating film so as to be flush with the upper surface of the lower plug.

By doing so, the lower interlayer insulating film, which is the base of the mask pattern for forming the lower wiring, is further flattened, so that the mask pattern can be made finer. Can be

In the method for manufacturing a semiconductor device according to the present invention,
The area of the upper surface of the lower plug is preferably larger than the area of the lower surface of the upper plug.

In this way, even when misalignment occurs during the formation of the mask pattern for forming the second opening, that is, the connection hole for the upper plug, the connection between the lower plug and the upper plug can be made. Since the area is sufficiently secured, the electric resistance of the plug as a whole does not increase. Also, in the case where misalignment occurs during the formation of the mask pattern, even if over-etching is performed using the mask pattern, the upper surface of the lower plug acts as an etching stopper. Can be prevented from reaching the air gap.

In the method of manufacturing a semiconductor device according to the present invention,
The upper interlayer insulating film preferably has a first insulating film deposited so as to form an air gap, and a second insulating film deposited on the first insulating film. .

Thus, an insulating film having high directivity and a low coverage is used as the first insulating film, and the second insulating film is used.
By using an insulating film having good burying performance as the insulating film, an air gap can be increased in a space between wirings having a small width to reduce the capacitance between wirings. Further, since a high air gap at the top portion is not formed in the space between the wide wirings, it is possible to avoid a situation in which an opening is formed in the air gap in a polishing process or the like for a later interlayer insulating film. It is possible to prevent a decrease in the reliability of the multilayer wiring.

More specifically, it is preferable that the first insulating film is formed by, for example, a plasma CVD method and the second insulating film is formed by, for example, a high-density plasma CVD method.

Further, when the upper interlayer insulating film further has a third insulating film deposited on the second insulating film and having a flattened surface, the formation of the upper wiring can be facilitated. Can be done. At this time, most of the upper plug may be covered with the third insulating film.

Further, after the formation of the second insulating film, the surface of the second insulating film is planarized by polishing the second insulating film until the lower plug or the first insulating film is exposed. By doing so, the subsequent step of depositing the insulating film or the conductive film can be easily performed.

A semiconductor device according to the present invention includes a lower wiring formed on a semiconductor substrate and having an air gap in a space between wirings; an upper wiring formed on the lower wiring via an interlayer insulating film; And a plug for connecting to the upper wiring. The plug has a lower plug formed on the lower wiring, and an upper plug formed on the lower plug so as to be connected to the upper wiring.

According to the semiconductor device of the present invention, since the semiconductor device is formed by the method of manufacturing the semiconductor device of the present invention, the top of the air gap formed in the space between the lower wirings is made lower than the upper surface of the upper plug. The multilayer wiring can be miniaturized, and the formation of voids inside each of the lower plug and the upper plug can be prevented.

In the semiconductor device of the present invention, the area of the upper surface of the lower plug is preferably larger than the area of the lower surface of the upper plug.

In this way, even when misalignment occurs during the formation of the mask pattern for forming the connection hole for the upper plug, a sufficient connection area between the lower plug and the upper plug is ensured. Therefore, the electric resistance of the plug as a whole does not increase. Also, in the case where misalignment occurs during the formation of the mask pattern, even if over-etching is performed using the mask pattern, the upper surface of the lower plug acts as an etching stopper. Can be prevented from reaching the air gap.

In the semiconductor device according to the present invention, the lower wiring and the upper wiring are connected to each other, further comprising an adjacent plug adjacent to the plug, wherein the adjacent plug is formed on the lower wiring so as to be adjacent to the lower plug. It is preferable to have a lower plug and an adjacent upper plug formed on the adjacent lower plug so as to be adjacent to the upper plug.

With this arrangement, even if the plug composed of the lower plug and the upper plug and the adjacent plug composed of the adjacent lower plug and the adjacent upper plug are arranged close to each other, the gap between the upper plug and the adjacent upper plug is reduced. Since the air gap is not formed in the region, the top of the air gap can be lower than the upper surface of the upper plug or the adjacent upper plug.

In the semiconductor device of the present invention, the interlayer insulating film comprises a lower interlayer insulating film deposited so as to cover the upper surface of the lower wiring, and an upper interlayer insulating film deposited on the lower interlayer insulating film. The upper interlayer insulating film may include a first insulating film deposited so as to form an air gap, and a second insulating film deposited on the first insulating film. preferable.

Thus, an insulating film having high directivity and a low coverage is used as the first insulating film, and the second insulating film is used.
By using an insulating film having good burying performance as the insulating film, an air gap can be increased in a space between wirings having a small width to reduce the capacitance between wirings. Further, since a high air gap at the top portion is not formed in the space between the wide wirings, it is possible to avoid a situation in which an opening is formed in the air gap in a polishing process or the like for a later interlayer insulating film. It is possible to prevent a decrease in the reliability of the multilayer wiring.

Further, when the upper interlayer insulating film further has a third insulating film deposited on the second insulating film and having a flattened surface, it is easy to form the upper layer wiring. Can be done. At this time, most of the upper plug may be covered with the third insulating film.

[0048]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIGS. 1 (a) to 1 (d) and FIGS. 2 (a) to 2 (c)
FIGS. 3A to 3C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, a base insulating film 101 made of, for example, silicon oxide and a first conductive film made of, for example, an aluminum alloy having a thickness of about 600 nm are formed on a semiconductor substrate 100 made of, for example, silicon. Membrane 10
2 are sequentially deposited. After that, a film thickness of 300 to 600 n made of, for example, silicon oxide is formed on the first conductive film 102.
m of the first interlayer insulating film 103 ("Claims"
After that, a mask pattern (not shown) having an opening in a lower plug formation region is formed on the first interlayer insulating film 103, and then the mask pattern is used. Etching is performed on the first interlayer insulating film 103, and the aperture 4 reaching the first conductive film 102 is obtained.
A first connection hole 104 of about 00 nm is formed.

Next, a second conductive film made of, for example, tungsten is formed on the entire surface of the first interlayer insulating film 103 including the first connection hole 104 by, for example, an evaporation method. After the connection hole 104 is deposited so as to be completely filled, C
By polishing and removing the second conductive film outside the first connection hole 104 using the MP method, as shown in FIG. 1B, the lower plug 105 connected to the first conductive film 102 is removed.
To form At this time, since the aspect ratio (for example, about 1 to 1.5) of the first connection hole 104 is relatively small, the first connection hole 104 can be completely buried with the second conductive film. No void is formed inside 105. At this time, the upper surface of the first interlayer insulating film 103 is flattened so as to be flush with the upper surface of the lower plug 105.

Next, as shown in FIG. 1C, a resist pattern 106 covering the lower wiring formation region is formed on the first interlayer insulating film 103. At this time, the resist pattern 106 is formed on a base having no unevenness (the first interlayer insulating film 10).
3) Since the resist pattern 106 is formed thereon, the resist pattern 106 can be miniaturized.

Next, as shown in FIG. 1D, the first interlayer insulating film 103 and the first conductive film 102 are sequentially etched using the resist pattern 106 and the lower plug 105 as a mask. One lower conductive layer 102A made of one conductive film 102 and connected to the lower plug 105 is formed.

In the step shown in FIG. 1D, after forming the lower wiring 102A, the underlying insulating film 101 is etched using the resist pattern 106 and the lower plug 105 as a mask, and the surface of the underlying insulating film 101 is formed. For example, the lower side of the inter-wiring space of the lower wiring 102A in the portion is removed by about 300 nm. Thus, an air gap 109 (see FIG. 2A) formed in a later step is formed to a lower position, whereby the air gap 109 can be formed so as to face the entire side surface of the lower wiring 102A. In addition, the inter-wiring capacitance of the lower wiring 102A is further reduced.

Next, after the resist pattern 106 is removed, as shown in FIG. 2A, over the entire surface of the semiconductor substrate 100, for example, by a plasma CVD method using a silane gas and a nitrous oxide gas. For example, a second interlayer insulating film 107 made of, for example, silicon oxide and having a film thickness of about 200 to 500 nm (the “first insulating film” of the “upper interlayer insulating film” in the claims) is deposited. Subsequently, plasma CVD using higher-density plasma than the plasma CVD method used to form the second interlayer insulating film 107
The third interlayer insulating film 108 made of, for example, silicon oxide and having a thickness of about 1000 nm (“upper interlayer insulating film” in the claims)
Of the "second insulating film"). This allows
An air gap 10 is provided in the space between the lower wirings 102A.
9 is formed.

Here, the second interlayer insulating film 107 has a high directivity and a low coverage, while the third interlayer insulating film 108 has a good burying performance. Therefore, as shown in FIG. The inter-wiring capacitance can be reduced by increasing the air gap 109 formed in the narrow inter-wiring space of the interwiring space of the wiring 102A. Further, in the space between the wide wirings in the space between the wirings of the lower wiring 102A,
Since a high air gap 109 at the top is not formed, a polishing step for the interlayer insulating film to be performed later (FIG.
(Refer to (b)) and the like, the situation where an opening is formed in the air gap 109 can be avoided, thereby preventing a decrease in the reliability of the multilayer wiring.

Next, as shown in FIG. 2B, the second interlayer insulating film 107 and the third interlayer insulating film 108 are polished by using the CMP method so that the second interlayer insulating film 107 is polished. The upper surfaces of the insulating film 107 and the third interlayer insulating film 108 are flattened. At this time, the third interlayer insulating film 108
Is performed until the second interlayer insulating film 107 is exposed, so that the upper surface of the third interlayer insulating film 108 is flattened so as to be flush with the upper surface of the second interlayer insulating film 107. Good. Further, the second interlayer insulating film 107 and the third interlayer insulating film 108 are polished until the lower plug 105 is exposed, so that the second interlayer insulating film 107 is polished.
The upper surface of each of the third interlayer insulating film 108 and the upper surface of the lower plug 105 may be flattened.

Next, as shown in FIG. 2C, the planarized second interlayer insulating film 107 and third interlayer insulating film 10
A fourth interlayer insulating film 110 made of, for example, silicon oxide and having a thickness of about 400 to 800 nm
(“Third insulating film” of “upper interlayer insulating film” in the claims) is deposited. After planarizing the surface of the fourth interlayer insulating film 110, a mask pattern 111 having an opening in an upper plug formation region is formed on the flattened fourth interlayer insulating film 110.

Next, at least the fourth interlayer insulating film 110 is etched using the mask pattern 111, and as shown in FIG. A connection hole 112 is formed.

Next, a third conductive film made of, for example, tungsten is formed on the entire surface of the fourth interlayer insulating film 110 including the second connection hole 112 by, for example, an evaporation method. After the contact hole 112 is deposited so as to be completely filled, C
By polishing and removing the third conductive film outside the second connection hole 112 using the MP method, an upper plug 113 connected to the lower plug 105 is formed as shown in FIG. . At this time, since the aspect ratio (for example, about 1 to 2) of the second connection hole 112 is relatively small, the second connection hole 112 can be completely buried with the second conductive film. No voids are formed inside. At this time, the lower plug 105
And the upper plug 113 are directly connected,
They are electrically connected to each other.

Next, as shown in FIG. 3C, an upper wiring 114 is formed on the fourth interlayer insulating film 110 so as to be connected to the upper plug 113, thereby completing a two-layer wiring structure. Let it.

As described above, according to the first embodiment, the lower plug 105 is formed on the first interlayer insulating film 103 formed on the first conductive film 102 on the semiconductor substrate 100.
, The first conductive film 102 is patterned using a resist pattern 106 formed on the first interlayer insulating film 103 and the lower plug 105 to form the lower wiring 102.
Form A. After that, a second interlayer insulating film 107 and a third interlayer insulating film 108 are sequentially deposited so that an air gap 109 is formed in a space between the lower wires 102A, and then a fourth interlayer insulating film 110 is formed. After that, an upper plug 113 connected to the lower plug 105 is formed on at least the fourth interlayer insulating film 110. Therefore, the top of the air gap 109 is connected to the fourth interlayer insulating film 11.
0, that is, lower than the upper surface of the upper plug 113. Therefore, in order to control the position of the top of the air gap 109, the first plug embedded with the lower plug 105 is formed.
It is not necessary to etch back the interlayer insulating film 103 to make the lower plug 105 protrude. Accordingly, since the resist pattern 106 for forming the lower wiring can be formed on the first interlayer insulating film 103 having no unevenness (see FIG. 1C), the resist pattern 106 can be miniaturized, thereby forming the lower wiring 102A, that is, the multilayer. Wiring can be miniaturized.

According to the first embodiment, the plug for connecting the lower wiring 102A and the upper wiring 114 is divided into the lower plug 105 and the upper plug 113, and different connection holes, specifically, It is formed by embedding a conductive film in the first connection hole 104 and the second connection hole 112. For this reason, the aspect ratio of each connection hole can be reduced, so that the conductive film can be sufficiently buried in each connection hole, thereby forming voids inside each of the lower plug 105 and the upper plug 113. Can be prevented. Therefore, the lower plug 105 and the upper plug 1
A plug having a sufficient height can be easily realized while preventing an increase in electric resistance of the plug constituted by the plug 13. Also, if the plug surface is etched or polished during the manufacturing process,
Since an opening is not formed in a void inside the plug, a formation defect such as disconnection of the upper wiring 114 occurs,
Alternatively, it is possible to prevent the abrasive grains from entering the plug from deteriorating the electromigration resistance of the plug.

According to the first embodiment, when the lower plug 105 is embedded in the first connection hole 104 formed in the first interlayer insulating film 103, the first interlayer insulating film 10
3 is flattened so as to be flush with the upper surface of the lower plug 105, so that the first interlayer insulating film 103 serving as a base of the resist pattern 106 for forming the lower wiring is further flattened. The resist pattern 106 can be made finer, whereby the lower wiring 102A, that is, the multilayer wiring, can be made finer.

In the first embodiment, the lower wiring 1
Although a two-layer wiring structure composed of the upper wirings 02A and the upper wiring 114 is assumed, the present invention is not limited to this, and even in a wiring structure of three or more layers, plugs connecting vertically adjacent wirings are divided into a lower part and an upper part. The same effect as in the first embodiment can be obtained by repeating the process of forming the conductive film by burying the conductive film in different connection holes.

In the first embodiment, the plug for connecting the lower wiring 102A and the upper wiring 114 is divided into two stages of the lower plug 105 and the upper plug 113, and the conductive films are embedded in different connection holes. However, the present invention is not limited to this. Even if the plug for connecting the vertically adjacent wirings is divided into three or more stages and the conductive films are buried in different connection holes, the first embodiment is different from the first embodiment. Similar effects can be obtained.

In the first embodiment, the first interlayer insulating film 103, the first conductive film 102, and the underlying insulating film 1
01 (FIG. 1D)
In the etching process for the first conductive film 102 or the base insulating film 101, the resist pattern 106 was used as a mask, but the first conductive film 10
2 or in the etching process for the base insulating film 101,
The patterned first interlayer insulating film 103 may be used as a mask. In this case, it is preferable that the first interlayer insulating film 103 is deposited thicker in the step shown in FIG.

In the first embodiment, the second interlayer insulating film 107 and the third interlayer insulating film 108 are formed after the lower wiring 102A is formed and before the upper wiring 114 is formed.
And the fourth interlayer insulating film 110 is formed.
The number, type, deposition method, and the like of the interlayer insulating film (upper interlayer insulating film) formed after the formation of 02A and before the formation of the upper wiring 114 are not particularly limited.

(Modification of First Embodiment) Hereinafter, a semiconductor device according to a modification of the first embodiment and a method of manufacturing the same will be described with reference to the drawings.

FIG. 4 is a sectional view showing one step in a method for manufacturing a semiconductor device according to a modification of the first embodiment. FIG. 4 corresponds to FIG. 3B showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

The modification of the first embodiment differs from the first embodiment in that, as shown in FIG.
An adjacent lower plug 115 is formed on 2A so as to be adjacent to the lower plug 105, and an adjacent upper plug 116 is formed on the adjacent lower plug 115 so as to be adjacent to the upper plug 113. It is. At this time, the adjacent lower plug 115 is formed by the same forming method as the lower plug 105 (see FIGS. 1A and 1B), and the adjacent upper plug 116 is formed by the same forming method as the upper plug 113 (FIG. 2). (C) and FIGS. 3 (a) and 3 (b)).

According to the modification of the first embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

That is, one plug composed of the lower plug 105 and the upper plug 113 and the adjacent lower plug 115
And the upper plug 113 and the adjacent upper plug 116 are at least the fourth interlayer insulating film 1 even if the other upper plug 116 and the other upper plug 116 are arranged close to each other.
10, the air gap 109 is not formed even in the region between the upper plug 113 and the adjacent upper plug 116. Therefore, since the top of the air gap 109 can be made lower than the upper surface of the upper plug 113 or the adjacent upper plug 116, an opening is not formed in the air gap 109 on the upper surface of the fourth interlayer insulating film 110. Therefore, it is possible to prevent defective formation of the upper wiring 114 and the like.

(Second Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described.
This will be described with reference to the drawings.

FIGS. 5A to 5D and FIGS. 6A to 6C.
FIGS. 7A to 7C are cross-sectional views illustrating each step of the method for manufacturing a semiconductor device according to the second embodiment.

First, as shown in FIG. 5A, a base insulating film 201 made of, for example, silicon oxide and a first conductive film made of, for example, an aluminum alloy and having a thickness of about 600 nm are formed on a semiconductor substrate 200 made of, for example, silicon. Membrane 20
2 are sequentially deposited. Thereafter, a film thickness of 300 to 600 n made of, for example, silicon oxide is formed on the first conductive film 202.
m of the first interlayer insulating film 203 ("Claims"
Is deposited, a mask pattern (not shown) having an opening in a lower plug formation region is formed on the first interlayer insulating film 203, and then the mask pattern is used. Etching is performed on the first interlayer insulating film 203 so that the aperture 5 reaching the first conductive film 202 is removed.
A first connection hole 204 of about 00 nm is formed.

Next, a second conductive film made of, for example, tungsten is formed on the entire surface of the first interlayer insulating film 203 including the first connection hole 204 by using, for example, an evaporation method. After the connection hole 204 is deposited so as to be completely filled, C
By polishing and removing the second conductive film outside the first connection hole 204 using the MP method, as shown in FIG. 5B, the lower plug 205 connected to the first conductive film 202 is removed.
To form At this time, the aspect ratio (about 0.6 to 1.2) of the first connection hole 204 is relatively small.
The connection hole 204 can be completely filled with the second conductive film, so that no void is formed inside the lower plug 205. Also, at this time, the lower plug 2
The area of the upper surface of 05 is made larger than the area of the lower surface of the upper plug 213 (see FIG. 7B) formed in a later step. Further, at this time, the upper surface of the first interlayer insulating film 203 is flattened so as to be flush with the upper surface of the lower plug 205.

Next, as shown in FIG. 5C, a resist pattern 206 is formed on the first interlayer insulating film 203 so as to cover the lower wiring formation region. At this time, the resist pattern 206 is formed on a base having no unevenness (the first interlayer insulating film 20).
3) Since the resist pattern 206 is formed thereon, the resist pattern 206 can be miniaturized.

Next, as shown in FIG. 5D, the first interlayer insulating film 203 and the first conductive film 202 are sequentially etched using the resist pattern 206 and the lower plug 205 as a mask. One lower conductive layer 202A made of one conductive film 202 and connected to the lower plug 205 is formed.

In the step shown in FIG. 5D, after the lower wiring 202A is formed, the underlying insulating film 201 is etched by using the resist pattern 206 and the plug lower portion 205 as a mask, and the surface of the underlying insulating film 201 is formed. For example, the lower side of the space between the wirings of the lower wiring 202A in the portion is removed by, for example, about 300 nm. Thus, an air gap 209 (see FIG. 6A) formed in a later step is formed to a lower position, whereby the air gap 209 can be formed so as to face the entire side surface of the lower wiring 202A. In addition, the inter-wiring capacitance of the lower wiring 202A is further reduced.

Next, after the resist pattern 206 is removed, as shown in FIG. 6A, over the entire surface of the semiconductor substrate 200, for example, by a plasma CVD method using a silane gas and a nitrous oxide gas. For example, a second interlayer insulating film 207 made of, for example, silicon oxide and having a film thickness of about 200 to 500 nm (the “first insulating film” of the “upper interlayer insulating film” in the claims) is deposited. Subsequently, plasma CVD using a higher-density plasma than the plasma CVD method used to form the second interlayer insulating film 207
A third interlayer insulating film 208 (for example, “upper interlayer insulating film” in the claims) having a thickness of about 1000 nm made of, for example, silicon oxide by a high-density plasma CVD method.
Of the "second insulating film"). This allows
The air gap 20 is provided in the space between the lower wirings 202A.
9 is formed.

Here, the second interlayer insulating film 207 has a high directivity and a low coverage, while the third interlayer insulating film 208 has a good burying performance. Therefore, as shown in FIG. The inter-wiring capacitance can be reduced by increasing the air gap 209 formed in the narrow inter-wiring space of the interwiring space of the wiring 202A. Further, in the space between the wide wirings of the space between the lower wirings 202A,
Since an air gap 209 having a high top position is not formed, a polishing step for the interlayer insulating film (FIG. 6)
(Refer to (b)) and the like, it is possible to avoid a situation in which an opening is formed in the air gap 209, thereby preventing a decrease in the reliability of the multilayer wiring.

Next, as shown in FIG. 6B, the second interlayer insulating film 207 and the third interlayer insulating film 208 are polished by using the CMP method so that the second interlayer insulating film 208 is polished. The upper surfaces of the insulating film 207 and the third interlayer insulating film 208 are flattened. At this time, the third interlayer insulating film 208
Is performed until the second interlayer insulating film 207 is exposed, so that the upper surface of the third interlayer insulating film 208 is flattened so as to be flush with the upper surface of the second interlayer insulating film 207. Good. Further, the second interlayer insulating film 207 and the third interlayer insulating film 208 are polished until the lower plug 205 is exposed, whereby the second interlayer insulating film 207 is formed.
The upper surface of each of the third interlayer insulating film 208 and the upper surface of the lower plug 205 may be planarized.

Next, as shown in FIG. 6C, the planarized second interlayer insulating film 207 and third interlayer insulating film 20 are planarized.
And a fourth interlayer insulating film 210 made of, for example, silicon oxide and having a thickness of about 400 to 800 nm.
(“Third insulating film” of “upper interlayer insulating film” in the claims) is deposited. Then, after the surface of the fourth interlayer insulating film 210 is planarized, a mask pattern 211 having an opening in an upper plug formation region is formed on the planarized fourth interlayer insulating film 210.

Next, etching is performed on at least the fourth interlayer insulating film 210 using the mask pattern 211, and as shown in FIG. A connection hole 212 is formed.

Next, a third conductive film made of, for example, tungsten is formed on the entire surface of the fourth interlayer insulating film 210 including the second connection hole 212 by using, for example, an evaporation method. After the contact hole 212 is deposited so as to be completely filled, C
By polishing and removing the third conductive film outside the second connection hole 212 using the MP method, an upper plug 213 connected to the lower plug 205 is formed as shown in FIG. 7B. . At this time, since the aspect ratio (about 1.0 to 2.5) of the second connection hole 212 is relatively small, the second connection hole 212 can be completely buried with the second conductive film. No void is formed inside the plug 213. At this time, the lower plug 20
5 and the upper plug 213 are electrically connected to each other by being directly connected. Further, at this time, the area of the lower surface of the upper plug 213 is smaller than the area of the upper surface of the lower plug 205.

Next, as shown in FIG. 7C, an upper wiring 214 is formed on the fourth interlayer insulating film 210 so as to be connected to the upper plug 213, thereby completing a two-layer wiring structure. Let it.

As described above, according to the second embodiment, the lower plug 205 is formed on the first interlayer insulating film 203 formed on the first conductive film 202 on the semiconductor substrate 200.
After that, the first conductive film 202 is patterned using the resist pattern 206 formed on the first interlayer insulating film 203 and the lower plug 205 to form the lower wiring 202A.
To form After that, a second interlayer insulating film 207 and a third interlayer insulating film 208 are sequentially deposited so that an air gap 209 is formed in a space between the lower wires 202A, and then a fourth interlayer insulating film 210 is formed. Then, the lower plug 2 is formed on at least the fourth interlayer insulating film 210.
The upper plug 213 connecting to the upper plug 05 is formed. Therefore, the top of the air gap 209 is connected to the fourth interlayer insulating film 21.
0, that is, lower than the upper surface of the upper plug 213, so that the first plug embedded with the lower plug 205 can be used to control the position of the top of the air gap 209.
It is not necessary to etch back the interlayer insulating film 203 to project the lower plug 205. Accordingly, since the resist pattern 206 for forming the lower wiring can be formed on the first interlayer insulating film 203 having no unevenness (see FIG. 5C), the resist pattern 206 can be miniaturized, thereby forming the lower wiring 202A, that is, the multilayer. Wiring can be miniaturized.

Further, according to the second embodiment, the plug for connecting the lower wiring 202A and the upper wiring 214 is divided into the lower plug 205 and the upper plug 213, and different connection holes, specifically, It is formed by embedding a conductive film in the first connection hole 204 and the second connection hole 212. Therefore, the aspect ratio of each connection hole can be reduced, so that the conductive film can be sufficiently buried in each connection hole, thereby forming a void inside each of the lower plug 205 and the upper plug 213. Can be prevented. Therefore, the lower plug 205 and the upper plug 2
A plug having a sufficient height can be easily realized while preventing an increase in electric resistance of the plug constituted by the plug 13. Also, if the plug surface is etched or polished during the manufacturing process,
Since an opening is not formed in a void inside the plug, a formation defect such as disconnection of the upper wiring 214 occurs,
Alternatively, it is possible to prevent the abrasive grains from entering the plug from deteriorating the electromigration resistance of the plug.

According to the second embodiment, when the lower plug 205 is buried in the first connection hole 204 formed in the first interlayer insulating film 203, the first interlayer insulating film 20 is formed.
3 is flattened so as to be flush with the upper surface of the lower plug 205, so that the first interlayer insulating film 203 serving as a base for the resist pattern 206 for forming the lower wiring is further flattened. The resist pattern 206 can be made finer, whereby the lower wiring 202A, that is, the multilayer wiring, can be made finer.

According to the second embodiment, the area of the upper surface of the lower plug 205 is made larger than the area of the lower surface of the upper plug 213.
Pattern 211 for forming connection hole 212 of
Even if misalignment occurs during the formation of the plug, the connection area between the lower plug 205 and the upper plug 213 is sufficiently ensured, so that the electrical resistance of the entire plug does not increase. Further, when misalignment occurs during the formation of the mask pattern 211, even if over-etching is performed using the mask pattern 211, the upper surface of the lower plug 205 acts as an etching stopper. Can be prevented from reaching the air gap 209.

In the second embodiment, the lower wiring 2
Although a two-layer wiring structure composed of the second wiring layer 02A and the upper wiring layer 214 is premised, the present invention is not limited to this. Even in a wiring structure of three or more layers, plugs connecting vertically adjacent wiring are divided into a lower part and an upper part. The same effect as in the second embodiment can be obtained by repeating the step of forming the conductive film in different connection holes.

Further, in the second embodiment, the plug for connecting the lower wiring 202A and the upper wiring 214 is divided into two stages of a lower plug 205 and an upper plug 213, and the conductive films are embedded in different connection holes. However, the present invention is not limited to this. Even if the plug is formed by dividing the plug connecting the vertically adjacent wirings into three or more stages and embedding a conductive film in different connection holes, the second embodiment is different from the second embodiment. Similar effects can be obtained.

In the second embodiment, the first interlayer insulating film 203, the first conductive film 202, and the base insulating film 2
01 (FIG. 5D)
In the etching process for the first conductive film 202 or the base insulating film 201, the resist pattern 206 was used as a mask.
2 or in the etching process for the base insulating film 201,
The patterned first interlayer insulating film 203 may be used as a mask. In this case, it is preferable to deposit the first interlayer insulating film 203 thicker in the step shown in FIG.

In the second embodiment, the second interlayer insulating film 207 and the third interlayer insulating film 208 are formed after the lower wiring 202A is formed and before the upper wiring 214 is formed.
And the fourth interlayer insulating film 210 is formed.
The number, type, deposition method, and the like of the interlayer insulating film (upper interlayer insulating film) formed after the formation of 02A and before the formation of the upper wiring 214 are not particularly limited.

In the second embodiment, the area of the upper surface of the lower plug 205 is made larger than the area of the lower surface of the upper plug 213.
May be larger than the area of the upper surface of the lower plug 205. In this case, even if misalignment occurs during the formation of the mask pattern 211, the lower plug 205
Since the connection area between the plug and the upper plug 213 is sufficiently ensured, the electric resistance of the entire plug does not increase.

Further, in the second embodiment, the same forming method as that of the lower plug 205 (see FIGS. 5A and 5B).
7A, an adjacent lower plug is formed on the lower wiring 202A so as to be adjacent to the lower plug 205, and the same forming method as that for the upper plug 213 (FIG. 6C and FIG.
(See (a) and (b)), the adjacent upper plug may be formed on the adjacent lower plug so as to be adjacent to the upper plug 213. In this way, even if one plug composed of the lower plug 205 and the upper plug 213 and another plug composed of the adjacent lower plug and the adjacent upper plug are arranged close to each other, the upper plug 213 and the adjacent upper plug can be connected. Since each is buried at least in the fourth interlayer insulating film 210, the air gap 209 is not formed even in the region between the upper plug 213 and the adjacent upper plug. Therefore, since the top of the air gap 209 can be lower than the upper surface of the upper plug 213 or the adjacent upper plug, an opening is not formed in the air gap 209 on the upper surface of the fourth interlayer insulating film 210. In addition, defective formation of the upper wiring 214 can be prevented. When forming the adjacent lower plug and the adjacent upper plug, the area of the upper surface of the adjacent lower plug is made larger than the area of the lower surface of the adjacent upper plug, or the area of the lower surface of the adjacent upper plug is changed to the upper surface of the adjacent lower plug. It is preferable that the area be larger than the area.

[0098]

According to the present invention, the top of the air gap can be made lower than the upper surface of the upper plug. Therefore, in order to control the position of the top of the air gap, the lower interlayer insulating film in which the lower plug is embedded is provided. It is not necessary to perform etch-back on and to project the lower plug. Therefore,
Since a mask pattern for forming the lower wiring can be formed on the lower interlayer insulating film having no unevenness, the mask pattern can be miniaturized, and thereby the multi-layer wiring can be miniaturized.

According to the present invention, even when the plugs connecting the lower layer wiring and the upper layer wiring are arranged close to each other, the top of the air gap is made lower than the upper surface of the upper plug constituting each plug. be able to. For this reason, since no opening is formed in the air gap on the upper surface of the upper interlayer insulating film, it is possible to prevent defective formation of the upper wiring and the like.

Further, according to the present invention, it is possible to prevent voids from being formed inside each of the lower plug and the upper plug, thereby preventing an increase in electric resistance of the plug constituted by the lower plug and the upper plug. In addition, since openings are not formed in the voids inside the plug due to polishing or the like, it is possible to prevent poor formation of the upper wiring or deterioration of the electromigration resistance of the plug.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.

FIGS. 5A to 5D are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 6A to 6C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A to 7C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A to 8C are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

FIGS. 9A to 9C are cross-sectional views showing steps of a conventional method for manufacturing a semiconductor device.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a conventional method for manufacturing a semiconductor device.

FIG. 11 is a diagram illustrating a problem that occurs when a pair of plugs that connect a lower wiring and an upper wiring are formed by using a conventional method of manufacturing a semiconductor device.

FIG. 12 is a diagram illustrating a problem that occurs when a conventional method of manufacturing a semiconductor device is used.

FIG. 13 is a diagram illustrating a problem that occurs when a conventional method of manufacturing a semiconductor device is used.

[Explanation of symbols]

 Reference Signs List 100, 200 Semiconductor substrate 101, 201 Base insulating film 102, 202 First conductive film 102A, 202A Lower wiring 103, 203 First interlayer insulating film 104, 204 First connection hole 105, 205 Lower plug 106, 206 Resist Pattern 107, 207 Second interlayer insulating film 108, 208 Third interlayer insulating film 109, 209 Air gap 110, 210 Fourth interlayer insulating film 111, 211 Mask pattern 112, 212 Second connection hole 113, 213 Top Plug 114, 214 Upper layer wiring 115 Adjacent lower plug 116 Adjacent upper plug

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 HH09 JJ19 KK09 NN03 PP19 QQ08 QQ09 QQ24 QQ37 QQ48 RR04 RR29 SS02 SS15 XX00 XX01 XX03 XX04 XX15 XX25

Claims (14)

[Claims] A step of depositing a first conductive film on the semiconductor substrate; and forming a lower interlayer insulating film on the first conductive film.
Selectively etching the lower interlayer insulating film to form a first opening reaching the first conductive film, and embedding a second conductive film in the first opening. Forming a lower plug connected to the first conductive film, and after forming a mask pattern on the lower interlayer insulating film, using the mask pattern and the lower plug as a mask to form the lower interlayer insulating film and A step of sequentially performing etching on the first conductive film to form a lower wiring formed of the first conductive film and connected to the lower plug; and forming an upper interlayer insulating film on the semiconductor substrate, Forming an air gap in a space between the lower interconnects; and selectively etching the upper interlayer insulating film to form a second opening reaching the lower plug. Forming an opening; forming an upper plug connected to the lower plug by embedding a third conductive film in the second opening; and forming the upper plug on the upper interlayer insulating film Forming an upper wiring so as to be connected to the semiconductor device. 2. The method according to claim 1, wherein forming the lower plug includes flattening an upper surface of the lower interlayer insulating film so as to be flush with an upper surface of the lower plug. Of manufacturing a semiconductor device. 3. The method according to claim 1, wherein an area of an upper surface of the lower plug is larger than an area of a lower surface of the upper plug. 4. An upper interlayer insulating film comprising: a first insulating film deposited so as to form the air gap; and a second insulating film deposited on the first insulating film. The method for manufacturing a semiconductor device according to claim 1, further comprising: 5. The first insulating film is formed by a plasma CVD method, and the second insulating film is formed by a high-density plasma CVD method using a higher-density plasma than the plasma CVD method. The method for manufacturing a semiconductor device according to claim 4, wherein: 6. The upper interlayer insulating film further comprises a third insulating film deposited on the second insulating film and having a planarized surface. Item 5. The method for manufacturing a semiconductor device according to Item 4. 7. The method according to claim 6, wherein most of the upper plug is covered with the third insulating film. 8. The surface of the second insulating film is planarized by polishing until the lower plug or the first insulating film is exposed after the second insulating film is formed. 5. The method for manufacturing a semiconductor device according to item 4. 9. A lower wiring formed on a semiconductor substrate and having an air gap in a space between wirings; an upper wiring formed on the lower wiring via an interlayer insulating film; a lower wiring and the upper wiring; A plug for connecting the lower layer wiring, and an upper plug formed on the lower plug to connect to the upper layer wiring. Characteristic semiconductor device. 10. The semiconductor device according to claim 9, wherein an area of an upper surface of said lower plug is larger than an area of a lower surface of said upper plug. 11. The semiconductor device further comprises: an adjacent plug connecting the lower wiring and the upper wiring, adjacent to the plug, wherein the adjacent plug is formed on the lower wiring so as to be adjacent to the lower plug. The semiconductor device according to claim 9, further comprising: an adjacent lower plug; and an adjacent upper plug formed on the adjacent lower plug so as to be adjacent to the upper plug. 12. The interlayer insulating film includes a lower interlayer insulating film deposited so as to cover an upper surface of the lower wiring, and an upper interlayer insulating film deposited on the lower interlayer insulating film. The interlayer insulating film has a first insulating film deposited so as to form the air gap, and a second insulating film deposited on the first insulating film. The semiconductor device according to claim 9, wherein 13. The semiconductor device according to claim 13, wherein the upper interlayer insulating film further includes a third insulating film deposited on the second insulating film and having a planarized surface. Item 13. The semiconductor device according to item 12. 14. The semiconductor device according to claim 13, wherein most of said upper plug is covered by said third insulating film.