JP2002189427A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide structure of a semiconductor device capable of realizing low power consumption even when the screen of the device is made to be large in size and its manufacturing method. SOLUTION: In this device, the lowering resistance of wirings is attained by applying plating treatment to surfaces of source wirings 126 of a pixel part 205 and the source wirings 126 of the pixel part 205 are manufactured in processes different from those in manufacturing of source wirings of a driving circuit part. Moreover, the lowering of resistance of electrodes is attained also in electrodes of a terminal part by applying plating treatment to the electrodes similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to a device typified by a liquid crystal display device (mounted with a liquid crystal module) and an electronic device mounted with such a device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

Conventionally, a liquid crystal display device has been known as an image display device. Active-matrix liquid crystal display devices have come to be used more often because high-definition images can be obtained as compared with passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and a counter electrode corresponding to the pixel electrode, optical modulation of a liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is perceived by the observer as a display pattern.

The use of such an active matrix type liquid crystal display device is expanding, and the demand for higher definition, higher aperture ratio, and higher reliability is increasing as the screen size is increased. At the same time, demands for higher productivity and lower cost have been increasing.

[0006]

Conventionally, when a TFT is manufactured using aluminum as a gate wiring material of the above-mentioned TFT, a protrusion such as a hillock or a whisker is formed by heat treatment, and diffusion of aluminum atoms into a channel formation region is performed. As a result, TFT malfunctions and TFT characteristics are degraded. Therefore, when a metal material that can withstand heat treatment, typically a metal element having a high melting point, is used, problems such as an increase in screen resistance and an increase in wiring resistance occur, and an increase in power consumption. And so on.

Accordingly, an object of the present invention is to provide a structure of a semiconductor device which realizes low power consumption even when the screen is enlarged, and a method for manufacturing the same.

[0008]

According to the present invention, the surface of the source wiring in the pixel portion is plated to reduce the resistance of the wiring. Note that in the present invention, the source wiring in the pixel portion is manufactured in a step different from that of the source wiring in the driver circuit portion. Also, the electrode of the terminal portion is similarly plated to reduce the resistance.

In the present invention, it is desirable that the wiring before plating is formed of the same material as the gate electrode, and the surface of the wiring is plated to form the source wiring.
Further, it is desirable to use a material film to be plated that has lower electric resistance than the gate electrode. Therefore, the source wiring of the pixel portion becomes a low-resistance wiring due to the plating process.

[0010] The structure of the invention disclosed in this specification includes a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. A semiconductor device having a TFT, comprising: a first n-channel TFT having a source wiring surrounding a wiring made of the same material as the gate electrode and having a surface covered with a material film having a lower resistance than the gate electrode; A driving circuit including a pixel portion provided with a second n-channel TFT and a p-channel TFT; and a surface surrounding the wiring made of the same material as the gate electrode having a lower resistance than the gate electrode. And a terminal portion covered with a flexible material film.

In the above structure, the low-resistance material film is a material film containing Cu, Al, Au, Ag, or an alloy thereof as a main component.

Also, there is provided a semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. , Having a plated source wiring
A pixel portion having an n-channel TFT, a driving circuit having a circuit including a second n-channel TFT and a p-channel TFT, and a plated terminal portion. It is a semiconductor device.

In the above structure, the surface of the terminal portion and the surface of the source wiring of the pixel portion may be formed of Cu, Al, Au, A
g or a thin film made of a material containing these alloys as a main component.

In the above structure, the terminal portion and the source line of the pixel portion may be plated simultaneously or separately. The plated source wiring is obtained by plating a wiring made of the same material as the gate electrode. Further, the plated source wiring is a wiring formed by a printing method and made of a material having lower resistance than the gate electrode.

In the above structure, the second n-channel TFT and the p-channel TFT may be formed by a CMOS.
A circuit is formed.

In the above structure, the first n-channel TFT has a gate electrode and a channel formation region overlapping the gate electrode, and the width of the channel formation region is equal to the width of the gate electrode. It is characterized by being. Alternatively, in the above structure, the first n-channel TFT includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. In that case, a triple gate structure having three channel formation regions is preferable.

In the above structure, the n-channel TFT of the driving circuit has a gate electrode having a tapered portion, a channel formation region overlapping the gate electrode, and an impurity region partially overlapping the gate electrode. ing.

In the above structure, the impurity concentration in the impurity region of the n-channel TFT includes a region having a concentration gradient in a range of at least 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ^3. It is characterized in that the impurity concentration increases as the distance from the region increases.

The structure of the present invention relating to a manufacturing method for obtaining each of the above structures is a method for manufacturing a semiconductor device having a driving circuit, a pixel portion, and a terminal portion on an insulating surface, wherein Forming a layer, forming a first insulating film on the semiconductor layer, and forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film. Adding an impurity element imparting n-type to the semiconductor layer using the first gate electrode as a mask,
Forming a first impurity region of a mold, forming a tapered portion by etching the first gate electrode,
Adding an impurity element imparting n-type to the semiconductor layer by passing through the tapered portion of the first gate electrode to form an n-type second impurity region; and forming a tapered portion of the first gate electrode. Forming a p-type impurity region by adding an impurity element imparting p-type to the semiconductor layer by passing through the portion, plating the source wiring of the pixel portion and the surface of the terminal portion, A method for manufacturing a semiconductor device, comprising: forming a second insulating film covering a source wiring of a pixel portion and the terminal portion; and forming a gate wiring and a source wiring of a driver circuit over the second insulating film. It is.

Further, another aspect of the present invention relates to a method of manufacturing a semiconductor device having a driving circuit, a pixel portion, and a terminal portion on an insulating surface, the method including forming a semiconductor layer on the insulating surface. Forming a first insulating film on the semiconductor layer, forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film; Forming an n-type first impurity region by adding an impurity element imparting n-type to the semiconductor layer using the gate electrode as a mask; and etching the first gate electrode to form a tapered portion. Forming an n-type second impurity region by adding an impurity element imparting n-type to the semiconductor layer by passing through a tapered portion of the first gate electrode; Through the taper portion of Forming a p-type impurity region by adding an impurity element to be provided, plating the surface of the source wiring of the pixel portion, plating the surface of the terminal portion, A method for manufacturing a semiconductor device, comprising: a step of forming a second insulating film covering a source wiring and the terminal portion; and a step of forming a gate wiring and a source wiring of a driver circuit over the second insulating film.

In the above structure, the source wiring and the terminal of the pixel portion may be formed of Cu, Al, Au, Ag,
Alternatively, it is characterized by being made of a material containing these alloys as main components.

Further, in the above structure, in the plating step, the source wirings of the pixel portion are connected by wirings so as to have the same potential. The wiring connected to have the same potential is
After plating, the substrate may be divided by laser light, or after plating, the substrate may be divided at the same time as the substrate.

[0023]

Embodiments of the present invention will be described below.

First, after forming a base insulating film on a substrate,
A semiconductor layer having a desired shape is formed by a first photolithography step.

Next, an insulating film (including a gate insulating film) covering the semiconductor layer is formed. A first conductive film and a second conductive film are stacked over the insulating film. These stacked films are subjected to a first etching process in a second photolithography step, and a gate electrode including a first conductive layer and a second conductive layer, a source wiring in a pixel portion, and an electrode in a terminal portion are formed. Form. Note that, in the present invention, after a gate electrode is formed first, a gate wiring is formed on the interlayer insulating film.

Next, while keeping the resist mask formed in the second photolithography process as it is,
An n-type impurity region (high concentration) is formed in a self-aligned manner by adding an impurity element imparting n-type to the semiconductor (such as phosphorus).

Next, while keeping the resist mask formed in the second photolithography process as it is,
A second etching process is performed by changing the etching conditions,
A first conductive layer (first width) and a second conductive layer (second width) having a tapered portion are formed. Note that the first width is the second width.
, And the electrode composed of the first conductive layer and the second conductive layer here is the gate electrode of the n-channel TFT (first electrode).
Gate electrode).

Next, after removing the resist mask, an impurity element imparting n-type to the semiconductor layer is added to the semiconductor layer through the tapered portion of the first conductive layer using the second conductive layer as a mask. Here, a channel formation region is formed below the second conductive layer, and an impurity region (low concentration) whose impurity concentration gradually increases with distance from the channel formation region is formed below the first conductive layer. .

Thereafter, the tapered portion is selectively removed in order to reduce the off current of the TFT in the pixel portion. Dry etching may be performed with the mask shown in FIG. 17 being overlaid to remove only the tapered portion of the gate electrode in the pixel portion. In particular, it is not necessary to selectively remove the tapered portion, but if not removed, it is desirable to reduce the off-state current with a triple gate structure as shown in FIG.

Next, a mask is formed by a third photolithography method so as to cover a region where an n-channel TFT is to be formed, and a third doping process is performed. In the third doping process, a p-type impurity region (high concentration) is formed by adding an impurity element (boron) imparting p-type to the semiconductor.

Next, after activating the impurity element added to each semiconductor layer, plating (electroplating) is performed to form a metal film on the surface of the source wiring in the pixel portion and the surface of the electrode in the terminal portion. Form. The plating method is a method in which a direct current is passed through an aqueous solution containing metal ions to be formed by the plating method to form a metal film on the cathode surface. As the metal to be plated, a material having a lower resistance than the gate electrode, for example, copper, silver, gold, chromium, iron, nickel, platinum, or an alloy thereof can be used. Copper has an extremely low electric resistance and is most suitable for the metal film covering the surface of the source wiring of the present invention. As described above, in the present invention, since the source wiring of the pixel portion is covered with the low-resistance metal material, the pixel portion can be driven at a sufficiently high speed even if the area of the pixel portion is increased.

The thickness of the metal film formed by the plating method can be appropriately set by a practitioner by controlling the current density and the time.

In the present invention, the term “source wiring” includes the metal film formed on the surface.

Next, an interlayer insulating film is formed, and a transparent conductive film is formed. Next, the transparent conductive film is patterned by a fourth photolithography method to form a pixel electrode. Next, a contact hole is formed by a fifth photolithography step. Here, a contact hole reaching the impurity region, a contact hole reaching the gate electrode, and a contact hole reaching the source wiring are formed.

Next, a conductive film made of a low-resistance metal material is formed, and a gate wiring, an electrode connecting the source wiring and the impurity region, and an electrode connecting the pixel electrode and the impurity region are formed by a sixth photolithography process. To form In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. The source wiring is electrically connected to the impurity region (source region) through a contact hole provided in the interlayer insulating film. Further, the electrode connected to the pixel electrode is electrically connected to the impurity region (drain region) through a contact hole provided in the interlayer insulating film.

In this way, an element substrate including a pixel portion having a pixel TFT (n-channel TFT) with six masks and a driving circuit having a CMOS circuit is formed by a total of six photolithography steps. be able to. Note that an example in which a transmissive display device is manufactured is described here; however, a reflective display device can be manufactured using a highly reflective material for a pixel electrode. In the case of manufacturing a reflective display device, a reflective electrode can be formed at the same time as a gate wiring; therefore, an element substrate can be formed with five masks.

Although an example in which the source wiring of the pixel portion and the electrode of the terminal portion are formed simultaneously with the gate electrode has been described,
They may be formed separately. For example, after adding an impurity element to each semiconductor layer, an insulating film for protecting a gate electrode is formed, and the impurity element added to each semiconductor layer is activated.
Further, a source wiring of a pixel portion made of a low-resistance metal material (typically, a material containing aluminum, silver, and copper as a main component) and an electrode of a terminal portion are simultaneously formed on the insulating film by a photolithography process. Is also good. The thus obtained source wiring of the pixel portion and the electrode of the terminal portion are plated. Further, in order to reduce the number of masks, a source wiring in a pixel portion may be formed by a printing method.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0039]

[Embodiment 1] Here, a pixel portion (n-channel type TFT) and a TFT (n-channel type TFT) constituting a CMOS circuit of a driving circuit provided around the pixel portion are provided on the same substrate.
A method for simultaneously manufacturing an FT and a p-channel TFT will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 100 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that the substrate 100 is not particularly limited as long as it has a light-transmitting property, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 100,
A base film 101 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. For the first layer of the base film 101, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 101a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 101a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as a second layer of the base film 101, a silicon oxynitride film 101b formed using SiH ₄ and N ₂ O as a reaction gas is formed by a plasma CVD method to a thickness of 50 to 200 n.
m (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 101b (composition ratio: Si = 32%, O = 59%, N = 7)
%, H = 2%).

Next, the semiconductor layers 102 to 10 are formed on the underlying film.
5 is formed. The semiconductor layers 102 to 105 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 102 to 105 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferable to use silicon or a silicon-germanium alloy. In this embodiment, a 55-nm-thick amorphous silicon film is formed by a plasma CVD method, and then a solution containing nickel is held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed, and further, laser annealing treatment for improving crystallization is performed. Thus, a crystalline silicon film was formed. Then, semiconductor layers 102 to 105 were formed by patterning the crystalline silicon film using a photolithography method.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 40.
(Typically ^{200~300mJ / cm 2) 0mJ / cm} 2 to. When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 35 to
0 to 500 mJ / cm ² ). And width 100-1
A laser beam condensed linearly at 000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 80 to 98%
What should be done.

Next, a gate insulating film 106 covering the semiconductor layers 102 to 105 is formed. The gate insulating film 106 has a thickness of 40 to 40
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59) having a thickness of 115 nm by a plasma CVD method.
%, N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 1A, a first conductive film 107a having a thickness of 20 to 100 nm and a second conductive film 1 having a thickness of 100 to 400 nm are formed on the gate insulating film 106.
07b is formed. In this embodiment, the thickness is 30 nm.
A first conductive film 107a made of a TaN film, and a film thickness of 37
A second conductive film 107b made of a 0-nm W film was formed by lamination. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. Also,
The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore,
In this embodiment, a sputtering method using a high-purity W (purity 99.9999% or 99.99%) target is employed.
Further, by forming the W film with sufficient care so as not to mix impurities from the gas phase at the time of film formation, the resistivity is 9 to 2%.
0 μΩcm was realized.

In this embodiment, the first conductive film 107 is used.
a is TaN, and the second conductive film 107b is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, and C may be used.
It may be formed of an element selected from u, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, and the second conductive film is formed of a second conductive film.
The first conductive film is formed of a titanium nitride (TiN) film, the second conductive film is formed of a W film, and the first conductive film is formed of a tantalum nitride (TaN).
A combination of a film and an Al film as the second conductive film;
The first conductive film may be formed of a tantalum nitride (TaN) film and the second conductive film may be formed of a Cu film.

Next, masks 108a to 112a made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow ratio was 2
At 5/25/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. In addition, Cl ₂ , BCl ₃ , SiCl ₄ , C
Chlorine gas such as Cl ₄ or CF ₄ , S
Fluorine gas such as F ₆ , NF ₃ , or O ₂
Can be used as appropriate. Here, a dry etching apparatus using ICP manufactured by Matsushita Electric Industrial Co., Ltd. (Mode
lE645- □ ICP) was used. Apply 150W RF (13.56MHz) power to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 200.39 nm / m.
etching rate for in, TaN is 80.32 nm
/ Min and the selectivity ratio of W to TaN is about 2.5
It is. Further, according to the first etching condition, W
Has a taper angle of about 26 °.

Thereafter, a mask 108a made of resist is formed.
Change to the second etching condition without removing ~ 112a,
CF ₄ and Cl ₂ are used as etching gases, the respective gas flow ratios are 30/30 (sccm), and 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma. After the formation, etching was performed for about 30 seconds. 20 W of RF (1
3.56MHz) Power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees.

In this manner, the first-shaped conductive layers 113 to 117 (the first conductive layers 113 a to 117 a and the second conductive layer 113 b) including the first conductive layer and the second conductive layer are formed by the first etching process. To 117b). (Figure 1
(B) The width of the first conductive layer in the channel length direction here corresponds to the first width described in the above embodiment.
Although not illustrated, a region of the insulating film 106 serving as a gate insulating film which is not covered with the first shape conductive layers 113 to 117 is etched to a thickness of about 10 to 20 nm to form a thinned region.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer. (FIG. 1C) The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ¹³
-5 × 10 ¹⁵ / cm ^2, and acceleration voltage of 60-100 keV
Do as. In this embodiment, the dose amount is 1.5 × 10 ¹⁵ / c
and m ^2, an accelerating voltage is set to 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 113 to 116
Serve as a mask for the impurity element imparting n-type, and n-type impurity regions (high concentration) 118 to 121 are self-aligned.
Is formed. 1 × 10 in impurity regions 118 to 121
An impurity element for imparting n-type is added in a concentration range of ²⁰ to 1 × 10 ²¹ / cm ³ .

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are set to 24/12/24 (sccm).
700W RF (13.56MHZ) on coil type electrode at pressure of Pa
z) Apply power and generate plasma to perform etching 2
Performed for 5 seconds. 10W RF on substrate side (sample stage)
(13.56 MHz) Power is applied and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate for W is 227.3 nm / min, the etching rate for TaN is 32.1 nm / min, and T
The selectivity ratio of W to aN is 7.1, and the insulating film 106
The etching rate for SiON is 33.7 nm.
/ Min, and the selectivity ratio of W to TaN is 6.83.
It is. As described above, when SF ₆ is used as the etching gas, the selectivity with respect to the insulating film 106 is high, so that the film loss can be suppressed.

The taper angle of the second conductive layer (W) became 70 ° by the second etching process. By this second etching process, the second conductive layers 122b to 126b
To form On the other hand, the first conductive layer is hardly etched, and forms first conductive layers 122a to 126a. The masks 108a to 112a made of resist are deformed into masks 108b to 112b made of resist by the second etching process. (Figure 1
(D)) Although not shown, actually, the width of the first conductive layer is reduced by about 0.15 μm, that is, about 0.3 μm in the entire line width as compared with before the second etching process. The width of the second conductive layer in the channel length direction here corresponds to the second width described in the embodiment.

Note that an electrode formed by the first conductive layer 122a and the second conductive layer 122b becomes a gate electrode of an n-channel TFT of a CMOS circuit formed in a later step, and the first conductive layer An electrode formed by the second conductive layer 125b and the second conductive layer 125b serves as one electrode of a storage capacitor formed in a later step.

In the second etching process, CF ₄ , Cl ₂ and O ₂ can be used as an etching gas. In that case, if the gas flow ratio of each gas is 25/25/10 (sccm), and RF (13.56 MHz) power of 500 W is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Good. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. C
When F ₄ , Cl ₂ and O ₂ are used, the etching rate for W is 124.62 nm / min, the etching rate for TaN is 20.67 nm / min, and TaN
Is 6.05. Therefore, the W film is selectively etched. In this case, the insulating film 1
Of the area 06, the area not covered with the first shape conductive layers 122 to 126 is etched by about 50 nm to form a thinned area.

Next, after removing the resist mask, a second doping process is performed to obtain the state shown in FIG. Doping is performed in the second conductive layers 122b to 125b
Is used as a mask for the impurity element, and the semiconductor layer below the tapered portion in the first conductive layer is doped so that the impurity element is added. In this embodiment, P (phosphorus) is used as an impurity element, doping conditions are a dose of 1.5 × 10 ¹⁴ / cm ² , an acceleration voltage of 90 keV, an ion current density of 0.5 μA / cm ² , and phosphine (PH ₃ ) 5. Plasma doping was performed with a hydrogen dilution gas of 30% and a gas flow rate of 30 sccm. Thus, impurity regions (low concentration) 127 to 136 overlapping with the first conductive layer are formed in a self-aligned manner. The concentration of phosphorus (P) added to the impurity regions 127 to 136 is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ ,
In addition, the first conductive layer has a concentration gradient according to the thickness of the tapered portion. Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration (P concentration) gradually decreases from the end of the tapered portion in the first conductive layer toward the inside. That is, a concentration distribution is formed by the second doping process. Further, an impurity element is further added to the impurity regions (high concentration) 118 to 121 to form impurity regions (high concentration) 137 to 145.

In this embodiment, the width of the tapered portion (width in the channel length direction) is preferably at least 0.5 μm, and the limit is 1.5 μm to 2 μm. Therefore, the width in the channel length direction of the impurity region (low concentration) having a concentration gradient is also 1.5 μm to 2 μm although it depends on the film thickness.
Is the limit. Here, the impurity region (high concentration)
Although the impurity region and the impurity region (low concentration) are shown as being separate from each other, there is actually no clear boundary, and a region having a concentration gradient is formed. Similarly, there is no clear boundary between the channel formation region and the impurity region (low concentration).

Next, a third etching process is performed while the portions other than the pixel portion are covered with the mask 146 later. Mask 14
As 6, a metal plate, a glass plate, a ceramic plate, or a ceramic glass plate may be used. A top view of the mask 146 is shown in FIG. In this third etching process,
The tapered portion of the first conductive layer in a region not overlapping with the mask 146 is selectively dry-etched so that a region overlapping with the impurity region of the semiconductor layer is eliminated. The third etching process is performed using an ICP etching apparatus using Cl ₃ having a high selectivity to W as an etching gas.
In this embodiment, the gas flow ratio of Cl ₃ is set to 80 (sccm).
Then, 350 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma, and etching was performed for 30 seconds. A 50 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. By the third etching, first conductive layers 124c and 126c are formed.
(FIG. 2 (B))

In this embodiment, an example in which the third etching process is performed has been described. However, if it is not necessary to perform the third etching process, it is not necessary to perform the third etching process.

Next, a semiconductor layer which will later become an active layer of an n-channel TFT is covered with a mask 147 made of a resist formed by a third photolithography method.
A third doping process is performed. By the third doping treatment, a p-type impurity in which an impurity element imparting a conductivity type (p-type) opposite to the one conductivity type (n-type) is added to a semiconductor layer serving as an active layer of a p-channel TFT. Regions (high-concentration impurity regions and low-concentration impurity regions) 148 to 150 are formed. In order to dope by passing through the tapered portion,
The p-type low concentration impurity region has the same concentration gradient as the n-type low concentration impurity region. (FIG. 2C) Using the first conductive layer as a mask for an impurity element, adding an impurity element imparting p-type to the p-type impurity regions 148 to 1
Form 50. In this embodiment, the p-type impurity region 148
150 are formed by ion doping using diborane (B ₂ H _6). Note that phosphorus is added at different concentrations to the impurity regions by the first doping process and the second doping process, and the boron concentration is 2 × 10 ²⁰ to 2 × 10 ^{21 in} any of the regions. By performing the doping treatment to have a density of / cm ³ , there is no problem because it functions as the source region and the drain region of the p-channel TFT.

Further, when the film is not reduced by the second etching process, for example, when SF ₆ is used as an etching gas,
In order to facilitate the doping of boron, etching (C) for thinning the insulating film 207 before the third doping process is performed.
Reactive ion etching using HF ₃ gas (RIE
Method)).

Next, as shown in FIG. 2D, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Although not shown, the impurity element is diffused by this activation treatment, and the boundary between the n-type impurity region (low concentration) and the impurity region (high concentration) is almost eliminated.

In this embodiment, at the same time as the above-mentioned activation treatment, nickel used as a catalyst during crystallization is gettered into an impurity region containing high-concentration phosphorus, and the semiconductor layer mainly serving as a channel formation region is formed. The nickel concentration in is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Next, heat treatment is performed in a hydrogen atmosphere to hydrogenate the semiconductor layer. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be used.

When a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, plating is performed on the surface of the source wiring 126 in the pixel portion and the electrode surface in the terminal portion. FIG. 7 (A)
FIG. 7B shows a top view immediately after plating, and FIG. 7B shows a cross-sectional view thereof. 7, reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. FIG.
Shows one TFT in the drive circuit portion for simplification, and shows only the source wiring 126 in the pixel portion. In this embodiment, a copper plating solution (manufactured by EEJA: Microfab Cu
2200). Further, at the time of this plating, as shown in an example in FIG. 10, wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, when the substrate is divided, the electrodes are divided and separated from each other. Further, a short ring may be formed with a dummy pattern.

Next, a first interlayer insulating film 155 covering the source wiring of the pixel is formed. As the first interlayer insulating film 155, an inorganic insulating film containing silicon as its main component may be used.

Next, a second interlayer insulating film 156 made of an organic insulating material is formed on the first interlayer insulating film 155. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed.

Next, a pixel electrode 147 made of a transparent conductive film was patterned on the second interlayer insulating film using a photomask. The transparent conductive film used as the pixel electrode 147 is, for example, ITO (indium tin oxide alloy), indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (Z
nO) or the like may be used.

Next, the second insulating film is selectively etched using a photomask to form each impurity region (137, 1).
38, 149, 150, 151, 153, 144), a contact hole reaching the source wiring 126 in the pixel portion, a contact hole reaching the gate electrode 124, and a contact hole reaching the electrode 125b.

Next, the impurity regions (137, 138, 1
49, 150) and an electrode 157 electrically connected to each of them.
160 and the source wiring of the driving circuit and the impurity region 14
4 and electrode 15 electrically connected to impurity region 153
0, 163, an electrode (connection electrode) 161 for electrically connecting the impurity region 151 serving as a source region to the source wiring 126 of the pixel portion, a gate wiring 162 for electrically connecting to the gate electrode 124, and an electrode 125b. A capacitor wiring 169 electrically connected to the capacitor wiring 169 is formed.

The pixel electrode 147 is connected to the pixel electrode 147.
Is electrically connected to the impurity region 153 of the pixel TFT 206 by the electrode 163 overlapping and in contact with the pixel electrode 147.
Is electrically connected to the impurity region 144 of the storage capacitor 207 by the electrode 150 which overlaps with the storage capacitor 207.

In this embodiment, the example in which the electrodes 150 and 163 are formed after the pixel electrode is formed has been described. Pixel electrodes may be formed.

The impurity regions 135, 136, 144, and 145 functioning as one electrode of the storage capacitor 207 are each doped with an impurity element imparting p-type. The storage capacitor 207 is formed by using the insulating film 106 as a dielectric.
Electrodes 125a and 125b connected to capacitance wiring 169
And a semiconductor layer.

As described above, the n-channel TFT 20
A driver circuit 201 including a CMOS circuit 202 including three and p-channel TFTs 204 and a pixel portion 205 including a pixel TFT 206 including n-channel TFTs and a storage capacitor 207 can be formed over the same substrate.
(FIG. 3B) In this specification, such a substrate is referred to as an active matrix substrate for convenience.

FIG. 5 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. FIG. 3B
Are assigned the same reference numerals. FIG. 3 (B)
A chain line AA ′ in FIG. 4 corresponds to a cross-sectional view taken along a line AA ′ in FIG. In addition, a chain line B- in FIG.
B ′ corresponds to a cross-sectional view taken along a dashed line BB ′ in FIG. FIG. 4 shows a top view immediately after the source wiring 126 of the pixel is formed.

In the pixel structure of this embodiment, the end of the pixel electrode 147 is arranged so as to overlap with the source wiring 126 so that the gap between the pixel electrodes is shielded from light without using a black matrix.

Further, according to the steps described in this embodiment, the number of photomasks required for manufacturing the active matrix substrate could be six.

A process for manufacturing an active matrix type liquid crystal display device from the active matrix substrate thus obtained will be described below. FIG. 6 is used for the description.

After obtaining the active matrix substrate in the state shown in FIG. 3B, an alignment film 301 is formed on the active matrix substrate shown in FIG. In addition,
In this embodiment, before forming the alignment film 301, an organic resin film such as an acrylic resin film is patterned to form columnar spacers at desired positions for maintaining a substrate interval. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 300 is prepared. The opposite substrate is provided with a color filter in which a coloring layer 302 and a light-shielding layer are arranged corresponding to each pixel. A flattening film 304 covering the color filter and the light shielding layer was provided. Next, a counter electrode 305 made of a transparent conductive film was formed in the pixel portion over the planarization film 304, an alignment film 306 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealant 307.
Paste in. A filler is mixed in the sealant 307, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 308 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 308. Then, the active matrix substrate or the opposing substrate is cut into a desired shape. Here, the dummy pattern provided for the plating process is divided.

FIG. 8A shows a top view after division, and FIG. 8B shows a cross-sectional view taken along a dotted line DD ′. FIG.
Reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. FIG. 8 shows one TFT in the driver circuit portion for simplification, and shows only the source wiring 126 in the pixel portion. The electrode 401 is connected to the wiring 157
To 160 are electrically connected. In the terminal section 400, a part of the plated electrode 401 is exposed,
The transparent conductive film 404 made of ITO is formed.

Further, the polarizing plate 309 is formed by using a known technique.
Etc. were provided as appropriate. Then, an FPC was attached to an exposed portion of the terminal portion using a known technique. FIG.
(C) shows a cross-sectional view of the FPC 405 after bonding.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG. Note that the same reference numerals are used for portions corresponding to FIG.

The top view shown in FIG. 9 shows a pixel portion, a driving circuit,
FPC (Flexible Printed Wiring Board: Flexible Print
ed Circuit) external input terminal 309 to which 311 is attached,
Wiring 31 connecting external input terminals to the input section of each circuit
An active matrix substrate on which 0 and the like are formed and a counter substrate 300 provided with a color filter and the like are attached to each other with a sealant 307 interposed therebetween.

A light-shielding layer 303a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 201a, and a light-shielding layer 403b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 201b. In the color filter 302 provided on the counter substrate side on the pixel portion 205, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displaying, a red (R) colored layer, a green (G) colored layer,
A color display is formed by three colors of a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

Here, the color filter 302 is provided on the opposite substrate in order to achieve colorization. However, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer 303 is provided between adjacent pixels in the color filter, and shields portions other than the display area from light. Further, a light-blocking layer may be provided in a region covering the driver circuit. Since the area covering the drive circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device, a structure in which a light-blocking layer is not particularly provided may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, an FPC 411 composed of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

[0092] Although an example in which all the driving circuits are formed on the substrate is shown here, several ICs may be used as a part of the driving circuit.

The liquid crystal module manufactured as described above can be used as a display unit of various electronic devices.
By incorporating this liquid crystal module, the backlight 31
0, if the light guide plate 311 is provided and covered with the cover 312, FIG.
Is completed. Note that the cover 312 and the liquid crystal module are attached to each other using an adhesive or an organic resin. Further, when the substrate and the counter substrate are attached to each other, an organic resin may be filled between the frame and the substrate so as to be adhered.

[Embodiment 2] The present invention is characterized in that the source wiring of the pixel portion is formed in a step different from that of the source wiring of the driving circuit. In this embodiment, differences from the related art will be described in detail with reference to FIG. In FIG. 10, only three source wirings 91 and three gate wirings 92 are shown in the pixel portion for simplification. The source wirings 91 in the pixel portion are in the form of strips parallel to each other, and the interval between them is equal to the pixel pitch.

FIG. 10 is a block diagram for performing digital driving. In the present embodiment, a source-side drive circuit 93, a pixel portion 94, and a gate-side drive circuit 95 are provided. Note that in this specification, a drive circuit is a general term including a source-side drive circuit and a gate-side drive circuit.

The source side drive circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, D
A / A converter 93d and a buffer 93e are provided.
Further, the gate-side drive circuit 95 includes a shift register 95.
a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.

Further, in this embodiment, as shown in FIG. 10, a contact portion exists between the source side drive circuit 93 and the pixel portion 94. This is because the source wiring of the source side driver circuit and the source wiring 91 of the pixel portion are formed by different processes. In the present invention, the source wiring of the pixel portion is formed by a process different from that of the source wiring of the source side driver circuit in order to cover the wiring using the same material as the gate electrode with a material having a low resistance. I have.

In order to perform the plating process, the source lines of the pixel portion are all connected by a wiring pattern so as to have the same potential, and an electrode for the plating process is provided. Also, the terminal portions are similarly connected by a wiring pattern, and provided with electrodes for plating. In FIG. 10, the electrodes for plating are separately provided. However, the electrodes may be connected by a wiring pattern and plated with one electrode at a time. Further, the dotted line in FIG. 10 is a dividing line of the substrate, and indicates a portion to be cut after the plating process.

The pixel section 94 includes a plurality of pixels, and each of the plurality of pixels is provided with a TFT element. Further, in the pixel portion 94, a large number of gate wirings 92 connected to the gate side driving circuit are provided in parallel with each other. Also, it is desirable that the terminal portion be plated with an electrode using the same material as the gate electrode and covered with a low-resistance material.

Note that a gate-side drive circuit may be provided on the side opposite to the gate-side drive circuit 95 with the pixel portion 94 interposed therebetween.

In the case of analog driving, a sampling circuit may be provided instead of the latch circuit.

This embodiment can be combined with the first embodiment.

[Embodiment 3] In the embodiment 1, the example in which the tapered portion is selectively etched is shown. In this embodiment, an example is shown in which the etching is not performed. Note that only the pixel unit is different, so only the pixel unit is illustrated in FIG.

This embodiment is similar to the third embodiment shown in FIG.
This is an example in which the etching process is not performed. In FIG. 11A, the gate electrode of the pixel TFT 709 corresponds to FIG.
As in (A), a pixel electrode 700 made of a transparent conductive film is formed.

FIG. 11A is different from Example 1 in the structure of the gate electrode, and the first conductive layers 707 and 708 have a tapered portion. Therefore, the first conductive layer 707 overlaps with the impurity region with the insulating film interposed therebetween.

The first conductive layer 7 having a tapered portion
Reference numerals 07 and 708 correspond to the first conductive layer 124a of the first embodiment.

FIG. 11B shows an example of a triple gate structure. In FIG. 11B, the first conductive layer 804 overlaps with the impurity regions 803 and 805 with the insulating film interposed therebetween, and the first conductive layer 807 overlaps with the impurity regions 806 and 808 with the insulating film interposed therebetween. The conductive layer 810 overlaps with the impurity regions 809 and 811 with the insulating film interposed therebetween.

In this embodiment, the off current can be reduced by employing the triple gate structure. Further, the off-state current may be further reduced by reducing the width of the gate electrode, for example, to 1.5 μm.

This embodiment corresponds to the first embodiment or the second embodiment.
And can be freely combined.

[Embodiment 4] In Embodiment 1, an example of manufacturing an active matrix substrate used for a transmission type liquid crystal display device was described, but this embodiment shows an example of a reflection type. Note that only the pixel portion is different, so only the pixel portion is shown in FIG.

As a substrate, a glass substrate, a quartz substrate, or a plastic substrate can be used. Further, the present embodiment is not particularly limited since it is of a reflection type, and a silicon substrate, a metal substrate or a stainless steel substrate having an insulating film formed on the surface can also be used.

FIG. 12 shows that a source wiring 1401 is obtained by plating in accordance with the first embodiment, a second interlayer insulating film is formed, and then patterned using a photomask to form a contact hole. In this example, a gate wiring and a pixel electrode 1406 are formed. The pixel electrode 1406 is
It is electrically connected to the impurity region 1405. As a material of these electrodes and the pixel electrode 1406, a material having excellent reflectivity such as a film containing Al or Ag as a main component or a stacked film thereof is used. Note that, in FIG.
02 is a double gate structure, and the gate electrode 140
3 and 1404 and two channel forming regions overlapping with an insulating film interposed therebetween.

In the manufacturing method for obtaining the structure shown in FIG. 12, since the pixel electrode and the gate wiring can be manufactured at the same time, the number of photomasks required for manufacturing the active matrix substrate can be reduced to five.

[Embodiment 5] In this embodiment, an example in which a source wiring is formed in a step different from that of Embodiment 1 is shown in FIG.

FIG. 13A shows the source wiring 90 of the pixel portion.
In this example, an interlayer insulating film is formed after plating No. 3, a contact hole is formed in the interlayer insulating film, and then the terminal portion 900 is plated.

First, an electrode 901 in a terminal portion is formed in the same step as the gate electrode 902 in the drive circuit portion. A source wiring 903 is formed in the same step as the electrodes. First, only the source wiring 903 in the pixel portion is selectively plated. After that, an interlayer insulating film is formed, and a contact hole is formed. When forming this contact hole, the terminal portion 900 is formed.
Part of the electrode 901 is exposed. Next, only the exposed region of the electrode 901 in the terminal portion is plated to form a plating film 904. After that, a lead wiring, a source wiring, and a drain wiring are formed. In the subsequent steps, the structure shown in FIG.

However, the activation of the impurity element contained in the semiconductor layer is preferably performed before the formation of the plating film 904.

Further, similarly to the first embodiment, at the time of plating, wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, when the substrate is divided, the electrodes are divided and separated from each other. Further, a short ring may be formed with these dummy patterns.

FIG. 13B shows an example in which plating is performed in a step different from that shown in FIG. This embodiment is an example in which the gate electrode 1002 is formed and the source wiring 1003 is not formed at the same time.

After an insulating film for protecting the gate electrode 1002 is formed, an impurity element added to each semiconductor layer is activated, and a low-resistance metal material (typically, aluminum, A pixel portion source wiring 1003 made of a material mainly containing silver and copper);
The electrode 1001 of the terminal portion is formed at the same time. As described above, in the present invention, since the source wiring of the pixel portion is formed of a low-resistance metal material, the pixel portion can be sufficiently driven even if the area of the pixel portion is increased. Also, in order to reduce the number of masks,
The source wiring may be formed by a printing method.

Next, a plating process (electrolytic plating method) is performed to form a metal film on the surface of the source wiring 1003 in the pixel portion and on the surface of the electrode 1001 in the terminal portion. In the subsequent steps, the structure shown in FIG.

FIG. 13C shows an example in which a source wiring is formed in a step different from that shown in FIG.

In this embodiment, a source wiring is formed by a printing method. A conductive layer was provided in order to improve the positional accuracy of the source wiring of the pixel.

In this embodiment, in the same step as the gate electrode,
The conductive layers 905a and 905b were formed. Next, the impurity element was activated without covering the gate electrode with an insulating film. The activation was performed, for example, by performing thermal annealing under reduced pressure in an inert atmosphere to suppress the increase in resistance due to oxidation of the conductive layer. Next, a source wiring was formed by a printing method so as to fill the space between the conductive layers. Further, by providing a conductive layer along the source wiring, disconnection which is likely to occur in a printing method (screen printing) can be prevented. In the subsequent steps, the structure shown in FIG.

Screen printing is performed, for example, using metal particles (A
g, Al, etc.), and a paste (diluent) or ink mixed with a plate having an opening of a desired pattern as a mask, and a paste is formed on the substrate, which is a printing medium, from the opening, followed by thermal firing. By doing so, a wiring of a desired pattern is formed. Such a printing method is suitable for the present invention since it is relatively inexpensive and can cope with a large area.

It is also possible to apply a letterpress printing method using a rotating drum, an intaglio printing method, and various offset printing methods to the present invention instead of the screen printing method.

As described above, the source wiring of the pixel portion can be formed by various methods.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In Embodiment 1, a TFT having a top gate structure is shown, but the present invention is not limited to the TFT structure and can be applied. In this embodiment, an example of a pixel TFT 1502 having a bottom gate structure is shown in FIG.

First, after a gate electrode 1503 and a source wiring are formed over a substrate, a gate insulating film is formed. Next, a semiconductor film is formed so as to overlap with the gate electrode with the gate insulating film interposed therebetween. Next, an insulating layer is selectively formed in a portion of the semiconductor film to be a channel formation region, and doping is performed. Next, after performing an activation process, the semiconductor film and the gate insulating film are selectively removed. At this time, the insulating film covering the source wiring is removed to expose the surface. Next, a source wiring 1501 whose resistance is reduced by performing plating on the surface of the source wiring is formed.

Next, an interlayer insulating film is formed, a pixel electrode 1504 made of ITO is formed, and a contact hole is formed. Next, an electrode connecting the source region of the pixel TFT 1502 to the source wiring 1501, a gate wiring connecting to the gate electrode, and an electrode connecting the drain region of the pixel TFT 1502 and the pixel electrode 1504 are formed. Thus, the pixel TFT 1502 is completed.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 7] In this embodiment, an example in which a source wiring is formed in a step different from that of Embodiment 1 is shown in FIG.

FIG. 15 shows that after forming an interlayer insulating film, a pixel electrode 1600 made of ITO is formed on the interlayer insulating film.
This is an example in which a source wiring 1601 is formed.

In this embodiment, the source wiring is formed by screen printing, and the source wiring and the pixel TFT 160 are formed.
A connection electrode is provided to connect the two source regions.

Screen printing is performed, for example, using metal particles (A
g, Al, Cu, etc.), a paste (diluent) or ink mixed with a plate having an opening of a desired pattern as a mask, and a paste is formed on the substrate, which is a printing medium, from the opening, and then heated. The baking is performed to form a wiring having a desired pattern. Such a printing method is suitable for the present invention since it is relatively inexpensive and can cope with a large area.

It is also possible to apply a letterpress printing method using a rotating drum, an intaglio printing method, and various offset printing methods to the present invention instead of the screen printing method.

In this embodiment, the source wiring is formed of copper, and the connection electrode and the gate wiring are formed of a three-layered structure of Ti / Al / Ti.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 8] In this embodiment, an example of a top view of a pixel in a triple gate structure is shown in FIG.
It is shown in FIG.

In FIG. 17, reference numeral 1201 denotes a semiconductor layer;
Is a gate electrode, 1203 is a capacitor electrode, 1204 is a source wiring, 1205 is a gate wiring, 1206 is a capacitor wiring connected to a capacitor electrode, 1207 is an electrode connecting a semiconductor layer and a source wiring, 1209 is a pixel electrode, and 1208 is a pixel electrode. It is an electrode that connects the semiconductor layer and the pixel electrode.

In this embodiment, a gate electrode 1202 and a capacitor electrode 1203 are formed over the insulating film covering the semiconductor layer 1201 in the same step. The source wiring 1204 is formed in the same step as these electrodes or in another step. In this example, after the addition of the impurity element of the semiconductor layer and the activation treatment thereof, the semiconductor layer was formed on the gate insulating film in another step, and the surface was plated to reduce the resistance of the wiring. In this embodiment, the gate wiring 12 is formed on the interlayer insulating film covering the gate electrode 1202, the capacitor electrode 1203, and the source wiring 1204.
05, a capacitor wiring 1206, electrodes 1207 and 1208 are formed in the same step. Further, an electrode 1208 is provided so as to partially overlap with the pixel electrode 1209 formed of a transparent conductive film formed over the interlayer insulating film. In addition, as shown in FIG. 17, when viewed from above, the electrode 1208 has a capacitor wiring 1206 disposed between the electrode 1208 and the electrode 1207.

The gate electrode 1202 overlaps the semiconductor layer 1201 at three places with a gate insulating film interposed therebetween, and has a triple gate structure. The cross-sectional view near the gate electrode is almost the same as that in FIG.

In FIG. 11B, the capacitance of the pixel portion is changed to the pixel T.
FIG. 1 shows an example in which a semiconductor layer different from FT is used.
In 7, the capacitance is formed by a part of the semiconductor layer of the pixel TFT. In order to increase the capacity, the thickness of the insulating film is set to 80 nm.
It may be as thin as possible.

In this embodiment, the off-state current can be reduced by using the triple gate structure. Further, the off-state current may be further reduced by reducing the width of the gate electrode 1202, for example, to 1.5 μm.

This embodiment can be freely combined with any one of Embodiments 1 to 7.

[Embodiment 9] In this embodiment, as the heat treatment in Embodiment 1, PPTA (Plural Pulse Thermal A
nnealing).

PPTA means heating by a light source (halogen lamp, metal halide lamp, high-pressure mercury lamp, high-pressure sodium lamp, xenon lamp, etc.) and circulation of a refrigerant (nitrogen, helium, argon, krypton, xenon, etc.) into the processing chamber. Is a heat treatment in which a cooling cycle is repeated a plurality of times. The light emission time per light source is 0.1.
The irradiation is performed for 1 to 60 seconds, preferably 0.1 to 20 seconds, and a plurality of times. Note that the light source is turned on in a pulsed manner by the power supply and the control circuit so that the retention period of the semiconductor film is 0.5 to 5 seconds.

By irradiating the light selectively absorbed by the semiconductor film from the light source provided on one side or both sides by reducing the actual heating time by the PPTA, the substrate itself is not heated so much. Then, only the semiconductor film is selectively heated (heating rate: 100 to 200 ° C./sec). Also,
In order to suppress a rise in the temperature of the substrate, the substrate is cooled from the surroundings with a refrigerant (temperature reduction rate: 50 to 150 ° C./sec).

Among the heat treatments in the first embodiment, an example used for activation is shown below.

In the activation shown in FIG.
A activates. The pulse light is emitted from one side or both sides of the substrate using a tungsten halogen lamp as a light source. At this time, the flow rate of He is increased or decreased in synchronization with the blinking of the tungsten halogen lamp, and the semiconductor film is selectively heated.

The impurity element is activated by the PPTA, and the metal element used for crystallization contained in the semiconductor layer can be gettered from the channel formation region to the impurity region. Note that it is more effective if an impurity element imparting p-type is added to the impurity region in addition to phosphorus. Therefore, it is preferable to add a step of adding boron for imparting p-type after the first doping. Further, the PPTA processing chamber may be placed under a reduced pressure of 13.3 Pa or less to prevent oxidation and contamination.

This embodiment can be freely combined with any one of Embodiments 1 to 8.

[Embodiment 10] A drive circuit and a pixel portion formed by carrying out the present invention are composed of various modules (active matrix type liquid crystal module, active matrix type E).
C module). That is, the present invention can be applied to all electronic devices in which they are incorporated in the display unit.

Such electronic devices include a video camera, a digital camera, a head mounted display (goggle type display), a car navigation, a projector, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). Examples of these are shown in FIGS.

FIG. 18A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 18B shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 18C shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium), and includes a main body 2401, a display 2402, and a speaker 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 19A shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 19B shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103 having a diagonal of 10 to 50 inches.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to methods for manufacturing electronic devices in various fields. Further, the electronic apparatus of the present embodiment is the same as those of the first to third embodiments.
9 can be realized by using a configuration composed of any combination of.

[0162]

According to the present invention, in a semiconductor device typified by an active matrix type liquid crystal display device, excellent display can be realized even if the area of the pixel portion is increased and the screen is enlarged. Since the resistance of the source wiring in the pixel portion is greatly reduced, the present invention can be applied to a large screen having a diagonal of 40 inches or 50 inches, for example.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram illustrating a top view of a pixel.

FIG. 5 is a top view illustrating a pixel.

FIG. 6 is a diagram showing a cross-sectional structure of an active matrix liquid crystal display device.

FIG. 7 is a diagram showing a terminal unit.

FIG. 8 is a diagram showing a terminal unit.

FIG. 9 is a diagram showing an appearance of a liquid crystal module.

FIG. 10 is a top view.

FIG. 11 illustrates a cross section of a pixel portion.

FIG. 12 illustrates a cross section of a pixel portion.

FIG. 13 is a diagram showing a terminal portion.

FIG. 14 is a diagram showing an example of a bottom gate type TFT.

FIG. 15 illustrates a cross section of a pixel portion.

FIG. 16 is a view showing a mask 146;

FIG. 17 illustrates a top view of a pixel.

FIG. 18 illustrates an example of an electronic device.

FIG. 19 illustrates an example of an electronic device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 H01L 21/28 F 5F052 21/288 21/288 E 5F110 21/3213 27/08 331E 21 / 3205 21/88 D 21/8238 F 27/092 E 27/08 331 Z 29/786 27/08 321F 321D 29/78 612C F term (reference) 2H092 GA59 JA25 JA29 JA33 JA35 JA38 JA39 JA42 JA43 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB51 JB58 JB63 JB69 KA04 MA05 MA08 MA11 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA35 MA37 MA41 NA28 PA06 4M104 AA09 BB04 BB13 BB32 CC05 DD12 DD26 DD37 DD43 DD51 DD52 DD53 DD65 DD67 FF13 GG14 AGG14A14A14 EA04 EA07 FB12 5F033 HH04 HH08 HH11 HH14 HH17 HH18 HH19 HH20 HH21 HH32 MM05 MM08 MM19 PP06 PP15 PP26 PP27 PP28 QQ08 QQ09 QQ10 QQ12 QQ34 QQ35 QQ37 QQ53 QQ58 QQ73 QQ82 RR08 RR21 SS08 SS15 VV01 VV06 VV07 VV15 XX10 5F048 AA00 AA08 AA09 AC04 BA16 BB01 BB02 BB06 BB07 BB09 BB11 BB12 BB13 BC06 5F052 AA02 AA12 BA07 BB02 BB03 DB03 DB03 A03 DD15 DD17 EE01 EE02 EE03 EE04 EE09 EE23 EE28 EE44 EE45 FF04 FF09 FF28 FF30 GG01 GG02 GG13 GG25 GG43 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL02 HL03 HL21 HM15 Q24 NN15 PP03

Claims (25)

[Claims] 1. A semiconductor device having a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. A pixel portion provided with a first n-channel TFT having a source wiring surrounding a wiring made of the same material as the gate electrode and having a surface covered with a material film having a lower resistance than the gate electrode; a drive circuit including a circuit composed of an n-channel TFT and a p-channel TFT; and a terminal portion surrounding a wiring made of the same material as the gate electrode and having a surface covered with a material film having a lower resistance than the gate electrode. And a semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said low-resistance material film is a material film containing Cu, Al, Au, Ag, or an alloy thereof as a main component. 3. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film. A driving circuit including a pixel portion including a first n-channel TFT having a plated source wiring and a circuit including a second n-channel TFT and a p-channel TFT; And a terminal portion. 4. The semiconductor device according to claim 3, wherein the surface of the terminal portion and the surface of the source wiring of the pixel portion are formed of Cu, Al, Au, and A, respectively.
g, or a semiconductor device covered with a thin film made of a material containing these alloys as a main component. 5. The semiconductor device according to claim 3, wherein the terminal portion and the source line of the pixel portion are plated at the same time. 6. The semiconductor device according to claim 3, wherein the terminal portion and the source line of the pixel portion are separately plated. 7. The semiconductor device according to claim 3, wherein the plated source wiring is formed by plating a wiring made of the same material as a gate electrode. 8. The semiconductor device according to claim 3, wherein the plated source wiring is obtained by plating a wiring made of a material having a lower resistance than a gate electrode. 9. The semiconductor device according to claim 8, wherein the wiring made of a material having lower resistance than the gate electrode is formed by a printing method. 10. The method according to claim 1, wherein
The second n-channel TFT and the p-channel TFT
A semiconductor device comprising a CMOS circuit formed by FT. 11. The method according to claim 1, wherein the first n-channel type TFT includes a gate electrode,
A semiconductor device having a channel formation region overlapping with the gate electrode, wherein a width of the channel formation region is equal to a width of the gate electrode. 12. The first n-channel TFT according to claim 1, wherein the first n-channel TFT has a gate electrode having a tapered portion, a channel formation region overlapping the gate electrode, and a part of the gate electrode. A semiconductor device having overlapping impurity regions. 13. The semiconductor device according to claim 12, wherein said first n-channel type TFT has three channel formation regions. 14. The driving circuit according to claim 1, wherein the n-channel TFT of the driving circuit includes a gate electrode having a tapered portion, a channel formation region overlapping the gate electrode, and a part of the gate electrode. A semiconductor device having overlapping impurity regions. 15. The n-channel TFT according to claim 1, wherein an impurity concentration in the impurity region of the n-channel TFT is at least 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ^3.
Wherein the impurity concentration increases as the distance from the channel formation region increases. 16. The semiconductor device according to claim 1, wherein the first n-channel TFT has a plurality of channel formation regions. 17. A semiconductor device according to claim 1, wherein the semiconductor device is a transmissive liquid crystal module. 18. A semiconductor device according to claim 1, wherein the semiconductor device is a reflection-type liquid crystal module. 19. A semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera,
A semiconductor device, which is a car navigation system, a personal computer, a portable information terminal, a digital video disc player, or an electronic game machine. 20. A method for manufacturing a semiconductor device having a drive circuit, a pixel portion, and a terminal portion on an insulating surface, comprising: forming a semiconductor layer on the insulating surface; and forming a first insulating film on the semiconductor layer. Forming; forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film; and forming n on the semiconductor layer using the first gate electrode as a mask.
A step of forming an n-type first impurity region by adding an impurity element for imparting a mold; a step of etching the first gate electrode to form a tapered portion; and a step of tapering the first gate electrode. Forming an n-type second impurity region by adding an impurity element imparting n-type to the semiconductor layer by passing through the-portion; and passing through the tapered portion of the first gate electrode to the semiconductor layer. a step of forming a p-type impurity region by adding an impurity element imparting p-type; a step of plating a surface of the source line of the pixel portion and the surface of the terminal portion; a source line of the pixel portion and the terminal Forming a second insulating film covering the portion; and forming a gate wiring and a source wiring of a driver circuit over the second insulating film. 21. A method for manufacturing a semiconductor device having a driving circuit, a pixel portion, and a terminal portion on an insulating surface, comprising: forming a semiconductor layer on the insulating surface; and forming a first insulating film on the semiconductor layer. Forming; forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film; and forming n on the semiconductor layer using the first gate electrode as a mask.
A step of forming an n-type first impurity region by adding an impurity element for imparting a mold; a step of etching the first gate electrode to form a tapered portion; and a step of tapering the first gate electrode. Forming an n-type second impurity region by adding an impurity element imparting n-type to the semiconductor layer by passing through the-portion; and passing through the tapered portion of the first gate electrode to the semiconductor layer. a step of adding a p-type impurity element to form a p-type impurity region; a step of plating the surface of the source wiring of the pixel portion; a step of plating the surface of the terminal portion; A method for manufacturing a semiconductor device, comprising: a step of forming a second insulating film covering a source wiring of a pixel portion and the terminal portion; and a step of forming a gate wiring and a source wiring of a driver circuit over the second insulating film. . 22. The method according to claim 20, wherein
The source line and the terminal portion of the pixel portion are Cu, A
A method for manufacturing a semiconductor device, comprising a material containing l, Au, Ag, or an alloy thereof as a main component. 23. The semiconductor device according to claim 20, wherein in the step of applying plating according to any one of claims 20 to 22, the source lines of the pixel portion are connected to each other so as to have the same potential. Production method. 24. The method for manufacturing a semiconductor device according to claim 23, wherein the wirings connected to have the same potential are separated by a laser beam after plating. 25. The method for manufacturing a semiconductor device according to claim 23, wherein the wiring connected to have the same potential is cut at the same time as the substrate after plating.