JP2002176121A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2002176121A
JP2002176121A JP2000373086A JP2000373086A JP2002176121A JP 2002176121 A JP2002176121 A JP 2002176121A JP 2000373086 A JP2000373086 A JP 2000373086A JP 2000373086 A JP2000373086 A JP 2000373086A JP 2002176121 A JP2002176121 A JP 2002176121A
Authority
JP
Japan
Prior art keywords
conductive
electrode
thermoplastic resin
semiconductor device
conductive foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000373086A
Other languages
Japanese (ja)
Inventor
Haruhiko Sakai
春彦 境
Haruo Hyodo
治雄 兵藤
Shigeru Fujii
茂 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000373086A priority Critical patent/JP2002176121A/en
Publication of JP2002176121A publication Critical patent/JP2002176121A/en
Pending legal-status Critical Current

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Classifications

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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for realizing a small thin package suitable for mounting a small semiconductor chip by making a supporting board thin. SOLUTION: Two sheet of conductive foils 82 and 83, and a thermoplastic resin film 81 between them are subjected to thermo compression bonding in a body to form a supporting board 80. During the thermo compression bonding, a conductive material 87 for connecting both conductive foils 82 and 83 is so formed that the conductive material 87 is passed through the thermoplastic resin film 81 without using a via hole. Each electrode is formed from the conductive foil 82 and a semiconductor chip 88 is mounted. In the final step, each connection electrode is formed from the conductive foil 83, so the semiconductor chip 88 during the bonding can be prevented from the vertical shift. In this way, a greatly thin mounting structure can be realized by using a simple structure, and a semiconductor device optimum for mounting the small semiconductor chip can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法、特にパッケージ外形を超小型で薄型に形成できる微
小チップを収容する樹脂封止型の半導体装置の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a resin-sealed semiconductor device accommodating a small chip capable of forming an ultra-compact and thin package.

【0002】[0002]

【従来の技術】従来の半導体装置の組立工程において
は、ウェハからダイシングして分離した半導体チップを
リードフレームに固着し、金型と樹脂注入によるトラン
スファーモールドによって半導体チップを封止し、リー
ドフレームを切断して個々の半導体装置毎に分離すると
いう工程が行われている。この方法によって得れらる半
導体装置は、図8に示したように、半導体チップ1の周
囲を樹脂層2で被覆し、該樹脂層2の側部から外部接続
用のリード端子3を導出した構造になる(例えば特開平
05−129473号)。
2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip is sealed by a transfer mold using a mold and resin injection. A process of cutting and separating each semiconductor device is performed. In the semiconductor device obtained by this method, as shown in FIG. 8, the periphery of the semiconductor chip 1 is covered with the resin layer 2, and the lead terminals 3 for external connection are led out from the side of the resin layer 2. (For example, JP-A-05-129473).

【0003】この構造は、樹脂層2の外側にリード端子
3が突出すること、リードフレームの加工精度の問題や
金型との位置あわせ精度の問題により、外形寸法とその
実装面積の縮小化には限界が見えていた。
[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

【0004】近年、外形寸法を半導体チップサイズと同
等あるいは近似した寸法にまで縮小する事が可能な、ウ
ェハスケールCSP(チップサイズパッケージ)が注目
され始めている。これは、図9(A)を参照して、半導
体ウェハ11に各種拡散などの前処理を施して多数の半
導体チップ12を形成し、図9(B)に示したように半
導体ウェハ11の上部を樹脂層13で被覆すると共に樹
脂層13表面に外部接続用の電極14を導出し、その後
半導体ウェハ11のダイシングラインに沿って半導体チ
ップ11を分割して、図9(C)に示したような完成品
としたものである。樹脂層13は半導体チップ12の表
面(裏面を被覆する場合もある)を被覆するだけであ
り、半導体チップ12の側壁にはシリコン基板が露出す
る。電極14は樹脂層13下部に形成された集積回路網
と電気的に接続されており、実装基板上に形成した導電
パターンに対して電極14を対向接着することによりこ
の半導体装置の実装が実現する。
In recent years, attention has been paid to a wafer-scale CSP (chip size package) capable of reducing an outer dimension to a size similar to or close to a semiconductor chip size. 9A, the semiconductor wafer 11 is subjected to various pretreatments such as diffusion to form a large number of semiconductor chips 12, and the upper portion of the semiconductor wafer 11 is formed as shown in FIG. 9B. Is covered with a resin layer 13, electrodes 14 for external connection are led out on the surface of the resin layer 13, and then the semiconductor chips 11 are divided along dicing lines of the semiconductor wafer 11, as shown in FIG. 9C. It is a finished product. The resin layer 13 only covers the front surface (the back surface may be covered) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed below the resin layer 13, and the semiconductor device is mounted by bonding the electrode 14 to a conductive pattern formed on a mounting substrate. .

【0005】斯かる半導体装置は、装置のパッケージサ
イズが半導体チップのチップサイズと同等であり、実装
基板に対しても対向接着で済むので、実装占有面積を大
幅に減らすことが出来る利点を有する。また、後工程に
拘わるコストを大幅に減じることが出来る利点を有する
ものである。(例えば、特開平9−64049号)しか
しながら、チップサイズが10数mm角にも及ぶLSI
チップであればその寸法内に多数個の電極を配置するこ
とが可能であるものの、例えばチップサイズが1mm角
に満たない程度のトランジスタチップ等では、この寸法
内に複数個の電極を配置することは物理的に無理がある
し、実現したとしても実装が困難である欠点がある。
[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor chip, and the device can be adhered to the mounting substrate by opposing, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. (For example, Japanese Patent Laid-Open No. 9-64049)
Although it is possible to arrange a large number of electrodes within the dimensions of a chip, for example, for a transistor chip having a chip size of less than 1 mm square, it is necessary to arrange a plurality of electrodes within this dimension. Has the drawback that it is physically unreasonable and difficult to implement even if realized.

【0006】そこで、チップサイズが1mm角に満たな
い程度のチップでは図10(A)(B)(C)に示すよ
うに実装されている。図中、21はセラミックやガラス
エポキシ等からなる絶縁基板であり、それらが1枚ある
いは数枚重ね合わされて、板厚が250〜350μmと
製造工程における機械的強度を維持し得る厚みと、長辺
×短辺が1.0mm×0.8mm程度の矩形形状を有し
ている。
Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 10A, 10B, and 10C. In the figure, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are stacked to have a thickness of 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process, and a long side. X It has a rectangular shape with a short side of about 1.0 mm x 0.8 mm.

【0007】絶縁基板21の表面には、タングステン等
の金属ペーストの印刷と、電解メッキ法による前記金属
ペースト上への金メッキによって導電パターンを形成
し、アイランド部22と電極部23a、23bとを形成
している。アイランド部22の上には、Agペーストな
どの導電性接着剤24によって半導体チップ25が固着
されている。
On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 22 and electrode portions 23a and 23b. are doing. A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.

【0008】半導体チップ25の表面にはアルミ電極パ
ッド26が形成され、電極パッド26と電極部23a、
23bとが、ボンディングワイヤ27によって電気接続
される。電極パッド26側に1stボンド、電極部23
側に2ndボンドが打たれる。バイポーラトランジスタ
で有れば、電極部23a、23bはエミッタとベースに
対応し、パワーMOSFETで有れば、ソースとゲート
に対応する。
An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portion 23a are formed.
23b are electrically connected to each other by a bonding wire 27. 1st bond on electrode pad 26 side, electrode section 23
A 2nd bond is struck on the side. If it is a bipolar transistor, the electrode portions 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【0009】前記絶縁基板21の裏面側には、同じく金
メッキ層によって第1の外部接続電極28と第2の外部
接続電極29a、29bが形成される。絶縁基板21に
はこれを貫通する、円形の第1のビアホール30と第2
のビアホール31a、31bが形成され、各ビアホール
30、31a、31bの内部はタングステンなどの導電
材料によって埋設される。素材としては、電気的導電性
と熱伝導性に優れた素材で埋設する。該ビアホール3
0、31a、31bによって、アイランド部22と第1
の外部接続電極28とを、電極部23a、23bと第2
の外部接続電極29a、29bとを、各々電気接続す
る。第1の外部接続電極28が例えばコレクタ電極とな
り、第2の外部接続電極29a、29bが例えばベー
ス、エミッタ電極となる。
A first external connection electrode 28 and second external connection electrodes 29a and 29b are formed on the back surface of the insulating substrate 21 by the same gold plating layer. A circular first via hole 30 and a second
Are formed, and the inside of each via hole 30, 31a, 31b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 3
0, 31a and 31b, the island portion 22 and the first
Of the external connection electrode 28 and the electrode portions 23a and 23b and the second
Are electrically connected to the external connection electrodes 29a and 29b, respectively. The first external connection electrodes 28 are, for example, collector electrodes, and the second external connection electrodes 29a, 29b are, for example, base and emitter electrodes.

【0010】絶縁基板21の上方は、半導体チップ25
とボンディングワイヤ27とを封止する樹脂層32で被
覆される。樹脂層32は絶縁基板21と共にパッケージ
外形を構成する。パッケージの周囲4側面は樹脂層32
と絶縁基板21の切断面で形成され、パッケージの上面
は平坦化した樹脂層32の表面、パッケージの下面は絶
縁基板21の裏面側で形成される。
The semiconductor chip 25 is located above the insulating substrate 21.
And the bonding wire 27 is covered with a resin layer 32. The resin layer 32 forms an outer shape of the package together with the insulating substrate 21. The four sides around the package are resin layers 32
The upper surface of the package is formed on the flattened surface of the resin layer 32, and the lower surface of the package is formed on the back surface side of the insulating substrate 21.

【0011】しかしながら図10で示した実装構造にお
いていろいろな問題点がある。第1にタングステン等の
高価な金属ペーストを用いているので、ローコストの実
装構造とは言えない。第2に両面の電極等を接続するた
めに、絶縁基板を貫通するビアホールが不可欠であり、
この加工精度も0.15mm程度が限界であるので、更な
る小型化の障害となっている。第3にこのビアホール内
を金属ペーストで充填するため作業性が極めて悪く、コ
スト高の原因となる。第4に絶縁基板が機械的強度を維
持するために0.25mmから0.35mmは必要であるた
めに薄型化の阻害要因となっている等々の多くの問題点
が発生している。
However, there are various problems in the mounting structure shown in FIG. First, since an expensive metal paste such as tungsten is used, it cannot be said that the mounting structure is low cost. Secondly, in order to connect the electrodes and the like on both surfaces, a via hole penetrating the insulating substrate is indispensable.
Since the processing accuracy is limited to about 0.15 mm, it is an obstacle to further miniaturization. Third, since the inside of the via hole is filled with a metal paste, workability is extremely poor, which causes an increase in cost. Fourth, since the insulating substrate needs to have a thickness of 0.25 mm to 0.35 mm in order to maintain the mechanical strength, there are many problems such as hindrance to thinning.

【0012】ここで上述した様々な問題点を解決するた
めに以下の支持基板に液晶ポリマーを用いた半導体装置
が提案されている。
Here, in order to solve the various problems described above, the following semiconductor device using a liquid crystal polymer for a supporting substrate has been proposed.

【0013】この実施例を図11を参照して説明する。
図11は、完成された個別の半導体装置を説明する図で
あり、(A)が平面図、(B)が裏面図であり、図12
はボンディング時の断面図である。
This embodiment will be described with reference to FIG.
FIGS. 11A and 11B are diagrams illustrating completed individual semiconductor devices. FIG. 11A is a plan view, FIG.
Is a sectional view at the time of bonding.

【0014】この半導体装置の特徴とする支持基板50
は、熱可塑性樹脂のフィルム51の両面に2枚の導電箔
を熱圧着して形成されている。熱可塑性樹脂は加熱する
ことにより軟化して二次加工が容易であり、従来用いて
いたセラミックスやガラスエポキシの硬質基板よりはる
かに扱いやすくなる。熱可塑性樹脂としては液晶ポリマ
ーが最適であり、本実施例では全芳香族ポリエステル系
液晶ポリマー(商品名ベクトラ)を用いた。
A support substrate 50 which is a feature of this semiconductor device
Is formed by thermocompression bonding two conductive foils on both surfaces of a thermoplastic resin film 51. The thermoplastic resin is softened by heating and is easily subjected to secondary processing, and is much easier to handle than a conventionally used ceramic or glass epoxy hard substrate. A liquid crystal polymer is most suitable as the thermoplastic resin. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used.

【0015】熱可塑性樹脂フィルム51の両面にはこの
樹脂フィルムで離間されかつ電気的に絶縁された2枚の
導電箔が圧着されている。この導電箔としては安価で電
気的抵抗の小さい銅箔が最適である。具体的には50μ
mの厚みの熱可塑性樹脂フィルム51の両面に各々20
μmの厚みの銅箔が圧着されている。一方の導電箔はエ
ッチングされて所望形状のパターンに加工され、固着電
極54と取り出し電極55a、55bを形成する。固着
電極54は少なくとも半導体チップ58が載置できる大
きさと形状を有しており、この固着電極54に隣接して
少し離間して取り出し電極55a、55bが複数個形成
されている。他方の導電箔もエッチングされて所望形状
のパターンに加工され、固着電極54と取り出し電極5
5a、55bと対向する位置に接続電極56、56a、
56bを形成する。接続電極56、56a、56bはプ
リント基板にはんだ付けできる大きさに形成され、はん
だ付けの際にはんだブリッジが形成されないように離間
され、対応する固着電極54および取り出し電極55
a、55bよりは小さく形成される。なお固着電極5
4、取り出し電極55a、55bおよび接続電極56、
56a、56bは電解メッキによりその表面をニッケル
メッキ層と金メッキ層で被覆されており、導電ペースト
との接触抵抗を減少させ、またボンディング細線の固着
を可能にしている。
Two conductive foils which are separated by the resin film and electrically insulated are pressure-bonded to both surfaces of the thermoplastic resin film 51. As the conductive foil, an inexpensive copper foil having a small electric resistance is optimal. Specifically, 50μ
m on each side of the thermoplastic resin film 51 having a thickness of 20 m.
A copper foil having a thickness of μm is pressed. One conductive foil is etched and processed into a desired shape pattern to form the fixed electrode 54 and the extraction electrodes 55a and 55b. The fixed electrode 54 has a size and a shape at least on which the semiconductor chip 58 can be mounted, and a plurality of extraction electrodes 55a and 55b are formed adjacent to the fixed electrode 54 and slightly apart therefrom. The other conductive foil is also etched and processed into a desired shape pattern, and the fixed electrode 54 and the extraction electrode 5 are formed.
The connection electrodes 56, 56a,
Form 56b. The connection electrodes 56, 56 a, 56 b are formed in a size that can be soldered to a printed circuit board, are separated so that a solder bridge is not formed at the time of soldering, and the corresponding fixed electrodes 54 and extraction electrodes 55 are formed.
a and 55b. Note that the fixed electrode 5
4, extraction electrodes 55a and 55b and connection electrodes 56,
The surfaces 56a and 56b are covered with a nickel plating layer and a gold plating layer by electrolytic plating to reduce the contact resistance with the conductive paste and to enable the bonding of the fine bonding wires.

【0016】導電材57は一方の導電箔で形成された固
着電極54、取り出し電極55a、55bと他方の導電
箔で形成された対応する接続電極56、56a、56b
とを接続している。導電材57としては銀ペーストを用
い、熱可塑性樹脂51を加熱して軟化させて導電材57
を貫通させている。従って予めビアホールを設ける必要
が無くなる。導電材57を貫通させる位置は図12
(A)(B)に破線丸印で示すように、固着電極54で
は取り出し電極55a、55bと離れた側の上下両端近
くに2個設け、取り出し電極55a、55bではほぼ中
央部に1個形成している。
The conductive material 57 includes a fixed electrode 54 and lead electrodes 55a and 55b formed of one conductive foil and corresponding connection electrodes 56, 56a and 56b formed of the other conductive foil.
And are connected. A silver paste is used as the conductive material 57, and the thermoplastic resin 51 is heated and softened by heating.
Through. Therefore, it is not necessary to provide a via hole in advance. The position where the conductive material 57 is penetrated is shown in FIG.
(A) and (B), two fixed electrodes 54 are provided near the upper and lower ends on the side remote from the extraction electrodes 55a and 55b, and one is formed substantially at the center of the extraction electrodes 55a and 55b, as indicated by the broken circles. are doing.

【0017】半導体チップ58は固着電極54上にAg
ペーストなどの導電ペースト59により固着されてい
る。半導体チップ58としては、バイポーラトランジス
タ、パワーMOSFET等の3端子素子又はダイオード
などの2端子素子が形成されているウエファーから供給
される。半導体チップ58自体は、N+/N型構造のよ
うに、裏面側に高濃度不純物層を有しており、該高濃度
層を介して、ダイオード素子で有ればアノード又はカソ
ードの一方の端子を、バイポーラ型トランジスタで有れ
ばコレクタ端子を、パワーMOSFETで有ればドレイ
ン端子を導出する構造を有しているので、この高濃度層
が導電ペースト59を介して固着電極54にオーミック
接続される。
The semiconductor chip 58 has Ag fixed on the fixed electrode 54.
It is fixed by a conductive paste 59 such as a paste. The semiconductor chip 58 is supplied from a wafer on which a three-terminal element such as a bipolar transistor or a power MOSFET or a two-terminal element such as a diode is formed. The semiconductor chip 58 itself has a high-concentration impurity layer on the back side like an N + / N-type structure, and through the high-concentration layer, connects one terminal of an anode or a cathode if it is a diode element. In the case of a bipolar transistor, the collector terminal is provided, and in the case of a power MOSFET, the drain terminal is provided, so that this high concentration layer is ohmically connected to the fixed electrode 54 via the conductive paste 59. .

【0018】半導体チップ58の表面にはアルミ電極パ
ッド60が形成され、電極パッド60と取り出し電極5
5a、55bとが、金線ボンディングワイヤ61によっ
て電気接続される。電極パッド60側に1stボンド、
取り出し電極55a、55b55b側に2ndボンドが
打たれる。バイポーラトランジスタで有れば、取り出し
電極55a、55bはエミッタとベースに対応し、パワ
ーMOSFETで有れば、ソースとゲートに対応する。
An aluminum electrode pad 60 is formed on the surface of the semiconductor chip 58, and the electrode pad 60 and the extraction electrode 5 are formed.
5a and 55b are electrically connected by a gold wire bonding wire 61. 1st bond on the electrode pad 60 side,
A second bond is formed on the side of the extraction electrodes 55a and 55b55b. If it is a bipolar transistor, the extraction electrodes 55a and 55b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【0019】支持基板50の上面は、半導体チップ5
8、固着電極54、取り出し電極55a、55bおよび
ボンディングワイヤ61とを被覆する絶縁樹脂62で封
止される。絶縁樹脂62は支持基板51と共にパッケー
ジ外形を構成する。パッケージの周囲4側面は絶縁樹脂
62と支持基板51の切断面で形成され、パッケージの
上面は平坦化した絶縁樹脂層62の表面、パッケージの
下面は支持基板50の裏面側で形成される。絶縁樹脂6
2は一般的に用いられるエポキシ樹脂を用いる。
The upper surface of the supporting substrate 50 is
8. Sealed with insulating resin 62 covering fixed electrode 54, extraction electrodes 55a and 55b and bonding wire 61. The insulating resin 62 forms a package outer shape together with the support substrate 51. The four peripheral sides of the package are formed by the cut surface of the insulating resin 62 and the support substrate 51, the upper surface of the package is formed by the flattened surface of the insulating resin layer 62, and the lower surface of the package is formed by the back surface of the support substrate 50. Insulating resin 6
2 uses a commonly used epoxy resin.

【0020】ここでこの半導体装置の製造方法を図13
から図17を参照して説明する。
Here, a method of manufacturing this semiconductor device is shown in FIG.
This will be described with reference to FIG.

【0021】第1工程:図13(A)(B)(C)参照 本工程ではまず支持基板50を形成することにある。図
13(A)に示すように、第1の導電箔52、熱可塑性
樹脂から成るフィルム51および第2の導電箔53を準
備する。第1および第2の導電箔52,53は安価で電
気抵抗の低い銅箔が適しており、20μm厚で熱可塑性
樹脂から成るフィルム51と当接する面を凹凸に粗面化
して固着強度を高めるようにしている。熱可塑性樹脂フ
ィルム51としては液晶ポリマーが最適である。第2の
導電箔53表面には導電材57である銀ぺーストを所定
の位置にスクリーン印刷して熱可塑性樹脂フィルム51
を貫通する高さにバンプ110を予め形成しておく。
First Step: See FIGS. 13A, 13B and 13C In this step, first, a support substrate 50 is formed. As shown in FIG. 13A, a first conductive foil 52, a film 51 made of a thermoplastic resin, and a second conductive foil 53 are prepared. As the first and second conductive foils 52 and 53, inexpensive and low-resistance copper foil is suitable, and the surface in contact with the film 51 made of a thermoplastic resin and having a thickness of 20 μm is roughened into irregularities to increase the bonding strength. Like that. As the thermoplastic resin film 51, a liquid crystal polymer is optimal. On the surface of the second conductive foil 53, a silver paste, which is a conductive material 57, is screen-printed at a predetermined position, and the thermoplastic resin film 51 is formed.
The bump 110 is formed in advance at a height that penetrates.

【0022】次に、図13(B)に示すように第1の導
電箔52、熱可塑性樹脂フィルム51および第2の導電
箔53を熱圧着して一体化された支持基板50を形成す
る。この熱圧着時に熱可塑性樹脂フィルム51は加熱さ
れて軟化するので、第2の導電箔53に付着された導電
材57となるバンプ110は熱可塑性樹脂フィルム51
を貫通し第1の導電箔52まで到達する。
Next, as shown in FIG. 13B, the first conductive foil 52, the thermoplastic resin film 51, and the second conductive foil 53 are thermocompression-bonded to form an integrated support substrate 50. During this thermocompression bonding, the thermoplastic resin film 51 is heated and softened, so that the bumps 110 serving as the conductive material 57 attached to the second conductive foil 53 are formed of the thermoplastic resin film 51.
And reaches the first conductive foil 52.

【0023】更に、図13(C)に示すように熱圧着を
完了すると、第1の導電箔52、熱可塑性樹脂フィルム
51、第2の導電箔53は密着して一体化されるので、
導電ペーストよりなるバンプ110も潰されて0.15
mmの径の柱状の導電材57を形成する。
Further, when the thermocompression bonding is completed as shown in FIG. 13 (C), the first conductive foil 52, the thermoplastic resin film 51, and the second conductive foil 53 are tightly integrated and integrated.
The bump 110 made of the conductive paste is also crushed to 0.15.
A columnar conductive material 57 having a diameter of mm is formed.

【0024】第2工程:図14(A)(B)参照 斯かる支持基板50の両主面は第1および第2の導電箔
52,53で被覆されている。図14(A)示すよう
に、この第1の導電箔52上には所定の形状の固着電極
54、取り出し電極55上を覆うようにレジスト膜11
1を付着し、第2の導電箔53上にも所定の形状の第1
および第2の接続電極56、56a、56b上を覆うよ
うにレジスト膜111を付着する。
Second step: See FIGS. 14A and 14B Both main surfaces of the support substrate 50 are covered with first and second conductive foils 52 and 53. As shown in FIG. 14A, a resist film 11 is formed on the first conductive foil 52 so as to cover the fixed electrode 54 having a predetermined shape and the extraction electrode 55.
1 on the second conductive foil 53,
Then, a resist film 111 is attached so as to cover the second connection electrodes 56, 56a, and 56b.

【0025】続いて図14(B)示すようにレジスト膜
111をマスクとして第1および第2の導電箔52,5
3を塩化第2鉄溶液を用いて化学的にエッチングして、
第1の導電箔52で固着電極54、取り出し電極55
a、55bを形成し、第2の導電箔53で第1および第
2の接続電極56、56a、56bを形成する。
Subsequently, as shown in FIG. 14B, using the resist film 111 as a mask, the first and second conductive foils 52 and 5 are used.
3 is chemically etched using a ferric chloride solution,
The fixed electrode 54 and the extraction electrode 55 are formed by the first conductive foil 52.
a and 55b are formed, and the first and second connection electrodes 56, 56a and 56b are formed by the second conductive foil 53.

【0026】第3工程:図15参照 上述したように各電極を形成した支持基板50に、半導
体チップ58をダイボンドする。半導体チップ58は固
着電極54表面にAgペーストなどの導電ペースト59
によって固着される。
Third Step: See FIG. 15 A semiconductor chip 58 is die-bonded to the support substrate 50 on which the electrodes are formed as described above. The semiconductor chip 58 has a conductive paste 59 such as an Ag paste on the surface of the fixed electrode 54.
Fixed by

【0027】第4工程:図16(A)(B)参照 半導体チップ58の電極パッド60と取り出し電極55
a、55bとを各々金などのボンディングワイヤ61で
接続する。金線によりボールボンドをする場合は、支持
基板50を150℃に加熱して半導体チップ58の電極
パッド60に金線の一端に形成したボール部分を熱圧着
し、多端を取り出し電極55a、55bに熱圧着する。
Fourth step: See FIGS. 16A and 16B The electrode pad 60 and the extraction electrode 55 of the semiconductor chip 58
a and 55b are connected by bonding wires 61 such as gold. In the case of performing ball bonding with a gold wire, the supporting substrate 50 is heated to 150 ° C., and the ball portion formed at one end of the gold wire is thermocompression-bonded to the electrode pad 60 of the semiconductor chip 58, and multiple ends are taken out to the electrodes 55a and 55b. Thermocompression bonding.

【0028】第5工程:図17参照 支持基板50の各載置部に半導体チップ58のダイボン
ドとボンディング細線61による接続が終了すると、絶
縁樹脂62により全体のモールドを行う。本工程では支
持基板50の裏面に露出する接続電極56、56a、5
6bを除き、半導体チップ58、固着電極54、取り出
し電極55a、55bおよびボンディング細線61をエ
ポキシ系樹脂62で被覆する。
Fifth step: See FIG. 17 When the die bonding of the semiconductor chip 58 and the connection by the bonding thin wire 61 to each mounting portion of the support substrate 50 are completed, the entire molding is performed by the insulating resin 62. In this step, the connection electrodes 56, 56a, 5
Except for 6b, the semiconductor chip 58, the fixed electrode 54, the extraction electrodes 55a and 55b, and the bonding thin wires 61 are covered with an epoxy resin 62.

【0029】[0029]

【発明が解決しようとする課題】しかしながら図12で
示した実装構造において重要な問題点がある。それは支
持基板となる液晶ポリマーがとても軟らかいということ
である。斯かる半導体装置では構造上固着電極および取
り出し電極よりも接続電極は小さく形成される。そのこ
とにより図13(A)に示すごとく接続電極のない部分
が金線ボンディングワイヤによって電気接続される際
に、基板が押さえつけられる力に耐えきれなくなり歪ん
でしまい、接続の際の超音波がうまく伝わらないという
問題点が発生している。
However, there is an important problem in the mounting structure shown in FIG. That is, the liquid crystal polymer serving as the support substrate is very soft. In such a semiconductor device, the connection electrode is formed smaller in structure than the fixed electrode and the extraction electrode. As a result, as shown in FIG. 13A, when a portion having no connection electrode is electrically connected by a gold bonding wire, the substrate cannot withstand the pressing force and is distorted. There is a problem of not being transmitted.

【0030】[0030]

【課題を解決するための手段】本発明は上述した種々の
問題点に鑑みてなされたものであり、第1の導電箔と、
軟質樹脂と、導電材を所望の位置に付着した第2の導電
箔とを熱圧着して前記導電材を前記軟質樹脂を貫通させ
て前記第1および第2の導電箔を電気的に接続する支持
基板を形成する工程と、前記第1の導電箔で固着電極お
よび取り出し電極を形成する工程と、前記固着電極に導
電ペーストを用いて半導体素子を固着する工程と、前記
半導体素子の電極と前記取り出し電極をボンディング接
続する工程と、前記第2の導電箔を露出して全体を絶縁
樹脂で被覆する工程と、前記第2の導電箔で前記固着電
極および取り出し電極に対応し前記導電材で電気的に接
続された接続電極を形成する工程とを具備することを特
徴とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the various problems described above, and comprises a first conductive foil,
A soft resin and a second conductive foil having a conductive material adhered to a desired position are thermocompressed to penetrate the conductive material through the soft resin to electrically connect the first and second conductive foils. A step of forming a support substrate, a step of forming a fixed electrode and a take-out electrode with the first conductive foil, a step of fixing a semiconductor element to the fixed electrode using a conductive paste, A step of bonding and connecting the extraction electrode, a step of exposing the second conductive foil and covering the whole with an insulating resin, and a step of electrically connecting the second conductive foil with the conductive material corresponding to the fixed electrode and the extraction electrode. Forming a connection electrode that is electrically connected.

【0031】[0031]

【発明の実施の形態】本発明の一実施例を図1および図
2を参照して説明する。図1は、本発明の完成された個
別の半導体装置を説明する図であり、(A)が平面図、
(B)が断面図、(C)が裏面図である。図2は、本発
明に用いる支持基板を説明する図であり、(A)が平面
図、(B)が裏面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams illustrating a completed individual semiconductor device of the present invention, wherein FIG.
(B) is a sectional view, and (C) is a back view. 2A and 2B are diagrams illustrating a support substrate used in the present invention, wherein FIG. 2A is a plan view and FIG. 2B is a rear view.

【0032】本発明の支持基板80は、熱可塑性樹脂フ
ィルム81の両面に2枚の導電箔82,83(図3参
照)を熱圧着して形成されている。熱可塑性樹脂は加熱
することにより軟化して二次加工が容易であり、従来用
いていたセラミックスやガラスエポキシの硬質基板より
はるかに扱いやすくなる。上述したように熱可塑性樹脂
としては液晶ポリマーが最適であり、本実施例では全芳
香族ポリエステル系液晶ポリマー(商品名ベクトラ)を
用いた。
The support substrate 80 of the present invention is formed by thermocompression bonding two conductive foils 82 and 83 (see FIG. 3) on both surfaces of a thermoplastic resin film 81. The thermoplastic resin is softened by heating and is easily subjected to secondary processing, and is much easier to handle than a conventionally used ceramic or glass epoxy hard substrate. As described above, a liquid crystal polymer is most suitable as the thermoplastic resin. In this embodiment, a wholly aromatic polyester-based liquid crystal polymer (Vectra) is used.

【0033】熱可塑性樹脂フィルム81の両面にはこの
樹脂フィルムで離間されかつ電気的に絶縁された2枚の
導電箔82,83が圧着されている。この導電箔として
は安価で電気的抵抗の小さい銅箔が最適である。具体的
には50μmの厚みの熱可塑性樹脂フィルム81の両面
に各々20μmの厚みの銅箔82,83が圧着されてい
る。一方の導電箔82はエッチングされて所望形状のパ
ターンに加工され、固着電極84と取り出し電極85
a、85bを形成する。固着電極84は少なくとも半導
体チップ88が載置できる大きさと形状を有しており、
この固着電極84に隣接して少し離間して取り出し電極
85a、85bが複数個形成されている。
Two conductive foils 82 and 83 which are separated by the resin film and electrically insulated are pressed on both surfaces of the thermoplastic resin film 81. As the conductive foil, an inexpensive copper foil having a small electric resistance is optimal. Specifically, copper foils 82 and 83 each having a thickness of 20 μm are pressure-bonded to both surfaces of a thermoplastic resin film 81 having a thickness of 50 μm. One conductive foil 82 is etched and processed into a desired shape pattern, and the fixed electrode 84 and the extraction electrode 85 are formed.
a and 85b are formed. The fixed electrode 84 has at least a size and a shape on which the semiconductor chip 88 can be mounted.
A plurality of extraction electrodes 85a and 85b are formed adjacent to the fixed electrode 84 and slightly apart therefrom.

【0034】他方の導電箔83もエッチングされて所望
形状のパターンに加工され、固着電極84と取り出し電
極85a、85bと対向する位置に接続電極86、86
a、86bを形成する。接続電極86、86a、86b
はプリント基板にはんだ付けできる大きさに形成され、
はんだ付けの際にはんだブリッジが形成されないように
離間され、対応する固着電極84および取り出し電極8
5a、85bよりは小さく形成される。なお固着電極8
4、取り出し電極85a、85bおよび接続電極86、
86a、86bは電解メッキによりその表面をニッケル
メッキ層と金メッキ層で被覆されており、導電ペースト
との接触抵抗を減少させ、またボンディング細線の固着
を可能にしている。
The other conductive foil 83 is also etched and processed into a desired pattern, and the connection electrodes 86 and 86 are located at positions facing the fixed electrode 84 and the extraction electrodes 85a and 85b.
a and 86b are formed. Connection electrodes 86, 86a, 86b
Is formed in a size that can be soldered to a printed circuit board,
In order to prevent formation of a solder bridge during soldering, the corresponding fixed electrode 84 and extraction electrode 8 are separated.
It is formed smaller than 5a and 85b. Note that the fixed electrode 8
4, take-out electrodes 85a, 85b and connection electrodes 86,
The surfaces 86a and 86b are covered with a nickel plating layer and a gold plating layer by electrolytic plating to reduce the contact resistance with the conductive paste and to enable the bonding of the bonding thin wires.

【0035】導電材87は一方の導電箔82で形成され
た固着電極84、取り出し電極85a、85bと他方の
接続電極86a、86bを接続している。導電材87と
しては銀ペーストを用い、熱可塑性樹脂81を加熱して
軟化させて導電材87を貫通させている。従って予めビ
アホールを設ける必要が無くなる。導電材87を貫通さ
せる位置は図1(A)(C)に破線丸印で示すように、
固着電極84では取り出し電極85a、85bと離れた
側の上下両端近くに2個設け、取り出し電極85a、8
5bではほぼ中央部に1個形成している。
The conductive material 87 connects the fixed electrode 84 and the lead electrodes 85a and 85b formed of one conductive foil 82 to the other connection electrodes 86a and 86b. A silver paste is used as the conductive material 87, and the thermoplastic resin 81 is heated and softened to penetrate the conductive material 87. Therefore, it is not necessary to provide a via hole in advance. The position through which the conductive material 87 is penetrated is indicated by a broken-line circle in FIGS.
Two fixed electrodes 84 are provided near the upper and lower ends on the side distant from the extraction electrodes 85a and 85b.
5b, one is formed almost at the center.

【0036】半導体チップ88は固着電極84上にAg
ペーストなどの導電ペースト89により固着されてい
る。半導体チップ88としては、バイポーラトランジス
タ、パワーMOSFET等の3端子素子又はダイオード
などの2端子素子が形成されているウエファーから供給
される。半導体チップ88自体は、N+/N型構造のよ
うに、裏面側に高濃度不純物層を有しており、該高濃度
層を介して、ダイオード素子で有ればアノード又はカソ
ードの一方の端子を、バイポーラ型トランジスタで有れ
ばコレクタ端子を、パワーMOSFETで有ればドレイ
ン端子を導出する構造を有しているので、この高濃度層
が導電ペースト89を介して固着電極84にオーミック
接続される。
The semiconductor chip 88 has Ag fixed on the fixed electrode 84.
It is fixed by a conductive paste 89 such as a paste. The semiconductor chip 88 is supplied from a wafer on which a three-terminal element such as a bipolar transistor or a power MOSFET or a two-terminal element such as a diode is formed. The semiconductor chip 88 itself has a high-concentration impurity layer on the back surface like an N + / N-type structure, and through the high-concentration layer, connects one terminal of an anode or a cathode if it is a diode element. In the case of a bipolar transistor, the collector terminal is provided, and in the case of a power MOSFET, the drain terminal is provided, so that this high-concentration layer is ohmically connected to the fixed electrode 84 via the conductive paste 89. .

【0037】半導体チップ88の表面にはアルミ電極パ
ッド90が形成され、電極パッド90と取り出し電極8
5a、85bとが、金線ボンディングワイヤ91によっ
て電気接続される。電極パッド90側に1stボンド、
取り出し電極85a、85b側に2ndボンドが打たれ
る。バイポーラトランジスタで有れば、取り出し電極8
5a、85bはエミッタとベースに対応し、パワーMO
SFETで有れば、ソースとゲートに対応する。
An aluminum electrode pad 90 is formed on the surface of the semiconductor chip 88, and the electrode pad 90 and the extraction electrode 8 are formed.
5a and 85b are electrically connected by a gold wire bonding wire 91. 1st bond on the electrode pad 90 side,
A second bond is formed on the extraction electrodes 85a and 85b. If it is a bipolar transistor, the extraction electrode 8
5a and 85b correspond to the emitter and the base, respectively.
If it is an SFET, it corresponds to the source and the gate.

【0038】熱可塑性樹脂フィルム81の上面は、半導
体チップ88、固着電極84、取り付け電極85a、8
5bおよびボンディングワイヤ91とを被覆する絶縁樹
脂92で封止される。絶縁樹脂92は熱可塑性樹脂フィ
ルム81と共にパッケージ外形を構成する。パッケージ
の周囲4側面は絶縁樹脂92と熱可塑性樹脂フィルム8
1の切断面で形成され、パッケージの上面は平坦化した
絶縁樹脂層92の表面、パッケージの下面は熱可塑性樹
脂フィルム81の裏面側で形成される。絶縁樹脂92は
一般的に用いられるエポキシ樹脂を用いる。
The upper surface of the thermoplastic resin film 81 has the semiconductor chip 88, the fixed electrode 84, and the mounting electrodes 85a, 8
5b and the bonding wire 91 are sealed with an insulating resin 92. The insulating resin 92 forms a package outer shape together with the thermoplastic resin film 81. The four sides around the package are insulating resin 92 and thermoplastic resin film 8
1, the upper surface of the package is formed on the flattened surface of the insulating resin layer 92, and the lower surface of the package is formed on the back surface of the thermoplastic resin film 81. As the insulating resin 92, a commonly used epoxy resin is used.

【0039】次に、図2を参照して支持基板81の上面
に一方の導電箔82から形成される固着電極84および
取り出し電極85a、85bと、裏面に他方の導電箔8
3から形成される接続電極86、86a、86bの関係
を説明する。
Next, referring to FIG. 2, fixed electrode 84 and extraction electrodes 85a and 85b formed from one conductive foil 82 on the upper surface of support substrate 81, and the other conductive foil 8 on the back surface.
The relationship between the connection electrodes 86, 86a and 86b formed from 3 will be described.

【0040】点線で囲んだ各搭載部100は、例えば長
辺×短辺が0.9mm×0.8mmの矩形形状を有して
おり、これらは互いに20〜50μmの間隔を隔てて2
4行24列の行列上に縦横に配置されている。前記間隔
は後の工程でのダイシングライン101となる。導電パ
ターンは、各搭載部100内において固着電極84と取
り出し電極85a、85bを形成し、これらのパターン
は各搭載部100内において同一形状である。
Each mounting section 100 surrounded by a dotted line has a rectangular shape of, for example, 0.9 mm × 0.8 mm long side × short side, and these are spaced apart from each other by 20 to 50 μm.
They are arranged vertically and horizontally on a matrix of 4 rows and 24 columns. The interval becomes a dicing line 101 in a later step. The conductive pattern forms the fixed electrode 84 and the extraction electrodes 85a and 85b in each mounting portion 100, and these patterns have the same shape in each mounting portion 100.

【0041】固着電極84からは2本の連結部102が
連続したパターンで延長される。これらの線幅は固着電
極84よりも狭い線幅で、例えば0.075mmの線幅
で延在する。連結部102はダイシングライン101を
超えて隣の搭載部100の取り出し電極85a、85b
に連結するまで延在する。更に、固着電極84から上下
方向に連結部103が、連結部102とは直行する方向
に延在され、ダイシングライン101を越えて隣の搭載
部100の固着電極84に連結するまで延在される。連
結部103は更に、搭載部100周囲を取り囲む共通連
結部104に連結され、各搭載部100の固着電極84
と取り出し電極85a、85bとを電気的に共通接続す
る。
From the fixed electrode 84, two connecting portions 102 are extended in a continuous pattern. These line widths are narrower than the fixed electrode 84 and extend with a line width of, for example, 0.075 mm. The connecting portion 102 extends beyond the dicing line 101 to the extraction electrodes 85a, 85b of the adjacent mounting portion 100.
Extend until connected to Further, the connecting portion 103 extends vertically from the fixed electrode 84 in a direction perpendicular to the connecting portion 102 and extends beyond the dicing line 101 until the connecting portion 103 is connected to the fixed electrode 84 of the adjacent mounting portion 100. . The connection portion 103 is further connected to a common connection portion 104 surrounding the periphery of the mounting portion 100, and the fixed electrode 84 of each mounting portion 100 is connected.
And the extraction electrodes 85a and 85b are electrically connected in common.

【0042】熱可塑性樹脂フィルム81の裏面側には、
第1と第2の接続電極86、86a、86bを形成す
る。これらの接続電極86、86a、86bは、搭載部
100の端から0.05〜0.1mm程度後退されたパ
ターンで形成されている。両導電箔82,83を離間す
る熱可塑性樹脂フィルム81は丸印で図示する位置で導
電材87で貫通されて電気的接続をされている。具体的
には固着電極84と第1の接続電極86は上下に2個設
けた導電材87で接続され、各々の取り出し電極85
a、85bは第2の接続電極86a、86bとその中央
部に設けた導電材87で接続されている。従って各電極
は導電材87を介して、熱可塑性樹脂フィルム81の表
面側の共通連結部104に接続される。従って、ダイシ
ング後にそれぞれが細い連結部103,104を切断さ
れることで個々の電極として機能する。全パターンが電
気的に共通接続されるので、電解メッキ法により各電極
表面をニッケルメッキ層および金メッキ層で被覆するこ
とが可能となる。
On the back side of the thermoplastic resin film 81,
First and second connection electrodes 86, 86a, 86b are formed. These connection electrodes 86, 86a, 86b are formed in a pattern recessed from the end of the mounting portion 100 by about 0.05 to 0.1 mm. The thermoplastic resin film 81 separating the two conductive foils 82 and 83 is penetrated by a conductive material 87 at a position shown by a circle to be electrically connected. Specifically, the fixed electrode 84 and the first connection electrode 86 are connected to each other by two conductive materials 87 provided on the upper and lower sides.
a and 85b are connected to the second connection electrodes 86a and 86b by a conductive material 87 provided at the center thereof. Therefore, each electrode is connected to the common connection portion 104 on the front surface side of the thermoplastic resin film 81 via the conductive material 87. Therefore, each of the thin connecting portions 103 and 104 is cut after dicing to function as an individual electrode. Since all the patterns are electrically connected in common, it is possible to cover the surface of each electrode with a nickel plating layer and a gold plating layer by an electrolytic plating method.

【0043】熱可塑性樹脂81はセラミックやガラスエ
ポキシ基板に比較すると軟質であるので、ボンディング
する際にボンディング圧力が発散する欠点がある。これ
を防止するために本発明の製造方法が効果的である。
Since the thermoplastic resin 81 is softer than a ceramic or glass epoxy substrate, there is a disadvantage that a bonding pressure is diverged during bonding. In order to prevent this, the manufacturing method of the present invention is effective.

【0044】本発明では最終工程に前記導電箔83をエ
ッチングして所望形状のパターンに加工し、固着電極8
4と取り出し電極85a、85bと対向する位置に接続
電極86、86a、86bを形成するので、ボンディン
グする際にボンディング圧力が発散しないので、熱可塑
性に起因する軟質性の障害を取り除くことが可能であ
る。しかも熱可塑性樹脂フィルムとして液晶ポリマーを
用いることによる数々の利点も有している。電気特性で
は、誘電率において1MH(20℃、96H、65%R
H)で3.0,1GHzで2.9であり、ガラスエポキ
シ基板で誘電率が1MHzで4.7〜5.0と比較する
とかなり優れている。また表面抵抗は14×1013Ωで
あり、ポリイミド樹脂の1.1×1013Ωと比較しても
大幅に絶縁性が高い。これらから本発明の支持基板は極
めて高周波領域での特性が良好であることが明らかであ
る。更に耐折性についてはJIS C5016評価規格
でR=0.38mmで44回もあり、同一条件でポリイ
ミド樹脂は33回と比較すれば細線の断線が少ない。更
に吸水率0.04%であり、湿度下での絶縁性は良好で
あり、ガスバリヤー性も高く、ノンハロゲン、スルーホ
ールメッキレスと環境調和も優れている。
In the present invention, in the final step, the conductive foil 83 is etched and processed into a desired shape pattern,
Since the connection electrodes 86, 86a, 86b are formed at positions facing the electrode 4 and the extraction electrodes 85a, 85b, bonding pressure does not diverge during bonding, so that a soft failure caused by thermoplasticity can be removed. is there. Moreover, there are many advantages of using a liquid crystal polymer as the thermoplastic resin film. In electrical characteristics, the dielectric constant is 1 MH (20 ° C., 96 H, 65% R
H) is 3.0, and 2.9 at 1 GHz, which is considerably better than that of a glass epoxy substrate having a dielectric constant of 4.7 to 5.0 at 1 MHz. The surface resistance is 14 × 10 13 Ω, which is much higher than the polyimide resin 1.1 × 10 13 Ω. From these, it is apparent that the support substrate of the present invention has excellent characteristics in an extremely high frequency range. Further, the folding resistance is 44 times at R = 0.38 mm according to the JIS C5016 evaluation standard, and under the same conditions, the number of breaks in the fine wire is smaller than that of the polyimide resin 33 times. Furthermore, it has a water absorption of 0.04%, good insulation under humidity, high gas barrier properties, and is environmentally friendly with no halogen and no through-hole plating.

【0045】続いて本発明の半導体装置の製造方法を図
3から図8を参照して説明する。
Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

【0046】第1工程:図3(A)(B)(C)参照 本工程ではまず支持基板80を形成することにある。図
3(A)に示すように、第1の導電箔82、熱可塑性樹
脂から成るフィルム81および第2の導電箔83を準備
する。第1および第2の導電箔82,83は安価で電気
抵抗の低い銅箔が適しており、20μm厚で熱可塑性樹
脂から成るフィルム81と当接する面を凹凸に粗面化し
て固着強度を高めるようにしている。熱可塑性樹脂フィ
ルム81としては液晶ポリマーが最適であり、本実施例
では全芳香族ポリエステル系液晶ポリマー(商品名ベク
トラ)を用いた。上述したようにこの全芳香族ポリエス
テル系液晶ポリマーは物性的特性として、融点が325
℃、はんだ耐熱性は320℃であり、十分に半導体素子
の実装基板として使用できる。これは例えばガラスエポ
キシ基板のはんだ耐熱性が260℃であることからも容
易に分かる。第2の導電箔83表面には導電材87であ
る銀ぺーストを所定の位置にスクリーン印刷して熱可塑
性樹脂フィルム81を貫通する高さ(例えば50μm以
上)にバンプ120を予め形成しておく。
First Step: See FIGS. 3A, 3B and 3C In this step, first, a support substrate 80 is formed. As shown in FIG. 3A, a first conductive foil 82, a film 81 made of a thermoplastic resin, and a second conductive foil 83 are prepared. As the first and second conductive foils 82 and 83, an inexpensive and low-resistance copper foil is suitable, and the surface contacting the film 81 made of a thermoplastic resin having a thickness of 20 μm is roughened into irregularities to increase the bonding strength. Like that. As the thermoplastic resin film 81, a liquid crystal polymer is most suitable. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used. As described above, this wholly aromatic polyester-based liquid crystal polymer has a melting point of 325 as a physical property.
° C and solder heat resistance are 320 ° C, and can be sufficiently used as a mounting substrate for a semiconductor element. This can be easily understood from the fact that the solder heat resistance of the glass epoxy substrate is 260 ° C., for example. On the surface of the second conductive foil 83, a silver paste as a conductive material 87 is screen-printed at a predetermined position, and a bump 120 is formed in advance at a height (for example, 50 μm or more) penetrating the thermoplastic resin film 81. .

【0047】第1および第2の導電箔82,83と熱可
塑性樹脂フィルム81は最初は幅1mのロール状で供給
され、多数の支持基板80を形成した後に個別の支持基
板80に分離される。この個別の支持基板80が図2に
示すものであり、この個別の支持基板80にも24行2
4列に576個の半導体素子の搭載部100が形成され
ることになる。
The first and second conductive foils 82 and 83 and the thermoplastic resin film 81 are initially supplied in the form of a roll having a width of 1 m, formed into a large number of support substrates 80, and then separated into individual support substrates 80. . This individual support substrate 80 is shown in FIG.
The mounting portion 100 of 576 semiconductor elements is formed in four rows.

【0048】次に、図3(B)に示すように第1の導電
箔82、熱可塑性樹脂フィルム81および第2の導電箔
83を熱圧着して一体化された支持基板80を形成す
る。この熱圧着時に熱可塑性樹脂フィルム81は加熱さ
れて軟化するので、第2の導電箔83に付着された導電
材87となるバンプ120は熱可塑性樹脂フィルム81
を貫通し第1の導電箔82まで到達する。熱可塑性樹脂
フィルム81として液晶ポリマーを用いた場合は、加熱
温度300℃、圧着圧力4.4〜8.7kPaで真空熱
圧着を行う。このとき液晶ポリマーはガラス転移点に近
くかなり軟化しているので、導電ペーストで形成された
先端が尖ったバンプ120がこの液晶ポリマーを貫通す
る。なおこのときに接着剤は使用していない。
Next, as shown in FIG. 3B, the first conductive foil 82, the thermoplastic resin film 81 and the second conductive foil 83 are thermocompression-bonded to form an integrated support substrate 80. During this thermocompression bonding, the thermoplastic resin film 81 is heated and softened, so that the bumps 120 serving as the conductive material 87 attached to the second conductive foil 83 are formed of the thermoplastic resin film 81.
And reaches the first conductive foil 82. When a liquid crystal polymer is used as the thermoplastic resin film 81, vacuum thermocompression is performed at a heating temperature of 300 ° C. and a compression pressure of 4.4 to 8.7 kPa. At this time, since the liquid crystal polymer is considerably softened near the glass transition point, a bump 120 having a sharp tip made of a conductive paste penetrates the liquid crystal polymer. At this time, no adhesive was used.

【0049】更に、図3(C)に示すように熱圧着を完
了すると、第1の導電箔82、熱可塑性樹脂フィルム8
1、第2の導電箔83は密着して一体化されるので、導
電ペーストよりなるバンプ120も潰されて0.15m
mの径の柱状の導電材87を形成する。
Further, when the thermocompression bonding is completed as shown in FIG. 3C, the first conductive foil 82 and the thermoplastic resin film 8
Since the first and second conductive foils 83 are tightly integrated, the bumps 120 made of the conductive paste are also crushed by 0.15 m.
A columnar conductive material 87 having a diameter of m is formed.

【0050】第2工程:図4(A)(B)参照 斯かる支持基板80の両主面は第1および第2の導電箔
82,83で被覆されている。図4(A)示すように、
この第1の導電箔82上には所定の形状の固着電極8
4、取り出し電極85上を覆うようにレジスト膜112
を付着し、第2の導電箔83上はフラットな状態にして
おく。レジスト膜112としては液状のレジスト材料を
スピンコートして感光現像しても良いし、フィルム状の
レジスト材料を貼り付けて感光現像しても良い。
Second step: See FIGS. 4A and 4B Both main surfaces of the support substrate 80 are covered with first and second conductive foils 82 and 83. As shown in FIG.
The fixed electrode 8 having a predetermined shape is formed on the first conductive foil 82.
4. A resist film 112 is formed so as to cover the extraction electrode 85.
And the second conductive foil 83 is kept flat. As the resist film 112, a liquid resist material may be spin-coated and subjected to photosensitive development, or a film-shaped resist material may be attached and subjected to photosensitive development.

【0051】続いて図4(B)に示す如く、レジスト膜
112をマスクとして第1の導電箔82を塩化第2鉄溶
液を用いて化学的にエッチングして、第1の導電箔82
で固着電極84、取り出し電極85a、85bを形成す
る。これらの電極は全てが連結電極102,103や導
電材87で電気的に接続されているので、電解メッキに
よりこれらの電極上に金メッキの下地となるニッケルメ
ッキ層(5μm以上)とその上に金メッキ層(0.5μ
m以上)を形成している。
Subsequently, as shown in FIG. 4B, using the resist film 112 as a mask, the first conductive foil 82 is chemically etched using a ferric chloride solution to form the first conductive foil 82.
To form the fixed electrode 84 and the extraction electrodes 85a and 85b. Since all of these electrodes are electrically connected by the connection electrodes 102 and 103 and the conductive material 87, a nickel plating layer (5 μm or more) serving as a base for gold plating is formed on these electrodes by electrolytic plating, and gold plating is performed thereon. Layer (0.5μ
m or more).

【0052】第3工程:図5参照 上述したように各電極を形成した支持基板80の各搭載
部100毎に、半導体チップ88をダイボンドする。半
導体チップ88は固着電極84表面にAgペーストなど
の導電ペースト89によって固着される。導電ペースト
89は個別の支持基板80の固着電極84上にスクリー
ン印刷で付着された後、半導体チップ88を載置して、
還元雰囲気中の電気炉内で熱可塑性樹脂フィルムのガラ
ス転移点205℃以下の約150℃の温度で約30分間
硬化させる。
Third step: see FIG. 5 A semiconductor chip 88 is die-bonded to each mounting portion 100 of the support substrate 80 on which the electrodes are formed as described above. The semiconductor chip 88 is fixed to the surface of the fixed electrode 84 by a conductive paste 89 such as an Ag paste. After the conductive paste 89 is attached by screen printing on the fixed electrodes 84 of the individual support substrates 80, the semiconductor chip 88 is placed thereon,
The thermoplastic resin film is cured in an electric furnace in a reducing atmosphere at a temperature of about 150 ° C. below a glass transition point of 205 ° C. for about 30 minutes.

【0053】第4工程:図6参照 半導体チップ88の電極パッド90と取り出し電極85
a、85bとを各々金などのボンディングワイヤ91で
接続する。金線によりボールボンドをする場合は、支持
基板80を150℃に加熱して半導体チップ88の電極
パッド90に金線の一端に形成したボール部分を熱圧着
し、多端を取り出し電極85a、85bに熱圧着する。
この際、支持基板80の裏面側の第2の導電箔83はフ
ラットな状態なのでボンディングする際にボンディング
圧力が発散しないので、熱可塑性に起因する軟質性の障
害を取り除くことが可能であり、半導体チップ88の上
下の沈みを抑えることができボンディング細線のループ
形状を安定化できる。
Fourth step: See FIG. 6 The electrode pads 90 of the semiconductor chip 88 and the extraction electrodes 85
a and 85b are connected by bonding wires 91 such as gold. In the case of performing ball bonding with a gold wire, the supporting substrate 80 is heated to 150 ° C., and a ball portion formed at one end of the gold wire is thermocompression-bonded to the electrode pad 90 of the semiconductor chip 88, and multiple ends are taken out to the electrodes 85a and 85b. Thermocompression bonding.
At this time, since the second conductive foil 83 on the back surface side of the support substrate 80 is in a flat state, the bonding pressure does not diverge during bonding, so that it is possible to remove a soft failure caused by thermoplasticity. The sinking of the chip 88 in the vertical direction can be suppressed, and the loop shape of the bonding thin wire can be stabilized.

【0054】第5工程:図7(A)(B)(C)参照 支持基板80の各載置部に半導体チップ88のダイボン
ドとボンディング細線91による接続が終了すると、絶
縁樹脂92により全体のモールドを行う。本工程では支
持基板80の裏面に露出する第2の導電箔83を除き、
半導体チップ88、固着電極84、取り出し電極85
a、85bおよびボンディング細線91をエポキシ系樹
脂92で被覆する。
Fifth Step: See FIGS. 7A, 7B and 7C When the die bonding of the semiconductor chip 88 and the connection by the fine bonding wires 91 are completed on each mounting portion of the supporting substrate 80, the entire molding is performed by the insulating resin 92. I do. In this step, except for the second conductive foil 83 exposed on the back surface of the support substrate 80,
Semiconductor chip 88, fixed electrode 84, extraction electrode 85
a, 85 b and the bonding thin wire 91 are covered with an epoxy resin 92.

【0055】続いて図7(B)に示すように、この第2
の導電箔83上に固着電極54と取り出し電極55a、
55bと対向する位置に接続電極56、56a、56b
を覆うようにレジスト膜112を付着する。
Subsequently, as shown in FIG.
Fixed electrode 54 and extraction electrode 55a on conductive foil 83 of
Connection electrodes 56, 56a, 56b
A resist film 112 is attached so as to cover.

【0056】続いて図7(C)に示すように、レジスト
膜112をマスクとして第2の導電箔83を塩化第2鉄
溶液を用いて化学的にエッチングして、第2の導電箔8
3で接続電極56、56a、56bを形成する。
Subsequently, as shown in FIG. 7C, the second conductive foil 83 is chemically etched using a resist film 112 as a mask using a ferric chloride solution to form a second conductive foil 8.
3, the connection electrodes 56, 56a and 56b are formed.

【0057】[0057]

【発明の効果】本発明によれば、第1にボンディング終
了後に接続電極を形成することによりボンディング時に
第2の導電箔で軟質樹脂全面を支持するので、半導体チ
ップの上下の沈みを防止し、安定したボンディングを実
現できる。
According to the present invention, firstly, the entire surface of the soft resin is supported by the second conductive foil at the time of bonding by forming the connection electrodes after the completion of the bonding. Stable bonding can be realized.

【0058】第2に2枚の導電箔と導電材で各電極を形
成するので、従来用いていたタングステン等の高価な金
属ペーストが不要となり、極めて安価な実装構造を実現
できる利点を有する。また導電箔として銅箔を用いると
電気抵抗も低くでき、飽和オン抵抗も大幅に改善でき
る。
Second, since each electrode is formed of two conductive foils and a conductive material, an expensive metal paste such as tungsten conventionally used is not required, and there is an advantage that an extremely inexpensive mounting structure can be realized. When a copper foil is used as the conductive foil, the electric resistance can be reduced, and the saturation on-resistance can be greatly improved.

【0059】第3に2枚の導電箔の層間絶縁膜として熱
可塑性樹脂フィルムを用いているので、ビアホールの形
成やスルーホールメッキ等を不要にでき、導電材を熱可
塑性樹脂フィルムを熱圧着時に貫通させるだけで両導電
箔で形成した各電極を電気的に接続できる極めて簡単な
実装構造を提供できる。このためにノンハロゲン、スル
ーホールめっきレスで極めて環境に優しい実装構造とな
る。
Third, since a thermoplastic resin film is used as an interlayer insulating film between the two conductive foils, the formation of via holes and through-hole plating can be eliminated, and the conductive material can be used when the thermoplastic resin film is thermocompressed. It is possible to provide a very simple mounting structure that can electrically connect the electrodes formed of both conductive foils only by penetrating. For this reason, a non-halogen, no through-hole plating and extremely environmentally friendly mounting structure is obtained.

【0060】第4に本発明の支持基板は銅箔が約20μ
m、熱可塑性樹脂フィルムが約50μmで形成されるの
で、全体では厚みが高々90μmにでき、従来のセラミ
ック基板の厚みがセラミックだけで0.25mmから
0.35mmもあり、約1/3に薄型化できる利点を有
する。このため完成された半導体装置の薄型化にも大い
に貢献でき、1mm×1mm以下の極めて微細なトラン
ジスタチップ等の実装構造には最適である。
Fourth, the supporting substrate of the present invention has a copper foil of about 20 μm.
m, since the thermoplastic resin film is formed with a thickness of about 50 μm, the overall thickness can be at most 90 μm, and the thickness of a conventional ceramic substrate is only 0.25 mm to 0.35 mm with ceramic alone, and is about 1/3 thin. It has the advantage that it can be. For this reason, it can greatly contribute to the reduction in thickness of the completed semiconductor device, and is most suitable for a mounting structure of an extremely fine transistor chip of 1 mm × 1 mm or less.

【0061】第5に本発明で用いた熱可塑性樹脂フィル
ムは、高周波領域における誘電率はポリイミド樹脂と同
じであり、また表面抵抗はガラスエポキシ基板と同等で
あり、良好な高周波特性を得られる。
Fifth, the thermoplastic resin film used in the present invention has the same dielectric constant in the high-frequency region as the polyimide resin, and has the same surface resistance as the glass epoxy substrate, so that good high-frequency characteristics can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置を説明する(A)平面図、
(B)断面図、(C)裏面図である。
FIG. 1A is a plan view illustrating a semiconductor device of the present invention,
(B) is a sectional view, (C) is a back view.

【図2】本発明に用いる支持基板を説明する(A)平面
図、(B)裏面図である。
FIGS. 2A and 2B are a plan view and a rear view illustrating a support substrate used in the present invention. FIGS.

【図3】本発明の半導体装置の製造方法を説明する断面
図である。
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図4】本発明の半導体装置の製造方法を説明する断面
図である。
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図5】本発明の半導体装置の製造方法を説明する断面
図である。
FIG. 5 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図6】本発明の半導体装置の製造方法を説明する断面
図である。
FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図7】本発明の半導体装置の製造方法を説明する断面
図である。
FIG. 7 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図8】従来の半導体装置を説明する断面図である。FIG. 8 is a cross-sectional view illustrating a conventional semiconductor device.

【図9】従来の半導体装置を説明する(A)平面図
(B)断面図(C)斜視図である。
9A is a plan view, FIG. 9B is a sectional view, and FIG. 9C is a perspective view illustrating a conventional semiconductor device.

【図10】従来の半導体装置を説明する(A)平面図
(B)断面図(C)裏面図である。
10A is a plan view, FIG. 10B is a cross-sectional view, and FIG. 10C is a rear view illustrating a conventional semiconductor device.

【図11】従来の半導体装置を説明する(A)平面図
(B)裏面図である。
11A is a plan view and FIG. 11B is a rear view illustrating a conventional semiconductor device.

【図12】従来の半導体装置を説明する断面図である。FIG. 12 is a cross-sectional view illustrating a conventional semiconductor device.

【図13】従来の半導体装置の製造方法を説明する断面
図である。
FIG. 13 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【図14】従来の半導体装置の製造方法を説明する断面
図である。
FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

【図15】従来の半導体装置の製造方法を説明する断面
図である。
FIG. 15 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

【図16】従来の半導体装置の製造方法を説明する断面
図である。
FIG. 16 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

【図17】従来の半導体装置の製造方法を説明する断面
図である。
FIG. 17 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤井 茂 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 Fターム(参考) 5F044 AA02 CC07  ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shigeru Fujii 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 5F044 AA02 CC07

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 第1の導電箔と、軟質樹脂と、導電材を
所望の位置に付着した第2の導電箔とを熱圧着して前記
導電材を前記軟質樹脂を貫通させて前記第1および第2
の導電箔を電気的に接続する支持基板を形成する工程
と、 前記第1の導電箔で固着電極および取り出し電極を形成
する工程と、 前記固着電極に導電ペーストを用いて半導体素子を固着
する工程と、 前記半導体素子の電極と前記取り出し電極をボンディン
グ接続する工程と、 前記第2の導電箔を露出して全体を絶縁樹脂で被覆する
工程と、 前記第2の導電箔で前記固着電極および取り出し電極に
対応し前記導電材で電気的に接続された接続電極を形成
する工程とを具備することを特徴とする半導体装置の製
造方法。
1. A first conductive foil, a soft resin, and a second conductive foil having a conductive material adhered to a desired position are thermocompression-bonded to penetrate the conductive material through the soft resin to form the first conductive foil. And the second
Forming a support substrate for electrically connecting the conductive foils, forming a fixed electrode and a lead-out electrode with the first conductive foil, and fixing a semiconductor element to the fixed electrode using a conductive paste. Bonding the electrode of the semiconductor element to the take-out electrode; exposing the second conductive foil to cover the whole with an insulating resin; and taking the fixed electrode and take-out with the second conductive foil. Forming a connection electrode corresponding to the electrode and electrically connected by the conductive material.
【請求項2】 前記第1および第2の導電箔として銅箔
を用い、化学的エッチングで前記固着電極、取り出し電
極および接続電極を形成することを特徴とする請求項1
記載の半導体装置の製造方法。
2. The fixed electrode, the extraction electrode and the connection electrode are formed by chemical etching using a copper foil as the first and second conductive foils.
The manufacturing method of the semiconductor device described in the above.
【請求項3】 前記軟質樹脂として熱可塑性樹脂を用い
たことを特徴とする請求項1記載の半導体装置の製造方
法。
3. The method according to claim 1, wherein a thermoplastic resin is used as the soft resin.
【請求項4】 前記熱可塑性樹脂として液晶ポリマーを
用いたことを特徴とする請求項1記載の半導体装置の製
造方法。
4. The method according to claim 1, wherein a liquid crystal polymer is used as the thermoplastic resin.
【請求項5】 前記導電材として銀ペーストを用いたこ
とを特徴とする請求項1記載の半導体装置の製造方法。
5. The method according to claim 1, wherein a silver paste is used as the conductive material.
【請求項6】 前記半導体素子を固着する前記導電ペー
ストとして銀ペーストを用い、該銀ペーストの硬化を前
記熱可塑性樹脂フィルムのガラス転移点以下の温度で行
うことを特徴とする請求項1記載の半導体装置の製造方
法。
6. The method according to claim 1, wherein a silver paste is used as the conductive paste for fixing the semiconductor element, and the silver paste is cured at a temperature equal to or lower than a glass transition point of the thermoplastic resin film. A method for manufacturing a semiconductor device.
【請求項7】 前記絶縁樹脂の被覆は前記熱可塑性樹脂
フィルムのガラス転移点以下の温度でトランスファーモ
ールドで行うことを特徴とする請求項1記載の半導体装
置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 1, wherein the coating of the insulating resin is performed by transfer molding at a temperature equal to or lower than a glass transition point of the thermoplastic resin film.
JP2000373086A 2000-12-07 2000-12-07 Method for manufacturing semiconductor device Pending JP2002176121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000373086A JP2002176121A (en) 2000-12-07 2000-12-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000373086A JP2002176121A (en) 2000-12-07 2000-12-07 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2002176121A true JP2002176121A (en) 2002-06-21

Family

ID=18842528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000373086A Pending JP2002176121A (en) 2000-12-07 2000-12-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2002176121A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020116306A1 (en) * 2018-12-04 2020-06-11 株式会社クラレ High voltage circuit board and high voltage device using same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020116306A1 (en) * 2018-12-04 2020-06-11 株式会社クラレ High voltage circuit board and high voltage device using same
JPWO2020116306A1 (en) * 2018-12-04 2021-10-14 株式会社クラレ High-voltage circuit board and high-voltage device using it
JP7407732B2 (en) 2018-12-04 2024-01-04 株式会社クラレ High voltage circuit board and high voltage device using the same

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