JP2002176120A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002176120A
JP2002176120A JP2000373085A JP2000373085A JP2002176120A JP 2002176120 A JP2002176120 A JP 2002176120A JP 2000373085 A JP2000373085 A JP 2000373085A JP 2000373085 A JP2000373085 A JP 2000373085A JP 2002176120 A JP2002176120 A JP 2002176120A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
conductive
electrodes
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000373085A
Other languages
Japanese (ja)
Inventor
Shigeru Fujii
茂 藤井
Haruo Hyodo
治雄 兵藤
Haruhiko Sakai
春彦 境
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000373085A priority Critical patent/JP2002176120A/en
Publication of JP2002176120A publication Critical patent/JP2002176120A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize a small size and thinner package just suitable for the loading of an ultra-fine semiconductor chip by reducing thickness of a supporting substrate. SOLUTION: The supporting substrate 80 is formed by integrating two sheets of conductive foils 82, 83 and a thermosetting resin film 81 disposed between these foils with a thermal pressurizing process, and a conductive material 87 is also provided through the thermosetting resin film 81 in above thermal pressurizing process to form the conductive material 87 for electrically connecting both conductive foils 82, 83 without via-hole. Each electrode is formed with both conductive foils 82, 83 to mount a semiconductor chip 88. In this timing, a resist layer 120 is formed among the connecting electrodes 86, 86a, 86b formed of the conductive foil 83 to prevent vertical sink of the semiconductor chip 88 in the bonding process. Consequently, an extremely thin mounting structure can be realized with a simplified structure and a semiconductor device just suitable for mounting of an ultra-fine semiconductor chip can also be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置、特にパ
ッケージ外形を超小型で薄型に形成できる微小チップを
収容する樹脂封止型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device for accommodating a small chip whose package outer shape can be formed to be ultra-small and thin.

【０００２】[0002]

【従来の技術】従来の半導体装置の組立工程において
は、ウェハからダイシングして分離した半導体チップを
リードフレームに固着し、金型と樹脂注入によるトラン
スファーモールドによって半導体チップを封止し、リー
ドフレームを切断して個々の半導体装置毎に分離すると
いう工程が行われている。この方法によって得れらる半
導体装置は、図９に示したように、半導体チップ１の周
囲を樹脂層２で被覆し、該樹脂層２の側部から外部接続
用のリード端子３を導出した構造になる（例えば特開平
０５−１２９４７３号）。2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip is sealed by a transfer mold using a mold and resin injection. A process of cutting and separating each semiconductor device is performed. In the semiconductor device obtained by this method, as shown in FIG. 9, the periphery of the semiconductor chip 1 is covered with a resin layer 2, and lead terminals 3 for external connection are led out from the side of the resin layer 2. (For example, JP-A-05-129473).

【０００３】この構造は、樹脂層２の外側にリード端子
３が突出すること、リードフレームの加工精度の問題や
金型との位置あわせ精度の問題により、外形寸法とその
実装面積の縮小化には限界が見えていた。[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 3 outside the resin layer 2, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

【０００４】近年、外形寸法を半導体チップサイズと同
等あるいは近似した寸法にまで縮小する事が可能な、ウ
ェハスケールＣＳＰ（チップサイズパッケージ）が注目
され始めている。これは、図１０（Ａ）を参照して、半
導体ウェハ１１に各種拡散などの前処理を施して多数の
半導体チップ１２を形成し、図１０（Ｂ）に示したよう
に半導体ウェハ１１の上部を樹脂層１３で被覆すると共
に樹脂層１３表面に外部接続用の電極１４を導出し、そ
の後半導体ウェハ１１のダイシングラインに沿って半導
体チップ１１を分割して、図１０（Ｃ）に示したような
完成品としたものである。樹脂層１３は半導体チップ１
２の表面（裏面を被覆する場合もある）を被覆するだけ
であり、半導体チップ１２の側壁にはシリコン基板が露
出する。電極１４は樹脂層１３下部に形成された集積回
路網と電気的に接続されており、実装基板上に形成した
導電パターンに対して電極１４を対向接着することによ
りこの半導体装置の実装が実現する。In recent years, attention has been paid to a wafer-scale CSP (chip size package) capable of reducing an outer dimension to a size similar to or close to a semiconductor chip size. In this, referring to FIG. 10A, a large number of semiconductor chips 12 are formed by performing various pretreatments such as diffusion on a semiconductor wafer 11, and an upper portion of the semiconductor wafer 11 is formed as shown in FIG. Is covered with a resin layer 13, electrodes 14 for external connection are led out on the surface of the resin layer 13, and then the semiconductor chips 11 are divided along dicing lines of the semiconductor wafer 11, as shown in FIG. It is a finished product. The resin layer 13 is the semiconductor chip 1
2 only covers the front surface (which may cover the back surface) of the semiconductor chip 12, and the silicon substrate is exposed on the side wall of the semiconductor chip 12. The electrode 14 is electrically connected to an integrated circuit network formed below the resin layer 13, and the semiconductor device is mounted by bonding the electrode 14 to a conductive pattern formed on a mounting substrate. .

【０００５】斯かる半導体装置は、装置のパッケージサ
イズが半導体チップのチップサイズと同等であり、実装
基板に対しても対向接着で済むので、実装占有面積を大
幅に減らすことが出来る利点を有する。また、後工程に
拘わるコストを大幅に減じることが出来る利点を有する
ものである。（例えば、特開平９−６４０４９号）しか
しながら、チップサイズが１０数ｍｍ角にも及ぶＬＳＩ
チップであればその寸法内に多数個の電極を配置するこ
とが可能であるものの、例えばチップサイズが１ｍｍ角
に満たない程度のトランジスタチップ等では、この寸法
内に複数個の電極を配置することは物理的に無理がある
し、実現したとしても実装が困難である欠点がある。[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor chip, and the device can be adhered to the mounting substrate by opposing, so that the area occupied by the mounting can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. (For example, Japanese Patent Laid-Open No. 9-64049)
Although it is possible to arrange a large number of electrodes within the dimensions of a chip, for example, for a transistor chip having a chip size of less than 1 mm square, it is necessary to arrange a plurality of electrodes within this dimension. Has the drawback that it is physically unreasonable and difficult to implement even if realized.

【０００６】そこで、チップサイズが１ｍｍ角に満たな
い程度のチップでは図１１（Ａ）（Ｂ）（Ｃ）に示すよ
うに実装されている。図中、２１はセラミックやガラス
エポキシ等からなる絶縁基板であり、それらが１枚ある
いは数枚重ね合わされて、板厚が２５０〜３５０μｍと
製造工程における機械的強度を維持し得る厚みと、長辺
×短辺が１．０ｍｍ×０．８ｍｍ程度の矩形形状を有し
ている。Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 11A, 11B and 11C. In the figure, reference numeral 21 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are stacked to have a thickness of 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process, and a long side. X It has a rectangular shape with a short side of about 1.0 mm x 0.8 mm.

【０００７】絶縁基板２１の表面には、タングステン等
の金属ペーストの印刷と、電解メッキ法による前記金属
ペースト上への金メッキによって導電パターンを形成
し、アイランド部２２と電極部２３ａ、２３ｂとを形成
している。アイランド部２２の上には、Ａｇペーストな
どの導電性接着剤２４によって半導体チップ２５が固着
されている。On the surface of the insulating substrate 21, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 22 and electrode portions 23a and 23b. are doing. A semiconductor chip 25 is fixed on the island portion 22 by a conductive adhesive 24 such as an Ag paste.

【０００８】半導体チップ２５の表面にはアルミ電極パ
ッド２６が形成され、電極パッド２６と電極部２３ａ、
２３ｂとが、ボンディングワイヤ２７によって電気接続
される。電極パッド２６側に１ｓｔボンド、電極部２３
側に２ｎｄボンドが打たれる。バイポーラトランジスタ
で有れば、電極部２３ａ、２３ｂはエミッタとベースに
対応し、パワーＭＯＳＦＥＴで有れば、ソースとゲート
に対応する。An aluminum electrode pad 26 is formed on the surface of the semiconductor chip 25, and the electrode pad 26 and the electrode portion 23a are formed.
23b are electrically connected to each other by a bonding wire 27. 1st bond on electrode pad 26 side, electrode section 23
A 2nd bond is struck on the side. If it is a bipolar transistor, the electrode portions 23a and 23b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【０００９】前記絶縁基板２１の裏面側には、同じく金
メッキ層によって第１の外部接続電極２８と第２の外部
接続電極２９ａ、２９ｂが形成される。絶縁基板２１に
はこれを貫通する、円形の第１のビアホール３０と第２
のビアホール３１ａ、３１ｂが形成され、各ビアホール
３０、３１ａ、３１ｂの内部はタングステンなどの導電
材料によって埋設される。素材としては、電気的導電性
と熱伝導性に優れた素材で埋設する。該ビアホール３
０、３１ａ、３１ｂによって、アイランド部２２と第１
の外部接続電極２８とを、電極部２３ａ、２３ｂと第２
の外部接続電極２９ａ、２９ｂとを、各々電気接続す
る。第１の外部接続電極２８が例えばコレクタ電極とな
り、第２の外部接続電極２９ａ、２９ｂが例えばベー
ス、エミッタ電極となる。A first external connection electrode 28 and second external connection electrodes 29a and 29b are formed on the back surface of the insulating substrate 21 by the same gold plating layer. A circular first via hole 30 and a second
Are formed, and the inside of each via hole 30, 31a, 31b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 3
0, 31a and 31b, the island portion 22 and the first
Of the external connection electrode 28 and the electrode portions 23a and 23b and the second
Are electrically connected to the external connection electrodes 29a and 29b, respectively. The first external connection electrodes 28 are, for example, collector electrodes, and the second external connection electrodes 29a, 29b are, for example, base and emitter electrodes.

【００１０】絶縁基板２１の上方は、半導体チップ２５
とボンディングワイヤ２７とを封止する樹脂層３２で被
覆される。樹脂層３２は絶縁基板２１と共にパッケージ
外形を構成する。パッケージの周囲４側面は樹脂層３２
と絶縁基板２１の切断面で形成され、パッケージの上面
は平坦化した樹脂層３２の表面、パッケージの下面は絶
縁基板２１の裏面側で形成される。The semiconductor chip 25 is located above the insulating substrate 21.
And the bonding wire 27 is covered with a resin layer 32. The resin layer 32 forms an outer shape of the package together with the insulating substrate 21. The four sides around the package are resin layers 32
The upper surface of the package is formed on the flattened surface of the resin layer 32, and the lower surface of the package is formed on the back surface side of the insulating substrate 21.

【００１１】しかしながら図１１で示した実装構造にお
いていろいろな問題点がある。第１にタングステン等の
高価な金属ペーストを用いているので、ローコストの実
装構造とは言えない。第２に両面の電極等を接続するた
めに、絶縁基板を貫通するビアホールが不可欠であり、
この加工精度も０．１５mm程度が限界であるので、更な
る小型化の障害となっている。第３にこのビアホール内
を金属ペーストで充填するため作業性が極めて悪く、コ
スト高の原因となる。第４に絶縁基板が機械的強度を維
持するために０．２５mmから０．３５mmは必要であるた
めに薄型化の阻害要因となっている等々の多くの問題点
が発生している。However, there are various problems in the mounting structure shown in FIG. First, since an expensive metal paste such as tungsten is used, it cannot be said that the mounting structure is low cost. Secondly, in order to connect the electrodes and the like on both surfaces, a via hole penetrating the insulating substrate is indispensable.
Since the processing accuracy is limited to about 0.15 mm, it is an obstacle to further miniaturization. Third, since the inside of the via hole is filled with a metal paste, workability is extremely poor, which causes an increase in cost. Fourth, since the insulating substrate needs to have a thickness of 0.25 mm to 0.35 mm in order to maintain the mechanical strength, there are many problems such as hindrance to thinning.

【００１２】ここで上述した様々な問題点を解決するた
めに以下の支持基板に液晶ポリマーを用いた半導体装置
が提案されている。Here, in order to solve the various problems described above, the following semiconductor device using a liquid crystal polymer for a supporting substrate has been proposed.

【００１３】この実施例を図１２を参照して説明する。
図１２は、完成された個別の半導体装置を説明する図で
あり、（Ａ）が平面図、（Ｂ）が裏面図であり、図１２
（Ｃ）はボンディング時の断面図である。This embodiment will be described with reference to FIG.
12A and 12B are diagrams illustrating completed individual semiconductor devices. FIG. 12A is a plan view, FIG. 12B is a rear view, and FIG.
(C) is a sectional view at the time of bonding.

【００１４】この半導体装置の特徴とする支持基板５０
は、熱可塑性樹脂のフィルム５１の両面に２枚の導電箔
を熱圧着して形成されている。熱可塑性樹脂は加熱する
ことにより軟化して二次加工が容易であり、従来用いて
いたセラミックスやガラスエポキシの硬質基板よりはる
かに扱いやすくなる。熱可塑性樹脂としては液晶ポリマ
ーが最適であり、本実施例では全芳香族ポリエステル系
液晶ポリマー（商品名ベクトラ）を用いた。A support substrate 50 which is a feature of this semiconductor device
Is formed by thermocompression bonding two conductive foils on both surfaces of a thermoplastic resin film 51. The thermoplastic resin is softened by heating and is easily subjected to secondary processing, and is much easier to handle than a conventionally used ceramic or glass epoxy hard substrate. A liquid crystal polymer is most suitable as the thermoplastic resin. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used.

【００１５】熱可塑性樹脂フィルム５１の両面にはこの
樹脂フィルムで離間されかつ電気的に絶縁された２枚の
導電箔が圧着されている。この導電箔としては安価で電
気的抵抗の小さい銅箔が最適である。具体的には５０μ
ｍの厚みの熱可塑性樹脂フィルム５１の両面に各々２０
μｍの厚みの銅箔が圧着されている。一方の導電箔はエ
ッチングされて所望形状のパターンに加工され、固着電
極５４と取り出し電極５５ａ、５５ｂを形成する。固着
電極５４は少なくとも半導体チップ５８が載置できる大
きさと形状を有しており、この固着電極５４に隣接して
少し離間して取り出し電極５５ａ、５５ｂが複数個形成
されている。他方の導電箔もエッチングされて所望形状
のパターンに加工され、固着電極５４と取り出し電極５
５ａ、５５ｂと対向する位置に接続電極５６、５６ａ、
５６ｂを形成する。接続電極５６、５６ａ、５６ｂはプ
リント基板にはんだ付けできる大きさに形成され、はん
だ付けの際にはんだブリッジが形成されないように離間
され、対応する固着電極５４および取り出し電極５５
ａ、５５ｂよりは小さく形成される。なお固着電極５
４、取り出し電極５５ａ、５５ｂおよび接続電極５６、
５６ａ、５６ｂは電解メッキによりその表面をニッケル
メッキ層と金メッキ層で被覆されており、導電ペースト
との接触抵抗を減少させ、またボンディング細線の固着
を可能にしている。Two conductive foils which are separated by the resin film and electrically insulated are pressure-bonded to both surfaces of the thermoplastic resin film 51. As the conductive foil, an inexpensive copper foil having a small electric resistance is optimal. Specifically, 50μ
m on each side of the thermoplastic resin film 51 having a thickness of 20 m.
A copper foil having a thickness of μm is pressed. One conductive foil is etched and processed into a desired shape pattern to form the fixed electrode 54 and the extraction electrodes 55a and 55b. The fixed electrode 54 has a size and a shape at least on which the semiconductor chip 58 can be mounted, and a plurality of extraction electrodes 55a and 55b are formed adjacent to the fixed electrode 54 and slightly apart therefrom. The other conductive foil is also etched and processed into a desired shape pattern, and the fixed electrode 54 and the extraction electrode 5 are formed.
The connection electrodes 56, 56a,
Form 56b. The connection electrodes 56, 56 a, 56 b are formed in a size that can be soldered to a printed circuit board, are separated so that a solder bridge is not formed at the time of soldering, and the corresponding fixed electrodes 54 and extraction electrodes 55 are formed.
a and 55b. Note that the fixed electrode 5
4, extraction electrodes 55a and 55b and connection electrodes 56,
The surfaces 56a and 56b are covered with a nickel plating layer and a gold plating layer by electrolytic plating to reduce the contact resistance with the conductive paste and to enable the bonding of the fine bonding wires.

【００１６】導電材５７は一方の導電箔で形成された固
着電極５４、取り出し電極５５ａ、５５ｂと他方の導電
箔で形成された対応する接続電極５６、５６ａ、５６ｂ
とを接続している。導電材５７としては銀ペーストを用
い、熱可塑性樹脂５１を加熱して軟化させて導電材５７
を貫通させている。従って予めビアホールを設ける必要
が無くなる。導電材５７を貫通させる位置は図１２
（Ａ）（Ｂ）に破線丸印で示すように、固着電極５４で
は取り出し電極５５ａ、５５ｂと離れた側の上下両端近
くに２個設け、取り出し電極５５ａ、５５ｂではほぼ中
央部に１個形成している。The conductive material 57 includes a fixed electrode 54 and lead electrodes 55a and 55b formed of one conductive foil and corresponding connection electrodes 56, 56a and 56b formed of the other conductive foil.
And are connected. A silver paste is used as the conductive material 57, and the thermoplastic resin 51 is heated and softened by heating.
Through. Therefore, it is not necessary to provide a via hole in advance. The position where the conductive material 57 is penetrated is shown in FIG.
(A) and (B), two fixed electrodes 54 are provided near the upper and lower ends on the side remote from the extraction electrodes 55a and 55b, and one is formed substantially at the center of the extraction electrodes 55a and 55b, as indicated by the broken circles. are doing.

【００１７】半導体チップ５８は固着電極５４上にＡｇ
ペーストなどの導電ペースト５９により固着されてい
る。半導体チップ５８としては、バイポーラトランジス
タ、パワーＭＯＳＦＥＴ等の３端子素子又はダイオード
などの２端子素子が形成されているウエファーから供給
される。半導体チップ５８自体は、Ｎ＋／Ｎ型構造のよ
うに、裏面側に高濃度不純物層を有しており、該高濃度
層を介して、ダイオード素子で有ればアノード又はカソ
ードの一方の端子を、バイポーラ型トランジスタで有れ
ばコレクタ端子を、パワーＭＯＳＦＥＴで有ればドレイ
ン端子を導出する構造を有しているので、この高濃度層
が導電ペースト５９を介して固着電極５４にオーミック
接続される。The semiconductor chip 58 has Ag fixed on the fixed electrode 54.
It is fixed by a conductive paste 59 such as a paste. The semiconductor chip 58 is supplied from a wafer on which a three-terminal element such as a bipolar transistor or a power MOSFET or a two-terminal element such as a diode is formed. The semiconductor chip 58 itself has a high-concentration impurity layer on the back side like an N + / N-type structure, and through the high-concentration layer, connects one terminal of an anode or a cathode if it is a diode element. In the case of a bipolar transistor, the collector terminal is provided, and in the case of a power MOSFET, the drain terminal is provided, so that this high concentration layer is ohmically connected to the fixed electrode 54 via the conductive paste 59. .

【００１８】半導体チップ５８の表面にはアルミ電極パ
ッド６０が形成され、電極パッド６０と取り出し電極５
５ａ、５５ｂとが、金線ボンディングワイヤ６１によっ
て電気接続される。電極パッド６０側に１ｓｔボンド、
取り出し電極５５ａ、５５ｂ５５ｂ側に２ｎｄボンドが
打たれる。バイポーラトランジスタで有れば、取り出し
電極５５ａ、５５ｂはエミッタとベースに対応し、パワ
ーＭＯＳＦＥＴで有れば、ソースとゲートに対応する。An aluminum electrode pad 60 is formed on the surface of the semiconductor chip 58, and the electrode pad 60 and the extraction electrode 5 are formed.
5a and 55b are electrically connected by a gold wire bonding wire 61. 1st bond on the electrode pad 60 side,
A second bond is formed on the side of the extraction electrodes 55a and 55b55b. If it is a bipolar transistor, the extraction electrodes 55a and 55b correspond to the emitter and the base, and if it is a power MOSFET, it corresponds to the source and the gate.

【００１９】支持基板５０の上面は、半導体チップ５
８、固着電極５４、取り出し電極５５ａ、５５ｂおよび
ボンディングワイヤ６１とを被覆する絶縁樹脂６２で封
止される。絶縁樹脂６２は支持基板５１と共にパッケー
ジ外形を構成する。パッケージの周囲４側面は絶縁樹脂
６２と支持基板５１の切断面で形成され、パッケージの
上面は平坦化した絶縁樹脂層６２の表面、パッケージの
下面は支持基板５０の裏面側で形成される。絶縁樹脂６
２は一般的に用いられるエポキシ樹脂を用いる。The upper surface of the supporting substrate 50 is
8. Sealed with insulating resin 62 covering fixed electrode 54, extraction electrodes 55a and 55b and bonding wire 61. The insulating resin 62 forms a package outer shape together with the support substrate 51. The four peripheral sides of the package are formed by the cut surface of the insulating resin 62 and the support substrate 51, the upper surface of the package is formed by the flattened surface of the insulating resin layer 62, and the lower surface of the package is formed by the back surface of the support substrate 50. Insulating resin 6
2 uses a commonly used epoxy resin.

【００２０】[0020]

【発明が解決しようとする課題】しかしながら図１２で
示した実装構造において重要な問題点がある。それは支
持基板となる液晶ポリマーがとても軟らかいということ
である。斯かる半導体装置では構造上固着電極および取
り出し電極よりも接続電極は小さく形成される。そのこ
とにより図１２（Ｃ）に示すごとく接続電極のない部分
が金線ボンディングワイヤによって電気接続される際
に、基板が押さえつけられる力に耐えきれなくなり歪ん
でしまい、接続の際の超音波がうまく伝わらないという
問題点が発生している。However, there is an important problem in the mounting structure shown in FIG. That is, the liquid crystal polymer serving as the support substrate is very soft. In such a semiconductor device, the connection electrode is formed smaller in structure than the fixed electrode and the extraction electrode. As a result, as shown in FIG. 12 (C), when a portion having no connection electrode is electrically connected by the gold bonding wire, the substrate cannot withstand the pressing force and is distorted. There is a problem of not being transmitted.

【００２１】[0021]

【課題を解決するための手段】本発明は上述した種々の
問題点に鑑みてなされたものであり、軟質の樹脂で離間
された相対向する導電箔を有し、一方の導電箔を所望形
状に形成された固着電極および取り出し電極を設け、他
方の導電箔で形成された前記固着電極および取り出し電
極に対応して対向する接続電極を設け、かつ前記固着電
極および取り出し電極と対応する前記接続電極とを電気
的に接続し前記樹脂を貫通する導電材とを有する支持基
板と、前記固着電極上に固着された半導体素子と、前記
半導体素子の電極と前記取り出し電極とを接続するボン
ディング細線と、前記接続電極を露出して前記半導体素
子、固着電極、取り出し電極および前記ボンディング細
線を少なくとも被覆する絶縁樹脂とを具備する半導体装
置において、前記樹脂上の前記固着電極と前記取り出し
電極間に段差埋設絶縁物層を設けたことを特徴としてい
る。SUMMARY OF THE INVENTION The present invention has been made in view of the various problems described above, and has opposed conductive foils separated by a soft resin, and one of the conductive foils has a desired shape. A connection electrode facing the fixed electrode and the extraction electrode formed of the other conductive foil, and the connection electrode corresponding to the fixed electrode and the extraction electrode. And a supporting substrate having a conductive material that electrically connects and penetrates the resin, a semiconductor element fixed on the fixed electrode, a bonding thin wire connecting the electrode of the semiconductor element and the extraction electrode, A semiconductor device comprising: an insulating resin that exposes the connection electrode to cover at least the semiconductor element, the fixed electrode, the extraction electrode, and the bonding wire. Is characterized in that a stepped buried insulating layer between the said fixed electrode on the fat extraction electrode.

【００２２】[0022]

【発明の実施の形態】本発明の一実施例を図１および図
２を参照して説明する。 図１は、本発明の完成された
個別の半導体装置を説明する図であり、（Ａ）が平面
図、（Ｂ）が断面図、（Ｃ）が裏面図である。図２は、
本発明に用いる支持基板を説明する図であり、（Ａ）が
平面図、（Ｂ）が裏面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams illustrating a completed individual semiconductor device of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a cross-sectional view, and FIG. FIG.
It is a figure explaining a support substrate used for the present invention, (A) is a top view and (B) is a back view.

【００２３】本発明の特徴とする支持基板８０は、熱可
塑性樹脂フィルム８１の両面に２枚の導電箔８２，８３
（図３参照）を熱圧着して形成されている。熱可塑性樹
脂は加熱することにより軟化して二次加工が容易であ
り、従来用いていたセラミックスやガラスエポキシの硬
質基板よりはるかに扱いやすくなる。上述したように熱
可塑性樹脂としては液晶ポリマーが最適であり、本実施
例では全芳香族ポリエステル系液晶ポリマー（商品名ベ
クトラ）を用いた。The supporting substrate 80, which is a feature of the present invention, comprises two conductive foils 82, 83 on both surfaces of a thermoplastic resin film 81.
(See FIG. 3). The thermoplastic resin is softened by heating and is easily subjected to secondary processing, and is much easier to handle than a conventionally used ceramic or glass epoxy hard substrate. As described above, a liquid crystal polymer is most suitable as the thermoplastic resin. In this embodiment, a wholly aromatic polyester-based liquid crystal polymer (Vectra) is used.

【００２４】熱可塑性樹脂フィルム８１の両面にはこの
樹脂フィルムで離間されかつ電気的に絶縁された２枚の
導電箔８２，８３が圧着されている。この導電箔として
は安価で電気的抵抗の小さい銅箔が最適である。具体的
には５０μｍの厚みの熱可塑性樹脂フィルム８１の両面
に各々２０μｍの厚みの銅箔８２，８３が圧着されてい
る。一方の導電箔８２はエッチングされて所望形状のパ
ターンに加工され、固着電極８４と取り出し電極８５
ａ、８５ｂを形成する。固着電極８４は少なくとも半導
体チップ８８が載置できる大きさと形状を有しており、
この固着電極８４に隣接して少し離間して取り出し電極
８５ａ、８５ｂが複数個形成されている。他方の導電箔
８３もエッチングされて所望形状のパターンに加工さ
れ、固着電極８４と取り出し電極８５ａ、８５ｂと対向
する位置に接続電極８６、８６ａ、８６ｂを形成する。
接続電極８６、８６ａ、８６ｂはプリント基板にはんだ
付けできる大きさに形成され、はんだ付けの際にはんだ
ブリッジが形成されないように離間され、対応する固着
電極８４および取り出し電極８５ａ、８５ｂよりは小さ
く形成される。なお固着電極８４、取り出し電極８５
ａ、８５ｂおよび接続電極８６、８６ａ、８６ｂは電解
メッキによりその表面をニッケルメッキ層と金メッキ層
で被覆されており、導電ペーストとの接触抵抗を減少さ
せ、またボンディング細線の固着を可能にしている。Two conductive foils 82 and 83 which are separated by the resin film and electrically insulated are pressed on both surfaces of the thermoplastic resin film 81. As the conductive foil, an inexpensive copper foil having a small electric resistance is optimal. Specifically, copper foils 82 and 83 each having a thickness of 20 μm are pressure-bonded to both surfaces of a thermoplastic resin film 81 having a thickness of 50 μm. One conductive foil 82 is etched and processed into a desired shape pattern, and the fixed electrode 84 and the extraction electrode 85 are formed.
a and 85b are formed. The fixed electrode 84 has at least a size and a shape on which the semiconductor chip 88 can be mounted.
A plurality of extraction electrodes 85a and 85b are formed adjacent to the fixed electrode 84 and slightly apart therefrom. The other conductive foil 83 is also etched and processed into a pattern having a desired shape, and connection electrodes 86, 86a, 86b are formed at positions facing the fixed electrode 84 and the extraction electrodes 85a, 85b.
The connection electrodes 86, 86a, 86b are formed in a size that can be soldered to a printed circuit board, are separated so that a solder bridge is not formed during soldering, and are formed smaller than the corresponding fixed electrodes 84 and extraction electrodes 85a, 85b. Is done. Note that the fixed electrode 84 and the extraction electrode 85
The surfaces of the a and 85b and the connection electrodes 86, 86a and 86b are covered with a nickel plating layer and a gold plating layer by electrolytic plating, thereby reducing the contact resistance with the conductive paste and enabling the bonding of the fine bonding wires. .

【００２５】導電材８７は一方の導電箔８２で形成され
た固着電極８４、取り出し電極８５ａ、８５ｂと他方の
導電箔８３で形成された対応する接続電極８６、８６
ａ、８６ｂとを接続している。導電材８７としては銀ペ
ーストを用い、熱可塑性樹脂８１を加熱して軟化させて
導電材８７を貫通させている。従って予めビアホールを
設ける必要が無くなる。導電材８７を貫通させる位置は
図１（Ａ）（Ｃ）に破線丸印で示すように、固着電極８
４では取り出し電極８５ａ、８５ｂと離れた側の上下両
端近くに２個設け、取り出し電極８５ａ、８５ｂではほ
ぼ中央部に１個形成している。The conductive material 87 includes fixed electrodes 84 and lead electrodes 85a and 85b formed of one conductive foil 82 and corresponding connection electrodes 86 and 86 formed of the other conductive foil 83.
a and 86b. A silver paste is used as the conductive material 87, and the thermoplastic resin 81 is heated and softened to penetrate the conductive material 87. Therefore, it is not necessary to provide a via hole in advance. The position through which the conductive material 87 is penetrated is indicated by a broken-line circle in FIGS.
In No. 4, two electrodes are provided near the upper and lower ends on the side distant from the extraction electrodes 85a and 85b, and one is formed substantially at the center of the extraction electrodes 85a and 85b.

【００２６】半導体チップ８８は固着電極８４上にＡｇ
ペーストなどの導電ペースト８９により固着されてい
る。半導体チップ８８としては、バイポーラトランジス
タ、パワーＭＯＳＦＥＴ等の３端子素子又はダイオード
などの２端子素子が形成されているウエファーから供給
される。半導体チップ８８自体は、Ｎ＋／Ｎ型構造のよ
うに、裏面側に高濃度不純物層を有しており、該高濃度
層を介して、ダイオード素子で有ればアノード又はカソ
ードの一方の端子を、バイポーラ型トランジスタで有れ
ばコレクタ端子を、パワーＭＯＳＦＥＴで有ればドレイ
ン端子を導出する構造を有しているので、この高濃度層
が導電ペースト８９を介して固着電極８４にオーミック
接続される。The semiconductor chip 88 has Ag fixed on the fixed electrode 84.
It is fixed by a conductive paste 89 such as a paste. The semiconductor chip 88 is supplied from a wafer on which a three-terminal element such as a bipolar transistor or a power MOSFET or a two-terminal element such as a diode is formed. The semiconductor chip 88 itself has a high-concentration impurity layer on the back surface like an N + / N-type structure, and through the high-concentration layer, connects one terminal of an anode or a cathode if it is a diode element. In the case of a bipolar transistor, the collector terminal is provided, and in the case of a power MOSFET, the drain terminal is provided, so that this high-concentration layer is ohmically connected to the fixed electrode 84 via the conductive paste 89. .

【００２７】次に前記固着電極８４の前記半導体チップ
８８が設置された下に段差埋設絶縁物層を形成する。本
発明の特徴はこの段差埋設絶縁物層を形成することにあ
る。本発明では段差埋設絶縁物層としてレジスト層をも
ちいる。接続電極８６，８６ａ，８６ｂとほぼ同じ厚さ
にレジストを形成した後に、熱可塑性樹脂フィルム８１
に貼り付けて感光現像しレジスト層１２０を形成する。Next, a step buried insulator layer is formed below the fixed electrode 84 on which the semiconductor chip 88 is installed. The feature of the present invention resides in the formation of the step buried insulator layer. In the present invention, a resist layer is used as the step buried insulator layer. After a resist is formed to substantially the same thickness as the connection electrodes 86, 86a and 86b, the thermoplastic resin film 81 is formed.
To form a resist layer 120.

【００２８】半導体チップ８８の表面にはアルミ電極パ
ッド９０が形成され、電極パッド９０と取り出し電極８
５ａ、８５ｂとが、金線ボンディングワイヤ９１によっ
て電気接続される。電極パッド９０側に１ｓｔボンド、
取り出し電極８５ａ、８５ｂ側に２ｎｄボンドが打たれ
る。バイポーラトランジスタで有れば、取り出し電極８
５ａ、８５ｂはエミッタとベースに対応し、パワーＭＯ
ＳＦＥＴで有れば、ソースとゲートに対応する。An aluminum electrode pad 90 is formed on the surface of the semiconductor chip 88, and the electrode pad 90 and the extraction electrode 8 are formed.
5a and 85b are electrically connected by a gold wire bonding wire 91. 1st bond on the electrode pad 90 side,
A second bond is formed on the extraction electrodes 85a and 85b. If it is a bipolar transistor, the extraction electrode 8
5a and 85b correspond to the emitter and the base, respectively.
If it is an SFET, it corresponds to the source and the gate.

【００２９】熱可塑性樹脂フィルム８１の上面は、半導
体チップ８８、固着電極８４、取り付け電極８５ａ、８
５ｂおよびボンディングワイヤ９１とを被覆する絶縁樹
脂９２で封止される。絶縁樹脂９２は熱可塑性樹脂フィ
ルム８１と共にパッケージ外形を構成する。パッケージ
の周囲４側面は絶縁樹脂９２と熱可塑性樹脂フィルム８
１の切断面で形成され、パッケージの上面は平坦化した
絶縁樹脂層９２の表面、パッケージの下面は熱可塑性樹
脂フィルム８１の裏面側で形成される。絶縁樹脂９２は
一般的に用いられるエポキシ樹脂を用いる。The upper surface of the thermoplastic resin film 81 is provided with a semiconductor chip 88, a fixed electrode 84, and mounting electrodes 85a, 8a.
5b and the bonding wire 91 are sealed with an insulating resin 92. The insulating resin 92 forms a package outer shape together with the thermoplastic resin film 81. The four sides around the package are insulating resin 92 and thermoplastic resin film 8
1, the upper surface of the package is formed on the flattened surface of the insulating resin layer 92, and the lower surface of the package is formed on the back surface of the thermoplastic resin film 81. As the insulating resin 92, a commonly used epoxy resin is used.

【００３０】次に、図２を参照して支持基板８１の上面
に一方の導電箔８２から形成される固着電極８４および
取り出し電極８５ａ、８５ｂと、裏面に他方の導電箔８
３から形成される接続電極８６、８６ａ、８６ｂの関係
を説明する。Next, referring to FIG. 2, fixed electrode 84 and extraction electrodes 85a and 85b formed of one conductive foil 82 on the upper surface of support substrate 81, and the other conductive foil 8 on the back surface.
The relationship between the connection electrodes 86, 86a and 86b formed from 3 will be described.

【００３１】点線で囲んだ各搭載部１００は、例えば長
辺×短辺が０．９ｍｍ×０．８ｍｍの矩形形状を有して
おり、これらは互いに２０〜５０μｍの間隔を隔てて２
４行２４列の行列上に縦横に配置されている。前記間隔
は後の工程でのダイシングライン１０１となる。導電パ
ターンは、各搭載部１００内において固着電極８４と取
り出し電極８５ａ、８５ｂを形成し、これらのパターン
は各搭載部１００内において同一形状である。Each mounting portion 100 surrounded by a dotted line has, for example, a rectangular shape with a long side and a short side of 0.9 mm × 0.8 mm, which are spaced apart from each other by 20 to 50 μm.
They are arranged vertically and horizontally on a matrix of 4 rows and 24 columns. The interval becomes a dicing line 101 in a later step. The conductive pattern forms the fixed electrode 84 and the extraction electrodes 85a and 85b in each mounting portion 100, and these patterns have the same shape in each mounting portion 100.

【００３２】固着電極８４からは２本の連結部１０２が
連続したパターンで延長される。これらの線幅は固着電
極８４よりも狭い線幅で、例えば０．０７５ｍｍの線幅
で延在する。連結部１０２はダイシングライン１０１を
超えて隣の搭載部１００の取り出し電極８５ａ、８５ｂ
に連結するまで延在する。更に、固着電極８４から上下
方向に連結部１０３が、連結部１０２とは直行する方向
に延在され、ダイシングライン１０１を越えて隣の搭載
部１００の固着電極８４に連結するまで延在される。連
結部１０３は更に、搭載部１００周囲を取り囲む共通連
結部１０４に連結され、各搭載部１００の固着電極８４
と取り出し電極８５ａ、８５ｂとを電気的に共通接続す
る。From the fixed electrode 84, two connecting portions 102 are extended in a continuous pattern. These line widths are narrower than the fixed electrode 84 and extend with a line width of, for example, 0.075 mm. The connecting portion 102 extends beyond the dicing line 101 to the extraction electrodes 85a, 85b of the adjacent mounting portion 100.
Extend until connected to Further, the connecting portion 103 extends vertically from the fixed electrode 84 in a direction perpendicular to the connecting portion 102 and extends beyond the dicing line 101 until the connecting portion 103 is connected to the fixed electrode 84 of the adjacent mounting portion 100. . The connection portion 103 is further connected to a common connection portion 104 surrounding the periphery of the mounting portion 100, and the fixed electrode 84 of each mounting portion 100 is connected.
And the extraction electrodes 85a and 85b are electrically connected in common.

【００３３】熱可塑性樹脂フィルム８１の裏面側には、
第１と第２の接続電極８６、８６ａ、８６ｂを形成す
る。これらの接続電極８６、８６ａ、８６ｂは、搭載部
１００の端から０．０５〜０．１ｍｍ程度後退されたパ
ターンで形成されている。両導電箔８２，８３を離間す
る熱可塑性樹脂フィルム８１は丸印で図示する位置で導
電材８７で貫通されて電気的接続をされている。具体的
には固着電極８４と第１の接続電極８６は上下に２個設
けた導電材８７で接続され、各々の取り出し電極８５
ａ、８５ｂは第２の接続電極８６ａ、８６ｂとその中央
部に設けた導電材８７で接続されている。従って各電極
は導電材８７を介して、熱可塑性樹脂フィルム８１の表
面側の共通連結部１０４に接続される。従って、ダイシ
ング後にそれぞれが細い連結部１０３，１０４を切断さ
れることで個々の電極として機能する。全パターンが電
気的に共通接続されるので、電解メッキ法により各電極
表面をニッケルメッキ層および金メッキ層で被覆するこ
とが可能となる。On the back side of the thermoplastic resin film 81,
First and second connection electrodes 86, 86a, 86b are formed. These connection electrodes 86, 86a, 86b are formed in a pattern recessed from the end of the mounting portion 100 by about 0.05 to 0.1 mm. The thermoplastic resin film 81 separating the two conductive foils 82 and 83 is penetrated by a conductive material 87 at a position shown by a circle to be electrically connected. Specifically, the fixed electrode 84 and the first connection electrode 86 are connected to each other by two conductive materials 87 provided on the upper and lower sides.
a and 85b are connected to the second connection electrodes 86a and 86b by a conductive material 87 provided at the center thereof. Therefore, each electrode is connected to the common connection portion 104 on the front surface side of the thermoplastic resin film 81 via the conductive material 87. Therefore, each of the thin connecting portions 103 and 104 is cut after dicing to function as an individual electrode. Since all the patterns are electrically connected in common, it is possible to cover the surface of each electrode with a nickel plating layer and a gold plating layer by an electrolytic plating method.

【００３４】熱可塑性樹脂８１はセラミックやガラスエ
ポキシ基板に比較すると軟質であるので、ボンディング
する際にボンディング圧力が発散する欠点がある。これ
を防止するために本発明のレジスト層１２０が効果的で
ある。前記レジスト層１２０がボンディング時に軟質な
熱可塑性樹脂フィルム８１を裏面から支えるので半導体
チップの上下の沈みを抑えることができボンディング細
線のループ形状を安定化できる。Since the thermoplastic resin 81 is softer than a ceramic or glass epoxy substrate, there is a disadvantage that a bonding pressure is diverged during bonding. To prevent this, the resist layer 120 of the present invention is effective. Since the resist layer 120 supports the soft thermoplastic resin film 81 from the back surface at the time of bonding, the sinking of the semiconductor chip in the upper and lower directions can be suppressed, and the loop shape of the bonding fine wire can be stabilized.

【００３５】上述した本発明による半導体装置は固着電
極８４の半導体チップ８８が載置された下に段差埋設絶
縁物層としてレジスト層１２０を形成することにより、
熱可塑性に起因する軟質性の障害を取り除くことが可能
である。しかも熱可塑性樹脂フィルムとして液晶ポリマ
ーを用いることによる数々の利点も有している。電気特
性では、誘電率において１ＭＨ（２０℃、９６Ｈ、６５
％ＲＨ）で３．０，１ＧＨｚで２．９であり、ガラスエ
ポキシ基板で誘電率が１ＭＨｚで４．７〜５．０と比較
するとかなり優れている。また表面抵抗は１４×１０13
Ωであり、ポリイミド樹脂の１．１×１０13Ωと比較し
ても大幅に絶縁性が高い。これらから本発明の支持基板
は極めて高周波領域での特性が良好であることが明らか
である。更に耐折性についてはＪＩＳ Ｃ５０１６評価
規格でＲ＝０．３８ｍｍで４４回もあり、同一条件でポ
リイミド樹脂は３３回と比較すれば細線の断線が少な
い。更に吸水率０．０４％であり、湿度下での絶縁性は
良好であり、ガスバリヤー性も高く、ノンハロゲン、ス
ルーホールメッキレスと環境調和も優れている。In the above-described semiconductor device according to the present invention, the resist layer 120 is formed as a step buried insulator layer under the fixed electrode 84 on which the semiconductor chip 88 is mounted.
It is possible to remove soft obstacles due to thermoplasticity. Moreover, there are many advantages of using a liquid crystal polymer as the thermoplastic resin film. In terms of electrical characteristics, the dielectric constant is 1 MH (20 ° C., 96H, 65
% RH) of 3.0 and 2.9 at 1 GHz, which is considerably better than that of a glass epoxy substrate having a dielectric constant of 4.7 to 5.0 at 1 MHz. The surface resistance is 14 × 10 13
Ω, which is much higher in insulation than the polyimide resin of 1.1 × 10 13 Ω. From these, it is apparent that the support substrate of the present invention has excellent characteristics in an extremely high frequency range. Further, the folding resistance is 44 times at R = 0.38 mm according to the JIS C5016 evaluation standard, and under the same conditions, the number of breaks in the fine wire is smaller than that of the polyimide resin 33 times. Furthermore, it has a water absorption of 0.04%, good insulation under humidity, high gas barrier properties, and is environmentally friendly with no halogen and no through-hole plating.

【００３６】続いて本発明の半導体装置の製造方法を図
３から図８を参照して説明する。Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

【００３７】第１工程：図３（Ａ）（Ｂ）（Ｃ）参照 本工程ではまず支持基板８０を形成することにある。図
３（Ａ）に示すように、第１の導電箔８２、熱可塑性樹
脂から成るフィルム８１および第２の導電箔８３を準備
する。第１および第２の導電箔８２,８３は安価で電気
抵抗の低い銅箔が適しており、２０μｍ厚で熱可塑性樹
脂から成るフィルム８１と当接する面を凹凸に粗面化し
て固着強度を高めるようにしている。熱可塑性樹脂フィ
ルム８１としては液晶ポリマーが最適であり、本実施例
では全芳香族ポリエステル系液晶ポリマー（商品名ベク
トラ）を用いた。第２の導電箔８３表面には導電材８７
である銀ぺーストを所定の位置にスクリーン印刷して熱
可塑性樹脂フィルム５１を貫通する高さ（例えば５０μ
ｍ以上）にバンプ１１０を予め形成しておく。First Step: See FIGS. 3A, 3B and 3C In this step, first, a support substrate 80 is formed. As shown in FIG. 3A, a first conductive foil 82, a film 81 made of a thermoplastic resin, and a second conductive foil 83 are prepared. As the first and second conductive foils 82 and 83, an inexpensive and low-resistance copper foil is suitable, and the surface contacting the film 81 made of a thermoplastic resin having a thickness of 20 μm is roughened into irregularities to increase the bonding strength. Like that. As the thermoplastic resin film 81, a liquid crystal polymer is most suitable. In this example, a wholly aromatic polyester liquid crystal polymer (Vectra) was used. A conductive material 87 is provided on the surface of the second conductive foil 83.
Silver paste is screen-printed at a predetermined position and a height (for example, 50 μm) penetrating the thermoplastic resin film 51 is used.
m or more) is formed in advance.

【００３８】第１および第２の導電箔８２，８３と熱可
塑性樹脂フィルム８１は最初は幅１ｍのロール状で供給
され、多数の支持基板８０を形成した後に個別の支持基
板８０に分離される。この個別の支持基板８０が図２に
示すものであり、この個別の支持基板８０にも２４行２
４列に５７６個の半導体素子の搭載部１００が形成され
ることになる。The first and second conductive foils 82 and 83 and the thermoplastic resin film 81 are initially supplied in the form of a roll having a width of 1 m, and after forming a large number of support substrates 80, they are separated into individual support substrates 80. . This individual support substrate 80 is shown in FIG.
The mounting portion 100 of 576 semiconductor elements is formed in four rows.

【００３９】次に、図３（Ｂ）に示すように第１の導電
箔８２、熱可塑性樹脂フィルム８１および第２の導電箔
８３を熱圧着して一体化された支持基板８０を形成す
る。この熱圧着時に熱可塑性樹脂フィルム８１は加熱さ
れて軟化するので、第２の導電箔８３に付着された導電
材８７となるバンプ１１０は熱可塑性樹脂フィルム８１
を貫通し第１の導電箔８２まで到達する。熱可塑性樹脂
フィルム８１として液晶ポリマーを用いた場合は、加熱
温度３００℃、圧着圧力４．４〜８．７ｋＰａで真空熱
圧着を行う。このとき液晶ポリマーはガラス転移点に近
くかなり軟化しているので、導電ペーストで形成された
先端が尖ったバンプ１１０がこの液晶ポリマーを貫通す
る。なおこのときに接着剤は使用していない。Next, as shown in FIG. 3B, the first conductive foil 82, the thermoplastic resin film 81, and the second conductive foil 83 are thermocompression-bonded to form an integrated support substrate 80. During this thermocompression bonding, the thermoplastic resin film 81 is heated and softened, so that the bumps 110 serving as the conductive material 87 attached to the second conductive foil 83 are formed of the thermoplastic resin film 81.
And reaches the first conductive foil 82. When a liquid crystal polymer is used as the thermoplastic resin film 81, vacuum thermocompression is performed at a heating temperature of 300 ° C. and a compression pressure of 4.4 to 8.7 kPa. At this time, since the liquid crystal polymer is considerably softened near the glass transition point, a bump 110 having a sharp tip formed of a conductive paste penetrates the liquid crystal polymer. At this time, no adhesive was used.

【００４０】更に、図３（Ｃ）に示すように熱圧着を完
了すると、第１の導電箔８２、熱可塑性樹脂フィルム８
１、第２の導電箔８３は密着して一体化されるので、導
電ペーストよりなるバンプ１１０も潰されて０．１５ｍ
ｍの径の柱状の導電材８７を形成する。Further, as shown in FIG. 3C, when the thermocompression bonding is completed, the first conductive foil 82, the thermoplastic resin film 8
Since the first and second conductive foils 83 are closely attached and integrated, the bumps 110 made of the conductive paste are also crushed to 0.15 m.
A columnar conductive material 87 having a diameter of m is formed.

【００４１】第２工程：図４（Ａ）（Ｂ）参照 斯かる支持基板８０の両主面は第１および第２の導電箔
８２，８３で被覆されている。図４（Ａ）示すように、
この第１の導電箔８２上には所定の形状の固着電極８
４、取り出し電極８５上を覆うようにレジスト膜１１１
を付着し、第２の導電箔８３上にも所定の形状の第１お
よび第２の接続電極８６、８６ａ、８６ｂ上を覆うよう
にレジスト膜１１１を付着する。レジスト膜１１１とし
ては液状のレジスト材料をスピンコートして感光現像し
ても良いし、フィルム状のレジスト材料を貼り付けて感
光現像しても良い。Second step: See FIGS. 4A and 4B Both main surfaces of the support substrate 80 are covered with first and second conductive foils 82 and 83. As shown in FIG.
The fixed electrode 8 having a predetermined shape is formed on the first conductive foil 82.
4. A resist film 111 is formed to cover the extraction electrode 85.
And a resist film 111 is also attached on the second conductive foil 83 so as to cover the first and second connection electrodes 86, 86a, 86b having a predetermined shape. As the resist film 111, a liquid resist material may be spin-coated and subjected to photosensitive development, or a film-shaped resist material may be attached and subjected to photosensitive development.

【００４２】続いてレジスト膜１１１をマスクとして第
１および第２の導電箔８２，８３を塩化第２鉄溶液を用
いて化学的にエッチングして、第１の導電箔８２で固着
電極８４、取り出し電極８５ａ、８５ｂを形成し、第２
の導電箔８３で第１および第２の接続電極８６、８６
ａ、８６ｂを形成する。これらの電極の具体的な形状は
すでに図２（Ａ）（Ｂ）で説明しているので、その部分
を参照されたい。これらの電極は全てが連結電極１０
２，１０３や導電材８７で電気的に接続されているの
で、電解メッキによりこれらの電極上に金メッキの下地
となるニッケルメッキ層（５μｍ以上）とその上に金メ
ッキ層（０．５μｍ以上）を形成している。Subsequently, using the resist film 111 as a mask, the first and second conductive foils 82 and 83 are chemically etched using a ferric chloride solution, and the fixed electrode 84 is taken out by the first conductive foil 82. Forming electrodes 85a and 85b,
First and second connection electrodes 86, 86
a and 86b are formed. The specific shapes of these electrodes have already been described with reference to FIGS. 2A and 2B, so please refer to those portions. These electrodes are all connected electrodes 10
2, 103 and a conductive material 87, a nickel plating layer (5 .mu.m or more) serving as a base for gold plating and a gold plating layer (0.5 .mu.m or more) on these electrodes by electrolytic plating. Has formed.

【００４３】続いて第２の接続電極８６と８６ａ及び８
６ｂとの離間に段差埋設絶縁物層を形成する。本発明で
は段差埋設絶縁物層としてレジスト層１２０を用いる。
斯かるレジスト層１２０を第２の接続電極８６、８６
ａ、８６ｂとほぼ同じ厚さに形成し、熱可塑性樹脂フィ
ルム８１にスクリーン印刷する。Subsequently, the second connection electrodes 86, 86a and 8
A step buried insulator layer is formed at a distance from the insulating layer 6b. In the present invention, the resist layer 120 is used as the step buried insulator layer.
The resist layer 120 is connected to the second connection electrodes 86, 86.
a and 86b are formed to have substantially the same thickness, and are screen-printed on the thermoplastic resin film 81.

【００４４】第３工程：図５参照 上述したように各電極を形成した支持基板８０の各搭載
部１００毎に、半導体チップ８８をダイボンドする。半
導体チップ８８は固着電極８４表面にＡｇペーストなど
の導電ペースト８９によって固着される。導電ペースト
８９は個別の支持基板８０の固着電極８４上にスクリー
ン印刷で付着された後、半導体チップ８８を載置して、
還元雰囲気中の電気炉内で熱可塑性樹脂フィルムのガラ
ス転移点２０５℃以下の約１５０℃の温度で約３０分間
硬化させる。Third step: see FIG. 5 A semiconductor chip 88 is die-bonded to each mounting portion 100 of the support substrate 80 on which the electrodes are formed as described above. The semiconductor chip 88 is fixed to the surface of the fixed electrode 84 by a conductive paste 89 such as an Ag paste. After the conductive paste 89 is attached by screen printing on the fixed electrodes 84 of the individual support substrates 80, the semiconductor chip 88 is placed thereon,
The thermoplastic resin film is cured in an electric furnace in a reducing atmosphere at a temperature of about 150 ° C. below a glass transition point of 205 ° C. for about 30 minutes.

【００４５】第４工程：図６参照 半導体チップ８８の電極パッド９０と取り出し電極８５
ａ、８５ｂとを各々金などのボンディングワイヤ９１で
接続する。金線によりボールボンドをする場合は、支持
基板８０を１５０℃に加熱して半導体チップ８８の電極
パッド９０に金線の一端に形成したボール部分を熱圧着
し、多端を取り出し電極８５ａ、８５ｂに熱圧着する。
この際、レジスト層１２０の働きで半導体チップ８８上
下の沈みを抑えることができボンディング細線のループ
形状を安定化できる。Fourth Step: See FIG. 6 The electrode pads 90 of the semiconductor chip 88 and the extraction electrodes 85
a and 85b are connected by bonding wires 91 such as gold. In the case of performing ball bonding with a gold wire, the supporting substrate 80 is heated to 150 ° C., and a ball portion formed at one end of the gold wire is thermocompression-bonded to the electrode pad 90 of the semiconductor chip 88, and multiple ends are taken out to the electrodes 85a and 85b. Thermocompression bonding.
At this time, the upper and lower sinks of the semiconductor chip 88 can be suppressed by the function of the resist layer 120, and the loop shape of the bonding fine wire can be stabilized.

【００４６】第５工程：図７（Ａ）（Ｂ）（Ｃ）参照 支持基板８０の各載置部に半導体チップ８８のダイボン
ドとボンディング細線９１による接続が終了すると、絶
縁樹脂９２により全体のモールドを行う。本工程では支
持基板８０の裏面に露出する接続電極８６、８６ａ、８
６ｂを除き、半導体チップ８８、固着電極８４、取り出
し電極８５ａ、８５ｂおよびボンディング細線９１をエ
ポキシ系樹脂９２で被覆する。Fifth Step: See FIGS. 7A, 7B and 7C When the die bonding of the semiconductor chip 88 and the connection by the fine bonding wires 91 to the mounting portions of the support substrate 80 are completed, the entire molding is performed by the insulating resin 92. I do. In this step, the connection electrodes 86, 86a, 8 exposed on the back surface of the support substrate 80
Except for 6b, the semiconductor chip 88, the fixed electrode 84, the extraction electrodes 85a and 85b, and the thin bonding wires 91 are covered with an epoxy resin 92.

【００４７】すなわち、図７（Ａ）に示すように、支持
基板８０の上方に移送したディスペンサ（図示せず）か
ら所定量のエポキシ系液体樹脂を滴下（ポッティング）
し、すべての半導体チップ８８を共通の絶縁樹脂層９２
で被覆する。液体樹脂として例えばＣＶ５７６ＡＮ（松
下電工製）を用いた。滴下した液体樹脂は比較的粘性が
高く、表面張力を有しているので、その表面が湾曲す
る。That is, as shown in FIG. 7A, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the support substrate 80.
Then, all the semiconductor chips 88 are connected to a common insulating resin layer 92.
Cover with. For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved.

【００４８】次に、図７（Ｂ）に示すように、絶縁樹脂
層９２の湾曲した表面を、平坦面に加工する。加工する
には、樹脂が硬化する前に平坦な成形部材を押圧して平
坦面に加工する手法と、滴下した樹脂層９２を１８０℃
で数時間の熱処理（キュア）にて硬化させた後に、湾曲
面を例えばダイシングブレードで研削することによって
平坦面に加工する手法とが考えられる。この工程では、
絶縁樹脂層９２の表面が支持基板８０から０．３〜１．
０ｍｍの高さに揃うように、表面を削る。平坦面は、少
なくとも最も外側に位置する半導体チップ８８を個別半
導体装置に分離したときに、規格化したパッケージサイ
ズの樹脂外形を構成できるように、その端部まで拡張す
る。Next, as shown in FIG. 7B, the curved surface of the insulating resin layer 92 is processed into a flat surface. In order to process the resin, a flat molding member is pressed before the resin is cured to form a flat surface.
After curing by heat treatment (curing) for several hours, a method of processing the curved surface into a flat surface by grinding the curved surface with, for example, a dicing blade can be considered. In this step,
The surface of the insulating resin layer 92 is 0.3 to 1.
Grind the surface to make it equal to 0mm height. The flat surface is extended to its end so that at least when the outermost semiconductor chip 88 is separated into individual semiconductor devices, a resin outer shape having a standardized package size can be formed.

【００４９】更に図７（Ｃ）に示すように、搭載部１０
０毎に絶縁樹脂層９２と支持基板８０を切断して各々の
半導体素子に分離する。切断にはダイシング装置を用
い、ダイシングライン１０１に沿って絶縁樹脂層９２と
支持基板８０とをダイシングブレード１１５で同時に切
断することにより、搭載部１００毎に分割した半導体装
置を形成する。この工程で切断された接続部１０２，１
０３の残りが、図１で示した接続部１０２、１０３であ
る。ダイシング工程においては支持基板８０の裏面側に
ブルーシート（たとえば、商品名：ＵＶシート、リンテ
ック株式会社製）を貼り付け、前記ダイシングブレード
がブルーシートの表面に到達するような切削深さで切断
する。Further, as shown in FIG.
At every 0, the insulating resin layer 92 and the support substrate 80 are cut and separated into respective semiconductor elements. A dicing device is used for the cutting, and the insulating resin layer 92 and the support substrate 80 are simultaneously cut by the dicing blade 115 along the dicing line 101, thereby forming a semiconductor device divided for each mounting portion 100. Connections 102, 1 disconnected in this step
The rest of 03 are the connection units 102 and 103 shown in FIG. In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Corporation) is attached to the back side of the support substrate 80, and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet. .

【００５０】図８は、上述の工程によって形成された各
半導体素子を示す斜視図である。FIG. 8 is a perspective view showing each semiconductor element formed by the above-described steps.

【００５１】[0051]

【発明の効果】本発明によれば、第１に２枚の導電箔８
２、８３と導電材８７で各電極を形成するので、従来用
いていたタングステン等の高価な金属ペーストが不要と
なり、極めて安価な実装構造を実現できる利点を有す
る。また導電箔８２，８３として銅箔を用いると電気抵
抗も低くでき、飽和オン抵抗も大幅に改善できる。According to the present invention, first, two conductive foils 8 are formed.
Since each electrode is formed by the electrodes 2, 83 and the conductive material 87, an expensive metal paste such as tungsten conventionally used is not required, and there is an advantage that an extremely inexpensive mounting structure can be realized. When copper foil is used as the conductive foils 82 and 83, the electric resistance can be reduced and the saturation on-resistance can be greatly improved.

【００５２】第２に２枚の導電箔８２，８３の層間絶縁
膜として熱可塑性樹脂フィルム８１を用いているので、
ビアホールの形成やスルーホールメッキ等を不要にで
き、導電材８７を熱可塑性樹脂フィルム８１を熱圧着時
に貫通させるだけで両導電箔８２，８３で形成した各電
極を電気的に接続できる極めて簡単な実装構造を提供で
きる。このためにノンハロゲン、スルーホールめっきレ
スで極めて環境に優しい実装構造となる。Second, since the thermoplastic resin film 81 is used as an interlayer insulating film between the two conductive foils 82 and 83,
The formation of via holes and plating of through holes are unnecessary, and the electrodes formed by the conductive foils 82 and 83 can be electrically connected only by penetrating the conductive material 87 at the time of thermocompression bonding of the thermoplastic resin film 81. Provide mounting structure. For this reason, a non-halogen, no through-hole plating and extremely environmentally friendly mounting structure is obtained.

【００５３】第３に本発明の支持基板８０は銅箔が約２
０μｍ、熱可塑性樹脂フィルム８１が約５０μｍで形成
されるので、全体では厚みが高々９０μｍにでき、従来
のセラミック基板の厚みがセラミックだけで０．２５ｍ
ｍから０．３５ｍｍもあり、約１／３に薄型化できる利
点を有する。このため完成された半導体装置の薄型化に
も大いに貢献でき、１ｍｍ×１ｍｍ以下の極めて微細な
トランジスタチップ等の実装構造には最適である。Third, the supporting substrate 80 of the present invention is made of a copper foil of about 2
Since the thickness of the thermoplastic resin film 81 is about 50 μm, the thickness can be as high as 90 μm as a whole.
m to 0.35 mm, which is advantageous in that the thickness can be reduced to about 1/3. For this reason, it can greatly contribute to the reduction in thickness of the completed semiconductor device, and is most suitable for a mounting structure of an extremely fine transistor chip of 1 mm × 1 mm or less.

【００５４】第４に本発明で用いた熱可塑性樹脂フィル
ム８１は、高周波領域における誘電率はポリイミド樹脂
と同じであり、また表面抵抗はガラスエポキシ基板と同
等であり、良好な高周波特性を得られる。Fourth, the thermoplastic resin film 81 used in the present invention has the same dielectric constant in the high-frequency region as that of the polyimide resin and the same surface resistance as that of the glass epoxy substrate, so that good high-frequency characteristics can be obtained. .

【００５５】第５に本発明で用いたレジスト層１２０
は、熱可塑性樹脂フィルム８１の熱可塑性による軟質さ
によるボンディング時の半導体チップ８８の上下の沈み
を抑えることができボンディング細線のループ形状を安
定化できる利点を有する。Fifth, the resist layer 120 used in the present invention
Has the advantage that the vertical sinking of the semiconductor chip 88 during bonding due to the softness due to thermoplasticity of the thermoplastic resin film 81 can be suppressed, and the loop shape of the bonding fine wire can be stabilized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置を説明する（Ａ）平面図、
（Ｂ）断面図、（Ｃ）裏面図である。FIG. 1A is a plan view illustrating a semiconductor device of the present invention,
(B) is a sectional view, (C) is a back view.

【図２】本発明に用いる支持基板を説明する（Ａ）平面
図、（Ｂ）裏面図である。FIGS. 2A and 2B are a plan view and a rear view illustrating a support substrate used in the present invention. FIGS.

【図３】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図４】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図５】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 5 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図６】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

【図７】本発明の半導体装置の製造方法を説明する断面
図である。FIG. 7 is a sectional view illustrating the method for manufacturing a semiconductor device according to the present invention;

【図８】本発明の半導体装置を説明する斜視図である。FIG. 8 is a perspective view illustrating a semiconductor device of the present invention.

【図９】従来の半導体装置を説明する断面図である。FIG. 9 is a cross-sectional view illustrating a conventional semiconductor device.

【図１０】従来の半導体装置を説明する（Ａ）平面図
（Ｂ）断面図（Ｃ）斜視図である。10A is a plan view, FIG. 10B is a cross-sectional view, and FIG. 10C is a perspective view illustrating a conventional semiconductor device.

【図１１】従来の半導体装置を説明する（Ａ）平面図
（Ｂ）断面図（Ｃ）裏面図である。11A is a plan view, FIG. 11B is a cross-sectional view, and FIG.

【図１２】従来の半導体装置を説明する（Ａ）平面図
（Ｂ）裏面図（Ｃ）断面図である。12A is a plan view, FIG. 12B is a rear view, and FIG. 12C is a cross-sectional view illustrating a conventional semiconductor device.

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 軟質の樹脂で離間された相対向する導電
箔を有し、一方の導電箔を所望形状に形成された固着電
極および取り出し電極を設け、他方の導電箔で形成され
た前記固着電極および取り出し電極に対応して対向する
接続電極を設け、かつ前記固着電極および取り出し電極
と対応する前記接続電極とを電気的に接続し前記樹脂を
貫通する導電材とを有する支持基板と、前記固着電極上
に固着された半導体素子と、前記半導体素子の電極と前
記取り出し電極とを接続するボンディング細線と、前記
接続電極を露出して前記半導体素子、固着電極、取り出
し電極および前記ボンディング細線を少なくとも被覆す
る絶縁樹脂とを具備する半導体装置において、 前記樹脂上の前記固着電極と前記取り出し電極間に段差
埋設絶縁物層を設けたことを特徴とする半導体装置。1. A fixed resin and a take-out electrode each having a conductive foil opposed to each other and separated by a soft resin, wherein one of the conductive foils is provided with a fixed electrode and a take-out electrode, and the other is formed of the other conductive foil. A support substrate having a connection electrode facing the electrode and the extraction electrode, and a conductive material that electrically connects the fixed electrode and the extraction electrode and the corresponding connection electrode and penetrates the resin; A semiconductor element fixed on the fixed electrode, a bonding thin wire connecting the electrode of the semiconductor element and the extraction electrode, and at least the semiconductor element, the fixed electrode, the extraction electrode and the bonding thin wire exposing the connection electrode. A semiconductor device comprising an insulating resin to be coated, wherein a step-buried insulator layer is provided between the fixed electrode and the extraction electrode on the resin. The semiconductor device according to claim. 【請求項２】 前記導電箔として銅箔を用いたことを特
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a copper foil is used as said conductive foil. 【請求項３】 前記銅箔表面をニッケルおよび金のメッ
キ層で被覆することを特徴とする請求項２記載の半導体
装置。3. The semiconductor device according to claim 2, wherein said copper foil surface is covered with a nickel and gold plating layer. 【請求項４】 前記樹脂として熱可塑性の液晶ポリマー
を用いたことを特徴とする請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein a thermoplastic liquid crystal polymer is used as said resin. 【請求項５】 前記導電材として銀ペーストを用いたこ
とを特徴とする請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein a silver paste is used as said conductive material. 【請求項６】 前記段差埋設絶縁物層としてレジスト層
を用いたことを特徴とする請求項１記載の半導体装置。6. The semiconductor device according to claim 1, wherein a resist layer is used as said step buried insulator layer. 【請求項７】 前記固着電極の前記半導体素子が設置さ
れた下に前記段差埋設絶縁物層を設けたことを特徴とす
る請求項１記載の半導体装置。7. The semiconductor device according to claim 1, wherein the step-buried insulator layer is provided under the fixed electrode on which the semiconductor element is provided.
JP2000373085A 2000-12-07 2000-12-07 Semiconductor device Pending JP2002176120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000373085A JP2002176120A (en) 2000-12-07 2000-12-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000373085A JP2002176120A (en) 2000-12-07 2000-12-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2002176120A true JP2002176120A (en) 2002-06-21

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005123268A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Optical element and its manufacturing method, packaging structure and packaging method of optical element and packaging substrate, optical module, and optical transmission device
JP2006196734A (en) * 2005-01-14 2006-07-27 Renesas Technology Corp Semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005123268A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Optical element and its manufacturing method, packaging structure and packaging method of optical element and packaging substrate, optical module, and optical transmission device
JP4686967B2 (en) * 2003-10-14 2011-05-25 セイコーエプソン株式会社 Manufacturing method of optical element
JP2006196734A (en) * 2005-01-14 2006-07-27 Renesas Technology Corp Semiconductor device and its manufacturing method

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