JP2002270814A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a small-sized package having a curtailed mounting area is obtained, while the cost in a manufacturing process is reduced largely, and to provide its manufacturing method. SOLUTION: A semiconductor element is formed to a silicon semiconductor substrate, and a trench-type collector extracting electrode buried to the silicon semiconductor substrate is formed. Each pad electrode is brought into contact with base and emitter electrodes, and the collector extracting electrode is formed by a multi layer electrode structure, and external connecting electrodes brought into contact with each pad electrode and composed of solder balls are formed. Accordingly, the semiconductor device optimal for mounting an extremely thin type fine semiconductor chip at a low cost and its manufacturing method are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a semiconductor element is formed on a silicon semiconductor substrate and the semiconductor element is assembled using an extraction electrode provided on the silicon semiconductor substrate, and the semiconductor device. It relates to a manufacturing method.

[0002]

2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor element separated by dicing from a wafer is fixed to a lead frame, and the semiconductor element is sealed with a mold and transfer molding by resin injection. A process of cutting and separating each semiconductor device is performed. In the semiconductor device obtained by this method, as shown in FIG. 11, a periphery of the semiconductor element 51 is covered with a resin layer 52, and a lead terminal 53 for external connection is led out from a side of the resin layer 52. (For example, JP-A-05-129473).

[0003] This structure reduces the external dimensions and the mounting area due to the protrusion of the lead terminals 53 outside the resin layer 52, the problem of the processing accuracy of the lead frame and the problem of the positioning accuracy with the mold. Was seeing the limits.

[0004] In recent years, wafer scale CSPs (chip size packages) capable of reducing the outer dimensions to dimensions similar to or close to the size of a semiconductor chip have begun to attract attention. This is described with reference to FIG.
The semiconductor wafer 61 is subjected to various pretreatments such as diffusion to form a large number of semiconductor elements 62, and as shown in FIG. 12B, the upper portion of the semiconductor wafer 61 is covered with the resin layer 63 and the surface of the resin layer 63 is covered. The electrode 64 for external connection is led out, and then the dicing line 60 of the semiconductor wafer 61 is formed.
The semiconductor element 62 is divided along the line to obtain a completed product as shown in FIG. The resin layer 63 only covers the front surface (the back surface may be covered) of the semiconductor element 62, and the silicon semiconductor substrate is exposed on the side wall of the semiconductor element 62. The electrode 64 is electrically connected to an integrated circuit network formed below the resin layer 63, and the semiconductor device is mounted by adhering the electrode 64 to a conductive pattern formed on a mounting substrate. .

[0005] Such a semiconductor device has the advantage that the package size of the device is equivalent to the chip size of the semiconductor element, and the device can be opposed to the mounting substrate, so that the mounting area can be greatly reduced. Further, there is an advantage that the cost associated with the post-process can be significantly reduced. Therefore, chips having a chip size of less than 1 mm square are mounted as shown in FIGS. 13A, 13B and 13C.

In the drawing, reference numeral 71 denotes an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are superposed to have a thickness of 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process. Has a rectangular shape with a long side × a short side of about 1.0 mm × 0.8 mm.

On the surface of the insulating substrate 71, a conductive pattern is formed by printing a metal paste such as tungsten and gold plating on the metal paste by an electrolytic plating method to form an island portion 72 and electrode portions 73a and 73b. are doing. The semiconductor element 75 is fixed on the island portion 72 with a conductive adhesive such as an Ag paste.

An aluminum electrode pad 76 is formed on the surface of the semiconductor element 75, and the electrode pad 76 and the electrode portions 73a and 73 are formed.
3b is electrically connected by a bonding wire 77. A first bond is formed on the electrode pad 76 side, and a second bond is formed on the electrode section 73 side. In the case of a bipolar transistor, the electrode portions 73a and 73b correspond to an emitter and a base, and in the case of a power MOSFET, they correspond to a source and a gate.

A first external connection electrode 78 and second external connection electrodes 79a and 79b are also formed on the back side of the insulating substrate 71 by the same gold plating layer. A circular first via hole 80 and a second
Are formed, and the inside of each via hole 80, 81a, 81b is buried with a conductive material such as tungsten. The material is buried with a material having excellent electrical and thermal conductivity. The via hole 8
0, 81a and 81b, the island portion 72 and the first
The external connection electrode 78 and the electrode portions 73a and 73b and the second
Are electrically connected to the external connection electrodes 79a and 79b, respectively. The first external connection electrodes 78 are, for example, collector electrodes, and the second external connection electrodes 79a, 79b are, for example, base and emitter electrodes.

The upper part of the insulating substrate 71 is covered with a resin layer for sealing the semiconductor element 75 and the bonding wires 77. The resin layer forms the package outline together with the insulating substrate 71. The four sides around the package are a resin layer and an insulating substrate 71.
The upper surface of the package is formed on the flattened surface of the resin layer, and the lower surface of the package is formed on the back surface side of the insulating substrate 71.

[0011]

However, there are various problems in the mounting structure shown in FIG. First
In addition, since an expensive substrate material such as ceramic or glass epoxy is used and an expensive metal paste such as tungsten is used, it cannot be said that the mounting structure is low cost. Second
In addition, in order to connect electrodes and the like on both sides, a via hole penetrating the insulating substrate is indispensable, and the processing accuracy is 0.15
The limit of about mm is an obstacle to further miniaturization. Third, since the inside of the via hole is filled with a metal paste, workability is extremely poor, which causes an increase in cost. Fourth, the process is divided into a pre-process for forming a semiconductor device and a post-process for assembling a semiconductor device using an insulating substrate.
(Turn Around Time) is long, and the manufacturing cost is high.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems, and has an opposite conductivity type base region provided on a semiconductor substrate serving as a one conductivity type collector region; A plurality of emitter regions of one conductivity type provided on the surface of the base region, a trench provided in the collector region outside the base region, and a collector extraction electrode made of a semiconductor material embedded in the trench,
A base electrode, an emitter electrode, and a collector electrode that respectively contact the base region, the emitter region, and the collector extraction electrode; a first insulating film that covers the base electrode, the emitter electrode, and the collector electrode; It has a base external connection electrode, an emitter external connection electrode, and a collector external connection electrode connected to the collector electrode, and the collector electrode can be taken out from the semiconductor substrate surface, so that the chip size can be reduced in size and thickness. Become.

A step of forming a semiconductor element region comprising a base region of the opposite conductivity type and a plurality of emitter regions of the one conductivity type on a semiconductor substrate serving as a collector region of one conductivity type; and forming the collector region outside the base region. Forming a trench in the trench, forming a collector extraction electrode made of a semiconductor material embedded in the trench, and a base electrode, an emitter electrode, and a collector connected to the base region, the emitter region, and the collector extraction electrode, respectively. Forming an electrode; and covering the entire surface with a first insulating film and forming a base external connection electrode, an emitter external connection electrode, and a collector external connection electrode connected to the base electrode, the emitter electrode, and the collector electrode, respectively. Dicing the semiconductor substrate to separate into individual semiconductor elements; Characterized by comprising, those that can provide a method of manufacturing a semiconductor device which realizes a chip size package in Uefareberu omitting the assembly process.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 10 by taking an NPN planar transistor as an example.

FIG. 1 shows the structure of a semiconductor device according to the present invention.

The NPN planar transistor has a collector region 1, a base region 2, an emitter region 3, a trench 4, a collector extraction electrode 6, a base electrode 7, an emitter electrode 8, a collector electrode 9, First and second insulating films 10, base pad electrode 11, emitter pad electrode 12, collector pad electrode 13, base external connection electrode 15, and emitter external connection electrode 16
And a collector external connection electrode 17.

The collector region 1 is formed by laminating an N ⁻ type epitaxial layer on an N ⁺ type silicon semiconductor substrate.

The base region 2 is a P-type impurity diffusion region provided at a predetermined position on the surface of the collector region 1.

The emitter region 3 is a plurality of N ⁺ -type impurity diffusion regions provided at predetermined intervals on the surface of the base region 2.

A plurality of trenches 4 are provided in the collector region 1 outside the base region 2, penetrate the N ⁻ type epitaxial layer, and reach the N ⁺ type semiconductor substrate. The specific depth is 10
20 μm, the trench width is about 10 μm, and about 2 to 3 trenches are provided in an area of about 50 μm on the outer periphery of the base region 2.

The collector extraction electrode 6 is 1 × 10 ²⁰ at
Polysilicon doped with impurities of about oms / CC is buried in the trench 4. Thereby, the collector-side electrode can be taken out from the semiconductor substrate surface.

The base electrode 7, the emitter electrode 8, and the collector electrode 9 are formed in contact holes provided in an insulating film covering the entire surface.
Aluminum or the like is sputtered to make contact with the base region 2, the emitter region 3, and the collector extraction electrode 6, respectively.

The first insulating film 10 is provided on the base electrode 7, the emitter electrode 8, and the collector electrode 9. Interlayer film or passivation film such as P-SIN with thickness of 2-3μ
m. The first insulating film 10 has through holes TH that are in contact with the base electrode 7, the emitter electrode 8, and the collector electrode 9, respectively, in order to make the electrode a multilayer wiring.

The base pad electrode 11, the emitter pad electrode 12, and the collector pad electrode 13 are formed on the first insulating film 10
It is provided with Al / Au or the like, and is formed in a desired shape so as to be insulated from each other. In the embodiment of the present invention, each has a size of about 200 μm × 200 μm. A metal such as Al / Au for forming each pad electrode is also buried in a through hole TH provided in the first insulating film 10 and makes contact with the base electrode 7, the emitter electrode 8, and the collector electrode 9, respectively. At least a part of each pad electrode covers base region 2. That is, the collector pad electrode 13
Since there is an operating portion directly under the semiconductor device, only the portion of the collector extraction electrode 6 needs to be secured in the semiconductor element region.
Therefore, even with a structure in which the collector is taken out from the surface of the semiconductor substrate, it is not necessary to secure an extra area in the semiconductor element area, which can greatly contribute to miniaturization of the chip.

The second insulating film 10 includes the pad electrodes 11,
An interlayer film similar to the first insulating film 10 or a passivation film such as P-SIN is provided on the layers 12 and 13 and has a thickness of about 2 to 3 μm. In addition, contact holes are provided to expose part of the pad electrodes 11, 12, and 13, respectively.

The base external connection electrode 15, the emitter external connection electrode 16, and the collector external connection electrode 17 are solder balls. Solder balls are provided in the contact holes provided in the second insulating film 10 to make contact with the respective pad electrodes 11, 12, and 13. The size of the solder ball is about 100 μm in diameter, and one solder ball is provided for each pad electrode.

FIG. 2 shows a top view of the completed semiconductor device. A base pad electrode 11, an emitter pad electrode 12, and a collector pad electrode 13 are arranged on a semiconductor element region,
On each pad electrode, a base external connection electrode 15, an emitter external connection electrode 16, and a collector external connection electrode 17 are formed by solder balls.

Here, in the embodiment of the present invention, the solder balls and the respective pad electrodes are left unexposed, but the semiconductor element may be sealed with an insulating resin and polished to expose the solder balls. Good.

A feature of the present invention is that a trench-type collector extraction electrode 6 provided in the collector region 1 outside the base region 2 is provided.
And external connection electrodes 15 to 17 formed by solder balls provided on the element formation region by multilayer wiring. With this structure, the base electrode, the emitter electrode, and the collector electrode can all be taken out from the surface of the semiconductor substrate, and no extra area is required for leading out the collector. With the same current capacity, almost the same pellet size as the conventional product is possible. In addition, miniaturization and thinning, which are required by the market, can be achieved. As expected, specifically, in the case of the 15 V / 3 A class, the mounting area is 8.12 mm ² in the case of the SC-59 outer shape. / 1
It is about 0, and the mounting height is 1.1m with SC-59 outline
What was m becomes 以下 or less.

3 to 10 show a method for manufacturing a semiconductor device according to the present invention.

According to the method of manufacturing an NPN planar transistor of the present invention, a semiconductor element region comprising a base region 2 of opposite conductivity type and a plurality of emitter regions 3 of one conductivity type is formed on a semiconductor substrate to be a collector region 1 of one conductivity type. Forming a trench groove 4 in the collector region 1 outside the base region 2, forming a collector extraction electrode 6 made of a semiconductor material embedded in the trench groove 4, and forming the base region 2, the emitter region 3, and the like. A step of forming a base electrode 7, an emitter electrode 8, and a collector electrode 9 connected to the collector extraction electrode 6, respectively, covering the entire surface with a first insulating film 10, and connecting to the base electrode 7, the emitter electrode 8, and the collector electrode 9, respectively; Base external connection electrode 1
5, a step of forming the emitter external connection electrode 16 and the collector external connection electrode 17, and a step of dicing the semiconductor substrate into individual semiconductor elements 22.

In the first step of the present invention, as shown in FIG.
An object of the present invention is to form a semiconductor element region including a base region of the opposite conductivity type and a plurality of emitter regions of the one conductivity type on a semiconductor substrate serving as a collector region of one conductivity type.

In this step, a silicon semiconductor substrate having a thickness of about 400 μm, in which an N ⁻ type epitaxial layer is laminated on an N ⁺ type silicon semiconductor substrate, is used as a collector region 1 and a known selective diffusion method is applied to an element formation region of the silicon semiconductor substrate. To form a P ⁺ -type base region 2, and a plurality of N ^{+ -type}
A mold emitter region 3 is formed. Here, an NPN type planar transistor has been described as an example, but a semiconductor element such as a PNP type planar transistor or MOSFET may be formed.

In the second step of the present invention, as shown in FIGS. 4 and 5, a trench is formed in the collector region outside the base region, and a collector extraction electrode made of a semiconductor material embedded in the trench is formed. It is in.

This step is the first feature of the present invention. In FIG. 4, a trench 4 is formed in the collector region 1 outside the base region 2. A portion serving as an intended extraction electrode is exposed, and the other portion is covered with a photoresist layer, and the surface of the silicon semiconductor substrate is selectively dry-etched.
Thereby, a trench groove 4 having a depth of about 10 to 20 μm penetrating the N ⁻ type epitaxial layer and reaching the N ⁺ type silicon semiconductor substrate is formed. The trench 4 has a width of 10 μm.
m and about 2 to 3 are formed in a region of the collector region 1 having a width of approximately 50 μm. The semiconductor element is an oxide film 5
Protected by coating.

Next, in FIG. 5, a collector extraction electrode 6 buried in the trench 4 is formed. 1 × 10 ^{20 over the} entire surface
Polysilicon doped with impurities of about atoms / CC is deposited, and the entire surface is etched back after annealing. By this step, a collector extraction electrode 6 embedded in each trench 4 is formed.

Thus, the electrode on the collector side can be taken out from the surface of the semiconductor substrate, so that a chip size package at a wafer level can be realized.

In the third step of the present invention, as shown in FIG.
An object is to form a base electrode, an emitter electrode, and a collector electrode connected to a base region, an emitter region, and a collector extraction electrode, respectively.

In this step, a first-layer electrode connected to each semiconductor element region is formed. A contact hole is formed in the oxide film 5 on the surface of the semiconductor element, and aluminum or the like is sputtered and then etched to have a desired electrode shape. By this step, a base electrode 7, an emitter electrode 8, and a collector electrode 9 that are in contact with the base region 2, the emitter region 3, and the collector extraction electrode 6, respectively, are formed.

In the fourth step of the present invention, as shown in FIGS. 7 and 8, the entire surface is covered with a first insulating film, and a base external connection electrode and an emitter external connection are respectively connected to a base electrode, an emitter electrode and a collector electrode. It is to form a connection electrode and a collector external connection electrode.

This step is a second feature of the present invention. First, a pad electrode (a second-layer electrode) of each element region having a size capable of supporting and supporting an external connection electrode is formed. Then, external connection electrodes of solder balls are formed thereon.

In FIG. 7, the first surface is covered with the first layer electrode.
The passivation film 10 such as an interlayer film or P-SIN is formed to a thickness of about 2 to 3 μm. A through hole TH is formed in the interlayer film or the passivation film 10 so that the first-layer electrode and the second-layer electrode formed in a subsequent step can contact each other.

Thereafter, Au / Al or the like is sputtered on the entire surface,
Etching into a desired shape, contacting the base electrode 7, the emitter electrode 8, and the collector electrode 9 respectively,
Base pad electrode 11, emitter pad electrode 12, and collector pad electrode 1 having an area of about μm × 200 μm.
Form 3

As is apparent from FIG. 7, at least a part of the base pad electrode 11, the emitter pad electrode 12, and the collector pad electrode 13
Provided to cover. That is, the collector pad electrode 13
Since there is an operating portion directly under the semiconductor device, only the portion of the collector extraction electrode 6 needs to be secured in the semiconductor element region.
Therefore, even in a structure in which the collector is taken out from the surface of the semiconductor substrate, it is not necessary to secure an extra area in the semiconductor element area, which can greatly contribute to miniaturization of the chip.

Next, in FIG. 8, the entire surface is covered with a second insulating film, on which a base external connection electrode, an emitter external connection electrode and a collector external electrode are respectively in contact with a base pad electrode, an emitter pad electrode and a collector pad electrode. Form connection electrodes.

The electrodes for external connection are solder balls. Each pad electrode is covered with an interlayer film or a passivation film 10 serving as a second insulating film, and is etched so as to overlap with each pad electrode. Further, one contact hole is provided on each pad electrode to expose a part of each pad electrode. An unnecessary portion of the bonding metal is removed by sputtering Cr / Cu serving as the bonding metal. A mask with a resist having a thickness of 4 to 5 μm is applied to each contact hole, and Cu serving as a solder base is buried in the contact hole to a thickness of about 3.0 μm. Further, solder is formed on the contact hole Cu by electrolytic plating. The resist is removed and the solder is heated to make it spherical.

By this step, the base pad electrode 11,
Emitter pad electrode 12 and collector pad electrode 13
A solder ball having a diameter of about 100 μm is fixed thereon, and the base external connection electrode 15 and the emitter external connection electrode 1 are respectively provided.
6, the collector external connection electrode 17;

In the fifth step of the present invention, as shown in FIG.
Dicing the semiconductor substrate into individual semiconductor elements.

In this step, as shown in FIG. 9A, a silicon semiconductor substrate, that is, a semiconductor wafer 21 is cut into individual semiconductor elements 22 for each semiconductor element. The semiconductor wafer 21 is cut by a dicing blade along a dicing line 20 indicated by a dotted line using a dicing apparatus for cutting, thereby forming a semiconductor device divided for each semiconductor element 22. In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Corporation) is attached to the back side of the semiconductor wafer 21 and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet. .

In the embodiment of the present invention, as shown in FIG. 9B, the semiconductor element is not sealed with an insulating resin. good.

Here, FIG. 10 shows a case where a semiconductor element is sealed with a resin. In this case, as shown in FIG. 10A, a predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the semiconductor wafer 21, and all the semiconductor elements are connected to a common resin layer. Cover with 23. As the liquid resin, for example, CV57
6AN (manufactured by Matsushita Electric Works) was used. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved. In order to process the curved surface of the resin layer 23 into a flat surface, a method in which a flat molded member is pressed before the resin is cured to form a flat surface,
After curing by heat treatment (curing) at 0 to 200 degrees for several hours, a method of processing the curved surface into a flat surface by grinding the curved surface with, for example, a dicing blade is considered.

Thereafter, the electrodes 24 of the solder balls are ground by grinding.
To expose. Mechanically ground by back grinding,
The remaining 10 to 20 μm is chemically removed by spin etching and ground to a thickness of about 100 μm.
The electrodes 24 for external connection are led out to the three surfaces.

Further, as shown in FIG. 10 (B), the semiconductor element 22 is divided along the dicing line 20 of the semiconductor wafer 21 to obtain a completed product as shown in FIG. 12 (C). The resin layer 23 only covers the surface of the semiconductor element 22, and the silicon semiconductor substrate is exposed on the side wall of the semiconductor element 22.

A feature of the manufacturing method of the present invention resides in that a collector extraction electrode is formed in a collector region. Thereby, the collector can be taken out from the surface of the semiconductor substrate, and the operating portion can be arranged below the collector pad electrode by forming the electrode as a multilayer wiring. If an external connection electrode is formed by a solder ball on each pad electrode, a chip size package at a wafer level can be realized. Further, the resin sealing process can be omitted, and the assembly cost is not required, so that the cost can be significantly reduced.

Also, since there is no assembly process, TAT (Turn
Around Time) can be greatly reduced.

[0056]

As described above, according to the present invention, there is an advantage that it is possible to realize a package structure which can adopt a flip-chip method which can be further downsized than a semiconductor device using a lead frame.

At this time, since the structure is such that the lead terminals do not protrude, the occupied area at the time of mounting is reduced, and an extra area for the collector lead-out electrode is not required. Then, the pellet size which is almost the same as that of the conventional product can be obtained. In addition, miniaturization and thinning, which are required by the market, are possible, and although this is an expected value, specifically, in the case of a 15V / 3A class, the mounting area is SC-5.
In the case of 9, what was 8.12 mm ² becomes about 1/10,
In addition, the mounting height is 1.1 mm or less in the SC-59 outer shape, but is 以下 or less.

Further, since the extraction electrode is formed directly on the silicon semiconductor substrate on which the semiconductor element is formed, it is not necessary to use a ceramic substrate as in the conventional case, and it is not necessary to fix the semiconductor element to another mounting member. Cost can be reduced.

Further, the silicon semiconductor substrate can be processed by existing equipment, and no new equipment is required. Since the silicon semiconductor substrate can be processed in the preceding process, the subsequent process is eliminated, and T
AT (Turn Around Time) can be greatly reduced.

That is, a chip size package at the wafer level is realized, and no assembly cost is required, so that a significant cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a top view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

FIG. 6 is a cross-sectional view for explaining the present invention.

FIG. 7 is a cross-sectional view for explaining the present invention.

FIG. 8 is a cross-sectional view for explaining the present invention.

9A is a top view for explaining the present invention, and FIG.
It is sectional drawing.

10A is a cross-sectional view for explaining the present invention, FIG.
(B) is a top view, (C) is a perspective view.

FIG. 11 is a cross-sectional view for explaining a conventional example.

FIG. 12 is a diagram for explaining a conventional example.

FIG. 13 is a diagram for explaining another conventional example.

Continued on the front page F-term (reference) 4M104 BB01 BB02 BB40 CC01 DD06 DD17 FF01 FF06 FF26 GG06 GG15 HH20 5F003 AP09 AZ07 BA11 BA13 BB07 BC02 BC07 BC08 BE07 BH05 BH08 BH11 BH16 BH18 BH93 KK94 JJ94H08 PP15 QQ08 QQ31 QQ37 RR06 SS15 UU05 VV07 XX33 XX34

Claims (12)

[Claims] 1. A base region of an opposite conductivity type provided on a semiconductor substrate serving as a collector region of one conductivity type; an emitter region of a plurality of one conductivity type provided on a surface of the base region; A trench groove provided in the collector region; a collector extraction electrode made of a semiconductor material embedded in the trench groove; a base electrode, an emitter electrode, and a collector electrode contacting the base region, the emitter region, and the collector extraction electrode, respectively. A first insulating film covering the base electrode, the emitter electrode, and the collector electrode; and a base external connection electrode, an emitter external connection electrode, and a collector external connection electrode connected to the base electrode, the emitter electrode, and the collector electrode. A semiconductor device, comprising: 2. A base pad electrode, an emitter pad electrode, and a collector pad electrode provided on the first insulating film and in contact with the base electrode, the emitter electrode, and the collector electrode, respectively, and the base pad electrode, the emitter pad electrode, and A second insulating film covering the collector pad electrode, and the base pad electrode provided on the second insulating film;
2. The semiconductor device according to claim 1, further comprising: the base external connection electrode, the emitter external connection electrode, and the collector external connection electrode that are in contact with an emitter pad electrode and a collector pad electrode, respectively. 3. 3. The semiconductor device according to claim 2, wherein at least a part of the base pad electrode, the emitter pad electrode, and the collector pad electrode cover the base region. 4. The semiconductor device according to claim 1, wherein each of said external connection electrodes is a solder ball. 5. The semiconductor device according to claim 1, wherein each of the external connection electrodes is covered with an insulating resin, and a part of the surface is exposed. 6. The semiconductor device according to claim 1, wherein said semiconductor material is polysilicon containing impurities. 7. A step of forming a semiconductor element region comprising a base region of opposite conductivity type and a plurality of emitter regions of one conductivity type on a semiconductor substrate serving as a collector region of one conductivity type, and said collector region outside said base region. Forming a trench groove in the trench, and forming a collector extraction electrode made of a semiconductor material embedded in the trench groove; and a base electrode, an emitter electrode, and a collector respectively connected to the base region, the emitter region, and the collector extraction electrode. Forming an electrode, covering the entire surface with a first insulating film, and forming a base external connection electrode, an emitter external connection electrode, and a collector external connection electrode respectively connected to the base electrode, the emitter electrode, and the collector electrode; Dicing the semiconductor substrate to separate individual semiconductor elements. The method of manufacturing a semiconductor device, characterized by Bei. 8. The base electrode, on the first insulating film,
Forming a base pad electrode, an emitter pad electrode, and a collector pad electrode that are in contact with the emitter electrode and the collector electrode, respectively, covering the entire surface with a second insulating film, and further forming the base pad electrode, the emitter pad electrode, and the collector pad thereon; 8. The method of manufacturing a semiconductor device according to claim 7, comprising a step of forming the base external connection electrode, the emitter external connection electrode, and the collector external connection electrode that are respectively in contact with the electrodes. 9. The method according to claim 8, wherein at least a part of the base pad electrode, the emitter pad electrode, and the collector pad electrode are formed to cover the base region. 10. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of coating each of the external connection electrodes with an insulating resin and polishing the same to expose a part of each of the external connection electrodes. Method. 11. The method according to claim 7, wherein each of the external connection electrodes is formed of a solder ball. 12. The method according to claim 7, wherein the semiconductor material is formed of polysilicon containing impurities.