JP2002170928A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of high speed and low power consumption. SOLUTION: This semiconductor device possesses first wiring (28, 29) that connects circuits, second wiring (31, 32) that connects the circuits, and a change- over circuit (30) that selects either one of the first or the second wiring for transmitting signals between the circuits, wherein the second wiring is larger in size than the first wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device using a super connect (also referred to as a giant wiring) which has recently attracted attention.

[0002]

2. Description of the Related Art Superconnect is a wiring technique using a wiring layer having a width of about 5 to 10 .mu.m, and enables a high-speed and low-power semiconductor device.

The giant wiring has the following advantages over a normal wiring formed by fine processing. Low electrical resistance due to wide width. The parasitic capacitance is small because the interlayer between the bulk and the insulating layer is thick and the wiring interval between the huge wirings is wide. As described above, the time constant of the huge wiring is very low, and is suitable for high-speed operation.

The mounting area of semiconductor devices has been decreasing year by year, and high-density mounting techniques such as BGA (ball grid array) have been developed. In this method, bumps are arranged in an array on the surface of a semiconductor chip to form external electrodes. At this time, there is a rewiring technique as a method of wiring from the circuit of the semiconductor chip to the bump. This rewiring is also a wide wiring and a huge wiring.

[0005]

SUMMARY OF THE INVENTION The present invention provides a high-speed and low-power-consumption semiconductor device using a huge wiring conventionally used as rewiring as wiring for transmitting signals between circuits formed on a chip. The purpose is to do.

More specifically, the object of the present invention is to provide a wafer test (a test for selecting good or defective chips on a wafer after pattern formation using a wafer prober) and a subsequent chip test (logic function of a circuit). And an electrical characteristic test), and a semiconductor device having a wiring structure configured in consideration of an operation in a mounted state.

[0007]

According to the present invention, a first wiring connecting between circuits, a second wiring connecting between the circuits, and the first wiring for transmitting a signal between the circuits are provided. And a switching circuit for selecting one of the second wirings, wherein the second wiring is a semiconductor device having a size larger than that of the first wiring.

When the above wiring structure is specified from another viewpoint,
It can be said that the second wiring is formed in a layer above the first wiring.

When the above-mentioned wiring structure is specified from another viewpoint, the first wiring is a wiring used at the time of a wafer test, and the second wiring is a wiring used at the time of an operation after the wafer test.

[0010] As described above, the first and second modes having different forms are described.
By selectively using these wirings, a high-speed and low-power-consumption semiconductor device can be provided.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, in order to facilitate understanding of the present invention, a logic chip which is an example of a semiconductor device will be described with reference to FIG.

FIG. 1 is a block diagram showing a general configuration of a logic chip. Logic chip 10 shown
Has five functional blocks 11 to 15, an I / O circuit 16 for forming an interface with the outside, and a clock (CLK) buffer 17 for buffering a clock supplied from the outside and supplying the clock to an internal circuit. Functional blocks 11 to 15, I / O circuit 16 and clock buffer 1
Between 7, a bus 18 and a clock signal line 19 are provided. The bus 18 and the clock signal line 19 are signal lines (hereinafter, referred to as normal wiring) formed by a general fine processing technique. The bus 18 transmits data, addresses, control signals, and the like. The clock signal line 19 supplies the clock buffered by the clock buffer 17 to each unit.

The bus 18 and the clock signal line 19 are relatively long among the signal lines in the chip. A giant wiring described below is provided for such a relatively long signal line.

FIG. 2 is a block diagram showing a configuration of the semiconductor device according to the first embodiment of the present invention.

The illustrated semiconductor device 100 is a logic chip (logic device). Like the logic chip 10 shown in FIG. 1, functional blocks 21 to 25, an I / O circuit 26 forming an interface with the outside, and an external Clock (CLK) buffer 27 for buffering the clock supplied from the internal circuit and supplying the buffer to the internal circuit. Similarly, the logic chip 100 includes a bus 28 and a clock signal line 2 which are formed by microfabrication technology using normal wiring.
9

The logic chip 100 further includes a bus 31 formed by huge wiring, a clock signal line 32 formed by huge wiring, and a switching circuit 30. Each of the functional blocks 21 to 25, the I / O circuit 26, and the clock buffer 27 selectively select one of the buses 28 and 31 and one of the clock signal lines 29 and 32 according to the signal S1 output from the switching circuit 30. Connected to one side.

FIG. 3 is a schematic cross-sectional view showing the relationship between the bus 28 and the clock signal line 29 formed by the normal wiring and the bus 31 and the clock signal line 32 formed by the huge wiring.

On the semiconductor substrate 40 (on the chip surface), a multilayer wiring layer 42 is formed. The multilayer wiring layer 42 has wiring layers 42a and 42b configured in multiple layers. Each of the wiring layers 42a and 42b is insulated by an insulating layer of polyimide or the like, and an insulating layer of polyimide or the like is provided on the uppermost wiring layer 42b. In FIG. 3, for convenience, the multilayer wiring layer 4
The two insulating layers are collectively indicated by reference numeral 41. The bus 28 and the clock signal line 29 are wirings in the multilayer wiring layer 42 and are normal wirings formed by ordinary fine processing.

The multilayer wiring layer 42 has an electrode 43. The electrode 43 is electrically connected to a diffusion layer 44 formed on the semiconductor substrate 40 via contact portions 45 and 46 and an intermediate wiring layer.

On the insulating layer 47, a giant wiring layer 48 is formed. Each signal line of the bus 31 and the clock signal line 32 is formed by a huge wiring layer 48. Huge wiring layer 48
Are in contact with the electrode 43 at the contact portion 33. The electrode 43 is exposed from a contact hole provided in the insulating layer 41. The contact part 33 is formed of the insulating layer 4
Huge wiring layer 4 in contact holes formed in 1, 47
8 is connected to the electrode 43. The width and thickness of the giant wiring layer 48 are determined by the wiring layers 42 of the multilayer wiring layer 42.
a, 42b, for example, 5 to 10 μm.

On the huge wiring layer 48, a cover film 49 is provided. The cover film 49 has an opening (through hole) from which the huge wiring layer 48 is exposed.
An electrode 50 for connection to another chip formed on the huge wiring layer 48 is provided in the opening. The electrode 50 is a bump or the like.

The electrode 50 is for contacting an electrode provided on another chip when the chip is overlapped with another chip face to face to form a multi-chip semiconductor device. . Therefore, when there is no such purpose, the electrode 50 is unnecessary. That is,
The huge wiring 48 is completely covered with the cover film 49.

Returning to FIG. 2, the signal lines and the clock signal lines 32 of the bus 31 formed by the above-described huge wiring are connected to the respective functional blocks 21 to 25 via the contact portions 33. Further, the bus 31 is connected to the I / O circuit 26 via the contact section 33. Further, the clock signal line 32 is connected to the clock buffer 27 via the contact part 33.

FIG. 4 shows the configuration of another bus switching circuit provided in the switching circuit 30 shown in FIG. 2 and, as an example, a signal line 28i of a bus 28 with normal wiring between the functional blocks 21 and 25, and a huge FIG. 4 is a diagram showing a circuit configuration of a corresponding signal line 31i of a bus 31 by wiring and a related portion of the functional blocks 21 and 25. Buses 28 and 31
It includes a part for transmitting a signal in one direction and a part for transmitting a signal in two directions. FIG. 4 shows a configuration example in which a signal is transmitted from the functional block 21 to the functional block 25 in one direction. The signal transmitted in one direction is, for example, a control signal or an address signal.

The function block 21 has a driver 51. The driver 51 outputs the signal SGL from the internal circuit to the signal line (one of 28i and 31i) designated by the switching signal S1 passing through the control line 34. The driver 51 includes inverters 52, 53, 54, and a NAN.
D gates 55 and 56 are provided. When the switching signal S1 is at a high level (H), the NAND gate 56 is activated and the NAND gate 55 is deactivated. Therefore, the signal SGL from the internal circuit is supplied to the NAND gate 56
And a bus 28 with normal wiring via the inverter 54
On the signal line 28i. Conversely, the switching signal S
When 1 is at the low level (L), the NAND gate 55 is activated and the NAND gate 56 is deactivated. Therefore, the signal SGL from the internal circuit is supplied to the NAND gate 5
5 and a bus 3 with huge wiring via the inverter 53
The signal is transmitted to one signal line 31i.

The bus switching circuit 30A includes a huge wiring 6
1, a resistor 62 and an inverter 63. Huge wiring 6
A series circuit of 1 and the resistor 62 is provided between the power supply voltage VCC and the ground VSS. When the huge wiring is not formed, the input of the inverter 63 is at the ground level V.
SS, and the switching signal S1 is H. Huge wiring 6
When 1 is formed, the switching signal S1 becomes H.

The function block 25 has a receiver 57. The receiver 57 includes a NOR gate 58 and an inverter 5
9 and a field effect transistor (FET) such as an N-channel MOS transistor. Switching signal S
When 1 is H, the transistor 60 is turned on, and the signal line 28i of the bus 28 by the normal wiring is selected. Conversely, when the switching signal S1 is L, the transistor 60 is turned off, and the signal line 31i of the bus 31 formed by the huge wiring is selected.
The selected signal passes through the inverter 59 and is output to an internal circuit (not shown) of the functional block 25.

Here, switching of the bus switching circuit 30A is performed as follows in consideration of a wafer test and a chip test described below.

The purpose of the wafer test is to use a wafer prober to select non-defective and defective chips on the wafer after pattern formation. If it is determined that the product is defective, the defective portion is repaired by a redundant means provided in advance.
At this time, the fuse is blown by a laser or the like. The fuse is provided in the multilayer wiring layer 42 shown in FIG.
It is exposed from the opening (repair window) provided in 1. If the insulating layer 47 is provided and the giant wiring 48 is formed thereon, the repair window is closed. Therefore, the wafer test needs to be performed before the step of forming a huge wiring.

Before the formation of the giant wiring, the signal line 31i of the giant wiring in the configuration shown in FIG. 4 is not formed. Also, the giant wiring 61 of the bus switching circuit 30A is not formed. Therefore, the switching signal S1 becomes H, and the signal line 28i of the already formed normal wiring is selected.

After performing the wafer test in this manner, the giant wirings 48 and 61 shown in FIG. 3 are formed. Since the huge wiring 48 is a regular wiring, the huge wiring 48
The test (chip test) must be performed after the test is provided.
At that time, the signal line 28i of the normal wiring is no longer necessary. If the signal line 28i is left connected, this parasitic capacitance is added to the signal line 31i formed by a huge wiring, which is a problem.

Since the huge wiring 61 of the bus switching circuit 30A is formed after the wafer test is performed, the switching signal S1 becomes L at the time of the chip test. Therefore, the signal line 31i of the huge wiring is selected. Since the huge wiring 61 remains wired, the signal line 31i of the huge wiring is permanently selected. Since the huge wiring has the advantages described above, the semiconductor device 100 shown in FIG.
The power consumption is low.

FIG. 5 shows a clock signal line 2 of a normal wiring.
9 is a diagram showing a configuration related to control of a signal line 32 with a large wiring 9. FIG. The clock passes through the clock signal line 29 or 32 from the clock buffer 27 and passes through each functional block 11.
.. To one-way.

The clock buffer 27 has a clock input circuit 65 connected to an external clock terminal 64 and a driver 66. The driver 66 includes inverters 67 and 6
8 and 69, and NAND gates 70 and 71. Each of the functional blocks 11 to 15 includes a receiver 72. The receiver 72 includes a NOR gate 73, an inverter 74, and an N-channel transistor 75.

The clock signal line switching circuit 30B is provided in the switching circuit 30 shown in FIG. 2 and has the same configuration as the bus switching circuit 30A shown in FIG. That is, as illustrated, the clock signal line switching circuit 30B includes:
It has a huge wiring 61a, a resistor 62a and an inverter 63a. 4 and 5, the bus switching circuit 30
A and the clock signal line switching circuit 30B are provided separately. Accordingly, the control line 34A is connected to the control line 3 shown in FIG.
4 and provided separately. However, only one of the switching circuits may be provided and shared between bus switching and clock signal line switching.

When the switching signal S1 is H, the driver 6
6 and the receiver 72 are clock signal lines 2 of normal wiring.
Select 9. On the contrary, when the switching signal S1 is L,
The driver 66 and the receiver 72 select the clock signal line 32 by the huge wiring.

FIG. 6 is a block diagram showing a data bus for transmitting data among the buses 29 and 32 shown in FIG. 2 and a configuration relating to the data bus. In FIG. 6, one data bus line of the bus 28 with the normal wiring is set to 28j, and one data bus line of the bus 31 with the huge wiring is set to 31j.
It is shown as

Data D is transmitted on data bus lines 28j and 31j.
Since the ATA is transmitted in both directions, each functional block 21
To 25 (only the functional blocks 21 and 25 are shown in FIG. 6) include a driver and a receiver for each data bus line. More specifically, the function block 21 has a driver 81 and a receiver 28, and the function block 25 has a driver 101 and a receiver 102.

The driver 81 of the functional block 21 includes inverters 83, 84, 90, 91, a NAND gate 87,
99, NOR gates 85, 86, 92, 93, P-channel transistors 88, 95, N-channel transistor 8
9, 96. Receiver 82 of function block 21
Has a NOR gate 97, an inverter 98, and an N-channel transistor 99.

Driver 81 is activated when it receives H enable signal EN1 from the internal circuit. When the bus switching circuit 30A outputs the H switching signal, the NOR gate 92 is activated since the L level signal is input, whereas the NOR gate 85 is activated because the H level signal is input. Is done. Therefore, the transistor 95 or 96 is driven according to the value of the data, and the data is output to the data bus line 28j of the normal wiring. When the switching signal S1 is H, the output of the inverter 122 becomes L
Therefore, the N-channel transistor 121 connected to the data bus line 28j is off.

Under the condition that the H enable signal EN1 is received from the internal circuit, the L switching signal is applied to the bus switching circuit 3
When output from 0A, NOR gate 85 is activated and NOR gate 92 is deactivated. Therefore, the transistor 88 or 89 is driven according to the value of the data,
Data is output to the data bus line 31j formed by the huge wiring. When the switching signal S1 is L, the inverter 12
2 becomes H, the N-channel transistor 121 connected to the data bus line 28j turns ON,
The data bus line 28j of the normal wiring is at the ground level V
Set to SS.

Similarly to the driver 81, the driver 101 of the functional block 25 includes inverters 103, 104,
110, 111, NAND gates 107, 114, NO
It has R gates 105, 106, 112, 113, P-channel transistors 108, 115, and N-channel transistors 109, 116. The receiver 102 of the functional block 25 includes a NOR gate 117, an inverter 118, and an N-channel transistor 119. Driver 10
1 and the operation of the receiver 102 are the same as the operation of the driver 81 and the receiver 82 described above.

The other functional blocks have the same configuration.

FIG. 7 shows the bus switching circuit 30A described above.
FIG. 11 is a diagram illustrating another configuration example of the clock switching circuit 30B.

The configuration shown in FIG. 7A includes a resistor 131, an inverter 132, and a fuse 133. Resistance 13
1 and the fuse 133 are connected to the power supply voltage side VCC and the ground VS.
Connect between S. When the fuse 133 is connected, the switching signal S1 becomes H. When the fuse 133 is blown, the switching signal becomes L.

The structure shown in FIG.
34, a pull-up resistor 135 and an inverter 136. By setting a ground level VSS by applying a probe to the test pad 134 before forming a huge wiring, the switching signal S1 becomes H. Test pad 134
Is open, the switching signal S1 is L.

The configuration shown in FIG. 7C comprises an electrode 139, a resistor 140 and an inverter 141. The electrode 139 is a terminal for external connection, and is formed by, for example, the protruding electrode 50 in FIG. The protruding electrode 50 is connected to another chip or board 13.
7 and the semiconductor device, a chip or a board 13
7 electrode 138. For example, when the chip 137 and the semiconductor device (chip) are overlapped, the electrode 1
38 and 139 make contact. Thereby, the electrode 13
The power supply voltage VCC applied to 8 is also applied to the electrode 139. As a result, the switching signal S1 becomes L. That is, in a state where the semiconductor device is used, a bus or a clock signal line formed by a huge wiring is selected.

The configuration shown in FIG. 7D is composed of a mode selection circuit. The mode selection circuit is mounted on, for example, a DRAM chip, and sets an operation mode of an internal circuit specified by an external command signal or address signal. The switching signal S1 is set using such a mode selection circuit.

The configurations of the switching circuits 30A and 30B shown in FIGS. 4 to 6 and FIG. 7A are circuits using programmable elements.

FIG. 8 is a block diagram of a semiconductor device according to the second embodiment of the present invention.

Semiconductor device 200 according to the second embodiment
Considers the following points. In the wafer test, when using the normal wiring and operating after using the huge wiring after forming it, the signal in the wafer test and the operation after the huge wiring (chip test and operation when mounted) Timing will change. The second embodiment of the present invention has a configuration that prevents this.

In FIG. 8, each functional block 21-25
Are provided with clock buffers (circuits for receiving clocks) 145 to 149, respectively. As described later, the clock buffer 149 has a different circuit configuration from the other clock buffers 145 to 148. Pads (electrodes) 150 to 154 for external connection are connected to the clock buffers 145 to 149, respectively. Pads 150 to 154 are functional blocks 21 to 25, respectively.
Is formed at a position close to. The clock buffers 145 to 148 are connected to a clock signal line 156 formed of a huge wiring and a control line 34A.
The clock signal line 156 is connected to each of the functional blocks 21 to 25 via the contact section 157. Each of the clock buffers 145 to 148 has a pad 15 according to the clock switching signal S1 output from the clock switching circuit 30B.
Either an external clock supplied to 0 to 153 or an external clock supplied through the giant wiring 156 is selected, and the selected clock is output to the function blocks 21 to 24 as an internal clock.

The pads 150 to 154 are formed in a wiring layer of a normal wiring. That is, it corresponds to the electrode 43 of FIG. The pads 155 are the pads 151 to 1
Similar to 54, it receives an external clock, but is formed of a huge wiring layer. That is, FIG.
Of the electrode 50. Electrode 50 shown in FIG.
Is a bump, but may be a flat pad.

Since the electrodes 154 and 155 are arranged close to the functional block 25, the functional block 25
Clock signal line 15 with buffer 149 and normal wiring
The clock is supplied from outside only through 6A. That is, the clock supplied to the pad 154 is supplied during the wafer test, and the clock supplied to the pad 155 is supplied during the chip test after the formation of the huge wiring and the operation after mounting. Since the clock signal line 156A is short, the timing of the clock supplied to the functional block 25 does not change in either case.

During the wafer test, the pads 150 to 153
Is supplied to the clock buffer 145
148 to the functional blocks 21 to 24 at the same timing. At this time, the clock switching signal S1 is H. At the time of the chip test after the formation of the huge wiring, the clock switching signal becomes L, and the external clock given to the pad 155 is supplied to the functional blocks 21 to 24 through the buffer 149 and the clock signal line 156 of the huge wiring, and the normal wiring Is supplied to the functional block 25 via the clock signal line 156A. Since the clock signal line 156 is formed of a huge wiring, the clock delay is small, and the clock signal line 156A is short, so that the clock delay is small.

The clock buffer 145 includes a buffer 173, an inverter 174, a NOR gate 175,
It comprises channel transistors 176 and 177. When the clock switching signal S1 is H, the transistor 177 turns off and the clock signal line 156 is disabled.
When the clock switching signal S1 is L, the transistor 17
6 is turned off and the pad 150 is disabled. The clock buffers 146 to 148 have the same configuration. The buffers 149 and 173 have a two-stage configuration of, for example, a CMOS inverter.

Here, the pad 1 usually formed of a wiring layer
When the number of 50 to 154 is M and the number of pads 155 formed in the huge wiring layer is N, the pads may be provided so as to satisfy M> N ≧ 1. In the example of FIG. 8, M = 5,
N = 1.

FIG. 9 shows a semiconductor device according to the third embodiment of the present invention. The semiconductor device 300 according to the third embodiment corresponds to a modified example obtained by simplifying the second embodiment.

In the third embodiment, the clock selection performed in the clock buffers 145 to 148 of the second embodiment is not performed, and the clock signal line 156 formed by the pads 150 to 153 and the huge wiring is not used. Wired or. The clock signal line 156 extending from the pad 155 formed in the huge wiring layer is connected to the pads 150 to 154 via the contact portion 157, and the buffers 145A to 145A are arranged close to the functional blocks 21 to 25.
149A is connected to the input terminal. Buffer 145A ~
The output terminals of the 149A are functional blocks 21 to 2, respectively.
5 is connected.

Each of the buffers 145A to 149A is, for example, a plurality of CMOS inverters connected in cascade like the buffers 149 and 173 described above.

During the wafer test, the pads 150 to 154
The external clock is supplied to the pad 153 after the huge wiring.

The third embodiment having the above configuration has a simpler circuit than the second embodiment. However, in the third embodiment, since the external clock is connected to the plurality of clock buffers 145A to 149A after the huge wiring,
The load on the clock signal line 156 increases, which is disadvantageous for high-speed operation. That is, if priority is given to high-speed operation, the second embodiment is preferable.

Here, when high timing accuracy is required as in the case of a clock signal line, it is preferable to make the lengths of giant wires for transmitting the same to each unit as equal as possible.

FIG. 10 is a diagram showing a semiconductor device 400 in which the clock signal line 32 has the same wiring length in the configuration shown in FIG. The clock signal line 32A shown in FIG. 10 is configured to branch at the node N1, and the distance from the clock buffer 27 to each of the functional blocks 21 to 25 is completely equal to each other.
Almost equal. Even if there is a difference in the wiring distance, there is no problem as long as the required timing accuracy can be obtained. In other words, the difference in the wiring distance is allowed to the extent that the required timing accuracy is obtained.

FIG. 11 is a diagram showing a semiconductor device 500 in which the clock signal line 156 has the same wiring length in the configuration shown in FIG. The clock signal line 156A shown in FIG.
Are completely equal or almost equal to the function blocks 21 to 25. Even if there is a difference in the wiring distance, there is no problem as long as the required timing accuracy can be obtained. In other words, the difference in the wiring distance is allowed to the extent that the required timing accuracy is obtained. The semiconductor device 500 includes a pad 18 instead of the clock buffer 149 shown in FIG.
2 is used.
The clock buffer 181 has the same configuration as the clock buffer 145.

The embodiment of the present invention has been described above. The present invention is not limited to the above-described embodiment, but includes various embodiments. For example, the above embodiment is an example of a logic chip, but other chips,
For example, it includes various types of semiconductor devices such as a memory chip and a chip in which a functional block and a memory are mixed. (Supplementary Note) (Supplementary Note 1) The first wiring connecting between the circuits, the second wiring connecting between the circuits, and the first and second wirings for transmitting signals between the circuits. A switching circuit for selecting one of the first and second wirings, wherein the second wiring is larger in size than the first wiring.

(Supplementary Note 2) One of the first and second wirings for transmitting a signal between the first wiring connecting the circuits, the second wiring connecting the circuits, and the circuit. And a switching circuit for selecting one of the first and second wirings, wherein the second wiring is formed above the first wiring.

(Supplementary Note 3) One of the first and second wirings for transmitting a signal between the first wiring connecting the circuits, the second wiring connecting the circuits, and the circuit. A switching circuit for selecting one of the two, wherein the first wiring is a wiring used during a wafer test, and the second wiring is a wiring used during an operation after the wafer test.

(Supplementary Note 4) The semiconductor device according to any one of Supplementary notes 1 to 3, wherein the first and second wirings are wirings for transmitting the same signal.

(Supplementary Note 5) The first and second wirings are
5. The semiconductor device according to claim 1, wherein the wiring transmits at least one of an address, data, a control signal, and a clock.

(Supplementary Note 6) The first wiring may be connected to the second wiring.
6. The semiconductor device according to any one of supplementary notes 1 to 5, wherein the semiconductor device is operable at a stage where the wiring is not formed, and in this case, a signal is transmitted between circuits via the first wiring.

(Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the switching circuit fixedly selects the second wiring after the second wiring is formed.

(Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the switching circuit electrically connects only a selected wiring between the circuits.

(Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the switching circuit is programmable.

(Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the second wirings include signal lines having the same length.

(Supplementary Note 11) First Formed on Chip
And a second wiring layer formed above the wiring layer, and the number of the first electrodes formed on the first wiring layer is M, and the number of the first electrodes formed on the second wiring layer is M. A semiconductor device that satisfies the condition M> N ≧ 1 when the number of second electrodes is N and the first and second electrodes receive the same signal.

(Supplementary Note 12) The semiconductor device according to Supplementary Note 11 has a receiving circuit provided for each of the M first electrodes. 1
And a signal applied to a second electrode in a second predetermined state is applied to the internal circuit through a second wiring layer.

[0078]

As described above, according to the present invention,
By selectively using different forms of wiring, a semiconductor device with high speed and low power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a general configuration of a logic chip.

FIG. 2 is a block diagram showing a configuration of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram schematically showing a cross section of the semiconductor device shown in FIG. 2;

FIG. 4 is a diagram showing in detail a portion related to a signal transmitted in one direction such as an address and a control signal in the configuration shown in FIG. 2;

5 is a diagram showing in detail a portion related to clock transmission in the configuration shown in FIG. 2;

FIG. 6 is a diagram showing in detail a part related to data transmission in the configuration shown in FIG. 2;

FIG. 7 is a diagram illustrating a configuration example of a switching circuit.

FIG. 8 is a block diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a semiconductor device according to a third embodiment of the present invention.

10 is a diagram illustrating a semiconductor device in which clock signal lines of the semiconductor device illustrated in FIG. 2 have equal wiring lengths.

11 is a diagram illustrating a semiconductor device in which clock signal lines of the semiconductor device illustrated in FIG. 8 have equal wiring lengths.

[Explanation of symbols]

 28 Bus with Normal Wiring 29 Clock Signal Line with Normal Wiring 31 Bus with Giant Wiring 32 Clock Signal Line with Giant Wiring 32A Clock Signal Line with Giant Wiring 156 Clock Signal Line with Giant Wiring 156A Clock Signal Line with Giant Wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/88 Z 27/04 UT (72) Inventor Tadao Aikawa 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Masafumi Yamazaki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fujitsu Limited (reference) XX27 XX37 5F038 AV15 CD05 CD06 CD07 CD09 CD12 CD20 DF05 DF08 DF14 DF17 DT15 EZ20 5F064 BB05 BB06 BB07 BB14 BB26 CC09 EE08 EE09 EE23 EE27 EE42 EE47 EE54 EE60 FF02 FF04 HFF10FF

Claims (10)

[Claims] A first wiring connecting between the circuits, a second wiring connecting between the circuits, and the first and second wirings for transmitting a signal between the circuits.
And a switching circuit for selecting one of the wirings, wherein the second wiring is larger in size than the first wiring. 2. A first wiring connecting between circuits, a second wiring connecting between the circuits, and the first and second wirings for transmitting signals between the circuits.
And a switching circuit for selecting one of the wirings, wherein the second wiring is formed in a layer above the first wiring. 3. A first wiring connecting between the circuits, a second wiring connecting between the circuits, and the first and second wirings for transmitting a signal between the circuits.
And a switching circuit for selecting one of the wirings, wherein the first wiring is a wiring used during a wafer test, and the second wiring is a wiring used during an operation after the wafer test. Semiconductor device. 4. The semiconductor device according to claim 1, wherein said first and second wirings are wirings for transmitting the same signal. 5. The first wiring is operable at a stage where the second wiring is not formed. In this case,
The semiconductor device according to claim 1, wherein a signal is transmitted between the circuits via the first wiring. 6. The semiconductor device according to claim 1, wherein said switching circuit fixedly selects said second wiring after said second wiring is formed. 7. The semiconductor device according to claim 1, wherein said switching circuit electrically connects only a selected wiring between said circuits. 8. The semiconductor device according to claim 1, wherein said switching circuit is programmable. 9. The semiconductor device according to claim 1, wherein said second wiring includes signal lines having the same length. 10. A semiconductor device comprising: a first wiring layer formed on a chip; and a second wiring layer formed above the first wiring layer, and a first electrode formed on the first wiring layer. When the number is M, the number of second electrodes formed on the second wiring layer is N, and when the first and second electrodes receive the same signal, M
A semiconductor device satisfying the condition of> N ≧ 1.