JP2015534263A - Method and apparatus for routing die signals using external wiring - Google Patents

Abstract

Various aspects of an approach for routing die signals at the inner portion of die (152) using external wiring (202 + 222 + 212) are described herein. This approach provides contacts (102, 112) coupled to the circuitry of the inner portion of die (152), which are exposed on the outer portion of die (152). External wiring (202 + 222 + 212) is routed to these contacts (102, 112) for signals from the circuitry inside the die (152) to be routed from the outside to the die (152) and reinserted into the die (152). ). In various aspects of the disclosed approach, the external wiring (202 + 222 + 212) is protected by packaging (252) for the die (152). A test circuit configured to couple the circuit during the test mode is foreseen at the inner portion of the die (152). [Selection] Figure 1

Description

Cross-reference to related applications

  [0001] This application claims the priority and interest of provisional patent application 61/696092 entitled "METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS" filed with the US Patent and Trademark Office on August 31, 2012. The entire contents of which are hereby incorporated by reference.

  [0002] Aspects of the present disclosure relate generally to integrated circuits, and more specifically to a method and apparatus for routing a die signal using an external interconnect.

  [0003] Efficient routing of various signals in modern integrated circuits has many challenges, including ensuring proper timing of signal distribution, minimizing crosstalk, and matching impedance. To meet the real estate, which has all been reduced by a higher component count than ever before, while overcoming it. Clock signal routing is particularly important because these signals are used to synchronize different data signals arriving from different parts of the integrated circuit. However, due to the impedance present in the wiring, the various spatial distances between the clock source and the position of the circuit coupled to this clock source will cause a delay in the arrival time of the clock signal at various locations in the integrated circuit. Often there is a match. These inconsistencies in timing are known as clock cues. Also, a clock signal that reaches two different locations with the same clock input due to noise caused by other wiring, such as run in parallel with the clock signal line, is also commonly referred to as clock jitter. You can experience the phase noise known as

  [0004] A clock distribution network (CDN) can be used to ensure constraints on the clock queue, and jitter is minimized. Other considerations such as fast transition times and balanced duty cycle also need to be taken into account. The CDN can be designed using different techniques such as H-tree, buffer clock tree, balanced clock tree, mesh clock network. However, the task of designing an efficient CDN is the task of using these techniques because the wiring does not scale in proportion to the feature size of a rapidly scaling transistor operating at a high clock frequency. Even so, it has become even more difficult. For example, just using clock tree balancing is increasingly insufficient because clock buffer mismatch due to intra-die process variations limits the ability to minimize skew. Also, typical H-trees are not well suited for distributing clocks into asymmetric and irregularly shaped clock domains, but rather add additional complexity to integrated circuit floor planning and layout. In addition, skew reduction techniques for existing H-tree distribution are hampered by high power consumption and inefficient use of wiring. Another approach performs skew compensation at the source independently for each leaf. However, these approaches require long and varying lengths of reference lines that return from each leaf to the source, which introduces errors in skew correction due to the process dependent delay of each feedback line. In addition, as the difficulty in designing an efficient CDN increases at the end of the design, the CDN design is often finalized before the design of the remaining circuits in the integrated circuit can be completed. Must be done.

  [0005] Differential signaling is another approach that can be used to distribute clock signals. Although differential signaling is more efficient in many aspects compared to the clock tree approach, the implementation of this technique is more for use in the relatively complex circuitry required to provide differential signaling. Requires an area. Also, this is often valuable because careful routing is required to ensure low resistance of differential signals over long distances, and upper layers are often used to achieve this requirement. Consumes expensive routing resources. Yet another consideration is that differential signaling circuits require shielding and provisions that further reduce the desirability of this approach.

  [0006] With increasingly complex systems, reduced supply voltages, larger die sizes, and higher clock rates, clock distribution for modern integrated circuits is becoming more difficult to achieve. The desirability of overcoming the described problems has also become apparent.

  [0007] A simplified summary of one or more aspects of the disclosure is presented below to provide a basic understanding of such aspects. This summary is not an extensive overview of all possible features of the disclosure, and it may identify key or critical elements of all aspects of the disclosure, Nor is it intended to delineate the scope. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

  [0008] Various aspects of an approach for routing die signals at an interior portion of a die using an exterior interconnect are described herein. This approach provides contacts that are coupled to the circuitry of the inner portion of the die, and these contacts are exposed to the exterior portion of the die. The outer wiring is configured to couple these contacts so that signals from the circuitry on the inner portion of the die can be routed to the die from the outside. In various aspects of the disclosed approach, the outer wiring is protected by die packaging.

  [0009] In one aspect, the present disclosure provides an apparatus that includes a die that includes an outer portion and an inner portion that includes a plurality of circuits. The plurality of circuits in the inner portion includes a first circuit formed in the first area of the die and a second circuit formed in the second area of the die. The die has a first die exterior contact and a second die outer contact on the outer portion of the die, wherein the first die outer contact is electrically connected to the first circuit; The second die outer contact is electrically connected to the second circuit, the first die outer contact and the second die outer contact are electrically connected, and the second circuit is connected to the first circuit. And interconnects configured to couple, wherein the interconnects are located on the outer portion of the die.

  [0010] In another aspect, the present disclosure provides an apparatus that includes a die that includes an outer portion and an inner portion that includes a plurality of circuits. The plurality of circuits in the inner portion includes a first circuit formed in the first area of the die and a second circuit formed in the second area of the die. The die includes first die outer contact means and second die outer contact means on the outer portion of the die, wherein the first die outer contact means is electrically connected to the first circuit and the second die The die outer contact means is electrically connected to the second circuit, electrically connects the first die outer contact and the second die outer contact, and couples the second circuit to the first circuit. Wiring means configured to: wherein the wiring means is located on the outer portion of the die.

  [0011] In yet another aspect, the present disclosure provides a semiconductor device that includes a die that includes an outer portion and an inner portion that includes a plurality of circuits. The plurality of circuits in the inner portion includes a first circuit formed in the first area of the die and a second circuit formed in the second area of the die. The die includes a first die outer contact and a second die outer contact on the outer portion of the die, wherein the first die outer contact is coupled to the first circuit and the second die outer contact is the first die contact. A package including a wiring coupled to the first circuit and the second die outer contact and configured to couple the second circuit to the first circuit. Here, the package is located on the outer portion of the die.

  [0012] In yet another aspect, the present disclosure provides a method that includes exposing a plurality of contacts on an outer portion of a die, the plurality of contacts coupled to a first circuit. And a second contact coupled to the second circuit, the first circuit and the second circuit being in an inner portion of the die. The method combines at least two of the plurality of contacts via at least one wiring external to the die to connect the first circuit and the second circuit on the inner portion of the die. In addition.

  [0013] These or other aspects of the invention will be more fully understood upon review of the detailed description that follows.

  [0014] These and other exemplary aspects of the disclosure are described in the detailed description and the accompanying drawings that follow.

FIG. 1 is an exploded side view of an example of a die signal routing implementation for a semiconductor device assembly configured in accordance with various aspects of the disclosed approach. Figure 2 shows a diagram error! I can't find a reference. It is a top view of realization of die signal routing. FIG. 3 is an exploded side view of an example of an external die signal routing implementation configured in accordance with various aspects of the disclosed approach. Figure 4 shows a diagram error! I can't find a reference. FIG. 6 is a plan view of the realization of the external die signal routing. FIG. 5 is a block diagram of a conceptualized die signal routing implementation configured in accordance with various aspects of the disclosed approach. FIG. 6 is a flow diagram of a conceptualized die signal routing implementation configured in accordance with various aspects of the disclosed approach. FIG. 7 is a block diagram illustrating an example hardware implementation for an apparatus employing a processing system that may utilize a die signal routing implementation described in accordance with various aspects of the disclosed approach.

Detailed Description of the Invention

  [0022] In accordance with common practice, some of the drawings may be simplified for clarity. Thus, these drawings do not depict every component or method of a given apparatus (eg, device) and are not full scale. Finally, like reference numerals may be used to represent like features throughout the specification and drawings.

  [0023] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and represents the only configurations in which the concepts described herein can be implemented. Not intended. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

  [0024] FIG. 1 illustrates an exploded side view of a semiconductor device assembly 100 including a die 152 and a package 252 prior to being assembled in the manner described in detail herein. Although specific examples may be provided herein to describe the semiconductor device assembly 100 and other illustrated assemblies, various aspects of the disclosed approach may be applied to various integrated circuit packages. Note that it is possible. Therefore, these examples should not be considered limiting unless otherwise indicated. For example, the semiconductor device assembly 100 can be implemented as a single device or as part of a package on a package device assembly.

  [0025] The die 152 may be formed from a silicon wafer, where typically the individual discrete components and one or more of the die 152 are cut before the die 152 is cut from the silicon wafer and assembled into a package 252. The circuit is etched. Package 252 can be a casing made of metal, plastic, glass, and / or ceramic material to contain and protect die 152. Package 252 provides protection against shock and corrosion, holds contact pins or leads used to connect external circuitry to die 152, and dissipates heat generated by die 152. In one aspect of the disclosed approach, package 252 also includes a conductive wiring layer for routing signals that are normally routed within die 152. However, by extracting these signals from within die 152 and reinserting them into die 152, this approach of routing the signals provides great flexibility and reduced complexity in layout design. Provides valuable die area that would otherwise need to be reserved for these signals, increasing the operating speed and reliability of the routed signals.

  The die 152 includes first and second contact pillars 102, 112 that are exposed on the exterior surface 154 of the die 152. The first and second contact pillars 102, 112 may be coupled to one or more circuits of the inner portion of the die 152 via first and second traces 108, 118, respectively. For example, the first trace 108 is coupled to a clock signal generation circuit that generates a clock signal, and the second trace 118 is a clock of a memory circuit or I / O circuit that uses (ie, consumes) this clock signal. It can be coupled to a signal input. The first contact pillar 102 may be coupled to the output of the clock signal generation circuit, and the second contact pillar 112 may be coupled to the clock input of the memory circuit. Although the examples used herein may involve the distribution of a clock signal from a clock circuit to other circuits, various aspects of the disclosed approach are in addition to the clock and memory circuits described in the present system, It can also be applied to the distribution of other types of signals and the coupling of other types of circuits.

  [0027] In one aspect of the disclosed approach, a conductive path in the form of wiring is connected to the outside of the die 152 in the package 252 to connect the first contact pillar 102 to the second contact pillar 112. A signal such as a clock signal from the output of the clock signal generation circuit can be coupled to the clock signal input of the memory circuit. In the implementation illustrated in FIG. 1, the external conductive path is shown as a package wiring layer 222 in the package 252. This external conductive path avoids limitations in routing signals at the die 152 because it provides wiring layers that are separate from and separate from the various layers within the die 152.

  [0028] In one aspect of the disclosed approach, the respective electrical connections to the first and second contact pillars 102, 112 by the first and second package wiring layer contacts 202, 212 are the respective solder caps 104. , 114. Thus, in an implementation, the package 252 and die 152 assembly is such that the electrical connection between the first and second package wiring layer contacts 202, 212 and the first and second contact pillars 102, 112 is a solder cap 104, In order to be able to be done using 114, it involves placing the package 252 and die 152 in close physical proximity. The solder caps 104, 114 limit solder wicking during assembly, allow the use of less aggressive solder flux, and form a relatively smooth dome that minimizes lead content. It can be an eutectic solder cap that has been reflowed into The solder caps 104, 114 can also be lead-free solder, i.e. indium. In another aspect of the disclosed approach, thermal compression techniques can be used to form a connection between the contact pillar 102 and the package wiring layer contact 202. In yet another aspect of the disclosed approach, the connection between the contact pillar 102 and the package wiring layer contact 202 can be achieved using a conductive adhesive.

  FIG. 2 illustrates a routing scheme 200 that can be implemented using the package wiring layer 222 of FIG. 1 to route the clock signal generated by the phase-locked loop (PLL) circuit 162 in the die 152. Illustrate. The clock signal can be routed via a plurality of routes 222a-d, each of which is one or more of a respective plurality of contacts from various other circuits inside die 152 or Multiples can be used to couple to the clock signal. 2 is a combined view of both the die 152 and the package 252, the elements associated with the die 152, including the die 152 itself, are illustrated using dotted lines to more clearly distinguish the two. Will be done. For example, because PLL circuit 162 is associated with die 152, this PLL circuit 162 is represented using a dotted line.

  [0030] Further, FIG. 2 is a plan view, and the contact pillar on the die 152 connected to circuitry inside the die that consumes the clock signal, such as the second contact pillar 112, has a plurality of routes 222a-. These contact pillars are usually not visible from this point of view because they can be directly under d. However, as described in more detail herein, the second contact pillar 112 is illustrated to illustrate that the second contact pillar 112 is directly under at least one of the plurality of routes 222a-d. The exaggerated expression of would be used. Thus, other contact pillars connected to circuitry inside the die that consumes the clock signal are not visible in this view because they are covered by each one of the plurality of routes 222a-d. Note that can be configured in a manner similar to the second contact pillar 112.

  Referring also to FIG. 1, the package wiring layer 222 may include a plurality of routes 222 a-d including a route 222 c that can be coupled to the second contact pillar 112. Thus, the first contact pillar 102 that can be coupled to the clock signal generated by the PLL circuit 162 through the first trace 108 is a second contact that can be coupled to the memory circuit as described in the example of FIG. This clock signal may be passed to the pillar 112 through the route 222c. Thus, a memory circuit coupled to the second contact pillar 112 through the second trace 118 can use the clock signal from the first contact pillar 102.

  [0032] FIG. 2 also includes a plurality of contacts 182a-d that are not illustrated in FIG. 1 and correspond to contacts that allow access to circuitry within the die 152. These contacts can be connected to other pins (not shown) of the package 252 and are not electrically coupled to the plurality of routes 222a-d. Thus, the plurality of contacts 182 a-d can be contacts used for input / output (I / O), power, or other connections for the die 152. Note that the signal carried by the plurality of contacts 182a-d is different from the signal distributed to other locations in the die 152 using the package wiring layer 222, as described above. This is because the latter type of signals remain in the package 252 even if they are routed to the die 152 from the outside. Thus, unlike signals that are typically conducted through the package from the die to external circuitry, signals distributed using the various aspects disclosed herein are routed from the outside of the die, but are packaged. Can stay inside. As mentioned above, the approach of routing these signals from the outside to the die offers many advantages.

  [0033] Referring again to FIG. 1, first and second contact pillars 102, 112 provide mechanical and electrical connections to the exposed pad portions of the first and second traces 108, 118, respectively. Formed on respective first and second under-bump metallization (UBM) layers 106, 116. Thus, the first UMB layer 106 provides mechanical and electrical connection to the first contact pillar 102 to the exposed pad portion 108 ′ of the first trace 108, and the second UMB layer 116 includes the first UMB layer 116. A mechanical and electrical connection to the exposed pad portion 118 ′ of the second trace 118 is provided to the second contact pillar 112.

  [0034] The die 152 includes a passivation layer 110, which, together with the first and second UMB layers 106, 116, provides environmental protection for the die 152. As can be seen in this illustration, the passivation layer 110 covers the edges of both the exposed pad portion 108 ′ of the first trace 108 and the exposed pad portion 118 ′ of the second trace 118 and seals them. (Seal). The first and second UMB layers 106, 116 seal the openings in the passivation layer 110 and thus protect them while providing mechanical and electrical coupling to these pads, as described above.

[0035] In one aspect of the disclosed approach, the first and second contact pillars 102, 112 can be formed using cylindrical copper and can optionally be electroplated. Exemplary ranges of parameters associated with the first and second contact pillars 102, 112 include the following parameters:
-Pitch: current range is about 80-110 μm, low as about 60 μm;
-Diameter: 20-50 [mu] m; and-Height: 15-50 [mu] m;
Here, the pitch is the shortest distance between adjacent contact pillars when the center is measured from the center, the diameter is the diameter of the contact pillar, and the height is the height of the contact pillar.

  [0036] By using copper pillars instead of the more commonly used spherical leaded solder bumps, many undesirable side effects can be avoided. For example, the solder bump diameter is typically on the order of 100 μm, which requires a larger spacing (pitch) between the solder bumps, thereby reducing the interconnection density. Longer conductive paths through larger spheres also increase both the electrical and thermal resistance of any connection.

  [0037] The undissolved copper cylinder provides a larger die-to-package spacing than the solder bumps, thereby providing better stress relief. The high aspect ratio of the copper cylinder may also allow a narrower spacing (pitch) for a given height, thereby increasing the connection density. Often, no pressure is applied to the solder joints to provide a stronger mechanical connection between the die 152 and the package 252, to provide a heat bridge, and because of the different heating of the die 152 and the rest of the system. To ensure that, an electrically insulating adhesive is underfilled between them. If underfill is used, a higher height may allow for faster underfill flow and more uniform spreading. In addition, the stronger mechanical shear strength of copper compared to lead not only improves the strength of the connection, but also increases the overall durability of the semiconductor device assembly 100. The increased thermal conductivity of copper compared to lead also improves the thermal performance of this assembly.

  [0038] More importantly, the increased copper electrical conductivity and the first and second contact pillars 102, 112, the first and second package wiring layer contacts 202, 212, compared to lead, The relatively large size of package wiring layer 222 minimizes signal loss, and thus many different in die 152 without significant skew or jitter effects, even for critical signals such as clock signals. Can be distributed to locations. For example, the package wiring layer 222 is made of any appropriate conductive material, and may be as thick as 20 μm or thicker. This is much thicker than the typical value of the conductive layer in the die 152 which cannot be increased to about 10 μm in total. In various aspects of the disclosed approach, the thickness of the package wiring layer 122 is not limited. For example, the thickness of the package wiring layer 122 can be five times that of the die 152. Further, by allowing separate distribution of signals routed externally from die 152, crosstalk from other traces that are normally present can be effectively eliminated.

  FIG. 3 illustrates an exploded side view of another semiconductor device assembly 300 that includes a die 352 and a package 452. Die 352 and package 452 are similar to those described for die 152 and package 252 with the differences described below. In the example shown, instead of contact pillars, such as contact pillars 102, 112 of semiconductor device assembly 100, first and second traces 308, 318 are electrically connected through exposed pad portions 308 ', 318' of each trace. The contact bar 302 is exposed on the outer surface 354 of the die 352 for contact with the die. For example, the first trace 308 is coupled to a clock signal generation circuit that generates a clock signal, and the second trace 318 is a memory circuit that requires (ie consumes) the use of the clock signal at the clock signal input. A clock signal input may be coupled. Thus, the contact bar 302 can couple the output of the clock signal generation circuit with the clock input of the memory circuit.

  FIG. 4 illustrates a routing scheme 400 that may be implemented using the contact bar 302 of FIG. 3 to route the clock signal generated by the phase locked loop (PLL) circuit 362 in the die 352. To do. The clock signal can be routed through a plurality of contact bars 302a, b, each of which is one of each of a plurality of contacts from various other circuits inside the die 352. Can be used to couple to the clock signal. Since FIG. 4 is a combined view of both the die 352 and the package 452, in order to more clearly distinguish the two, the elements associated with the die 352 including the die 352 itself are illustrated using dotted lines. Will be done. For example, because PLL circuit 362 is associated with die 352, PLL circuit 362 is represented using a dotted line.

  [0041] Further, FIG. 4 is a plan view, with exposed pad portions on die 352 connected to circuitry inside the die that consumes the clock signal, such as exposed pad portion 318 'of second trace 318. Can be directly below the plurality of contact bars 302a, b, so that these exposed pad portions are usually not visible from this point of view. However, as will be described in more detail herein, an exaggerated representation of the exposed pad portion to illustrate that the exposed pad portion 318 'is directly under at least one of the plurality of contact bars 302a, b. Would be used. Thus, other exposed pad portions connected to circuitry inside the die that consumes the clock signal are seen in this figure because they are covered by each one of the plurality of contact bars 302a, b. However, it should be noted that it may be configured in the same manner as the exposed pad portion 318 ′.

  [0042] For example, referring back to FIG. 3, the contact bar 302 includes a plurality of contact bars 302a, b including a contact bar 302b used to connect to the exposed pad portion 318 'of the second trace 318. May be included. Thus, the first trace 308, which can be coupled to the clock signal generated by the PLL circuit 362 through the connection from the exposed pad portion 308 ′ of the first trace 308 to the contact bar 302, converts the signal into the example of FIG. The second trace 318, illustrated as an exposed pad portion 318 'under the contact bar 302b, can be routed through the contact bar 302b and coupled to the memory circuit as described by. Thus, the memory circuit coupled to the second trace 318 can use the clock signal from the first trace 308.

  [0043] FIG. 4 also includes a plurality of contacts 382a-b that are not illustrated in FIG. 3 and correspond to contacts that allow access to circuitry within die 352. These contacts can be connected to other pins and are not electrically coupled to contact bars 302a, b. Thus, the plurality of contacts 382a-b can be contacts used for input / output (I / O), power, or other connections for the die 352. Again, as described with respect to FIG. 2, the signal carried by the plurality of contacts 382a-b is distributed to other locations within the die 352 using the contact bar 302 as described above. Note that this is different from the signal being generated. This is because the latter type of signal remains in the package 452 even when they are routed to the die 352 from the outside. Thus, unlike signals that are typically conducted through the package from the die to external circuitry, signals distributed using the various aspects disclosed herein are routed from the outside of the die. Can stay in the package. As mentioned above, the approach of routing these signals from the outside to the die offers many advantages.

  [0044] Like the die 152, the die 352 includes a passivation layer 310 that, along with the UMB layer 306, provides environmental protection to the die 352. As can be seen in FIG. 3, the passivation layer 310 can cover and seal the edges of both the exposed pad portion 308 ′ of the first trace 308 and the exposed pad portion 318 ′ of the second trace 318. The first and second UMB layers 306 seal the openings in the passivation layer 306 and thus protect them while providing them with mechanical and electrical coupling as described above.

[0045] In one aspect of the disclosed approach, the contact bar 302 can be formed using a plurality of copper contact pillars and can optionally be electroplated. Specifically, copper contact pillars similar to the first and second contact pillars 102, 112 of FIG. 1 can be placed sufficiently close to each other to form wiring. Specifically, as shown in FIG. 3, these copper contact pillars can form a copper “bar”. Exemplary ranges of parameters associated with contact bar 302 include the following parameters:
-Thickness: 20-50 [mu] m; and-Height: 20-50 [mu] m;
Here, the thickness is the thickness of the contact bar 302, which can be similar in size to the diameter range described above, and the height is the height of the contact bar. It should be noted that the contact bar 302 need not be configured as a bar, but can be made in other shapes, including non-straight shapes.

  [0046] FIG. 5 illustrates another aspect of the disclosed approach for externally routing die signals generated by one circuit in die 522 and used by other circuits in die 522. An exemplary circuit diagram 500 is illustrated. Specifically, the circuit diagram illustrates an approach for testing the die 522. In the example provided, a clock signal provided by a clock signal generation circuit such as PLL 512 may be transmitted to destination circuit 546 through external signal route 502. For example, destination circuit 546 may be a memory circuit that uses a clock signal from PLL 512 to operate properly. The external signal route 502 can be one of the approaches described above. For example, the external signal route 502 may be the package wiring layer 222 introduced in FIG. 1 or the contact bar 302 introduced in FIG. In order for the destination circuit 546 to be coupled to the PLL 512 using the external signal route 502, the package in which the package wiring layer is located (or the contact bar formed on the die) needs to be coupled to the die 522. is there. However, this means that if the package routing approach is used, the die 552 is assembled with the package before it is tested, or if the connector bar routing approach is used, the connector bar The die 552 needs to be processed for inclusion, which wastes assembly / processing resources if it is ultimately determined that the die 522 is incomplete.

  [0047] In one aspect of the disclosed approach, a secondary signal path 580 can be provided separate from the primary signal path 510 to allow testing of the die 522 prior to assembly into a package. For example, the secondary signal path 580 is used to test the die 522 before the die 522 is integrated with the package, or a second clock that is further processed to add an external signal route 502. It can be a route. Secondary signal path 580 need not be at a full operating clock frequency, but includes a plurality of repeaters 582-1-n that can be operated at a clock frequency sufficient to test die 522. Both primary signal path 510 and secondary signal path 580 may be coupled to multiplexer (MUX) 542. MUX 542 may selectively send the appropriate signal based on whether die 522 is under test (secondary signal path 580) or under normal operating mode (primary signal path 510). In one aspect of the disclosed approach, MUX 542 may be controlled programmatically or through an automated test equipment vector.

  [0048] With respect to external signal route 502, die 552 includes a pair of diodes 524 in addition to repeater 522 to transmit a signal to a receiver including a pair of diodes 534, 536 and a resistive element 538 coupled to repeater 532. , 526 and a transmitter including a resistive element 528. These elements can be optional because they can be used to provide electrostatic discharge protection to the die 552 and are not directly related to providing clock signal functionality.

  [0049] FIG. 6 illustrates a process 600 for constructing a die, such as die 152, for routing die signals using external wiring, where at 602, multiple contacts are on the outer portion of the die. Exposed, wherein the plurality of contacts includes a first contact coupled to the first circuit and a second contact coupled to the second circuit, wherein the first and second contacts This circuit is in the inner part of the die. Thus, a plurality of contacts, such as the first and second contact pillars 102, 112, are exposed to an outer portion of the die, such as the outer surface 154 of the die 152. A plurality of contacts may be formed in accordance with various aspects of the disclosed approach, as described above, and coupled to circuitry on the inner portion of the die.

  [0050] At 604, at least two of the plurality of contacts are coupled via at least one wiring external to the die to connect the first and second circuits on the outer portion of the die. The Thus, two or more of the plurality of contacts on the outer portion of the die are interconnects such as package interconnect layer 222 in package 252 for coupling first and second contact pillars 102 and 112. Can be combined. In one aspect of the disclosed approach, the wiring can be located in a device package, such as package 252. In another aspect of the disclosed approach, the wiring may be a conductor, such as the contact bar 302 of the die 352 formed on the outer portion of the die, such as the outer surface 354 of the die 352.

  [0051] Various aspects of the disclosed approach not only provide flexibility in configuring routing, but also like space and interference problems when signals must be routed inside the die. Avoid problems. For example, the use of external wiring allows routing of signals normally routed inside the die, such as clock signals, to be routed outside the die.

  [0052] For purposes of simplifying the description of various aspects of the disclosed approaches, specific elements and layers such as semiconductors, additional passivation layers, and metal layers are not shown. Further, common materials that can be used to construct the various illustrated assemblies are not described as they are naturally known by those skilled in the art.

  [0053] It is to be understood that the specific order or hierarchy of steps in the disclosed methods is a diagram illustrating an exemplary process. It should be understood that a particular order or hierarchy in these methods can be rearranged based on design preferences. The accompanying method claims present elements of the various steps in a sample order, and are limited to the particular order or hierarchy presented, unless explicitly stated herein. Is not intended to be.

  [0054] FIG. 7 is a conceptual diagram illustrating an example hardware implementation for an apparatus 700 employing a processing system 710 that may utilize various aspects of the disclosed approach for external signal routing of die signals in a semiconductor device. It is. Thus, according to various aspects of the present disclosure, an element or any portion of an element or any combination of elements in apparatus 700 that may be used to implement any device, including a wireless node, The external die routing approach described herein may be utilized. The description of the apparatus 700 included herein is meant to provide a non-limiting example of how various aspects of the disclosed approach can be used to serve a variety of devices. To do.

  [0055] For example, the processing system 710 includes one or more processors, exemplified as the processor 714. Examples of processor 714 include a microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), state machine, gate logic, discrete hardware circuitry, and the entire disclosure. Other suitable hardware configured to perform the various functions described throughout are included. A processor, such as processor 714, typically includes various subsystems formed on a die, where these various subsystems need to be distributed across various portions of the die. Depending on the clock signal. In accordance with various aspects of the disclosed approach, the clock signal can be distributed externally to the dies in the package using at least one wiring external to the die. External routing may not only reduce the clock skew and phase offset of the clock signal being distributed in the processor 714, but also increase the available space in the inner portion of the die. Note that in addition to processor 714 of processing system 710, any integrated circuit in apparatus 700 may utilize external routing techniques in an advantageous manner.

  [0056] Processing system 710 may be implemented as having a bus architecture represented generally by bus 712. Bus 712 may include any number of interconnect buses and bridges, depending on the specific application of processing system 710 and the overall design constraints. Bus 712 links various circuits together, including one or more processors (generally represented by processor 718), memory 718, and computer-readable media (generally represented by computer-readable medium 716). Bus 712 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits that are well known in the art and will not be described in more detail. Bus interface 720 provides an interface between bus 712 and transceiver 750. The transceiver 750 may provide a means for communicating with various other devices over a transmission medium. Depending on the nature of the device, a user interface 730 (eg, keypad, display, speaker, microphone, joystick) may also be provided.

  [0057] The processor 714 is responsible for managing the bus 712 and general processing including execution of software that can be stored on the computer readable medium 716 or memory 718. This software, when executed by the processor 714, causes the processing system 710 to perform various functions described herein for any particular device. Software is called software, firmware, middleware, microcode, hardware description language, etc., and instructions, instruction set, code, code segment, program code, program, subprogram, software module, application, software It shall be interpreted broadly to mean applications, software packages, routines, subroutines, objects, execution files, execution threads, procedures, functions, etc.

  [0058] The computer-readable medium 716 or memory 718 may also be used to store data that is manipulated by the processor 714 in executing software. The computer readable medium 716 may be a non-transitory computer readable medium such as a computer readable storage medium. Non-transitory computer readable media include, by way of example, magnetic storage devices (eg, hard disks, floppy disks, magnetic strips), optical disks (eg, compact disks (CDs), digital versatile disks (DVDs)), Smart cards, flash memory devices (eg cards, sticks, key drives), random access memory (RAM), read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), registers, removable disks, and other suitable media for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media can also include, by way of example, carrier waves, transmission lines and other suitable media for transmitting instructions and / or software that can be accessed and read by a computer. Although illustrated as being within processing system 710, computer readable media 716 can reside external to processing system 710 or can be distributed across multiple entities including processing system 710. The computer readable medium 716 may be embodied in a computer program product. By way of example, a computer program product may include a computer readable medium of packaging material. Those skilled in the art will recognize how best to implement the described functionality shown throughout this disclosure, depending on the particular application and the overall design constraints imposed on the overall system. .

  [0059] Those skilled in the art further recognize that the various illustrative logic blocks, modules, processors, means, circuits, and algorithm steps described in connection with the aspects disclosed herein are electronic hardware (eg, Various forms of program or design code (in this document for convenience, "software", which may be designed using source coding or some other technique, digital implementation, analog implementation, or a combination of the two), instructions It will be further appreciated that it may be implemented as a "" or "software module"), or a combination of both. To clearly illustrate this hardware and software compatibility, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such a function is realized as hardware or software depends on a specific application and design constraints imposed on the entire system. Those skilled in the art can implement the functions described above in various ways for each particular application, but such implementation decisions are interpreted as causing deviations from the scope of this disclosure. Should not.

  [0060] Are the various illustrative logic blocks, modules, and circuits described in connection with aspects disclosed herein implemented in an integrated circuit (IC), access terminal, or access point? Or may be performed by them. ICs are general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, electrical Designed to perform components, optical components, mechanical components, or the functions described herein, and execute code or instructions that reside in, outside of, or both in an IC Any combination of these may be provided. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices such as, for example, a DSP and a macro processor, a plurality of microprocessors, one or more microprocessors associated with a DSP core, or other combinations of the above configurations. .

  [0061] It is understood that any specific order or hierarchy of steps in the disclosed processes is an example of an exemplary approach. It is understood that based on design preferences, a particular order or hierarchy of steps in the process can be rearranged while remaining within the scope of this disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not intended to be limited to the specific order or hierarchy presented.

  [0062] The algorithm or method steps described in connection with the aspects disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. Software modules (eg, including executable instructions and associated data) and other data include data such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM It may reside in memory, or any other form of computer readable storage medium known in the art. An exemplary storage medium is, for example, a computer / processor (referred to herein as a “processor” for convenience) so that the processor can read information (eg, code) from the storage medium and write information to the storage medium. ). An exemplary storage medium may be integral to the processor. A processor and a storage medium may reside in the ASIC. The ASIC can reside in the user equipment. In the alternative, the processor and the storage medium may reside as discrete components in user equipment. Further, in some aspects, any suitable computer program product comprises a computer-readable medium comprising code (eg, executable by at least one computer) associated with one or more of the aspects of the present disclosure. sell. In some aspects, the computer program product may comprise packaging material.

  [0063] The previous description is provided to enable any person skilled in the art to implement the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to be limited to the embodiments shown herein, but are to be given the full scope consistent with the language of the claims, where singular Reference to an element is not intended to mean "one or more", unless expressly stated otherwise, but rather to mean "one or more". Unless otherwise specified, the term “some” refers to “one or more”. An expression referring to “at least one of” a list of items refers to any combination of those items including a single member. By way of example, “at least one of a, b, or c” is intended to cover a, b, c, a and b, a and c, b and c, a and b and c. . All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that will be known or later known to those skilled in the art are expressly incorporated herein by reference. And is intended to be encompassed by the following claims. Moreover, nothing disclosed herein is intended to be publicly contributed, whether or not such disclosure is expressly recited in the claims. An element of a claim is not specifically stated using the expression “means for” or, in the case of a method claim, the element is “for Unless stated using the expression “step”, none should be construed under the provisions of 35 USC 112,6.

Claims (37)

A device,
A die comprising an outer portion and an inner portion comprising a plurality of circuits, wherein the plurality of circuits of the inner portion comprises:
A first circuit formed in a first area of the die;
A second circuit formed in a second area of the die; and
A first die outer contact and a second die outer contact on the outer portion of the die, wherein the first die outer contact is electrically connected to the first circuit; A die outer contact is electrically connected to the second circuit;
A wiring configured to electrically connect the first die outer contact and the second die outer contact and to couple the second circuit to the first circuit, wherein the wiring is Located on the outer portion of the die;
A device comprising:   The apparatus of claim 1, wherein the wiring comprises at least one of copper or aluminum.   The apparatus of claim 1, wherein the wiring comprises a plurality of conductive pillars.   The apparatus of claim 3, wherein the plurality of conductive pillars are formed as adjacent columns that are in physical contact with each other to form a rod.   The apparatus of claim 1, wherein the die and the wiring each have a thickness, and the thickness of the wiring is at least five times the thickness of the die.   The apparatus of claim 1, further comprising a package, wherein the die is supported by the package, and the package comprises the wiring.   The apparatus of claim 6, wherein the wiring comprises a layer of conductive material formed on the package.   The apparatus of claim 6, wherein a signal generated by the first circuit and provided to the second circuit remains between the package and the die.   The apparatus of claim 6, wherein a signal generated by the first circuit and provided to the second circuit remains in the package.   The apparatus of claim 1, wherein at least one of the first die outer contact and the second die outer contact comprises a copper pillar.   The first die outer contact and the second die outer contact are further coupled to a wiring layer under the outer portion of the die, and the wiring layer connects the first die outer contact to the first die. The apparatus of claim 1, wherein the apparatus is configured to separately couple the second die outer contact to the circuit to the second circuit.   The apparatus of claim 1, wherein the first circuit comprises a signal source and the second circuit comprises a signal sink.   The apparatus of claim 12, wherein the signal source is a clock circuit.   The apparatus of claim 1, wherein the first circuit comprises a clock generator configured to provide a clock signal.   The apparatus of claim 1, wherein the plurality of circuits of the inner portion of the die further comprises a test circuit configured to couple the first circuit and the second circuit during a test mode.   16. The test circuit of claim 15, comprising a multiplexer configured to allow selection from the test circuit and the wiring to couple the first circuit and the second circuit. Equipment.   The apparatus of claim 15, wherein only the test circuit couples the first circuit and the second circuit during the test mode.   The apparatus of claim 15, wherein the test circuit is not operable to couple the first circuit to the second circuit except during the test mode. A device,
A die comprising an outer portion and an inner portion comprising a plurality of circuits, wherein the plurality of circuits of the inner portion comprises:
A first circuit formed in a first area of the die;
A second circuit formed in a second area of the die; and
First outer contact means and second outer contact means on the outer portion of the die, wherein the first outer contact means is electrically connected to the first circuit and the second outer contact means; The outer contact means is electrically connected to the second circuit;
Wiring means for electrically connecting the second circuit to the first circuit, wherein the wiring means is located on the outer portion of the die; and
An apparatus comprising:   The apparatus of claim 19, wherein the wiring means comprises at least one of copper or aluminum.   The apparatus according to claim 19, wherein the wiring means includes a plurality of conductive pillars.   The apparatus of claim 21, wherein the plurality of conductive pillars are formed as adjacent columns that are in physical contact with each other to form a rod.   20. The apparatus of claim 19, wherein the die and the wiring means each have a thickness, and the thickness of the wiring means is at least five times the thickness of the die.   20. The apparatus of claim 19, further comprising a package, wherein the die is supported by the package, and the package comprises the wiring means.   25. The apparatus of claim 24, wherein the wiring means comprises a layer of conductive material formed in the package.   25. The apparatus of claim 24, wherein a signal generated by the first circuit and provided to the second circuit remains between the package and the die.   25. The apparatus of claim 24, wherein a signal generated by the first circuit and provided to the second circuit remains in the package.   The apparatus of claim 19, wherein at least one of the first outer contact means and the second outer contact means comprises a copper post.   The first outer contact means and the second outer contact means are further coupled to a wiring layer under the outer portion of the die, and the wiring layers respectively connect the first outer contact means to the first outer contact means. 21. The apparatus of claim 19, wherein the apparatus is configured to separately couple the second outer contact means to a second circuit.   The apparatus of claim 19, wherein the first circuit comprises means for generating a signal and the second circuit comprises a signal sink.   32. The apparatus of claim 30, wherein the means for generating the signal is a clock circuit.   20. The apparatus of claim 19, wherein the plurality of circuits in the inner portion of the die further comprises test means configured to couple the first circuit and the second circuit during a test mode.   33. The multiplexer of claim 32, wherein the test means comprises a multiplexer configured to allow a selection from a test circuit and the wiring means to couple the first circuit and the second circuit. Equipment.   33. The apparatus of claim 32, wherein only the test means couples the first circuit and the second circuit during the test mode.   33. The apparatus of claim 32, wherein the test means is inoperable to couple the first circuit to the second circuit except during the test mode. A semiconductor device,
A die comprising an outer portion and an inner portion comprising a plurality of circuits, wherein the plurality of circuits of the inner portion comprises:
A first circuit formed in a first area of the die;
A second circuit formed in a second area of the die; and
A first die outer contact and a second die outer contact on the outer portion of the die, wherein the first die outer contact is coupled to the first circuit and the second die outer contact; Is coupled to the second circuit;
A package coupled to the first die outer contact and the second die outer contact and comprising wiring configured to couple the second circuit to the first circuit, wherein the package comprises: Located on the outer portion of the die;
A device comprising: A method,
Exposing a plurality of contacts on the outer portion of the die, wherein the plurality of contacts are a first contact coupled to the first circuit and a second contact coupled to the second circuit; The first circuit and the second circuit are in an inner portion of the die,
In order to connect the first circuit and the second circuit of the inner portion of the die, at least two contacts of the plurality of contacts are connected via at least one wiring outside the die. A method comprising: combining.

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