JPH05190673A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a delay circuit which can adjust the timing by utilizing an output signal of an inverter circuit in the final stage as an input signal of an internal circuit and then connecting a bonding pad to an external lead in order to supply a timing-adjusted external input signal thereto. CONSTITUTION:A polysilicon layer as a first layer which is formed integrally with a gate electrode of an inverter circuit N3 is connected with a bonding pad P2. An output of the inverter N3 is connected, through a contact, with a polysilicon layer forming a gate electrode of an inverter circuit N4 in the latter stage. The inverter circuits N5, N6 of the third stage are also formed in the same manner as the second inverter circuit and the polysilicon layer as the first layer formed integrally with a gate electrode of the inverter circuit N5 in the input side is connected by a bonding pad P3. A timing-adjusted delay signal to be sent to an internal circuit is outputted from an output terminal OUT of an inverter circuit N6 in the latter stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effectively used for a device including a delay circuit capable of adjusting the timing of an external input signal.

[0002]

2. Description of the Related Art In the development and design of a semiconductor integrated circuit device, roughly speaking, the number of stages of a delay inverter circuit is determined for timing adjustment by circuit simulation or the like, and a photomask is prepared and applied to a product. Then, in the actual circuit evaluation, when the timing is shifted, the correction from the photomask is performed again. Regarding the development and design technology of such a semiconductor integrated circuit device, Ohm Co., Ltd.
December 25, 1985, page 107 to page 139 of "Microcomputer Handbook".

[0003]

If a deviation occurs in the actual circuit evaluation due to the timing adjustment or the like as described above, it is necessary to modify the circuit from the photomask again, which increases the number of development steps. Further, there is a problem that mass-produced products become defective due to process variations. An object of the present invention is to provide a semiconductor integrated circuit device having a delay circuit capable of timing adjustment with a simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of inverter circuits connected in a cascade form, and a bonding pad that supplies an input signal to the input of the first-stage inverter circuit and the input of the inverter circuit arranged in the middle are formed in advance.
Connect one of the bonding pads to the external lead depending on the timing adjustment.

[0005]

According to the above-mentioned means, the input signal supplied from the external terminal by the selective connection to the external lead in the bonding process according to the result of the circuit evaluation in the probing process after the circuit is formed on the semiconductor wafer. Since it is possible to determine the delay time corresponding to the number of the inverter circuit rows in which the transmission is performed, it is possible to adjust the timing without correction from the photomask.

[0006]

1 is a circuit diagram of an embodiment of an input circuit in a semiconductor integrated circuit device according to the present invention.
Shows a layout diagram of one embodiment corresponding thereto. Although not particularly limited, each circuit element in the same drawing is formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. The integrated circuit is formed on a semiconductor substrate made of, for example, single crystal P-type silicon. The N-channel MOSFET is formed by forming a source region, a drain region, and a semiconductor substrate (channel region) surface between the source region and the drain region on the surface of the semiconductor substrate through a thin gate insulating film. It is composed of a gate electrode made of silicon. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon.

In the input circuit of FIG. 1, two inverter circuits N1 and N2, N3 and N4, N5 and N6 are connected in series as a set. The input of the first set of input-side inverter circuits N1 is connected to the bonding pad P1. The second and third intermediate input-side inverter circuits N
The inputs of 3 and N5 are connected to bonding pads P2 and P3, respectively. Then, an input signal to be supplied to an internal circuit (not shown) is formed from the output OUT of the final stage inverter circuit N6.

In FIG. 2, the first-stage inverter circuit N1
P-channel MOSFET and N-channel MOS
In the gate of the FET, the first polysilicon layer forming the gate electrode extends as it is and is connected to the bonding pad P1. The output of this first-stage inverter circuit N1 is
Guided by the wiring shown by the solid line, it is connected to the first polysilicon layer forming the gate electrode of the next-stage inverter circuit N2 by the contact C4. The inverter circuit N1
In the two inverter circuits composed of N2 and N2, the sources of the P-channel type MOSFET and the N-channel type MOSFET are configured by a common diffusion layer, respectively, and although not shown, the source of the N-channel type MOSFET is given the ground potential of the circuit, The power supply voltage VCC is applied to the source of the P-channel MOSFET together with the N-type well region in which the P-channel MOSFET is formed.

The output of the inverter circuit N2 on the output side of the first group is guided by the wiring shown by the solid line to form a contact C5.
Thus, it is connected to the first polysilicon layer forming the gate electrode of the second-stage inverter circuit N3 in the preceding stage. The first polysilicon layer formed integrally with the gate electrode of the inverter circuit N3 extends as it is and is connected by the bonding pad P2. This inverter circuit N3
The output of the contact C is guided by the wiring shown by the solid line.
6 is connected to the first polysilicon layer forming the gate electrode of the inverter circuit N4 in the subsequent stage. In the two inverter circuits consisting of the inverter circuits N3 and N4, the sources of the P-channel type MOSFET and the N-channel type MOSFET are each formed of a common diffusion layer, and the source of the N-channel type MOSFET is connected to the ground potential of the circuit. Is given, and a P-channel MOSFET is formed at the source of the P-channel MOSFET N
Power supply voltage VCC is applied together with the type well region.

The third set of inverter circuits N5 and N6 are also constructed in the same manner as the first and second set of inverter circuits, and are integrated with the gate electrode of the input side inverter circuit N5. The first-layer polysilicon layer formed in (1) is extended as it is and is connected by the bonding pad P3, and a delay signal whose timing is adjusted and which is transmitted to the internal circuit is output from the output terminal OUT of the inverter circuit N6 in the subsequent stage.

According to the result of the circuit evaluation in the probing process, when the delay time is set to the maximum, the bonding pad P1 is selected and connected to the external lead in the bonding process. As a result, the external input signal input via the external lead is delayed by the first set of inverter circuits N1 and N2, the second set of inverter circuits N3 and N4, and the third set of inverter circuits N5 and N6. It is transmitted to the internal circuit.

According to the result of the circuit evaluation in the probing process, when the delay time is set to the intermediate value, the bonding pad P2 is selected and connected to the external lead in the bonding process. As a result, the external input signal input through the external lead passes through the first set of inverter circuits N1 and N2 and the second set of inverter circuits N1 and N2.
It is delayed by the third and third inverter circuits N5 and N6 and transmitted to the internal circuit. At this time, the output side inverter circuit N2 of the first set is not particularly limited.
By setting its current drive capacity small,
It is set so as not to adversely affect the input signal input through the bonding pad P2. Normally, the external input signal is made to have a large current capacity for driving a relatively large load such as the input capacitance of the semiconductor integrated circuit device or the wiring capacitance on the mounting substrate. Therefore, the input signal of the inverter circuit N3 is In most cases, no problem occurs because it is determined by the external lead and the external input signal input through the bonding pad P2 regardless of the output of the inverter circuit N2.

In order to prevent the input signal of the first set of inverter circuits from floating and a through current or the like between the power supply voltage and the ground potential of the circuit to occur, the bonding pad P1 and the ground potential of the circuit are prevented. In addition, a pull-down resistor R1 having a high resistance is provided. Instead of this, a pull-up resistor may be provided between it and the power supply voltage VCC. This means that the other bonding pads P2, P
Also in 3, the similar resistors R2 and R3 are provided. The resistors R1 to R3 are omitted in FIG. It should be noted that the inverter circuit N2 is provided by providing the pull-down resistor R1.
Output a low level steadily, and when a high level input signal is supplied from the bonding pad P2, an N-channel type MOSFET of the inverter circuit N2.
In order to prevent the DC current from flowing constantly, the wiring a connecting the output of the inverter circuit N2 on the output side of the first set and the input of the inverter circuit of the second set is cut by a laser beam or the like. It may be.

According to the result of the circuit evaluation in the probing process, when the delay time is set to the minimum, the bonding pad P3 is selected and connected to the external lead in the bonding process. As a result, the external input signal input through the external lead is transmitted to the first set of inverter circuits N1 and N2 and the second set of inverter circuits N3.
The signal is passed through N4, delayed by the third set of inverter circuits N5 and N6, and transmitted to the internal circuit. At this time, similarly to the above, the wiring b that connects the output of the inverter circuit N4 on the output side of the second set and the input of the inverter circuit of the third set is cut to prevent the generation of direct current. May be.

FIG. 3 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.
Although not particularly limited, each circuit block in the figure is formed on a semiconductor substrate such as single crystal silicon by a known Bi-CMOS circuit technique.

An address signal consisting of a plurality of bits consisting of the address signals A0 to An is supplied to the address buffers AB0 to AB0.
Informed to ABn. These address buffers AB0
The address signal taken in by ABn is transmitted to the decoder DC.
Informed to R. Of the decoder DCR, the decoder circuit corresponding to the X-system address signal decodes the address signal and forms a word line selection signal. The word line selection signal is output via a word driver (not shown). By providing such a word driver, a large number of memory cells are coupled to each other so that a word line having a relatively large load capacity can be switched between high speed and low speed.

The memory array M-ARY is constructed by arranging static type MOS memories in a matrix.
That is, memory cells are arranged at the intersections of the data lines and the word lines. In addition to the complete CMOS static type, the memory cell may use a memory MOSFET and a high resistance element formed on the drain of the information storage polysilicon layer. The decoder D
Of CRs, a decoder circuit corresponding to a Y-system address signal decodes the address signal and forms a data line selection signal. The data line selection signal is transmitted to the Y selection circuit (column switch). The Y selection circuit connects the data line of the memory array M-ARY to the common data line according to the selection signal of the data line. It should be understood that such a Y selection circuit and a common data line are also included in the memory array M-ARY.

The read signal of the common data line is supplied to the sense amplifier SA, where it is amplified at high speed. The amplified output signal of the sense amplifier SA is sent from the input / output terminal I / O through the data output circuit included in the input / output circuit IOB. Further, the write data supplied from the input / output terminal I / O is taken in through the data input circuit included in the input / output circuit IOB and written in the selected memory cell via the common data line.

The chip select signal CSB, the write enable signal WEB and the output enable signal OEB are supplied to the timing control circuit TG via the input buffers. The timing control circuit TG receives the above control signals passed through the input buffer and receives the address buffer activation signal AE necessary for the operation of the internal circuit, the activation signal SAC of the sense amplifier, the data input circuit and the data output circuit. And the activation signal DIC / DOC of

The delay circuit capable of adjusting the timing as described above constitutes the input circuits B1 to B3 for the chip select signal CSB, the write enable signal WEB and / or the output enable OEB. These control signals are activation signals A that activate the address buffers AB0 to ABn.
E, which is used to form an internal timing signal of the activation signal SAC of the sense amplifier and the activation signal DIC / DOC of the data input circuit and the data output circuit, and the operation timing of each circuit can be optimally adjusted by the timing adjustment. Will be things.

The effects obtained from the above embodiment are as follows. That is, a bonding pad that supplies an input signal to the input of the first-stage inverter circuit and the input of the intermediate-stage inverter circuit in the inverter circuit composed of a plurality of inverter circuits connected in tandem is formed and bonded to the external lead. At this time, one is selected to obtain the signal taken in the internal circuit from the output of the final stage inverter circuit. With this configuration, the number of inverter circuit rows to which the external input signal is transmitted can be determined in the bonding step performed after that according to the result of the circuit evaluation in the probing step after the circuit is formed on the semiconductor wafer. The effect that the timing can be adjusted without correction from is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In FIG. 2, the number of inverter circuits may be set to two sets, four sets or more, or a tap may be provided at a connection point of each inverter circuit. In this case, the delay time can be selected and the signal can be inverted. In FIG. 2, various aluminum wirings are directly extended from the bonding pads P1 to P3 and are connected to the first-layer polysilicon gate, which is an input of each inverter circuit N1, N3, N5, etc., through a contact portion. Embodiments can be adopted. The semiconductor integrated circuit device of this embodiment is used not only for photomask debugging in a developed product, but also for various applications such as application to a mass-produced product to correct or adjust timing deviation due to lot variation. You can The present invention can be widely used for various semiconductor integrated circuit devices that require timing adjustment.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a bonding pad that supplies an input signal to the input of the first-stage inverter circuit and the input of the intermediate-stage inverter circuit in the inverter circuit composed of a plurality of inverter circuits connected in tandem is formed and bonded to the external lead. At this time, one is selected to obtain the signal taken in the internal circuit from the output of the final stage inverter circuit. With this configuration, the number of inverter circuit rows to which the external input signal is transmitted can be determined in the bonding step performed after that according to the result of the circuit evaluation in the probing step after the circuit is formed on the semiconductor wafer. The timing can be adjusted without any modification.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an input circuit according to the present invention.

FIG. 2 is a layout diagram of an embodiment corresponding to the circuit diagram of FIG.

FIG. 3 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

[Explanation of symbols]

P1 to P3 ... Bonding pads, R1 to R3 ... Pulldown resistors, N1 to N6 ... Inverter circuit, C4 to C8 ...
Contact part, AB0 to ABn ... Address buffer, B
1 to B3 ... Input circuit, DCR ... Address decoder, M-
ARY ... memory array, SA ... sense amplifier, IOB ...
Input / output buffer, TG ... Timing control circuit.

Claims (2)

[Claims] 1. A bonding pad is formed corresponding to an input of an inverter circuit of a first stage and an input of an inverter circuit arranged in the middle of the inverter circuit composed of a plurality of inverter circuits connected in a cascade form. A semiconductor integrated circuit characterized in that the output signal of the inverter circuit at the final stage is used as an input signal of an internal circuit, and one of the bonding pads is connected to an external lead to supply a timing-adjusted external input signal. Circuit device. 2. The inverter circuit arranged in the middle of the tandem form is provided with a bonding pad for supplying an input signal to the input of the inverter circuit on the preceding stage side, with two inverter circuits as a unit. The semiconductor integrated circuit device according to claim 1.