JPH10285012A - Semiconductor integrated circuit, electronic circuit device and input/output buffer test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the operation test of a simultaneous biderectional input/ output buffer. SOLUTION: An output buffer section 100 that drives an external load via an external terminal, an input buffer section 200 that discriminates a logic of a signal received via the external terminal by comparing a voltage level of the external terminal with a reference voltage level, transistors(TRs) 181, 182 that are coupled with the external terminal to realize an ON-resistance equal to an output impedance of the output buffer section, and a control logic section 183 that applies on/off control to the TRs when a test enable signal is asserted, thereby discriminating propriety based on the output logic of the input buffer section 200 by applying on/off control to the TRs 181, 182.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for simultaneous bidirectional communication of a semiconductor integrated circuit, a semiconductor integrated circuit for performing such communication, and a technology for testing a simultaneous bidirectional input / output buffer incorporated therein. The present invention relates to a technique which is effective when applied to an electronic circuit device equipped with a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In an electronic circuit device, for example, an electronic circuit device in which a plurality of LSIs are mounted on a printed circuit board, when data transfer between the plurality of LSIs is performed at high speed,
In order to suppress signal reflection, impedance matching of a data transmission system becomes important. For example, when the characteristic impedance of a transmission line for exchanging data between a plurality of LSIs is set to 50Ω, the impedance of an input / output buffer included in an LSI coupled to such a transmission line becomes 50Ω. Is set.

For impedance matching, a predetermined terminating resistor such as 50Ω is added. However, the output buffer MO
Since the S transistor is always coupled to the data input / output terminal, if the impedance seen from the outside of the data input / output terminal is 50Ω due to the ON resistance of the transistor of the output buffer, the terminating resistor is unnecessary. You. The value of the on-resistance can be changed by adjusting the gate width of the MOS transistor.

As an example of a document describing the impedance matching technique, a CMOS gate incorporating a 600 Mb / S simultaneous bidirectional I / O circuit published by the Institute of Electronics, Information and Communication Engineers on August 25, 1995 is disclosed. Array "(pages 1 to).

[0005]

In an electronic circuit device equipped with a plurality of semiconductor integrated circuits, bidirectional communication may be simultaneously performed on one transmission line in order to exchange data at high speed. For example, when two semiconductor integrated circuits are coupled via a transmission line, one semiconductor integrated circuit receives data from the other semiconductor integrated circuit even though data is being sent to the other semiconductor integrated circuit. Output data can be captured internally. Such a communication method is referred to as “simultaneous two-way communication”.

For example, as shown in FIG. 5, a first semiconductor integrated circuit (simply referred to as “first chip”) 4 and a second semiconductor integrated circuit (simply referred to as “second chip”) 5 form a transmission line 40. It is assumed that data is exchanged with each other via a network.

The simultaneous bidirectional input / output buffer included in the first chip 4 is configured as follows.

That is, the simultaneous bidirectional input / output buffer included in the first chip 4 includes a series connection circuit of n-channel MOS transistors 44 and 45, a prebuffer 41 for driving the same, and Vre for generating a reference voltage Vref.
An f generation circuit 42 and an input buffer 43 are included. The source electrode of the n-channel MOS transistor 44 is coupled to the high potential power supply voltage Vdd, and the source electrode of the n-channel MOS transistor 45 is coupled to the low potential power supply voltage Vss. The serial connection of the n-channel MOS transistors 44 and 45 is connected to the transmission line 40 via an external terminal 46 provided on the first chip 4.
Is combined with

The pre-buffer 41 has an enable signal E
N * (* indicates low active) and transmission data S
IN is input. While the enable signal is asserted, the n-channel MOS transistors 44 and 45 are driven based on the transmission data SIN transmitted from an internal circuit (not shown) at the preceding stage of the pre-buffer 41, so that the transmission data is transmitted. Can be transmitted. Vref
The generation circuit 42 generates the
The level of the reference voltage Vref is switched. The input buffer 43 takes in the signal transmitted via the transmission line 40 by a logical judgment based on the reference voltage Vref.

The simultaneous bidirectional input / output buffer included in the second chip 5 has the same configuration as that included in the first chip. That is, the simultaneous bidirectional input / output buffer included in the second chip 5 includes a series connection circuit of n-channel MOS transistors 54 and 55, a pre-buffer 51 for driving the same, and Vre for generating the reference voltage Vref.
An f generation circuit 52 and an input buffer 53 are included.

Assuming that the impedances of the output buffers of both the first chip 4 and the second chip 5 match the characteristic impedance of the transmission line 40, as shown in FIG. (Indicated by “H”), the level of the transmission line 40 is changed by the high-level output from the second chip 5 to the high potential side power supply Vdd.
And the low level (“L”) from the second chip 5
), The level of the transmission line 40 becomes Vdd × 1 /
There are two levels. When the first chip 4 outputs a low level, the level of the transmission line 40 is set to Vdd × １ ／ level by the high level output from the second chip 5, and the transmission is performed by the low level from the second chip 5. The level of the line 40 is set to the Vss level (0). Therefore, in the Vref generation circuit 42 included in the first chip 4, when the first chip 4 outputs a high level, the reference voltage Vref = Vdd × 3/4, and the first chip 4 outputs a low level. In the state, the reference voltage Vref = Vdd ×
By setting it to 1/4, the output logic from the second chip 5 can be correctly recognized.

An operation test of such a simultaneous bidirectional input / output buffer included in the first chip 4 is performed by using the external terminals 46 of the first chip 4 via the transmission line 40 as shown in FIG.
To the tester 6. Enable signal EN *
Is asserted, a high-level signal or a low-level signal is output from the first chip 4. Therefore, if this output logic level differs from the output logic level from the tester 6, the transmission line 40 An undesired current flows through. For example, the output logic of the first chip is high level,
When the output logic of the tester 6 is at a low level, an undesired current I46 flows through the transmission line 40. The driver 61 in the tester 6 may be damaged by such a current.

By negating the enable signal EN * and setting it in a high impedance state, it is conceivable to eliminate the above-mentioned undesired current flow. In this case, however, the reference voltage output from the Vref generation circuit 42 is reduced. Vr
The switching of the level of ef is not performed, and the test of the logic determination of the input signal by the switching of the level of the reference voltage Vref cannot be performed as described above. That is, the operation test of the simultaneous bidirectional input / output buffer is performed by the enable signal EN.
The output logic must be switched by asserting *.

An object of the present invention is to provide a technique which enables an operation test of a simultaneous bidirectional input / output buffer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an output buffer unit (100) for driving an external load via an external terminal (24-1)
And the voltage level of the external terminal is referred to as a reference voltage (Vref).
An input buffer unit (200) capable of determining the logic of a signal taken in through the external terminal by comparing with the level, and an on-resistance coupled to the external terminal and equal to the output impedance of the output buffer unit. A semiconductor integrated circuit is constituted by including a transistor group to be realized (181, 182) and a control logic (183) for turning on / off the transistor group in a state where the test enable signal is asserted.

According to the above means, the operation of the transistor group is controlled by the control logic,
A state equivalent to the simultaneous bidirectional input / output buffer of another semiconductor integrated circuit being coupled through the external terminal is formed, and this enables an operation test of the simultaneous bidirectional input / output buffer.

In a further specific aspect, an output buffer unit (100) for driving an external load via an external terminal
An input buffer unit (200) that can determine the logic of a signal fetched via the external terminal by comparing the voltage level of the external terminal with a reference voltage level;
A plurality of first transistors (85 to 8) coupled to the external terminal and the high potential side power supply and connected in parallel with each other.
9), selecting a plurality of second transistors (90 to 94) coupled to the external terminal and the low potential side power supply and connected in parallel with each other, and selecting the plurality of first transistors and the plurality of second transistors The first control logic (75-78, 81-84) for realizing an on-resistance equal to the output impedance of the output buffer unit by causing the test enable signal to be asserted in a state where the test enable signal is asserted. , And a second control logic (71-74) for controlling ON / OFF of the first transistor and the second transistor to constitute a semiconductor integrated circuit.

According to the above-described means, the first control logic selectively causes the plurality of first transistors and the plurality of second transistors to participate in a circuit operation, thereby controlling the output impedance of the output buffer unit. Realizing equal on-resistance, the second control logic controls on / off of the first transistor and the second transistor in a state where the test enable signal is asserted. As a result, a state equivalent to the simultaneous bidirectional input / output buffer of another semiconductor integrated circuit being coupled via the external terminal is formed, which enables the operation test of the simultaneous bidirectional input / output buffer. And

Further, the semiconductor integrated circuit on which the operation test of the simultaneous bidirectional input / output buffer has been performed as described above achieves an improvement in reliability, and such a semiconductor integrated circuit is mounted on a board, and By connecting the external terminal of the integrated circuit to the external terminal of another semiconductor integrated circuit mounted on the board to form an electronic circuit device, the reliability of the electronic circuit device can be improved. .

An output buffer unit (100) for driving an external load via an external terminal and a voltage level of the external terminal are compared with a reference voltage (Vref) level, so that the external buffer is connected to the external terminal. An input buffer unit (200) capable of determining the logic of a fetched signal; a transistor group (181, 182) coupled to the external terminal for realizing an on-resistance equal to the output impedance of the output buffer unit; A control logic (183) for controlling on / off of the transistors in a state where the signal is asserted, and by switching the reference voltage level according to a current output logic from the output buffer unit, As an input / output buffer test method in a semiconductor integrated circuit that enables simultaneous bidirectional communication with the outside, A first step of setting the output logic of the output buffer unit to a first logic and setting the reference voltage to a first level accordingly; and, after the setting of the first step, the first transistor and the second transistor On / off control, a second step of determining whether the output logic of the input buffer unit at that time matches the expected value, and setting the output logic of the output buffer unit to the second logic, A third step of setting the reference voltage to a second level accordingly, and after the setting of the third step, turning on and off the first transistor and the second transistor to output the output of the input buffer unit at that time. A fourth step of determining whether the logic matches the expected value.

According to the above-mentioned means, in the first to fourth steps, in the simultaneous bidirectional communication performed via the simultaneous bidirectional input / output buffer included in the semiconductor integrated circuit having the above configuration, the buffer of the buffer is used. A possible state check can be performed, which enables a proper operation test of the simultaneous bidirectional input / output buffer.

Further, an output buffer section for driving an external load through an external terminal and a voltage level of the external terminal are compared with a reference voltage (Vref) level, thereby taking in the data through the external terminal. An input buffer unit (200) capable of determining the logic of a signal, a plurality of first transistors (85-89) coupled to the external terminal and the high-potential-side power supply and connected in parallel with each other; A plurality of second transistors (90 to 94) coupled to the low potential side power supply and connected in parallel with each other
And a first control logic (75 to 75) for realizing an on-resistance equal to the output impedance of the output buffer section by selectively causing the plurality of first transistors and the plurality of second transistors to participate in the circuit operation. 78,
81 to 84) and a second control logic (71 to 7) for turning on and off the first transistor and the second transistor in a state where the test enable signal is asserted.
4) A method for testing an input / output buffer in a semiconductor integrated circuit that enables simultaneous bidirectional communication with the outside by switching the reference voltage level according to the current output logic from the output buffer unit. A first step of setting the output logic of the output buffer unit to a first logic and setting the reference voltage to a first level accordingly, and after the setting of the first step, the first transistor and the second transistor A second step of controlling on / off of the transistor to determine whether or not the output logic of the input buffer unit at that time matches an expected value; and setting the output logic of the output buffer unit to the second logic. A third step of setting the reference voltage to a second level accordingly, and after the setting of the third step, the first transistor and the second transistor
Turning on / off the transistor to determine whether or not the output logic of the input buffer unit at that time matches an expected value, wherein the plurality of first transistors and the plurality of second transistors The setting or determination of the first to fourth steps is performed in a state where a transistor involved in the circuit operation is selected from the transistors based on the on-resistance adjustment signal.

According to the above-mentioned means, in a state where a transistor involved in a circuit operation among the plurality of first transistors and the plurality of second transistors is selected based on an on-resistance adjusting signal, 4th above
Setting or determining a step is performed in a simultaneous bidirectional communication performed through a simultaneous bidirectional input / output buffer included in the semiconductor integrated circuit having the above configuration, since an operation test is performed in a state where impedances are matched. A possible state check of the buffer is enabled, which realizes a proper operation test of the simultaneous bidirectional input / output buffer.

[0026]

FIG. 3 shows an example of an electronic circuit device according to the present invention.

Although not particularly limited, the electronic circuit device shown in FIG. 3 is a part of a motherboard in a computer system, and includes an LSI mounted on a printed circuit board.
21 and 22 (referred to as "chips"), which are connected to each other via transmission lines 25-1 to 25-n so as to be able to exchange signals. The transmission lines 25-1 to 25-n are
It is set to a predetermined characteristic impedance (for example, 50Ω).

The chip 21 has simultaneous bidirectional input / output buffers 23-1 to 23-n.
1 to 23-n are data input / output terminals 24-1 to 24-3, respectively.
It is connected to one end of the transmission lines 25-1 to 25-n via 24-n. The chip 22 includes an input / output buffer 27-
1 to 27-n.
7-n are coupled to the other ends of the transmission lines 25-1 to 25-n via external terminals 26-1 to 26-n, respectively.

The simultaneous bidirectional input / output buffers 27-1 to 27-1
27-n are not particularly limited, but have basically the same configuration. Therefore, in the following description, the input / output buffer 2
Only 3-1 will be described in detail.

FIG. 1 shows a simultaneous bidirectional input / output buffer 23-.
1 is representatively shown.

As shown in FIG. 1, this simultaneous bidirectional input / output buffer 23-1 is not particularly limited, but is an output buffer section for driving an external load coupled thereto via an external terminal 24-1. 100, the external terminal 24-1
Input buffer unit 200 for receiving a signal input from outside via the CPU, and a simultaneous bidirectional input / output buffer 23
And a test circuit 18 for testing whether or not -1 operates normally.

The output buffer section 100 includes a series connection circuit of n-channel type MOS transistors 14 and 15, and a prebuffer 11 for driving the circuit. The source electrode of the n-channel MOS transistor 14 is coupled to the high-potential-side power supply voltage Vdd.
The source electrode of the transistor 15 has a low potential side power supply voltage Vs
s. n-channel type MOS transistor 1
4, 15 are connected to the transmission line 25-1 (see FIG. 3) via an external terminal 24-1.

The pre-buffer 11 has an enable signal E
N *, transmission data SIN, and an on-resistance adjustment signal CN having a plurality of bits are input. While the enable signal EN * is asserted, the n-channel MOS transistors 14 and 15 are driven based on transmission data SIN transmitted from a functional module (not shown) disposed in a stage preceding the prebuffer 11. This enables transmission of transmission data.

The input buffer unit 200 receives the reference voltage Vre
Vref generating circuit 12 for generating f.
Input buffer 13 for taking in the signal transmitted through the logic circuit 1 through logic judgment based on the reference voltage Vref.
And

The Vref generation circuit 12 transmits the transmission data SI
The level of the reference voltage Vref is switched based on the logic level of N. The input buffer 13 is connected to the external terminal 24-1.
Is taken in by a logical decision based on the reference voltage Vref. The output impedance can be adjusted by the on-resistance adjustment signal CN input to the pre-buffer 41. That is, the n-channel MOS transistor 1 is turned on by the ON resistance adjustment signal CN.
The gate widths of the MOS transistors 4 and 15 can be adjusted, so that the on-resistances of the MOS transistors 14 and 15 can be matched to the characteristic impedance of the transmission line 25-1. The MOS transistors 14 and 15 are actually a plurality of n-channel type M transistors connected in parallel with each other.
The MOS transistors are formed of OS transistors, and the plurality of MOS transistors are selected by an on-resistance adjustment signal CN.

If the impedance of the output buffer unit 100 matches the characteristic impedance of the transmission line 40,
As described above with reference to FIG.
By switching the level of reference voltage Vref in accordance with the output logic from, it is possible to correctly recognize the logic of a signal input from outside via external terminal 24-1.

The test circuit 18 is connected to the external terminal 24
-1 to realize an on-resistance equal to the output impedance of the output buffer unit 100.
An S transistor group 181 and a second MOS transistor group 182 and a control unit 183 are included. The first MO
Each of the S transistor group 181 and the second MOS transistor group 182 is formed by connecting a plurality of n-channel type MOS transistors in parallel with one MOS transistor. In the first MOS transistor group 181 and the second MOS transistor group 182,
The control unit 183 controls how many MOS transistors are involved in the circuit operation. The first MOS transistor groups 181 and 182 are ON / OFF controlled complementarily. When the first MOS transistor group 181 is turned on, the input / output node coupled to the external terminal is driven to a high level. When the second MOS transistor group 182 is turned on, the input / output node is driven to a low level. You.

The control unit 183 includes a test enable signal TEN * designating a test mode as various signals for an operation test of the simultaneous bidirectional input / output buffer 23-1.
The test data TIN and the on-resistance adjustment signals TCN0 to TCN7 for adjusting the on-resistance of the MOS transistor are supplied from an internal circuit (not shown) in the chip 21.

FIG. 4 shows a detailed configuration example of the test circuit 18.

As shown in FIG. 4, the first MOS transistor group 181 includes n-channel MOS transistors 85 to 89 connected in parallel, and the second MOS transistor group 182 includes the n-channel MOS transistor 9.
0 to 94 are connected in parallel. n-channel type MOS
The drain electrodes of the transistors 85 to 89 are commonly connected to the high potential side power supply Vdd. The source electrodes of the n-channel MOS transistors 85 to 89 are connected to the external terminal 24-1 and commonly connected to the drain electrodes of the n-channel MOS transistors 90 to 94. The source electrodes of the n-channel MOS transistors 90 to 94 are commonly connected to a low potential side power supply Vss.

Further, an inverter 71 for inverting test enable signal TEN * is provided, and an output signal of inverter 71 is supplied to a NAND (NAN) disposed at a subsequent stage.
D) The signal is transmitted to one of the input terminals of the gates 73 and 74. When the test enable signal TN * is asserted low, the NAND gate 7
3, 74 are activated, and test data TIN is transmitted to the subsequent circuit.

The first MO is provided before the NAND circuit 74.
S transistor group 181, second MOS transistor group 1
Since it is necessary to perform on / off control on the complementary operation of the inverter 82, the inverter 7 for inverting the test data TIN is used.
The output signal of the inverter 72 is transmitted to the NAND gate 74.

The output signal of NAND gate 73 is transmitted to n-channel MOS transistors 85 to 88 via NOR gates 75 to 78.
Is transmitted to the n-channel MOS transistor 89 via the. The output signal of the NAND gate 74 is transmitted to the n-channel MOS transistors 91 to 94 via the NOR gates 81 to 84.
The power is transmitted to an n-channel MOS transistor 90 via an inverter 80.

When one of the on-resistance adjustment signals TCN0 to TCN3 is set to low level, one of the NOR gates 75 to 78 corresponding thereto is activated, and the output signal of the NAND gate 73 is selectively n. It is transmitted to channel type MOS transistors 85-88. Similarly, when any of the on-resistance adjustment signals TCN4 to TCN7 is set to low level, any of the corresponding NOR gates 81 to 84 is activated, and the output signal of the NAND gate 74 is selectively n. Channel type M
It is transmitted to OS transistors 91-94. The output logic of the NAND gates 73 and 74 is the test enable signal TE
In the state where N * is asserted at a low level, the output signal of the NAND gates 73 and 74 is changed according to the logic state of the test signals TCN0 to TCN7. It is selectively transmitted to the type MOS transistors 85 to 88, 91 to 94.

As described above, NOR gates 75-78, 81-
The signal transmission is controlled by 84, and among the n-channel MOS transistors 85 to 88, 91 to 94, the transistors involved in the circuit operation are selected according to the logic states of the on-resistance adjustment signals TCN0 to TCN7. You. For example, when all of the on-resistance adjustment signals TCN0 to TCN7 are at a high level, an n-channel MOS
MOS transistor 8 among transistors 85 to 94
When only the on-resistance adjustment signals TCN0 and TCN5 become low level, the NOR gates 75 and 81 are activated, so that the n-channel MOS transistor 89 and the n-channel MOS transistor 89 are activated. The MOS transistor 85 is operated, and the n-channel MOS transistor 91 is operated together with the n-channel MOS transistor 90. By selecting the n-channel MOS transistors involved in the circuit operation in this way, the adjustment of the combined on-resistance of the n-channel MOS transistors 85 to 89 (first MOS transistor group 181) and the n-channel MOS transistor 90 To 94 (second MOS transistor group 182)
Can be adjusted.

In the operation test of the simultaneous bidirectional input / output buffer 23-1, the adjustment of the combined on-resistance of the n-channel MOS transistors 85 to 89 and the combined on-resistance of the n-channel MOS transistors 90 to 94 correspond to the output buffer. The operation is performed in a state where the output impedance is equal to 100, that is, the on-resistance of the n-channel MOS transistors 14 and 15.

N-channel type MOS transistors 85 to 85
When viewed from the output buffer unit 100 shown in FIG. 1, 94 is equivalent to an output buffer unit in another semiconductor chip connected to the outside via the external terminal 24-1. Therefore, when the test enable signal TEN * is asserted at a low level, the operation test of the bidirectional input / output buffer 23-1 can be performed even though the external terminal 24-1 is in the released state. Note that a tester 6 as shown in FIG. 7 may be coupled to the external terminal 24-1. In this case, the tester 6 is connected to the tester 6 so as not to interfere with the operation test. The output terminal of the driver 61 is fixed in a high impedance state.

Specifically, according to the procedure described below,
An operation test of the bidirectional input / output buffer 23-1 is performed.

In the normal operation of the simultaneous bidirectional input / output buffer 23-1, the test enable signal TEN * is negated to a high level, and when this test enable signal TEN * is asserted to a low level,
The mode is shifted to the test mode.

When test enable signal TEN * is asserted low, NAND gate 7 shown in FIG.
3, 74 are activated, and test signal TIN can be transmitted to the subsequent circuit.

Next, the ON resistance adjustment signals TCN0 to TCN
According to 7, the combined on-resistance of the driver MOS transistor in the test circuit 18 is adjusted to be equal to the output impedance of the output buffer unit 100. For example, if the ON resistance of the output buffer unit 100 is 50Ω, the combined ON resistance of the driver MOS transistors in the test circuit 18 is also adjusted to 50Ω.

Next, when the enable signal EN * in the output buffer unit 100 is asserted to a low level, the output buffer unit 100 is enabled.
In this state, first, the logic of the transmission data SIN is fixed so that the output buffer unit 100 outputs a high-level signal. For example, when a high-level signal is output from the output buffer unit 100 when the transmission data SIN is at a high level, the transmission data SIN is fixed at a high level. When a high-level signal is output from the output buffer unit 100, the reference voltage Vref generated by the Vref generation circuit 12 is equal to the high-potential-side power supply Vdd.
Is equal to 3/4 of the level.

Then, by setting the test data TIN to a high level and causing the test circuit 18 to output a high level, the output logic of the input buffer 13 is changed to
The determination is made via an internal circuit arranged at the subsequent stage. When a high level is output from the test circuit 18, if the circuit is operating normally, the potentials of the external terminal 24-1 and the node coupled thereto become equal to the level of the high-potential-side power supply Vdd. Reference voltage Vref = V
dd × 3/4, input buffer 1
The expected value of the output logic of No. 3 becomes high level.

Next, the test data TIN is set to the low level, and the test circuit 18 outputs the low level. At this time, the output logic of the input buffer 13 is changed via the internal circuit arranged at the subsequent stage. judge. When a low level is output from the test circuit 18, if the circuit is operating normally, the potentials of the external terminal 24-1 and the node coupled thereto become equal to half the level of the high-potential-side power supply Vdd. , Which is the current reference voltage Vre
Since the level should be lower than f = Vdd × 3/4, the expected value of the output logic of the input buffer 13 is at the low level.

Then, the logic of the transmission data SIN is fixed so that a low-level signal is output from the output buffer unit 100, and the same test operation as described above is performed.

That is, the logic of the transmission data SIN is fixed so that the output buffer unit 100 outputs a low level signal. When a low-level signal is output from the output buffer unit 100, the reference voltage Vref generated by the Vref generation circuit 12 is equal to the high-potential-side power supply Vd
d equal to 1/4 level.

Next, the test data TIN is set to the high level, and the test circuit 18 outputs the high level. At this time, the output logic of the input buffer 13 is changed via the internal circuit arranged at the subsequent stage. judge. When a high level is output from the test circuit 18, if the circuit is operating normally, the potentials of the external terminal 24-1 and the node coupled to it become half the level of the high-potential-side power supply Vdd, It is the reference voltage Vref = V
Since it should exceed dd × １ ／, the input buffer 1
The expected value of the output logic of No. 3 becomes high level.

Further, by setting the test data TIN to a low level and causing the test circuit 18 to output a low level, the output logic of the input buffer 13 is determined at this time via an internal circuit arranged at the subsequent stage. I do. When a low level is output from the test circuit 18, if the circuit is operating normally, the potential of the external terminal 24-1 and the node coupled thereto becomes 0 volt, which is the reference voltage Vref = Vdd at that time. Since the level should be lower than × 入 力, the expected value of the output logic of the input buffer 13 is at the low level.

As described above, with the output logic from the output buffer 100 fixed at a high level, the test data T
IN is switched to a high level and a low level, the output logic of the input buffer 13 before and after the switching is determined, and further, while the output logic from the output buffer 100 is fixed at a low level, the test data TIN is set to a high level. By switching every low level and judging the output logic of the input buffer 13 before and after this switching, it is possible to judge the pass / fail of the simultaneous bidirectional input / output buffer 23-1.

As described above, the test circuit 18 is provided,
First transistor group 181, Second transistor group 182
Is controlled, a state equivalent to the simultaneous bidirectional input / output buffer in another semiconductor integrated circuit is formed via the external terminal 24-1. The operation test of the output buffer 23-1 is enabled.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, in the configuration example shown in FIG. 1, the test circuit 18 is controlled by the on-resistance adjustment signals TCN0 to TCN7.
Although the on-resistance of the driver MOS transistor included in the first embodiment can be adjusted, the present invention is not limited to this. That is, FIG.
As shown in FIG. 5, the first MOS transistor group 181 and the second MOS transistor group 181 are configured such that the combined on-resistance of each of the first MOS transistor group 181 and the second MOS transistor group 182 becomes equal to the maximum value of the output impedance that the output buffer unit 100 can take. 2 MOS transistor group 182
Are determined in each case. Making the output impedance equal to the maximum value of the output impedance that can be taken by the output buffer unit 100 means that the gate width of the MOS transistor may be small, and thus is applied to a case where a plurality of MOS transistors are connected in parallel. The number of elements is smaller than when the configuration shown in FIG. 4 is adopted.

The test mode of the simultaneous bidirectional input / output buffer 231 is a state in which the output impedance of the output buffer unit 100 is adjusted to the maximum value by the on-resistance adjustment signal CN input to the pre-buffer 11, that is, the impedance is matched. It is performed in the state where it was done. The procedure of the operation test is basically the same as the case where the configuration shown in FIG. 4 is adopted as the test circuit 18 except for the on-resistance adjustment step in the test circuit 18.

In the above description, the invention mainly made by the present inventor can be applied to various electronic circuit devices in the field of use as the background.

The present invention can be applied on the condition that it includes at least an output buffer section and an input buffer section.

[0066]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by controlling the operation of the transistor group by the control logic, a state equivalent to the simultaneous bidirectional input / output buffer of another semiconductor integrated circuit being coupled via the external terminal is formed. Thus, an operation test of the simultaneous bidirectional input / output buffer can be performed.

Also, the first control logic realizes an on-resistance equal to the output impedance of the output buffer section by selectively causing the plurality of first transistors and the plurality of second transistors to participate in the circuit operation. The control logic is
The first transistor and the second transistor are turned on / off while the test enable signal is asserted.
Thereby, a state equivalent to the simultaneous bidirectional input / output buffer of another semiconductor integrated circuit being coupled via the external terminal is formed, thereby enabling the operation test of the simultaneous bidirectional input / output buffer. You.

Further, since the reliability of the semiconductor integrated circuit on which the operation test of the simultaneous bidirectional input / output buffer has been performed as described above is improved, such a semiconductor integrated circuit is mounted on a board, and By connecting the external terminal of the integrated circuit to the external terminal of another semiconductor integrated circuit mounted on the board to form an electronic circuit device, the reliability of the electronic circuit device can be improved. .

Then, in the input / output buffer test method, a first step of setting the output logic of the output buffer unit to the first logic and setting the reference voltage to the first level accordingly, and after the setting of the first step, A second step of turning on / off the first transistor and the second transistor to determine whether or not the output logic of the input buffer unit at that time matches the expected value; A third step of setting the logic to logic and setting the reference voltage to the second level in accordance therewith; after the setting of the third step, the on / off control of the first transistor and the second transistor and the input buffer at that time And a fourth step of determining whether or not the output logic of the section matches the expected value. In simultaneous bidirectional communication through the §, to enable a check of the possible states of the buffer, whereby it is possible to achieve appropriate operation test of the simultaneous bidirectional output buffer.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a simultaneous bidirectional input / output buffer included in an electronic circuit device according to the present invention.

FIG. 2 is a circuit diagram of another configuration example of the simultaneous bidirectional input / output buffer.

FIG. 3 is a block diagram illustrating a configuration example of the electronic circuit device.

FIG. 4 is a circuit diagram showing a detailed configuration example of a test circuit included in the simultaneous bidirectional input / output buffer shown in FIG. 1;

FIG. 5 is a circuit diagram for explaining the operation principle of the simultaneous bidirectional input / output buffer.

6 is an explanatory diagram of a logic or voltage level of a main part in the circuit configuration shown in FIG. 5;

FIG. 7 is an explanatory diagram of a test method of the simultaneous bidirectional input / output buffer using a tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Pre-buffer 12 Vref generation circuit 13 Input buffer 24-1 to 24-n, 26-1 to 26-n External terminal 25-1 to 25-n Transmission line 21, 22 LSI (chip) 23-1 to 23-n , 27-1 to 27-n Simultaneous bidirectional input / output buffer 85 to 94 n-channel MOS transistor 71, 72 inverter 73, 74 NAND gate 100 output buffer section 181 first MOS transistor 182 second MOS transistor 183 control section 200 input buffer section

Claims (5)

[Claims] An output buffer unit for driving an external load through an external terminal; and a logic of a signal fetched through the external terminal by comparing a voltage level of the external terminal with a reference voltage level. A semiconductor integrated circuit that enables simultaneous bidirectional communication with the outside by switching the reference voltage level according to the current output logic from the output buffer unit. A transistor group coupled to the external terminal for realizing an on-resistance equal to the output impedance of the output buffer unit; and a control logic for controlling on / off of the transistor group in a state where a test enable signal is asserted. And a semiconductor integrated circuit comprising: 2. An output buffer unit for driving an external load through an external terminal, and a logic of a signal captured through the external terminal by comparing a voltage level of the external terminal with a reference voltage level. A semiconductor integrated circuit that enables simultaneous bidirectional communication with the outside by switching the reference voltage level according to the current output logic from the output buffer unit. And a plurality of first transistors coupled to the external terminal and the high-potential-side power supply and connected in parallel with each other, and a plurality of first transistors coupled to the external terminal and the low-potential-side power supply and connected in parallel to each other By selectively causing the two transistors and the plurality of first transistors and the plurality of second transistors to participate in the circuit operation, the output buffer A first control logic for realizing an on-resistance equal to the output impedance of the amplifier, and a second control logic for controlling on / off of the first and second transistors in a state where the test enable signal is asserted. And a semiconductor integrated circuit comprising: 3. The semiconductor integrated circuit according to claim 1 or 2 is mounted on a board, and the external terminal of the semiconductor integrated circuit is coupled to an external terminal of another semiconductor integrated circuit mounted on the board. Electronic circuit device comprising: 4. An output buffer unit for driving an external load through an external terminal, and a logic of a signal fetched through the external terminal by comparing a voltage level of the external terminal with a reference voltage level. An input buffer unit capable of determining the output impedance of the input buffer unit, a transistor coupled to the external terminal for realizing an on-resistance equal to the output impedance of the output buffer unit, and an on / off control of the transistor with a test enable signal asserted. And a control logic for switching the reference voltage level according to the current output logic from the output buffer unit, thereby enabling simultaneous bidirectional communication with the outside. An output buffer test method, comprising: setting an output logic of the output buffer unit to a first logic; A first step of setting a reference voltage to a first level, and after the setting of the first step, on / off control of the transistor to determine whether an output logic of the input buffer unit at that time matches an expected value. A second step of determining whether or not the output logic of the output buffer unit is set to the second logic, and a third step of setting the reference voltage to a second level accordingly; and after the setting of the third step, A fourth step of controlling on / off of the transistor to determine whether an output logic of the input buffer unit at that time matches an expected value. 5. An output buffer unit for driving an external load through an external terminal, and a logic of a signal fetched through the external terminal by comparing a voltage level of the external terminal with a reference voltage level. An input buffer unit coupled to the external terminal and the high-potential-side power supply, and a plurality of first transistors connected in parallel with each other; and an input buffer unit coupled to the external terminal and the low-potential-side power supply. A plurality of second transistors connected in parallel, and the plurality of first transistors and the plurality of second transistors are selectively involved in a circuit operation, thereby realizing an on-resistance equal to the output impedance of the output buffer unit. Control logic for controlling the on / off state of the transistor with the test enable signal asserted And a second control logic, wherein the input / output of the semiconductor integrated circuit enables simultaneous bidirectional communication with the outside by switching the reference voltage level according to the current output logic from the output buffer unit. A buffer test method, comprising: a first step of setting an output logic of the output buffer unit to a first logic, and setting the reference voltage to a first level accordingly; A second step of determining whether or not the output logic of the input buffer unit at that time matches an expected value, and setting the output logic of the output buffer unit to a second logic, A third step of setting the reference voltage to a second level in accordance therewith; after the setting of the third step, on / off control of the transistor, A fourth step of determining whether or not the output logic of the output buffer unit matches an expected value, and turning on a transistor involved in circuit operation among the plurality of first transistors and the plurality of second transistors. An input / output buffer test method, wherein the setting or determination of the first to fourth steps is performed in a state selected based on a resistance adjustment signal.