JP2002164471A - Thin semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin semiconductor and a method for manufacturing it wherein a material cost is reduced by effectively reducing the total thickness and thinning a substrate and it is possible to reduce the cost by providing a substrate which does not require a solder mask layer. SOLUTION: The thin semiconductor comprises a substrate 21 having at least one opening 212, an active surface 200 and a non active surface 201 opposing the active surface 200 and further includes a semiconductor chip 20 wherein the active surface 200 is adhered to a base layer 210, a first conductive element used for connection between the semiconductor chip 20 and the conductive trace 211, a second conductive element providing the semiconductor chip 20 with an external connection, a first glue 23 covering the semiconductor chip 20 and a second glue 25 covering the conductive trace 211, the first conductive element and the opening 212.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip is connected to the outside through conductive elements arranged on a substrate surface in an array.

[0002]

2. Description of the Related Art In recent years, BGA type semiconductor devices (Ball Grid type) have been developed.
Array Semiconductor Device) has become the main type of semiconductor package. The connection structure between the semiconductor chip provided by the solder balls arranged on the substrate surface in the form of an array and an external device such as a printed circuit board (PCB) is smaller than that of a conventional lead frame type semiconductor device in the unit area for input / output connection. The number of solder ball terminals can be increased, and the pitch between solder balls can be effectively reduced. Therefore, the structure of the BGA type semiconductor device is used for many electronic elements and electronic circuits and applied to a semiconductor chip.

[0003] In the conventional BGA type semiconductor device, a wire bonding process between a semiconductor chip and a substrate to which the semiconductor chip is bonded by Au wire is performed.
Bonder is the active surface of the semiconductor chip (active sur
face), that is, after a solder ball is formed on a bonding pad on a surface on which an electronic element and an electronic circuit are to be formed, an Au wire having one end connected to a bonding pad is formed on the substrate below an upper surface of the semiconductor chip with an appropriate length. And bonding is performed. In this case, since the apex of the wire loop formed by the Au wire is higher than the working surface of the semiconductor chip, the upper surface of the resin sealing body covering the semiconductor chip and the Au wire as the bonding wire is removed. By making the height higher than the apex of the wire loop, exposure of the Au wire is prevented. Therefore, the thickness of the sealed semiconductor device is restricted by the height of the wire loop, which is disadvantageous for thinning the semiconductor device.

In order to solve the problem that the thickness of the known BGA type semiconductor device becomes bulky, a thin BGA type semiconductor device 1 shown in FIG. 12 has been developed. This thin BGA type semiconductor device 1 has an opening 110 formed on a substrate 11 for bonding a semiconductor chip 10, and an Au wire 12 serving as a bonding wire connecting the semiconductor chip 10 and an electrode 111 of the substrate 11. After passing through the opening 110 to complete wire bonding, the Au wire 12 and the opening 110 are covered with a sealing resin such as epoxy to form a lower sealing body 13, and the Au wire 12 is formed. The height of the wire loop portion is absorbed by the substrate 11 so that the wire loop apex 120 of the Au wire 12 slightly protrudes from the bottom surface of the substrate 11. Is lower than the height h of the solder balls 14 formed on the bottom surface of the substrate 11. Therefore, the upper sealing body 1 of the semiconductor chip 10
5 is not directly affected by the distance between the apex of the wire loop and the ace of the working surface of the semiconductor chip 10, and the thickness of the semiconductor device after the completion of sealing is the same as that of the conventional B.
It is smaller than a GA semiconductor device.

[0005] The semiconductor device 1 shown in FIG. 12 can effectively reduce the overall thickness and achieve the purpose of thinning. However, it is necessary to prevent the electrode 111 on the substrate 11 from being exposed to the atmosphere. To avoid this, the electrode 111 on the bottom surface of the substrate 11
It is necessary to lay a solder resist layer 112 that completely covers the substrate 11, which increases the manufacturing cost of the substrate 11 and complicates the manufacturing process, and the solder mask layer 112 causes moisture absorption. In addition, the manufacturing cost of the substrate 11 is further increased in order to effectively prevent the occurrence of hygroscopicity.

[0006] By making the semiconductor device 1 thinner,
Well-known surface mounting technology
When mounting on an external device such as a printed board using
The high temperature generated in the heating and mounting operation acts on the substrate 11 and the upper sealing aggregate 15 having different thermal expansion coefficients of the semiconductor device 1 to generate thermal stress, causing the semiconductor device 1 to be distorted.
Eventually, a peeling phenomenon between the semiconductor chip 10 and the substrate 11 and a film layer peeling of the substrate 11 itself may occur, or a failure may occur in an electrical connection between the semiconductor device 1 and an external device.
It is conceivable to increase the thickness of the substrate 11 in order to reduce the occurrence rate of the distortion, thereby countering the thermal stress. However, as the cost of the substrate 11 increases, the thickness of the entire semiconductor device 1 also increases. . The semiconductor device 1 after the completion of the sealing operation
Since the bottom of the solder ball 14 has a spherical shape, it is difficult to bring the plurality of contact tips of the test probe into complete contact with all the solder balls 14 in the inspection process, and a test error due to poor contact of the test probe occurs. In addition, since the solder balls 14 are planted by using an expensive solder ball planting device in the manufacture of the semiconductor device 1, the cost of planting the solder balls 14 is a factor of the overall sealing work cost, and the cost reduction is achieved. Disadvantages. Moreover, it is difficult to ensure that the vertices of the surfaces of the solder balls 14 after the solder balls 14 are planted on the substrate 11 are in the same plane, and it is possible to secure the electrical connection between the semiconductor device 1 and the external device. become unable.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a thin semiconductor device capable of effectively reducing the entire thickness and a method of manufacturing the same. It is to be.

Also, by reducing the thickness of the substrate,
An object of the present invention is to provide a thin semiconductor device capable of reducing material costs and a method for manufacturing the same.

Another object of the present invention is to provide a thin semiconductor device capable of reducing the substrate cost by providing a substrate which does not require a solder mask layer to be laid on the substrate, and a method of manufacturing the same.

Further, by providing a substrate which does not cause thermal distortion of the substrate and other members in a high temperature environment, a separation phenomenon between the semiconductor chip and the substrate and a separation between layers of the substrate itself can be avoided. An object of the present invention is to provide a thin semiconductor device and a manufacturing method thereof.

It is another object of the present invention to provide a thin semiconductor device capable of improving test accuracy and a method of manufacturing the same.

It is another object of the present invention to provide a thin semiconductor device in which the vertices of the surfaces of the solder balls after the solder balls are planted are on the same plane and have no unevenness, and a method of manufacturing the same.

[0013]

According to the present invention, there is provided a thin semiconductor device provided with at least one opening, a substrate comprising a base layer and a plurality of conductive traces, and an active substrate. A semiconductor chip having a surface and a non-active surface facing the active surface, wherein the active surface is adhered to the base layer of the substrate; and a conductive trace of the semiconductor chip substrate through the opening. A first conductive element used for the connection of the semiconductor chip, a second conductive element provided at the end of each conductive trace and capable of providing the semiconductor chip with an external electrical connection, and a base layer of the substrate. A first aggregate portion covering the semiconductor chip; and a conductive trace formed on the conductive trace of the substrate and the first conductive element. Comprising a second Nikawatai portion to completely cover the opening, and, the second conductive element bottom end the second
A bottom surface of the second conductive element is exposed from the bottom surface of the glue portion, and the bottom end of the second conductive element and the bottom surface of the second glue portion are positioned on the same plane.

The second conductive member is formed by using a solder ball made of tin (Sn) or copper (Cu), aluminum (A1), a copper alloy, an aluminum alloy, or a tin-lead alloy. Wherein the second conductive member is in the form of a solder ball, is planted on the connection electrode of the substrate using a conventionally known ball planting device, In the case of the above, it is provided on the connection electrodes of the substrate by a general printing method or a plating method.

The semiconductor chip is completely covered with a first sealing body or a non-working surface of the semiconductor chip is exposed on the surface of the first sealing body, and a heat radiating piece is provided on the semiconductor chip to improve heat dissipation of the semiconductor device. May be provided on the non-working surface. In order to avoid an increase in the thickness of the semiconductor device due to the provision of the heat radiating piece, a heat radiating piece made of a heat conductive metal material is adhered on the base layer of the substrate, and a semiconductor chip is opened on the heat radiating piece. By incorporating the heat radiation piece in the opened hole, it is possible to prevent the thickness of the entire semiconductor device from increasing when the heat radiation piece is incorporated.

When an opening is formed in the substrate and a semiconductor chip of a central pad type is applied, the bonding pad of the semiconductor chip is exposed to the opening of the substrate and the first conductive member is formed. Is passed through the opening to perform wire bonding. Further, a pair of parallel opening portions are provided on the substrate, and a double-side pad type semiconductor chip is applied, and each of the bonding pad substrates formed on both side portions of the semiconductor chip is provided. The wire bonding can be performed by exposing to the opening corresponding to. In addition, four rectangular rows of openings are formed in the substrate, and a peripheral pad type semiconductor chip is applied, and each peripheral bonding pad on the semiconductor chip is placed in the corresponding opening of the substrate. It is also possible to perform wire bonding by exposing.

[0017]

(Embodiment 1) FIG. 1 is a sectional view of a thin semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor device 2 of the first embodiment includes a semiconductor chip 20, a substrate 21 for bonding the semiconductor chip 20, the semiconductor chip 20 and the substrate 21.
Wire 22 which is a bonding wire used for connection with
And an upper sealing portion 23 formed above the substrate 21, a plurality of solder balls 24 arranged in an array arranged below the substrate 21, and a lower sealing formed below the substrate 21. Unit 25 is included.

The semiconductor chip 20 has a working surface (main surface) 200 on which electronic circuits and transistors are formed, and a non-working surface (back surface) 201 facing the working surface 200, and a central position of the working surface 200. Are provided with a plurality of parallel solder pads (bonding pads) 202 in two rows. The semiconductor chip 20 is bonded to a predetermined position on the substrate 21 with a working surface 200 facing downward through a well-known bonding medium such as a polyimide tape. The semiconductor chip 20 and the substrate 21 in the temperature cycling in the subsequent process
In order to reduce the thermal stress on the bonding surface generated between the substrate and the substrate, an adhesive or tape of a thermoplastic or thermoelastic resin material is used.

The substrate 21 comprises a base body 210 and a plurality of connection electrode layers 211 on the bottom surface of the base body 210. The base body 210 is made of epoxy resin, polyimide resin, bismaleimidetriaxine resin, FR4 resin, glass epoxy The semiconductor chip 20 is made of a material such as a resin, a ceramic material, or a high temperature resistant paper material, and the semiconductor chip 20 is adhered to the base body 210 with an adhesive or an adhesive tape. The normal connection electrode layer 211 is formed of copper foil, and a solder pad 211a for implanting a solder ball 24 is provided at a terminal end of each connection electrode layer 211, and an Au wire 22 which is a bonding wire is welded at a tip end. Is formed. The connection electrode layer 211 of the substrate 21 is formed by applying an Au wire to the solder pad 21 in a step described later.
1b and the solder pad 202 of the semiconductor chip 20 are wire-bonded to each other, and are completely covered by the lower sealing portion 25 and are air-tightly isolated from the outside.
There is no need to lay a solder resist layer on the bottom surface of the substrate. Therefore, the manufacturing cost of the substrate 21 can be reduced.
Further, an upper sealing portion 23 and a lower sealing portion 25 are respectively formed on the upper surface and the bottom surface of the substrate 21, and the substrate 21 is sandwiched between the upper sealing portion 23 and the lower sealing portion 25. Since the upper sealing portion 23 and the lower sealing portion 25 are installed so as to face each other up and down, the thermal stress generated in the temperature circulation in the subsequent sealing process is greatly reduced.

Therefore, it is possible to effectively prevent the occurrence of distortion in the product after sealing, and also to effectively prevent the separation between the substrate 21 and the semiconductor chip 20 from occurring, and The yield is improved. In the structure in which the substrate 21 is sandwiched between the upper sealing portion 23 and the lower sealing portion 25, it is necessary to increase the thickness of the substrate 21 in order to avoid distortion of the substrate 21 and to increase the mechanical strength of the product. Absent. Accordingly, since the substrate 21 is thinner than the conventional thickness, the manufacturing cost of the substrate 21 can be reduced, and the thickness of the entire product is further reduced.

The substrate 21 has an opening 2 at its center.
After bonding the semiconductor chip 20 to the base body 210 of the substrate 21, the solder pad bonding pad 202 on the working surface 200 of the semiconductor chip 20 is exposed to the opening 212, and a bonding wire is formed. The Au wire 22 is wire-bonded between the solder pad 202 of the semiconductor chip 20 and the solder pad 211b of the connection electrode layer 211 of the substrate 21 through the opening 212 to form a connection electrode layer of the semiconductor chip 20 and the substrate 21. The electrical connection of 211 is performed.

The upper sealing portion 23 and the lower sealing portion 25 are formed of a sealing material such as epoxy resin. After the lower sealing portion 25 is formed on the bottom surface of the substrate 21, the connection electrode layer 211 is formed.
And bonding wire Au wire 22 and opening 21
2 and the connection electrode layer 211 and the Au wire 22
In addition, the working surface 200 of the semiconductor chip 20 is airtightly isolated from the outside. As shown in FIG. 2, the lower sealing portion 25 is configured to connect the bottom end 240 of the solder ball 24 to the bottom surface 250 of the lower sealing portion 25.
And the bottom surface 240 of the solder ball 24 and the bottom surface 250 of the lower sealing portion 25 are positioned on the same plane.
This design concept is based on the assumption that the bottom surface of the solder ball 24, that is, the surface 240 is flat, and the surface 240
Are on the same plane to maintain the work quality when the semiconductor device and the printed circuit board are externally connected. In this case, since the surface 240 of each solder ball 24 is not a conventional spherical surface but a flat surface, in the inspection process, the tips of the plurality of contacts of the test probe are all solder balls 24.
This makes it easier to make contact with the surface 240, so that test errors due to poor contact are eliminated. Since the lower sealing portion 25 covers the solder ball 24 and is integrally formed, the bottom surface of the semiconductor device of the present invention can be treated by polishing or other methods. The bottom surface 250 of the solder ball 24 and the surface 240 of the solder ball 24 form the same plane, and the thickness of the lower sealing portion 25 is reduced so that the wire loop apex 220 of the Au wire 22 is not exposed from the lower sealing portion 25. It is possible. That is, by making the surface 240 of the solder ball 24 slightly larger than the wire loop vertex 220 of the Au wire 22 from the bottom surface of the substrate 21, the thickness of the entire semiconductor device of the present invention can be reduced to a known BGA semiconductor device. , And the purpose of thinning can be achieved. Since the solder balls 24 are planted in an array on the connection electrode layer 211, sufficient I / O connection terminals are supplied to the semiconductor chip 20.

FIGS. 3A to 3H show Embodiment 1 of the present invention.
3 is a view showing a manufacturing process of the thin semiconductor device in FIG.

As shown in FIG. 3A, first, the base body 21
A base 21 having a connection electrode layer 211 including zero and a plurality of connection electrodes and an opening 212 is prepared, and as shown in FIG. 3B, the working surface 200 of the semiconductor chip 20 having electronic circuits and electronic members is turned downward. The substrate 2 is made of polyimide tape or the like.
1. Adhering to a predetermined position on 1. At this time, the solder pad (bonding pad) 202 on the semiconductor chip 20 is exposed in the opening 212 of the substrate 21.

As shown in FIG. 3C, the substrate 21
The wire bonding operation is performed by passing the Au wire 22 through the opening 212 of the semiconductor chip 20, and the semiconductor chip 20 and the connection electrode layer are electrically connected to the solder pad 202 and the solder pad 211b of the connection electrode layer 211.

Next, as shown in FIG. 3D, after the wire bonding operation is completed, the sealing resin 25a is filled in the opening 212 by the glove top method until the Au wire 22 is completely covered. I do.

In FIG. 3E, the structure completed in FIG. 3D is placed in an encapsulating mold to perform transfer molding, and a molten encapsulating resin is molded on the upper surface of the substrate 21. The upper sealing portion 23 covering the semiconductor chip 20 is formed. But,
Instead of the transfer mold, the upper sealing portion 23 can be formed by well-known injection molding or injection molding.

The solder pad 2 of the connection electrode layer 211 on the substrate 21 after the formation of the upper sealing portion 23 shown in FIG.
The operation of implanting the solder ball 24 into the solder 11a is a well-known operation, and a description thereof will be omitted.

FIG. 3G shows that the lower sealing portion 25 is formed on the bottom surface of the substrate 21 by transfer molding on the semi-finished product after the completion of the work of implanting the solder balls 24, and the connection electrode layer 21 is completely formed.
1 and the Au wire 22 are covered together with the solder ball 24. In addition, the lower sealing part 25 can be formed by a method such as a printing method or a coating method instead of the transfer mold.

In FIG. 3H, the dimension from the surface of the lower sealing portion 25 to the bottom surface of the substrate 21 using a conventional polishing machine P, that is, the thickness of the lower sealing portion 25 and the solder ball 24 By polishing the surface of the lower sealing portion 25 until the height becomes a predetermined value, the bottom surface 240 of the solder ball 24 is made flat, and the surface of each solder ball 24 is formed on the bottom surface of the lower sealing portion 25. 250 and the same plane. Note that the thickness of the sealing portion 25 is the same as that of the Au wire 2.
Since the semiconductor device 2 is covered so as not to be exposed, the overall thickness of the semiconductor device 2 having completed the sealing step is smaller than that of the conventional semiconductor device.

The step of covering the Au wire 22 with the sealing resin 25a in FIG. 3D is omitted, and the Au wire 22 in FIG. 3C is omitted.
It is also possible to go directly to the transfer molding step of FIG. 3E after wire bonding of line 22. In this case, the manufacturing process of the semiconductor device of the present invention is simplified.

FIGS. 4A and 4B show Embodiment 1 of the present invention.
13 is a view for explaining another sealing step of the thin semiconductor device in FIG. Since the steps before the solder ball planting operation in the sealing step are the same as the steps shown in FIGS. 3A to 3E, the description thereof is omitted, and the illustration is also omitted.
The steps after forming the sealing portion 23 will be described. Note that the same members as those shown in the sealing step of FIGS. 3A to 3E are denoted by the same reference numerals.

FIG. 4A shows an upper sealing portion 23 above a substrate 21.
Is formed, the connection electrode layer 211 is formed by screen printing technology.
Of tin / lead alloy on solder pad 211a
4 'is formed. The protrusion 24 ′ is a solder pad 21.
1a is formed on the surface by printing (or plating) method,
The height after the formation of the protrusion 24 ′ is slightly higher than the height of the wire loop vertex 220 of the Au wire 22, and the surface 240 ′ after the formation of the protrusion 24 ′ is made flat. The protrusion 24 '
Is formed by printing or plating, so that an expensive ball implanting device is not required. By replacing the solder ball 24 with the projection 24 ', the manufacturing cost can be greatly reduced.

FIG. 4B shows that the connection electrode layer 211 and the lower sealing portion 25 which completely covers the Au wire 22 and the opening 212 are formed by transfer molding after the formation of the projection 24 ′. 25 and each projection 24 'are integrally joined to expose the surface 240' of the projection 24 'outside the bottom surface 250 of the lower sealing portion 25, and the surface 24' of the projection 24 '
0 ′ and the surface 250 of the lower sealing portion 25 are made to be the same plane, and the height of the projection 24 ′ is set to be slightly higher than the height of the wire loop vertex 220 of the Au wire 22. . Therefore, the thickness of the lower sealing portion 25 is
The thickness is such that the Au wire 22 is covered so that the Au wire 22 is not exposed, and it is not necessary to adjust the thickness by polishing after molding, and the overall thickness of the semiconductor device 2 after sealing is completed is:
The thickness is smaller than the thickness of the known BGA type semiconductor device 1.

(Embodiment 2) FIG. 5 is a sectional view of a thin semiconductor device according to Embodiment 2 of the present invention. Embodiment 2
The configuration of the semiconductor device 3 is substantially the same as that of the first embodiment. The difference between the two is that the non-working surface 301 of the semiconductor chip 30 is exposed to the upper surface 330 of the upper sealing portion 33. 2, the upper sealing portion 33 is
Above. The exposed configuration is the same as that of the semiconductor chip 30.
The heat generated in the semiconductor device 3 is directly radiated from the non-working surface 301 to the atmosphere to improve the heat radiation effect, and the upper sealing portion 33 does not cover the non-working surface 301 of the semiconductor chip 30. The thickness is made thinner than the semiconductor device 3 described in the first embodiment. In addition, the exposed non-working surface 3
The heat dissipating piece 36 (indicated by a dotted line in FIG. 5) can be connected to the upper portion 01 to further improve the heat dissipating effect.

(Embodiment 3) FIG. 6 is a sectional view of a thin semiconductor device according to Embodiment 3 of the present invention. Embodiment 3
The configuration of the semiconductor device 4 in the first embodiment is almost the same as that of the first embodiment. The difference between the two is that a heat radiation piece 46 is provided on the non-working surface 401 of the semiconductor chip 40.
The upper sealing portion 43 is formed above the substrate 41 so that the upper end surface 460 of the upper sealing portion 43 is exposed from the upper surface 430 of the upper sealing portion 43.
In this way, the heat generated in the semiconductor chip 40 is radiated to the atmosphere through the heat radiation piece 46. Further, it is possible to completely cover the heat radiation piece 46 with the upper sealing portion 43.

(Embodiment 4) FIG. 7 is a sectional view of a thin semiconductor device according to Embodiment 4 of the present invention. Embodiment 4
The configuration of the semiconductor device 5 is almost the same as that of the first embodiment. The difference between the two is that the heat radiation piece 56 is connected to the base body 510 of the substrate 51. The heat radiation piece 56 has an opening 560, and the semiconductor chip 50 is housed in the opening 560.
Adhere on 10 Thus, the entire thickness of the semiconductor device 5 completed by sealing the combined body of the heat radiation piece 56 and the substrate 51 becomes the same as that described in the first embodiment, and the thickness does not increase.

(Embodiment 5) FIG. 8 is a sectional view of a thin semiconductor device according to Embodiment 5 of the present invention. Embodiment 5
The configuration of the semiconductor device 6 in the first embodiment is substantially the same as that of the first embodiment. The difference between the first and second embodiments is that the semiconductor chip 60 has a solder pad 602 formed at a position near both edges of the working surface. Opening portions 6 parallel to each other in the substrate 61 corresponding to the solder pads 602 of the semiconductor chip 60.
12 are provided, and when the semiconductor chip 60 is bonded onto the base body 610 of the substrate 61, each solder pad 60
2 is exposed in the opening 612 of the substrate 61 and the Au wire 62 is exposed.
The semiconductor chip 60 and the connection electrode layer 611 on the working surface are wire-bonded through the respective opening portions 612 to be electrically connected. The non-working surface of the semiconductor chip 60 is exposed on the upper sealing portion 63. This configuration is not shown because it can be easily inferred from the configuration shown in FIG. As shown in FIG. 9, each of the projections 64 of the semiconductor device 6 after completion of the sealing is provided.
Are exposed on the surface 650 of the lower sealing portion 65 in an array.

(Embodiment 6) FIG. 10 is a sectional view of a thin semiconductor device according to Embodiment 6 of the present invention. The configuration of the semiconductor device 7 according to the sixth embodiment is substantially the same as that of the first embodiment.
Solder pad 702 that moves to a position near the periphery of the working surface of
(Referred to as a peripheral pad method), and four rectangular openings 712 are provided in the substrate 71 corresponding to the solder pads 702 of the peripheral pad method, and each of the solder pads 702 corresponds to the substrate 71. The semiconductor chip 70 is exposed to the openings 712 and bonded to the base body 710 of the substrate 71, and the Au wires 72 are connected to the corresponding openings 712.
Through the connection electrode layer 71 of the semiconductor chip 70 and the substrate 71
1 is electrically connected by wire bonding to expose the non-working surface of the semiconductor chip 70 above the upper aggregate 73,
A heat radiation piece is provided on the exposed non-working surface to improve the heat radiation effect. This configuration can be easily inferred from the configuration shown in FIG. As shown in FIG. 11, the semiconductor device 7 has a surface end 740 of each projection 74 after completion of the sealing.
Are exposed on the surface 750 of the lower sealing portion 75 in an array.

Although the preferred embodiments of the present invention have been described above, these embodiments do not limit the scope of the present invention. Therefore, it is claimed that equivalent modifications and changes that can be completed on the basis of the gist disclosed in the present invention are included in the scope of the claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a thin semiconductor device according to Embodiment 1 of the present invention.

FIG. 2 is a top view of the thin semiconductor device according to the first embodiment of the present invention.

FIGS. 3A to 3H are views showing a manufacturing process of the thin semiconductor device according to the first embodiment of the present invention.

FIGS. 4A and 4B are diagrams showing another manufacturing process of the thin semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a thin semiconductor device according to Embodiment 2 of the present invention.

FIG. 6 is a sectional view of a thin semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a thin semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view of a thin semiconductor device according to a fifth embodiment of the present invention.

FIG. 9 is a top view of a thin semiconductor device according to Embodiment 5 of the present invention.

FIG. 10 is a sectional view of a thin semiconductor device according to a sixth embodiment of the present invention.

FIG. 11 is a top view of a thin semiconductor device according to Embodiment 6 of the present invention.

FIG. 12 is a sectional view of a conventional thin semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor device (conventional) 10 Semiconductor chip 11 Substrate 110 Opening part 111 Conductive trace 112 Solder mask layer 12 Au wire 120 Wire loop upper end point 13 Lower glue part 14 Solder ball 15 Upper glue part 2 Semiconductor device (first embodiment) 20 Semiconductor chip 200 Active surface 201 Non-active surface 202 Solder pad 21 Substrate 210 Base layer 211 Conductive trace 211a Solder pad 211b Solder pad 212 Opening 22 Au wire 220 Wire loop upper end point 23 Upper glue portion 24 Solder ball 24 'Projection 240 Bottom surface 240 ′ Bottom end surface 25 Lower glue portion 250 Bottom surface 3 Semiconductor device (second embodiment) 30 Semiconductor chip 301 Non-conductive surface 31 Substrate 33 Upper glue portion 330 Upper surface 36 Radie 4 Semiconductor device (Embodiment 3) 40 Semiconductor chip 401 Non-conductive surface 41 Substrate 43 Upper aggregate 430 Upper surface 46 Radiator 460 Upper end 5 Semiconductor device (Embodiment 4) 50 Semiconductor chip 51 Substrate 510 Base layer 53 Upper aggregate 56 Radiator 560 Slot 6 Semiconductor device (Embodiment 5) 60 Semiconductor chip 61 Substrate 610 Base layer 612 Opening portion 62 Au wire 63 Upper aggregate portion 64 Projection 640 Bottom end surface 65 Lower aggregate portion 650 Bottom surface 7 Semiconductor device (Embodiment 6) ) 70 Semiconductor chip 702 Solder pad 71 Substrate 710 Base layer 711 Conductive trace 712 Opening 72 Au line 73 Upper aggregate 74 Projection 740 Bottom end surface 75 Lower aggregate 750 Bottom surface

Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court II (Reference) H01L 23/31 (72) Inventor Chun-Che Tsai Taiwan, Taipei, Xianguin Street, Number 14, 2F.Fterm ( Reference) 4M109 AA01 BA03 CA21 DB03 5F061 AA01 BA03 CA21 CB13

Claims (8)

[Claims] 1. A substrate having at least one opening, a base body and a connection electrode layer including a plurality of connection electrodes on one surface of the base body, an operation surface including an electronic circuit and an electronic member, and the operation. A semiconductor chip having an opposite side and a non-working surface with respect to a surface, wherein the working surface is bonded to a surface of the base of the substrate opposite to the connection electrode layer; A first conductive member that connects the chip and the connection electrode layer of the substrate; a second conductive member provided on the connection electrode layer for electrical connection between the semiconductor chip and the outside; A surface of the base body opposite to the connection electrode layer,
A first sealing portion covering at least a portion of the semiconductor chip, and a second sealing portion completely covering the connection electrode layer, the first conductive member, and the opening of the substrate; and And exposing the surface of the second conductive member from the surface of the second sealing portion, and exposing the surface of the second conductive member to the second sealing member.
Wherein the surface of the sealing portion is formed on the same surface. 2. The thin semiconductor device according to claim 1, wherein said first conductive member is an Au wire, and said second conductive member is a solder ball. 3. The method according to claim 2, wherein the second conductive member is a protrusion (1 ump).
The thin semiconductor device according to claim 1, wherein 4. The material of the projection is made of one material selected from the group consisting of copper (Cu), aluminum (A1), copper alloy, aluminum alloy, and tin-lead alloy. Item 4. A thin semiconductor device according to item 3. 5. The thin semiconductor device according to claim 1, wherein at least a part of a non-working surface of said semiconductor chip is exposed from an upper surface of said upper sealing portion. 6. The thin semiconductor device according to claim 1, wherein the entire non-working surface of the semiconductor chip is covered with the upper sealing portion. 7. The thin semiconductor device according to claim 1, wherein a heat radiation piece is provided on a non-working surface of said semiconductor chip. 8. A method for manufacturing a thin semiconductor device, comprising: preparing a base having at least one opening and forming a base and a connection electrode layer including a plurality of connection electrodes on one surface of the base. Bonding a semiconductor chip having an operation surface including an electronic circuit and an electronic member to a predetermined position on a surface of the base body opposite to the surface having the connection electrode layer; and Connecting the first conductive member to the connection electrode layer of the semiconductor chip and the front substrate; and a first sealing portion formed on a surface of the base body opposite to the surface having the connection electrode layer on the base body. Covering at least a part of the semiconductor chip; forming a plurality of second conductive members in an array on the connection electrode layer of the substrate; and forming a plurality of second conductive members in an array on the surface of the substrate where the connection electrode layer is located. Second sealing To completely cover the connection electrode layer, the first conductive member, and the opening, and integrally combine the second conductive member and the second sealing portion to form the second conductive member. A step of exposing a surface from the surface of the second sealing portion, and a step of making the surface of the second conductive member and the surface of the second sealing portion flush with each other. Production method.