JP2002141357A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002141357A JP2002141357A JP2000332463A JP2000332463A JP2002141357A JP 2002141357 A JP2002141357 A JP 2002141357A JP 2000332463 A JP2000332463 A JP 2000332463A JP 2000332463 A JP2000332463 A JP 2000332463A JP 2002141357 A JP2002141357 A JP 2002141357A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- semiconductor device
- transistor
- semiconductor substrate
- coat layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 239000011521 glass Substances 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 32
- 230000006698 induction Effects 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 42
- 239000001257 hydrogen Substances 0.000 description 12
- 229910052739 hydrogen Inorganic materials 0.000 description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002485 combustion reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000075 oxide glass Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
- F02P3/00—Other installations
- F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
- F02P3/04—Layout of circuits
- F02P3/0407—Opening or closing the primary coil circuit with electronic switching means
- F02P3/0435—Opening or closing the primary coil circuit with electronic switching means with semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、自動車等の点火コ
イルの制御用半導体装置に関し、特に、トランジスタと
ツェナーダイオードを含む半導体装置に関する。The present invention relates to a semiconductor device for controlling an ignition coil of an automobile or the like, and more particularly, to a semiconductor device including a transistor and a zener diode.
【０００２】[0002]
【従来の技術】図４は、自動車等の内燃機関の点火回路
である。かかる点火回路は、点火コイルの制御用半導体
装置２１を含む。半導体装置２１のカソード端子（Ｃ）
には、誘導コイル２２と電源２３が接続されている。半
導体装置２１のゲート端子（Ｇ）には、抵抗２５が接続
されている。ゲート端子（Ｇ）には、半導体装置２１の
制御信号２６が入力される。また、半導体装置２１のエ
ミッタ端子（Ｅ）は接地されている。2. Description of the Related Art FIG. 4 shows an ignition circuit for an internal combustion engine of an automobile or the like. Such an ignition circuit includes a semiconductor device 21 for controlling an ignition coil. Cathode terminal (C) of semiconductor device 21
Is connected to an induction coil 22 and a power supply 23. The resistor 25 is connected to the gate terminal (G) of the semiconductor device 21. The control signal 26 of the semiconductor device 21 is input to the gate terminal (G). The emitter terminal (E) of the semiconductor device 21 is grounded.
【０００３】半導体装置２１は、絶縁ゲート型バイポー
ラトランジスタ（以下、「ＩＧＢＴ」という。）２７を
含む。ＩＧＢＴ２７のゲート、カソード間には、ツェナ
ーダイオード２８とダイオード２９とが直列に接続され
ている。The semiconductor device 21 includes an insulated gate bipolar transistor (hereinafter referred to as "IGBT") 27. A Zener diode 28 and a diode 29 are connected in series between the gate and the cathode of the IGBT 27.
【０００４】かかる点火回路では、制御信号２６により
ＩＧＢＴ２７をオン状態からオフ状態に変えると、誘導
コイル２２の１次側に所定の電圧が発生する。かかる電
圧は、ツェナーダイオード２８が設けられていることに
より、常に一定の電圧（以下、「クランプ電圧」とい
う。）となる。この結果、誘導コイル２２の２次側に
も、一定の誘導電圧が発生し、点火プラグ２４の両端に
この誘導電圧が印加される。これにより、端子間に火花
が飛んで内燃機関等を点火する。安定した点火を得るた
めには、点火プラグ２４の両端に、常に一定の電圧が印
加される必要がある。In such an ignition circuit, when the IGBT 27 is changed from the on state to the off state by the control signal 26, a predetermined voltage is generated on the primary side of the induction coil 22. Such a voltage is always a constant voltage (hereinafter, referred to as “clamp voltage”) due to the provision of the Zener diode 28. As a result, a constant induction voltage is also generated on the secondary side of the induction coil 22, and this induction voltage is applied to both ends of the spark plug 24. As a result, sparks fly between the terminals to ignite the internal combustion engine or the like. In order to obtain stable ignition, it is necessary to apply a constant voltage to both ends of the spark plug 24 at all times.
【０００５】図５は、点火回路に使用される、全体が符
号１５０で示される従来の半導体装置の断面図である。
かかる半導体装置１５０では、ｎ型のシリコン半導体基
板１にｐ型ウエル２が形成され、その中にｎ型のソース
領域３が形成されている。ウエル２上には絶縁層８を介
してゲート電極層９が設けられている。また、ウエル２
上に、ウエル２と電気的に接続されたエミッタ電極１０
が設けられている。FIG. 5 is a cross-sectional view of a conventional semiconductor device generally designated by reference numeral 150 used in an ignition circuit.
In such a semiconductor device 150, a p-type well 2 is formed on an n-type silicon semiconductor substrate 1, and an n-type source region 3 is formed therein. On the well 2, a gate electrode layer 9 is provided via an insulating layer 8. Also, well 2
On top, an emitter electrode 10 electrically connected to the well 2
Is provided.
【０００６】半導体基板１の上には、また、フィールド
酸化膜６が設けられ、その上に多結晶シリコンからなる
ツェナーダイオード７が形成される。ツェナーダイオー
ド７は、複数のｐｎ接合面を有し、各ｐｎ接合面は、半
導体基板１の表面に略垂直となる。図５では、ツェナー
ダイオード７と直列となるように、ダイオード（図４に
符号２９で表示）が形成されている。また、ツェナーダ
イオード７の上には、絶縁層８が設けられ、絶縁層８に
設けられた孔を介して、ゲート電極１１、コレクタ電極
１２がツェナーダイオード７に電気的に接続されてい
る。なお、ゲート電極１１とゲート電極層９とは電気的
に接続されている。また、ツェナーダイオード７の下方
の半導体基板１には、ｐ型のガードリング層４が設けら
れている。On the semiconductor substrate 1, a field oxide film 6 is further provided, on which a Zener diode 7 made of polycrystalline silicon is formed. Zener diode 7 has a plurality of pn junction surfaces, and each pn junction surface is substantially perpendicular to the surface of semiconductor substrate 1. In FIG. 5, a diode (indicated by reference numeral 29 in FIG. 4) is formed so as to be in series with the Zener diode 7. An insulating layer 8 is provided on the Zener diode 7, and the gate electrode 11 and the collector electrode 12 are electrically connected to the Zener diode 7 via holes provided in the insulating layer 8. Note that the gate electrode 11 and the gate electrode layer 9 are electrically connected. A p-type guard ring layer 4 is provided on the semiconductor substrate 1 below the Zener diode 7.
【０００７】半導体基板１の上面には、保護膜として窒
化シリコンからなるガラスコート層１３が形成される。On the upper surface of the semiconductor substrate 1, a glass coat layer 13 made of silicon nitride is formed as a protective film.
【０００８】一方、半導体基板１の裏面には、ｎ型バッ
ファ層１４、ｐ型コレクタ層１５が順次積層される。最
後に、ｐ型コレクタ層１５上に、コレクタ電極１６が形
成される。On the other hand, on the back surface of the semiconductor substrate 1, an n-type buffer layer 14 and a p-type collector layer 15 are sequentially laminated. Finally, a collector electrode 16 is formed on the p-type collector layer 15.
【０００９】[0009]
【発明が解決しようとする課題】しかし、図４の半導体
装置２１に、図５の半導体装置１５０を用いた点火回路
において、半導体装置１５０のスイッチング（オン／オ
フ）を、例えば、数１００万サイクル行った場合、クラ
ンプ電圧が上昇し、点火プラグ２４の両端に印加される
電圧が大幅に変化するという問題があった。However, in the ignition circuit using the semiconductor device 150 of FIG. 5 in the semiconductor device 21 of FIG. 4, switching (on / off) of the semiconductor device 150 is performed, for example, for several million cycles. If this is done, there is a problem that the clamp voltage increases and the voltage applied to both ends of the spark plug 24 changes significantly.
【００１０】そこで、本発明は、点火回路において、ク
ランプ電圧の上昇を防止し、点火プラグの両端に一定の
電圧を印加するための半導体装置を提供することを目的
とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device for preventing a clamp voltage from increasing in an ignition circuit and applying a constant voltage to both ends of an ignition plug.
【００１１】[0011]
【課題を解決するための手段】そこで、発明者は鋭意研
究の結果、半導体装置のガラスコート層を形成する工程
では、水素雰囲気中で半導体装置を加熱するが、かかる
工程でガラスコート層中に含まれた水素が、スイッチン
グ動作によってツェナーダイオード中に拡散し、ツェナ
ー電圧を変化させることを見出し本発明を完成した。Therefore, as a result of intensive studies, the present inventors have found that in the step of forming a glass coat layer of a semiconductor device, the semiconductor device is heated in a hydrogen atmosphere, and in such a step, the glass coat layer is formed in the glass coat layer. The inventors have found that the contained hydrogen diffuses into the Zener diode by the switching operation and changes the Zener voltage, and thus completed the present invention.
【００１２】即ち、本発明は、コレクタが誘導コイルに
接続されたトランジスタと、該トランジスタの該コレク
タとゲートとの間に接続されたツェナーダイオードとを
含み、該ゲートに入力された信号に応じて、該誘導コイ
ルに一定の誘導電圧を発生させる半導体装置であって、
半導体基板と、該半導体基板に形成されたトランジスタ
と、該半導体基板上に、ｐｎ接合面が該半導体基板の表
面に対して略垂直になるように形成されたツェナーダイ
オードと、該ツェナーダイオードを覆うように、該半導
体基板上に形成されたガラスコート層とを含み、該ガラ
スコート層が、酸化シリコン膜であることを特徴とする
半導体装置である。ガラスコート層を酸化シリコンから
形成することにより、ガラスコート層の製造工程を従来
のように水素還元雰囲気中で行う必要がなくなる。この
ため、スイッチング動作におけるツェナーダイオード中
への水素の拡散を防ぎ、半導体装置のクランプ電圧の変
化を低減できる。That is, the present invention includes a transistor having a collector connected to an induction coil, and a Zener diode connected between the collector and the gate of the transistor, and responds to a signal input to the gate. A semiconductor device for generating a constant induced voltage in the induction coil,
A semiconductor substrate, a transistor formed on the semiconductor substrate, a zener diode formed on the semiconductor substrate such that a pn junction surface is substantially perpendicular to a surface of the semiconductor substrate, and covering the zener diode And a glass coat layer formed on the semiconductor substrate, wherein the glass coat layer is a silicon oxide film. By forming the glass coat layer from silicon oxide, it is not necessary to perform the manufacturing process of the glass coat layer in a hydrogen reducing atmosphere as in the related art. Therefore, diffusion of hydrogen into the Zener diode during the switching operation can be prevented, and a change in the clamp voltage of the semiconductor device can be reduced.
【００１３】また、本発明は、コレクタが誘導コイルに
接続されたトランジスタと、該トランジスタの該コレク
タとゲートとの間に接続されたツェナーダイオードとを
含み、該ゲートに入力された信号に応じて、該誘導コイ
ルに一定の誘導電圧を発生させる半導体装置であって、
半導体基板と、該半導体基板に形成されたトランジスタ
と、該半導体基板上に、ｐｎ接合面が該半導体基板の表
面に対して略垂直になるように形成されたツェナーダイ
オードと、該半導体基板上に形成された、窒化シリコン
からなるガラスコート層とを含み、該ガラスコート層
が、該ツェナーダイオードのｐｎ接合面の上方を除く領
域に形成されたことを特徴とする半導体装置でもある。
かかる構造を用いることによっても、ツェナーダイオー
ド中への水素の拡散を防ぎ、半導体装置のクランプ電圧
の変化を低減できる。なお、窒化シリコンからなるガラ
スコート層は、少なくともツェナーダイオードのｐｎ接
合面の上方を除いた領域に形成することにより、半導体
装置のクランプ電圧の変化を有効に抑えることができ
る。Further, the present invention includes a transistor having a collector connected to the induction coil, and a Zener diode connected between the collector and the gate of the transistor, and responds to a signal input to the gate. A semiconductor device for generating a constant induced voltage in the induction coil,
A semiconductor substrate, a transistor formed on the semiconductor substrate, a Zener diode formed on the semiconductor substrate such that a pn junction surface is substantially perpendicular to a surface of the semiconductor substrate, And a glass coat layer formed of silicon nitride, wherein the glass coat layer is formed in a region excluding above a pn junction surface of the Zener diode.
By using such a structure, diffusion of hydrogen into the Zener diode can be prevented, and a change in the clamp voltage of the semiconductor device can be reduced. The glass coat layer made of silicon nitride is formed at least in a region excluding the region above the pn junction surface of the Zener diode, so that a change in clamp voltage of the semiconductor device can be effectively suppressed.
【００１４】上記ツェナーダイオードは複数のｐｎ接合
を有するものであっても良い。The Zener diode may have a plurality of pn junctions.
【００１５】上記ツェナーダイオードのｎ型領域が上記
トランジスタの上記ゲートに接続され、該ツェナーダイ
オードのｐ型領域が該トランジスタの該コレクタに接続
されたことが好ましい。It is preferable that an n-type region of the Zener diode is connected to the gate of the transistor, and a p-type region of the Zener diode is connected to the collector of the transistor.
【００１６】上記ツェナーダイオードが、上記半導体基
板上に形成されたフィールド酸化膜上に形成され、更
に、該ツェナーダイオードと上記ガラスコート層との間
に、絶縁膜が形成されたことが好ましい。It is preferable that the Zener diode is formed on a field oxide film formed on the semiconductor substrate, and that an insulating film is formed between the Zener diode and the glass coat layer.
【００１７】上記ツェナーダイオードは、多結晶シリコ
ンからなるものでも良い。The Zener diode may be made of polycrystalline silicon.
【００１８】更に、上記トランジスタの上記コレクタと
上記ゲートとの間に、上記ツェナーダイオードと逆向き
の順方向を有するダイオードを、該ツェナーダイオード
と直列に設けたことを特徴とする半導体装置でもある。Further, there is provided a semiconductor device in which a diode having a forward direction opposite to that of the Zener diode is provided between the collector and the gate of the transistor in series with the Zener diode.
【００１９】上記トランジスタは、絶縁ゲート型バイポ
ーラトランジスタであることが好ましい。Preferably, the transistor is an insulated gate bipolar transistor.
【００２０】[0020]
【発明の実施の形態】実施の形態１．図１に、本実施の
形態にかかる半導体装置の断面図である。図１の半導体
装置は、図５に示す半導体装置の窒化シリコンからなる
ガラスコート層３３を、酸化シリコンからなるガラスコ
ート層１３に置き換えたものである。他の構成部分は、
図５と同じである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. In the semiconductor device of FIG. 1, the glass coat layer 33 made of silicon nitride in the semiconductor device shown in FIG. 5 is replaced with a glass coat layer 13 made of silicon oxide. The other components are
It is the same as FIG.
【００２１】図１の半導体装置では、半導体基板１の上
に、ツェナーダイオード６や電極１０、１１、１２等を
形成した後に、酸化シリコンガラスコート層１３を表面
に堆積させる。かかる酸化シリコンガラスコート層１３
の堆積には、例えば、熱ＣＶＤ法が用いられる。熱ＣＶ
Ｄ法では、ツェナーダイオード６等が形成された半導体
基板１が加熱炉に入れられて加熱され、更に、加熱炉中
にＳｉＨ4とＯ2が導入される。この結果、半導体基板１
上に酸化シリコンのガラスコート層１３が形成される。In the semiconductor device shown in FIG. 1, after forming a Zener diode 6, electrodes 10, 11, 12 and the like on a semiconductor substrate 1, a silicon oxide glass coat layer 13 is deposited on the surface. Such silicon oxide glass coat layer 13
For example, a thermal CVD method is used for the deposition. Thermal CV
In the D method, the semiconductor substrate 1 on which the Zener diode 6 and the like are formed is heated in a heating furnace, and further, SiH 4 and O 2 are introduced into the heating furnace. As a result, the semiconductor substrate 1
A glass coat layer 13 of silicon oxide is formed thereon.
【００２２】このように、ガラスコート層１３の材料に
酸化シリコンを使用すると、ガラスコート層１３の製造
工程を水素還元雰囲気中で行う必要がなくなる。即ち、
従来のガラスコート層３３のように、水素還元雰囲気中
で形成することが必要な窒化シリコンに代えて、酸素雰
囲気中で形成できる酸化シリコンからガラスコート層１
３を形成することにより、ガラスコート層１３の堆積工
程で水素が含まれることがなく、スイッチング動作によ
り絶縁膜８を通ってツェナーダイオード６に水素が拡散
するのを防止することができる。As described above, when silicon oxide is used as the material of the glass coat layer 13, it is not necessary to perform the manufacturing process of the glass coat layer 13 in a hydrogen reducing atmosphere. That is,
Instead of silicon nitride which needs to be formed in a hydrogen reducing atmosphere like the conventional glass coat layer 33, the glass coat layer 1 is made of silicon oxide which can be formed in an oxygen atmosphere.
By forming 3, no hydrogen is contained in the deposition step of the glass coat layer 13, and diffusion of hydrogen into the Zener diode 6 through the insulating film 8 by the switching operation can be prevented.
【００２３】図２は、本実施の形態にかかる半導体装置
１００と、従来の半導体装置１５０を用いた点火回路
の、点火サイクルとクランプ電圧の変化率との関係であ
る。図２の横軸は点火サイクルであり、半導体装置のオ
ン／オフを１サイクルとする。また、縦軸は誘導コイル
２２の１次側に発生するクランプ電圧の変化率である。FIG. 2 shows the relationship between the ignition cycle and the rate of change of the clamp voltage of the semiconductor device 100 according to the present embodiment and the ignition circuit using the conventional semiconductor device 150. The horizontal axis in FIG. 2 is the ignition cycle, and the on / off of the semiconductor device is one cycle. The vertical axis indicates the rate of change of the clamp voltage generated on the primary side of the induction coil 22.
【００２４】図２において、（ａ）で示す結果は、従来
の半導体装置１５０を用いた点火回路の場合であり、
（ｂ）で示す結果は、本実施の形態にかかる半導体装置
１００を用いた点火回路の場合である。図２から明らか
なように、１０００万サイクルの点火を行った場合、従
来の半導体装置１５０ではクランプ電圧が約５．７％変
化するのに対し、本実施の形態にかかる半導体装置１０
１では、約０．４％の変化に抑えることができる。In FIG. 2, the result shown in FIG. 2A is a case of the ignition circuit using the conventional semiconductor device 150,
The result shown in (b) is for an ignition circuit using the semiconductor device 100 according to the present embodiment. As apparent from FIG. 2, when ignition is performed for 10 million cycles, the clamp voltage changes by about 5.7% in the conventional semiconductor device 150, whereas the semiconductor device 10 according to the present embodiment changes.
In the case of 1, the change can be suppressed to about 0.4%.
【００２５】このように、ガラスコート層１３の材料に
酸化シリコンを用いることにより、半導体装置１００の
製造工程において、ツェナーダイオード６の中に水素が
拡散するのを防止でき、ツェナーダイオード６のツェナ
ー電圧の変化を防止することができる。この結果、点火
回路の誘導コイルの１次側に印加されるクランプ電圧の
変化を約１５分の１に低減できる。As described above, by using silicon oxide as the material of the glass coat layer 13, it is possible to prevent hydrogen from diffusing into the Zener diode 6 in the manufacturing process of the semiconductor device 100, Can be prevented from changing. As a result, the change in the clamp voltage applied to the primary side of the induction coil of the ignition circuit can be reduced to about 1/15.
【００２６】実施の形態２．図３は、本実施の形態にか
かる半導体装置の断面図である。図３の半導体装置で
は、ガラスコート層３３は窒化シリコンから形成されて
いるが、その形成領域は、ツェナーダイオードのｐｎ接
合面の上方を除く領域に限定されている。Embodiment 2 FIG. FIG. 3 is a sectional view of the semiconductor device according to the present embodiment. In the semiconductor device of FIG. 3, the glass coat layer 33 is formed of silicon nitride, but its formation region is limited to a region except above the pn junction surface of the Zener diode.
【００２７】図３の半導体装置１０１では、実施の形態
１と同様に、ツェナーダイオード７、絶縁層８、電極１
０、１１、１２等が半導体基板１上に形成された後、従
来と同様に、例えば熱ＣＶＤ法を用いて窒化シリコンか
らなるガラスコート層３３を全面に形成する。In the semiconductor device 101 shown in FIG. 3, similarly to the first embodiment, the Zener diode 7, the insulating layer 8, the electrode 1
After the layers 0, 11, 12 and the like are formed on the semiconductor substrate 1, a glass coat layer 33 made of silicon nitride is formed on the entire surface by using, for example, a thermal CVD method as in the related art.
【００２８】窒化シリコンは、水素還元雰囲気中で形成
されるが、本実施の形態では、ツェナーダイオード７の
ｐｎ接合面１７の上方のガラスコート層３３をエッチン
グで除去するため、スイッチング動作により水素がツェ
ナーダイオード７中に拡散するのを防止することができ
る。なお、ツェナーダイオード７の上部は絶縁層８で覆
われているため、開口部１８を形成しても耐湿性の劣化
等の問題は生じない。Although silicon nitride is formed in a hydrogen reducing atmosphere, in the present embodiment, the glass coat layer 33 above the pn junction surface 17 of the Zener diode 7 is removed by etching, so that hydrogen is removed by a switching operation. Diffusion into the Zener diode 7 can be prevented. Since the upper part of the Zener diode 7 is covered with the insulating layer 8, even if the opening 18 is formed, there is no problem such as deterioration of moisture resistance.
【００２９】[0029]
【発明の効果】以上の説明から明らかなように、本発明
にかかる半導体装置を点火回路に使用することにより、
安定した点火動作を繰り返すことが可能となる。As is apparent from the above description, by using the semiconductor device according to the present invention in an ignition circuit,
It is possible to repeat a stable ignition operation.
【図１】 本発明の第１の実施の形態にかかる半導体装
置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】 点火プラグの点火サイクルと誘導コイルの１
次電圧の変化率との関係である。FIG. 2 shows the ignition cycle of a spark plug and one of an induction coil.
This is the relationship with the rate of change of the next voltage.
【図３】 本発明の第２の実施の形態にかかる半導体装
置の断面図である。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
【図４】 内燃機関の点火回路の回路図である。FIG. 4 is a circuit diagram of an ignition circuit of the internal combustion engine.
【図５】 従来の半導体装置の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device.
１ 半導体基板、２ ウエル、３ ソース領域、４ ガ
ードリング、５ ｎ+領域、６ 層間絶縁膜、７ ツェ
ナーダイオード、８ 絶縁膜、９ ゲート配線層、１０
エミッタ電極、１１ ゲート電極、１２ コレクタ電
極、１３ ガラスコート層、１４ バッファ層、１５
コレクタ層、１６ コレクタ電極、１７ｐｎ接合面、１
８ 開口部、１００、１０１ 半導体装置。DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 wells, 3 source regions, 4 guard rings, 5 n + regions, 6 interlayer insulating films, 7 Zener diodes, 8 insulating films, 9 gate wiring layers, 10
Emitter electrode, 11 Gate electrode, 12 Collector electrode, 13 Glass coat layer, 14 Buffer layer, 15
Collector layer, 16 collector electrode, 17 pn junction surface, 1
8 Openings, 100, 101 Semiconductor device.
Claims (8)
ンジスタと、該トランジスタの該コレクタとゲートとの
間に接続されたツェナーダイオードとを含み、該ゲート
に入力された信号に応じて、該誘導コイルに一定の誘導
電圧を発生させる半導体装置であって、 半導体基板と、 該半導体基板に形成されたトランジスタと、 該半導体基板上に、ｐｎ接合面が該半導体基板の表面に
対して略垂直になるように形成されたツェナーダイオー
ドと、 該ツェナーダイオードを覆うように、該半導体基板上に
形成されたガラスコート層とを含み、 該ガラスコート層が、酸化シリコン膜であることを特徴
とする半導体装置。1. A transistor having a collector connected to an induction coil and a Zener diode connected between the collector and the gate of the transistor, wherein the induction coil is responsive to a signal input to the gate. A semiconductor device that generates a constant induced voltage, wherein: a semiconductor substrate; a transistor formed on the semiconductor substrate; and a pn junction surface on the semiconductor substrate being substantially perpendicular to a surface of the semiconductor substrate. Semiconductor device, comprising: a Zener diode formed as described above; and a glass coat layer formed on the semiconductor substrate so as to cover the Zener diode, wherein the glass coat layer is a silicon oxide film. .
ンジスタと、該トランジスタの該コレクタとゲートとの
間に接続されたツェナーダイオードとを含み、該ゲート
に入力された信号に応じて、該誘導コイルに一定の誘導
電圧を発生させる半導体装置であって、 半導体基板と、 該半導体基板に形成されたトランジスタと、 該半導体基板上に、ｐｎ接合面が該半導体基板の表面に
対して略垂直になるように形成されたツェナーダイオー
ドと、 該半導体基板上に形成された、窒化シリコンからなるガ
ラスコート層とを含み、 該ガラスコート層が、該ツェナーダイオードのｐｎ接合
面の上方を除く領域に形成されたことを特徴とする半導
体装置。2. A transistor having a collector connected to an induction coil and a Zener diode connected between the collector and the gate of the transistor, wherein the induction coil is responsive to a signal input to the gate. A semiconductor device that generates a constant induced voltage, wherein: a semiconductor substrate; a transistor formed on the semiconductor substrate; and a pn junction surface on the semiconductor substrate being substantially perpendicular to a surface of the semiconductor substrate. And a glass coat layer made of silicon nitride formed on the semiconductor substrate, wherein the glass coat layer is formed in a region excluding above a pn junction surface of the Zener diode. A semiconductor device characterized by the above-mentioned.
合面を有することを特徴とする請求項１又は２のいずれ
かに記載の半導体装置。3. The semiconductor device according to claim 1, wherein said Zener diode has a plurality of pn junction surfaces.
記トランジスタの上記ゲートに接続され、該ツェナーダ
イオードのｐ型領域が該トランジスタの該コレクタに接
続されたことを特徴とする請求項１又は２のいずれかに
記載の半導体装置。4. The transistor according to claim 1, wherein an n-type region of said Zener diode is connected to said gate of said transistor, and a p-type region of said Zener diode is connected to said collector of said transistor. The semiconductor device according to any one of the above.
基板上に形成されたフィールド酸化膜上に形成され、更
に、該ツェナーダイオードと上記ガラスコート層との間
に、絶縁膜が形成されたことを特徴とする請求項１又は
２のいずれかに記載の半導体装置。5. The semiconductor device according to claim 1, wherein the Zener diode is formed on a field oxide film formed on the semiconductor substrate, and further, an insulating film is formed between the Zener diode and the glass coat layer. The semiconductor device according to claim 1.
コンからなることを特徴とする請求項１又は２のいずれ
かに記載の半導体装置。6. The semiconductor device according to claim 1, wherein said Zener diode is made of polycrystalline silicon.
と上記ゲートとの間に、上記ツェナーダイオードと逆向
きの順方向を有するダイオードを、該ツェナーダイオー
ドと直列に設けたことを特徴とする請求項１又は２のい
ずれかに記載の半導体装置。7. A diode having a forward direction opposite to that of the Zener diode is provided between the collector and the gate of the transistor in series with the Zener diode. Or the semiconductor device according to any one of 2.
ポーラトランジスタであることを特徴とする請求項１又
は２のいずれかに記載の半導体装置。8. The semiconductor device according to claim 1, wherein said transistor is an insulated gate bipolar transistor.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000332463A JP2002141357A (en) | 2000-10-31 | 2000-10-31 | Semiconductor device |
| US09/828,949 US6495866B2 (en) | 2000-10-31 | 2001-04-10 | Semiconductor device for preventing an increased clamp voltage in an ignition circuit |
| KR10-2001-0025385A KR100417097B1 (en) | 2000-10-31 | 2001-05-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000332463A JP2002141357A (en) | 2000-10-31 | 2000-10-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002141357A true JP2002141357A (en) | 2002-05-17 |
Family
ID=18808665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000332463A Pending JP2002141357A (en) | 2000-10-31 | 2000-10-31 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6495866B2 (en) |
| JP (1) | JP2002141357A (en) |
| KR (1) | KR100417097B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014142331A1 (en) | 2013-03-14 | 2014-09-18 | 富士電機株式会社 | Semiconductor device |
| WO2024135106A1 (en) * | 2022-12-22 | 2024-06-27 | 新電元工業株式会社 | Active clamp circuit and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1321090B1 (en) * | 2000-11-24 | 2003-12-30 | St Microelectronics Srl | SYSTEM AND PROCEDURE FOR THE CONTROL OF THE RESPONSE TO THE STEP OF ELECTRONIC COMPONENTS. |
| JP4136778B2 (en) * | 2003-05-07 | 2008-08-20 | 富士電機デバイステクノロジー株式会社 | Insulated gate bipolar transistor |
| JP4889072B2 (en) * | 2003-12-19 | 2012-02-29 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device |
| JP2005354031A (en) * | 2004-05-13 | 2005-12-22 | Mitsubishi Electric Corp | Semiconductor device |
| JP2005340550A (en) * | 2004-05-28 | 2005-12-08 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2005353991A (en) * | 2004-06-14 | 2005-12-22 | Sanyo Electric Co Ltd | Semiconductor device |
| US7258244B2 (en) * | 2004-10-04 | 2007-08-21 | Graham Packaging Company L.P. | Hot-fill plastic container and method of manufacture |
| JP5138274B2 (en) * | 2007-05-25 | 2013-02-06 | 三菱電機株式会社 | Semiconductor device |
| JP5332175B2 (en) * | 2007-10-24 | 2013-11-06 | 富士電機株式会社 | Semiconductor device provided with control circuit |
| KR20090112088A (en) * | 2008-04-23 | 2009-10-28 | 삼성전자주식회사 | Organic light emitting device and manufacturing method thereof |
| CN103839805B (en) * | 2012-11-23 | 2018-09-11 | 中国科学院微电子研究所 | Preparation method of power device |
| US20140264434A1 (en) * | 2013-03-15 | 2014-09-18 | Fairchild Semiconductor Corporation | Monolithic ignition insulated-gate bipolar transistor |
| DE102014005879B4 (en) * | 2014-04-16 | 2021-12-16 | Infineon Technologies Ag | Vertical semiconductor device |
| JP2015230896A (en) * | 2014-06-03 | 2015-12-21 | ソニー株式会社 | Solid-state image pickup device, manufacturing method for the same and electronic equipment |
| US10090294B2 (en) * | 2016-03-04 | 2018-10-02 | Rohm Co., Ltd. | Semiconductor device |
| US10522674B2 (en) * | 2016-05-18 | 2019-12-31 | Rohm Co., Ltd. | Semiconductor with unified transistor structure and voltage regulator diode |
| JP2018067570A (en) * | 2016-10-17 | 2018-04-26 | 富士電機株式会社 | Semiconductor device |
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|---|---|---|---|---|
| EP0144654A3 (en) * | 1983-11-03 | 1987-10-07 | General Electric Company | Semiconductor device structure including a dielectrically-isolated insulated-gate transistor |
| DE3417474A1 (en) * | 1984-05-11 | 1985-11-14 | Robert Bosch Gmbh, 7000 Stuttgart | MONOLITHICALLY INTEGRATED PLANAR SEMICONDUCTOR ARRANGEMENT |
| JP2672694B2 (en) * | 1990-07-13 | 1997-11-05 | 松下電子工業株式会社 | MOSFET |
| US5397914A (en) * | 1992-04-30 | 1995-03-14 | Hitachi Ltd. | Power transistor device including power transistors in darlington connection and zener diode which is coupled between collector and base of power transistors and which is formed in polysilicon film |
| JPH06275634A (en) | 1993-03-19 | 1994-09-30 | Hitachi Ltd | Power transistor device |
| US5536958A (en) * | 1995-05-02 | 1996-07-16 | Motorola, Inc. | Semiconductor device having high voltage protection capability |
| US6100728A (en) * | 1995-07-31 | 2000-08-08 | Delco Electronics Corp. | Coil current limiting feature for an ignition coil driver module |
| JPH0945912A (en) * | 1995-07-31 | 1997-02-14 | Nec Corp | Semiconductor device and its manufacture |
| JP2000109816A (en) * | 1998-10-05 | 2000-04-18 | Okamoto Machine Tool Works Ltd | Preparation of polishing agent slurry |
| KR100660917B1 (en) * | 1999-02-03 | 2006-12-26 | 페어차일드코리아반도체 주식회사 | Ldmos |
-
2000
- 2000-10-31 JP JP2000332463A patent/JP2002141357A/en active Pending
-
2001
- 2001-04-10 US US09/828,949 patent/US6495866B2/en not_active Expired - Fee Related
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014142331A1 (en) | 2013-03-14 | 2014-09-18 | 富士電機株式会社 | Semiconductor device |
| US9406666B2 (en) | 2013-03-14 | 2016-08-02 | Fuji Electric Co., Ltd. | Semiconductor device |
| WO2024135106A1 (en) * | 2022-12-22 | 2024-06-27 | 新電元工業株式会社 | Active clamp circuit and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100417097B1 (en) | 2004-02-05 |
| US20020050603A1 (en) | 2002-05-02 |
| US6495866B2 (en) | 2002-12-17 |
| KR20020034839A (en) | 2002-05-09 |
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