JP2002134623A - Semiconductor integrated circuit and method for designing its layout - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit where an increase of a chip area can be prevented by surely and easily connecting an auxiliary power wiring of a cell part and a main power supply wiring to be located in the region of a macro part. SOLUTION: This semiconductor integrated circuit comprises a macro part 1, a contact region 3 provided outside the macro part 1, and a cell part 2 formed around the macro-part 1 except the contact region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit and a layout method thereof, and more particularly, to a semiconductor integrated circuit.
The present invention relates to a semiconductor integrated circuit including a large-scale macro unit such as a PU, a RAM, and a ROM and a layout method thereof.

[0002]

2. Description of the Related Art Conventionally, a CPU is provided on one semiconductor substrate.
Also, there is known a semiconductor integrated circuit in which a large-scale macro unit such as a RAM or a ROM is used as a core and a logic circuit is formed around the core as a core in accordance with the use of a target system. The logic circuit is constituted by cell units arranged around the macro unit.

[0003] As one method used for forming the above-mentioned semiconductor integrated circuit, a conventional CAD method has been used.
(Computer Aided Design) using ASI to easily realize application-specific devices
C (Application Specific Int
(Egrated Circuit) is known. As an ASIC design method, a gate array, a standard cell, and an embedded array are conventionally known as methods for efficiently designing a semi-custom LSI.

In the design of the ASIC as described above, in order to fix a signal line in a circuit formed in a cell portion to a power supply potential or a ground potential, an auxiliary power supply line arranged in the cell portion is replaced with a main power supply line ( (Main power supply potential line or main ground potential line). In this case, conventionally, the main power supply wiring is arranged in a ring outside the macro part, and the auxiliary power supply wiring of the cell part is connected to the ring-shaped main power supply wiring. This technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-36829.
No., for example.

FIG. 5 is a flow chart for explaining a conventional layout design method when the above-mentioned ring-shaped main power supply wiring is used. Referring to FIG. 5, conventionally,
First, when laying out the macro section, a ring-shaped main power supply wiring is arranged outside the macro section. Then, when connecting the auxiliary power supply wiring of the cell section, it is connected to a ring-shaped main power supply wiring arranged outside the macro section.

[0006]

In the conventional method using a ring-shaped main power supply line, as described above, the ring-shaped main power supply line is arranged outside the macro section. Here, a large amount of current flows through the main power supply wiring. Therefore, it is necessary to increase the width of the main power supply wiring in order to prevent electromigration and voltage drop due to wiring resistance. Conventionally, such a ring-shaped main power supply line having a large width is arranged outside the macro section, so that there is a problem that the chip area increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent an increase in chip area due to a main power supply wiring arrangement region. An object of the present invention is to provide a semiconductor integrated circuit and a layout method thereof.

Another object of the present invention is to provide a semiconductor integrated circuit and a layout method therefor which, even when a main power supply line is arranged on a macro part, the main power supply line and an auxiliary power supply line of a cell part are connected to each other. The purpose is to enable easy and reliable connection.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a macro portion; a contact region provided outside the macro portion; and a cell portion formed around the macro portion other than the contact region. Have. Note that the macro unit in the present invention means a functional block that becomes a core (core) such as a CPU, a RAM, and a ROM. The cell section means a functional block that is arranged around the macro section and forms a logic circuit, such as a basic cell or a standard cell of a gate array.

According to the first aspect of the present invention, for example, by utilizing the contact region located between the cell portion and the macro portion, for example, an auxiliary power supply line arranged in the cell portion and a macro portion are provided. Can be reliably and easily connected to the main power supply wiring arranged in the region of the above. This eliminates the necessity of arranging the main power supply wiring outside the macro part unlike the related art, and as a result, it is possible to prevent an increase in the chip area caused when the main power supply wiring is arranged outside the macro part. .

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, a main power supply line disposed in a region of a macro unit, a first auxiliary power supply line disposed in a cell unit,
A second auxiliary power supply line arranged in the region of the macro portion and electrically connected to the main power supply line, a first auxiliary power supply line of the cell portion and a second auxiliary power supply line of the macro portion formed in the contact region; And connection wiring for connecting the two.

According to the second aspect of the present invention, the first auxiliary power supply wiring of the cell portion and the second auxiliary power supply wiring of the macro portion can be easily formed by using the connection wiring formed in the contact region. Can be connected. This makes it possible to reliably and easily connect the first auxiliary power supply wiring of the cell section to the main power supply wiring of the macro section via the second auxiliary power supply wiring of the macro section. This eliminates the necessity of arranging the main power supply wiring outside the macro part unlike the related art, and as a result, it is possible to prevent an increase in the chip area caused when the main power supply wiring is arranged outside the macro part. . Note that the connection wiring formed in the contact region may have a small width unlike the main power supply wiring which requires a large width.
The width of the contact region may be small. Thus, even if the contact region is provided, there is no problem because the chip area does not increase so much.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the main power supply line includes one of a main power supply potential line and a main ground potential line. In claim 3,
With this configuration, the first auxiliary power supply line of the cell unit can be reliably and easily connected to the main power supply potential line or the main ground potential line of the macro unit.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the second or third aspect, the first integrated circuit is arranged in the cell portion.
The auxiliary power supply wiring and the second auxiliary power supply wiring arranged in the macro unit are arranged to extend in substantially the same direction.
According to the fourth aspect of the present invention, the first configuration is provided by the above configuration.
Since the auxiliary power supply wiring and the second auxiliary power supply wiring are connected substantially linearly without bending, the total wiring length of the first auxiliary power supply wiring and the second auxiliary power supply wiring can be shortened.
As a result, the wiring capacitance can be reduced, and as a result, the speed of the circuit operation can be increased.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to any one of the second to fourth aspects, the contact region has a multi-layer wiring structure, and the connection wiring includes a plurality of connections forming the multi-layer wiring in the contact region. A wiring layer and a first connection hole wiring connecting the plurality of connection wiring layers are included. According to claim 5, by configuring in this way,
Even when the first auxiliary power supply wiring and the second auxiliary power supply wiring are formed by different layers having different heights, the first auxiliary power supply wiring can be easily formed by using the plurality of connection wiring layers and the first connection hole wirings.
The auxiliary power supply wiring and the second auxiliary power supply wiring can be connected.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to any one of the second to fifth aspects, the macro part has a multilayer wiring structure, and the main power supply wiring is an arbitrary wiring layer of the multilayer wiring in the macro part. The second auxiliary power supply wiring is formed by another wiring layer of the multilayer wiring in the macro part, and the main power supply wiring and the second auxiliary power supply wiring are formed through the second connection hole wiring. It is connected. According to the sixth aspect of the present invention, the main power supply wiring and the second auxiliary power supply wiring can be easily connected via the second connection hole wiring in the macro part of the multilayer wiring structure.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the macro section has three or more wiring layers, and one of the main power supply wiring and the second auxiliary power supply wiring is provided in the uppermost layer. It is formed by a wiring layer, and the other is formed by a second wiring layer from the top. According to the seventh aspect of the present invention, the internal wiring of the macro unit can be easily formed using the wiring layer lower than the third wiring layer from the top without being disturbed by the main power supply wiring and the second auxiliary power supply wiring. Can be done.

According to the layout method of a semiconductor integrated circuit of the present invention, a step of calculating a contact area where a connection wiring can be formed outside the macro section, and forming a cell section arrangement prohibition frame on the outermost periphery of the contact area. And connecting the first auxiliary power supply line arranged in the cell portion to the second auxiliary power supply line arranged in the region of the macro portion using the connection line formed in the contact region, and connecting the second auxiliary power supply line to the second auxiliary power supply line. Connecting the power supply wiring to a main power supply wiring arranged in the region of the macro section.

According to the eighth aspect of the present invention, with such a structure, the connection wiring formed in the contact region where the arrangement of the cell portion is prohibited, and the second wiring arranged in the region of the macro portion
By using the auxiliary power supply wiring, the first auxiliary power supply wiring of the cell section can be reliably and easily connected to the main power supply wiring arranged in the area of the macro section. This eliminates the necessity of arranging the main power supply wiring outside the macro part as in the related art, and as a result, it is possible to prevent an increase in the chip area caused when the main power supply wiring is arranged outside the macro part. And a layout method of the semiconductor integrated circuit can be provided. The connection wiring formed in the contact region is
Unlike the main power supply wiring which requires a large width, the width may be small, and therefore the width of the contact region may be small. Thus, even if the contact region is provided, there is no problem because the chip area does not increase so much.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a flowchart for explaining a layout design method of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a plan layout diagram of a macro unit designed based on the layout design method shown in FIG. FIG. 3 is a plan layout diagram showing a semiconductor integrated circuit designed based on the layout design method shown in FIG. 1, and FIG. 4 is a sectional view taken along line 100-100 in FIG.

First, a layout design method according to the present embodiment will be described with reference to FIG. In the layout design of the present embodiment, first, when laying out a macro part, an area where a contact can be made outside the macro part is calculated. Then, a cell arrangement prohibition frame is created in the macro part including the contact area. Thereby, the cell portion is designed not to be arranged in the cell arrangement prohibition frame.

Thereafter, when connecting the auxiliary power supply wiring of the cell part, the above-mentioned contact region is connected to the auxiliary power supply wiring of the macro part connected to the auxiliary power supply wiring of the cell part and the main power supply wiring of the macro part. Used as an area (transfer area).
Then, switch between the two auxiliary power supply wires in the same direction,
Securely connect to the main power supply wiring located on the macro part.

Next, a semiconductor integrated circuit designed based on the above-described layout design method will be described with reference to FIGS. First, referring to FIG. 2, a contact region 3 is provided outside macro section 1. At the outermost periphery of the contact region 3, a cell placement prohibition frame 10 for prohibiting the placement of the cell portion 2 (see FIG. 3) is created.

As shown in FIGS. 3 and 4, a main power supply wiring 4 is arranged in the region of the macro unit 1. The main power supply wiring 4 is either a main power supply potential line (Vcc) or a main ground potential line (GND). Cell part 2
Are arranged outside the cell arrangement prohibition frame 10.
In the cell unit 2, a first auxiliary power supply line 5 for supplying a power supply potential or a ground potential to a circuit in the cell unit 2 is arranged. In the macro section 1, a second auxiliary power supply line 6 extending in substantially the same direction as the first auxiliary power supply line 5 is arranged.

It should be noted that the macro unit 1 in the present embodiment
This is a large-scale functional block serving as a core (core) such as a CPU, a RAM, and a ROM. In addition, the cell unit 2 includes a macro unit 1
Is a functional block that constitutes a logic circuit, such as a basic cell or a standard cell of a gate array.

Here, as shown in FIG. 4, the first auxiliary power supply line 5 arranged in the cell section 2 is formed by the first wiring layer, and the second auxiliary power supply line 5 is arranged in the macro section 1. The power supply wiring 6 is formed by a fifth wiring layer.
For this reason, it is difficult to directly connect the first auxiliary power supply wiring 5 and the second auxiliary power supply wiring 6.

Therefore, in the present embodiment, the first auxiliary power supply wiring 5 composed of the first wiring layer and the second auxiliary power supply wiring 6 composed of the fifth wiring layer are connected to the connection wiring provided in the contact region. Layers 7a, 7b and 7c and plugs 8a, 8
b, 8c and 8d. Further, in the region of the macro section 1, the second auxiliary power supply wiring 6 and the main power supply wiring 4 are connected by a plug 8e. The plugs 8a, 8b, 8c and 8d correspond to the "first connection hole wiring" of the present invention. Further, the plug 8e corresponds to the "second connection hole wiring" of the present invention.

In this embodiment, as shown in FIG. 4, the macro unit 1 is formed by five wiring layers. The first to third layers of the macro unit 1 are used only for internal wiring, and external wiring is prohibited. On the fourth layer of the macro section 1, a main power supply wiring 4 is formed.
The second auxiliary power supply wiring 6 is formed in the layer.

In the present embodiment, as described above, by providing the contact region 3 outside the macro portion 1,
The connection wiring layers 7a to 7c and the plugs 8a to 8d for connecting the first auxiliary power supply wiring 5 and the second auxiliary power supply wiring 6 can be reliably formed in the contact region 3.
Thereby, the first auxiliary power supply wiring 5 of the cell unit 2 and the second auxiliary power supply wiring 6 of the macro unit 1 can be reliably connected. As a result, the first auxiliary power supply wiring 5 of the cell unit 2 can be reliably connected to the main power supply wiring 4 of the macro unit 1 via the second auxiliary power supply wiring 6 of the macro unit 1.

Here, inconvenience in the case where the contact region 3 is not provided in the configuration of the present embodiment shown in FIGS. 3 and 4 will be described. If the contact region 3 is not provided, the cell unit 2 may be arranged close to the macro unit 1. In this case, the space between the cell unit 2 and the macro unit 1 becomes small, and it is not possible to secure an area for forming a connection wiring for connecting the first auxiliary power supply wiring 5 and the second auxiliary power supply wiring 6. Inconvenience occurs. In this case, it is difficult to reliably connect the first auxiliary power supply line 5 of the cell unit 2 and the second auxiliary power supply line 6 of the macro unit 1. In the present embodiment, by providing the contact region 3 and setting the cell placement prohibition frame 10 for prohibiting the placement of the cell portion 2 at the outermost periphery of the contact region 3,
Connection wiring (connection wiring layers 7a to 7c and plug 8) for connecting the first auxiliary power supply wiring 5 and the second auxiliary power supply wiring 6
a to 8d) can be reliably secured. As a result, the first of the cell unit 2 can be reliably and easily performed.
The auxiliary power supply wiring 5 can be connected to the main power supply wiring 4 of the macro unit 1 via the second auxiliary power supply wiring 6 of the macro unit 1.

Further, in the present embodiment, as described above, the first auxiliary power supply wiring 5 of the cell section 2 can be securely connected to the main power supply wiring 4 arranged in the area of the macro section 1. The main power supply wiring 4 can be arranged in the area of the macro unit 1. This eliminates the necessity of arranging the main power supply wiring outside the macro part in a ring shape as in the related art. As a result, there is a disadvantage that the chip area increases when the main power supply wiring is arranged outside the macro part. Can be prevented. Note that connection wirings (connection wiring layers 7a to 7c and plugs 8a to 8a) formed in the contact region 3 are formed.
In the case of d), unlike the main power supply wiring 4 which requires a large width, the width may be small, so that the width of the contact region 3 may be small. Thus, even if the contact region 3 is provided, there is no problem because the chip area does not increase so much.

In this embodiment, the first auxiliary power supply line 5 and the second auxiliary power supply line 6 are arranged so as to extend in substantially the same direction. Are connected almost linearly without being bent, so that the first auxiliary power supply wiring 5 and the second auxiliary power supply wiring 6 are connected.
Can be shortened. As a result, the wiring capacitance can be reduced, and as a result, the speed of the circuit operation can be increased.

In this embodiment, as described above, the macro part 1 is formed by the five-layered multilayer wiring structure, and the main power supply wiring 4 is formed by the fourth wiring layer of the macro part 1.
Is formed, and the second auxiliary power supply wiring 6 is formed by the fifth wiring layer, so that the internal wiring of the macro part 1 can be formed using the first to third wiring layers of the macro part 1. ,
It can be easily performed without being hindered by the main power supply wiring 4 and the second auxiliary power supply wiring 6.

It should be noted that the embodiment disclosed this time is illustrative in all aspects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

For example, in the above embodiment, the macro unit 1
Has a five-layer structure, but the present invention is not limited to this, and a wiring structure other than five layers may be used.

In the above embodiment, the main power supply wiring 4 is provided in the fourth layer, and the second auxiliary power supply wiring 6 is provided in the fifth layer. However, the present invention is not limited to this. 4 and the second auxiliary power supply wiring 6 may be provided in layers other than the above. Further, the main power supply wiring 4 and the second auxiliary power supply wiring 6 may be provided on the same layer.

[0038]

As described above, according to the present invention, by providing the contact region outside the macro portion, the auxiliary power supply line in the cell portion and the main power supply line located in the region of the macro portion can be reliably and securely formed. Can be easily connected. Thus, unlike the related art, it is not necessary to arrange the main power supply wiring outside the macro unit, and as a result, it is possible to prevent the chip area from increasing when the main power supply wiring is arranged outside the macro unit. .

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a layout design method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a plan layout diagram showing a macro part of the semiconductor integrated circuit designed based on the layout design method of the embodiment shown in FIG. 1;

FIG. 3 is a plan layout diagram of a semiconductor integrated circuit designed based on the layout design method of the embodiment shown in FIG. 1;

FIG. 4 is a cross-sectional view of the semiconductor integrated circuit shown in FIG.
It is sectional drawing along the line.

FIG. 5 is a flowchart for explaining a conventional layout design method of a semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Macro part 2 Cell part 3 Contact area 4 Main power supply wiring 5 1st auxiliary power supply wiring 6 2nd auxiliary power supply wiring 7a, 7b, 7c Connection wiring layer 8a, 8b, 8c, 8d Plug (1st connection hole wiring) 8e Plug (Second connection hole wiring) 10 Cell placement prohibited frame (Cell part placement prohibited frame)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 U

Claims (8)

[Claims] 1. A semiconductor integrated circuit, comprising: a macro part; a contact region provided outside the macro part; and a cell part formed around the macro part other than the contact region. 2. A main power supply line disposed in a region of the macro unit, a first auxiliary power supply line disposed in the cell unit, and a main power supply line disposed in a region of the macro unit and electrically connected to the main power supply line. A second auxiliary power supply line, which is electrically connected, and a connection wiring formed in the contact region and connecting the first auxiliary power supply line of the cell unit and the second auxiliary power supply line of the macro unit. The semiconductor integrated circuit according to claim 1. 3. The semiconductor integrated circuit according to claim 2, wherein said main power supply line includes one of a main power supply potential line and a main ground potential line. 4. The second auxiliary power supply line arranged in the cell section and the second auxiliary power supply line arranged in the macro section are arranged to extend in substantially the same direction. 4. The semiconductor integrated circuit according to 3. 5. The contact region has a multilayer wiring structure, and the connection wiring is a first connection that connects a plurality of connection wiring layers constituting the multilayer wiring in the contact region and the plurality of connection wiring layers. The semiconductor integrated circuit according to claim 2, further comprising a hole wiring. 6. The macro unit has a multilayer wiring structure, wherein the main power supply wiring is formed by an arbitrary wiring layer of the multilayer wiring in the macro unit, and wherein the second auxiliary power supply wiring is The main power supply wiring and the second auxiliary power supply wiring are connected via a second connection hole wiring, and are formed by another wiring layer of the multilayer wiring in the portion. 2. The semiconductor integrated circuit according to claim 1. 7. The macro section has three or more wiring layers, one of the main power supply wiring and the second auxiliary power supply wiring is formed by the uppermost wiring layer, and the other is formed by the uppermost two wiring layers.
7. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is formed by a third wiring layer. 8. A step of calculating a contact area in which a connection wiring can be formed outside the macro section; a step of forming a cell section arrangement prohibition frame on the outermost periphery of the contact area; Connecting the first auxiliary power supply wiring to the second auxiliary power supply wiring disposed in the area of the macro section using the connection wiring formed in the contact region, and connecting the second auxiliary power supply wiring to the macro Connecting to a main power supply line arranged in a region of the semiconductor integrated circuit.