JP2002124673A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability and yield about the electric characteristics and the quality to contribute to a stable supply of more fined and multi-function semiconductor devices, by laminating plasma-reacted organic silane NSG and PSG films on a silicide electrode wiring or an impurity layer in a MOSLSI, etc., and forming a layer insulation film planarized with coat glass. SOLUTION: A plasma-reacted NSG film 20 and PSG film 21 with TEOS are formed on a gate electrode wiring 14 having a Ti silicide surface and an impurity layer 17. Cost glass 22 is spin-coated on the films 20, 21 and annealed at 800 deg.C. Contact holes are formed by wet etching with an HF-containing water solution and anisotropical etching by a reactive ion etcher, and then a metal wiring 23 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an interlayer insulating film formed on a gate electrode wiring or an impurity layer having a silidic surface.

[0002]

2. Description of the Related Art Conventionally, for the purpose of miniaturization and high speed, Po
A semiconductor device has been proposed in which each surface of a ly-Si gate electrode wiring or an impurity layer of a Si substrate has a silicide (silicide) structure of Ti, W, Mo or the like to reduce wiring resistance and contact resistance. As shown in FIG. 2, for example, a field insulating film 12 is formed on a Si substrate 11 by selective oxidation, and a gate oxide film 13 is formed on its active region.
After poly-Si is vapor-phase grown and selectively etched by a photolithography process to form a gate electrode wiring 14, impurities such as phosphorus are ion-implanted into the low-concentration impurity layers 16 of the source and drain, and then the side wall of the silicon oxide film is formed. Spacer 1
Arsenic or the like is ion-implanted into the high-concentration impurity layers 17 of the source and the drain through the LDD 5 to form an LDD (lightly dope).
d drain) structure. Next, the gate electrode wiring 14
After the Si surface of the impurity layer 17 is exposed, Ti is sputter-grown at about 500 °, instantaneously annealed with a halogen lamp at about 700 ° C., and immersed in a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide to selectively etch the Si surface. Only the monosilicide layer 19 of Ti remains, which is further subjected to lamp annealing at about 800 ° C. to form a disilicide. As a result, the gate electrode wiring 14 and the impurity layer 17 are separated via the side wall spacer 15 and the field insulating film 12. Salicide with self-aligned silicide (self
-Alignedsilicide) structure. Next, as an interlayer insulating film, for example, a silicon oxide film 31 obtained by subjecting an oxidizing gas such as O2 or N2O to a gas phase reaction with SiH4 as shown in Japanese Patent Publication No. 51-21753 is laminated for about 6000.degree. And annealed in an N2 atmosphere. Subsequently, after a contact hole is opened, an Al alloy of about 1.0 μm is sputtered to form a patterned metal wiring 23. Finally, a passivation film is laminated to open a bonding pad portion for taking out an external electrode.

[0003]

In the prior art, however, the surface of the Ti silicide layer 19 is easily oxidized. An oxide layer of Ti is formed at an initial stage until an oxide film is grown, and poor adhesion and cracks of the interlayer insulating film occur in a later process or the like, and cause of unstable contact resistance between the metal wiring 23 and the silicide layer 19. Had become. In particular, when a normal pressure heating method is used as the vapor phase growth apparatus for the silicon oxide film 31, when the substrate wafer is loaded into the apparatus, the entrapped air stagnates and the surface is oxidized until the temperature rises. With SiH4
The silicon oxide film 31 which has been subjected to a gas phase reaction at 450 ° C. or less tends to cause casping when the space of the lower wiring is narrowed, and the applied glass 22 easily accumulates therein. It is not suitable for miniaturization to sub-micron or less due to poor closeness of parts and poor film breakdown voltage. On the other hand, if the annealing is not performed at 600 ° C. or more, a large amount of OH groups and moisture remain in the coating glass 22 and the insulating property is poor. However, if the annealing is performed at a high temperature of 600 ° C. or higher, there is a problem that the surface of the silicide layer is oxidized through the underlying silicon oxide film 31 and the contact resistance increases, so that annealing at a low temperature of about 500 ° C. The vapor-grown silicon oxide film 31 needs to be as thick as possible in order to prevent the agent from entering. However, the present invention solves such a problem. In particular, a silicon oxide film obtained by subjecting an organic silane to a plasma reaction, a phosphorus glass film of the oxide film, and a coating are applied to an interlayer insulating film on a wiring of a semiconductor device, particularly, a wiring having a silicide layer. By using a laminated glass structure to prevent oxidation of the silicide layer surface and improve the flatness of the interlayer film, the stable supply of fine multifunctional semiconductor devices is achieved, and the quality associated with electrical characteristics and reliability is improved. It is intended for that purpose.

[0004]

According to the present invention, there is provided a semiconductor device comprising:
A silicide layer of a refractory metal is formed on the surface of an impurity layer such as a gate electrode or a source or a drain of a MOS transistor, and at least a first silicon oxide film subjected to plasma reaction is formed as an interlayer insulating film between the silicide layer and the metal wiring. A second silicon oxide film formed by a plasma reaction containing phosphorus as an impurity and a coating glass are stacked.

The method of manufacturing a semiconductor device according to the present invention comprises a step of forming a silicide layer of a refractory metal at least on a surface of an impurity layer such as a gate electrode wiring and a source and a drain of a MOS transistor; Forming a first silicon oxide film by plasma reaction of
A step of forming a second silicon oxide film obtained by adding an impurity containing phosphorus to an organic silane and an oxidizing gas to cause a plasma reaction, a step of spin-coating a coated glass and performing a heat treatment, and a step of opening a contact hole from the element to form a metal. The method is characterized by including a step of wiring.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c).
This will be described in detail with reference to FIG.

[0007] Sub-micron rule Si gate CMOS
When applied to the manufacture of a semiconductor device, the Si substrate 1
In FIG. 1, a field insulating film 12 is formed by selective oxidation, a gate oxide film 13 is formed in an active region by 150.degree., A threshold voltage is adjusted by channel injection, and Poly-Si obtained by thermally decomposing SiH4 is grown to 4000.degree. After the etched gate electrode wiring 14 is formed, phosphorus and phosphorus are added to Nch of the low concentration impurity layer 16 of source and drain.
After ion implantation of boron into Pch at about 2 × 10 ¹³ cm ^−2, a sidewall spacer 15 of a silicon oxide film is formed beside the gate electrode wiring 14, and then arsenic or BF 2 is deposited on the high-concentration impurity layers 17 of the source and drain. 5 × 10 ^{1 5} and cm ^-2 order of ion implantation. In each case of ion implantation, the purpose was to prevent generation of crystal defects through a thin silicon oxide film. Next, the Si surface of the gate electrode wiring 14 and the impurity layer 17 is light-etched with a thin HF aqueous solution and exposed, and then Ti18 is sputtered at about 600 ° (FIG. 1A). Subsequently, instantaneous annealing is performed for 30 seconds with a halogen lamp at 710 ° C. in an N 2 atmosphere in which O 2 is controlled to 20 ppm or less, whereby a Ti monosilicide layer is formed on the Si surface, and a Ti-rich TiN layer is formed on the silicon oxide film. Formed and subsequently immersed in a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide,
The TiN layer is removed by etching so that T
The monosilicide layer 19 of i was left, and a further 800 ° C. lamp annealing was performed to form a silicide layer 19 on the gate electrode wiring 14 and the impurity layer 17 in a self-aligned manner. Next, as an interlayer insulating film, first, TEOS
[Si (OC2H5) 4] and O2 were oxidized with silicon (N) at 380 ° C., 9 torr in a parallel plate type plasma reactor.
SG) The film 20 was grown at 2500 °. This NSG film 2
In the case of No. 0, the growth rate was as high as 8000 ° / min, there was no oxidation or cuffing of the silicide layer, the insulating property was higher than that of the film grown from SiH4, the etch rate with respect to the HF aqueous solution was lower, and a dense film was formed. Subsequently, P (OCH3) 3 is added and the same conditions as those of the silicon oxide film are applied for 2000 hours.
The phosphor glass (PSG) film 21 of 堆積 was deposited. This P
The SG film 21 had a P2O5 concentration of about 3.5 mol% and was laminated as a getter film against alkali contamination during the process. However, like the NSG film, there was no casping and the film growth conditions were N.
Simply adding P (OCH3) 3 to the conditions of the SG film does not greatly affect the growth rate and uniformity. Therefore, continuous growth is easy in the same reaction chamber. Conversely, when SiH4 is used, PSG and PSG are used. Since it is necessary to adjust the temperature, pressure, and the like of the growth conditions of the NSG film, continuous growth is not easy.
Next, for flattening, a coating glass 22 in which silanol and P2O5 were dissolved in ethanol and ethyl acetate was spin-coated, and further annealed at 800 DEG C. in an N2 atmosphere (FIG. 1).
(B)). Subsequently, after patterning the contact region with a photoresist, the coated glass 22 and the PSG film 21 were first subjected to isotropic wet etching with a mixed aqueous solution of HF and NH4F to taper the holes. At this time, PSG film 2
1 indicates that the wet etching speed is 3 to
As a result of being four times larger and the coating glass 22 being several times larger, the interlayer film has not only an etching throughput but also a tapered hole shape that is preferable for the coverage of the metal wiring as compared with the NSG single layer. Conversely, the NSG film 20
Since the wet etching rate is very low, the reproducibility of the NSG film residue after the PSG film 21 is wet-etched is good, and the control of the etching amount in the subsequent dry etching is easy. Subsequently, the remaining NSG film 20 was anisotropically etched with a reactive ion etcher using CHF3 and CF4 as main gases, contact holes were formed, and the photoresist was peeled off. Next, about 0.8 μm of Al—Cu is sputtered between TiN as a barrier and a cap material, and the laminated film is patterned into a metal wiring 23 (FIG. 1C). A silicon nitride film was deposited, and a bonding pad portion for taking out an external electrode was opened in a desired region. In the removal of the photoresist in the previous step, the surface altered layer by dry etching was removed by O2 plasma, and the entire surface was removed by a mixed solution of heated sulfuric acid and hydrogen peroxide solution. Since it is lightly oxidized, 4mto
After performing Ar high frequency sputter etching of about rr at 200 w for 20 seconds or more, the T
It was effective to continuously sputter the metal wiring material including iN. Since this sputter etching can remove the round at the end of the contact hole, it is also effective in improving the wiring coverage. In the semiconductor device thus configured, the coating glass annealing can be performed at a higher temperature than in the past, and the problems such as cracks do not occur. In addition, the thickness of the interlayer insulating film and the shape of the hole are used to improve the coverage of the metal wiring in the contact hole portion, to control the oxide film that is easily formed on the surface of the salicide layer, and to reduce the contact resistance to 0.6 to 0.8 micron. The diameter was stabilized at about 3Ω, and the yield and reliability were improved. On the other hand, although there was a concern about the conventional gate film destruction due to charge charge at the initial stage of the growth of the silicon oxide film by plasma, the structure according to the present invention did not have any problem. This is presumably because the charge easily escaped to the Si substrate side via the low-resistance silicide layer. As another embodiment, the present invention was applied to a logic LSI product having a two-layer metal wiring structure using an Al alloy. However, the problem was improved as compared with the related art, and the electrical characteristics, reliability, and yield were improved.

In the embodiment of the present invention, the manufacture of a MOS-LSI having a salicide structure using Ti silicide has been described. However, the gate electrode wiring and the Si impurity layer are separately silicided, or one of them has a silicide structure. It is also applicable to a multilayer structure of PolySi or silicide. On the other hand, silicide is not limited to Ti, and can be applied to a high melting point metal such as W, Mo, Co or Cr. In addition to silicidation of the high melting point metal and Si by annealing, a silicide film may be used alone or in advance.
It is also effective for a polycide gate electrode wiring structure in which a ly-Si film is laminated by sputtering or the like. On the other hand, as a silicon oxide film, C4H16Si4O4 or Si4O
Silicon oxide film obtained by plasma reaction of organic silane such as 4C8H24, or P (OCH3) 3
Use of a PSG film containing phosphorus by introducing oxygen or PH3, and N2O, CO2, CO2 instead of O2 as an oxidizing gas
And O3 applications are also possible.

[0009]

As described above, according to the present invention, the MOSLS
By stacking NSG and PSG films of plasma reaction using organic silane on silicide electrode wiring and impurity layer in I etc., and forming an interlayer insulating film flattened with coated glass, electrical characteristics and quality are improved. The related reliability and yield are improved, and it is possible to contribute to the stable supply of finer and multifunctional semiconductor devices.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic sectional views showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional view related to a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Si substrate 12 Field insulating film 13 Gate oxide film 14 Gate electrode wiring 15 Side wall spacer 16 Low concentration impurity layer 17 High concentration impurity layer 18 Ti 19 Silicide layer 20 NSG film 21 PSG film 22 Coating glass 23 Metal wiring 31 Silicon oxide film

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[Procedure amendment]

[Submission date] August 2, 2001 (2001.8.2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Semiconductor device

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, in particular, the surface is related to the interlayer insulating film formed on the gate electrode wiring and the impurity layer of silicon Sa id structure.

[0002]

2. Description of the Related Art Conventionally, for the purpose of miniaturization and high speed, Po
A semiconductor device has been proposed in which each surface of a ly-Si gate electrode wiring or an impurity layer of a Si substrate has a silicide (silicide) structure of Ti, W, Mo or the like to reduce wiring resistance and contact resistance. As shown in FIG. 2, for example, a field insulating film 12 is formed on a Si substrate 11 by selective oxidation, and a gate oxide film 13 is formed on its active region.
After poly-Si is vapor-phase grown and selectively etched by a photolithography process to form a gate electrode wiring 14, impurities such as phosphorus are ion-implanted into the low-concentration impurity layers 16 of the source and drain, and then the side wall of the silicon oxide film is formed. Spacer 1
Arsenic or the like is ion-implanted into the high-concentration impurity layers 17 of the source and the drain through the LDD 5 to form an LDD (lightly dope).
d drain) structure. Next, the gate electrode wiring 14
After the Si surface of the impurity layer 17 is exposed, Ti is sputter-grown at about 500 °, instantaneously annealed with a halogen lamp at about 700 ° C., and immersed in a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide to selectively etch the Si surface. Only the monosilicide layer 19 of Ti remains, which is further subjected to lamp annealing at about 800 ° C. to form a disilicide. As a result, the gate electrode wiring 14 and the impurity layer 17 are separated via the side wall spacer 15 and the field insulating film 12. Salicide with self-aligned silicide (self
( Aligned silicide) structure. Next as an interlayer insulating film, for example, Japanese Patent Publication 51 - 21753 as the SiH ₄ after lamination to O ₂ and N ₂ O or the like about 6000Å silicon oxide film 31 which the oxidizing gas was a gas phase reaction, for planarization Is coated with a coating glass 22 and annealed in an N ₂ atmosphere. Subsequently, after a contact hole is opened, an Al alloy of about 1.0 μm is sputtered to form a patterned metal wiring 23. Finally, a passivation film is laminated to open a bonding pad portion for taking out an external electrode.

[0003]

However, in the prior art, the surface of the Ti silicide layer 19 is easily oxidized.
There therefore, by the silicon oxide film 31 directly 450 ° C. or higher is grown in vapor phase O ₂ or the like, an oxide layer of Ti in the initial stage up to grow a silicon oxide film is formed.
As a result, poor adhesion or cracking of the interlayer insulating film occurs in a later step or the like, and the contact resistance between the metal wiring 23 and the silicide layer 19 becomes unstable.

In particular, when a normal pressure heating system is used as a vapor phase growth apparatus for the silicon oxide film 31, when the substrate wafer is loaded into the apparatus, the air entangled therein stagnates and the surface is oxidized until the temperature rises. I will.

[0005] Silicon oxide film 31 obtained by vapor phase reaction of SiH ₄ at 450 ° C. or less or vacuum heating tends to occur Kasupingu the space of the lower wiring is narrowed, wherein the coating glass 22 is accumulated not easy. As a result, cracks are generated by annealing in a later step . Further, since the tightness of the step side wall portion and the film breakdown voltage are poor, it is not suitable for miniaturization of submicron or less.

The coated glass 22 is annealed at 600 ° C.
Otherwise, a large amount of OH groups and moisture remain in the film, resulting in poor insulation. However, when carried out at a high temperature 600 ° C. or higher annealing, through a silicon oxide film 31 underlying be safely surface of the silicide layer becomes higher by contact resistance oxide, and annealing is performed at a low temperature of about 500 ° C.,
The vapor grown silicon oxide film 31 needs to be as thick as possible in order to prevent the oxidant from entering.

[0007] However the present invention, these problems solves the interlayer insulating film on the wiring in particular with a silicide layer of a semiconductor device, a first silicon oxide with an organic silane and an oxidizing gas to the plasma reaction Film , organic silane and oxidation
Second reaction in which a reactive gas is reacted with a compound containing phosphorus
A stacked structure of an oxide film and a coated glass film prevents oxidation of the surface of the silicide layer and further improves the flatness of the interlayer film. The purpose is to improve the quality with the property.

[0008]

According to the present invention, there is provided a semiconductor device comprising:
MOS transistor source and drain regions
A refractory metal silicide layer formed on the surface;
Organosilane and oxidizing gas on silicide layer of melting point metal
Silicon oxide film formed by plasma reaction of
Organic silane and oxidizing agent on the first silicon oxide film.
It is formed by a plasma reaction between a gas and a compound containing phosphorus.
Second silicon oxide film, and the second silicon oxide film
A coated glass film formed on the first silicon acid;
Oxide film, the second silicon oxide film, and the coated glass film
Formed in the interlayer insulating film containing
And a connection hole.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. 1 (a) to 1 (c).
This will be described in detail with reference to FIG.

[0010] Sub-micron rule Si gate CMOS
When applied to the manufacture of a semiconductor device, the Si substrate 1
After adjusting one to form a field insulating film 12 in the selective oxidation threshold voltage by the channel implanted 150Å form a gate oxide film 13 on the active region, the predetermined pattern of SiH ₄ to 4000Å grow Poly-Si pyrolyzed After the gate electrode wiring 14 is formed by etching, phosphorus, P is added to Nch of the low concentration impurity layer 16 of the source and the drain.
After ion implantation of about 2 × 10 ¹³ cm ⁻² of boron into the channel, a sidewall spacer 15 of a silicon oxide film is formed beside the gate electrode wiring 14, and then arsenic or BF ₂ is added to the high-concentration impurity layers 17 of the source and drain. ^Was ion-implanted at about 5 × 10 ¹⁵ cm ⁻² . Each ion implantation was performed through a thin silicon oxide film for the purpose of preventing generation of crystal defects.
Next, after the gate electrode wiring 14 and the Si surface of the impurity layer 17 are light-etched with a thin HF aqueous solution and exposed,
Sputter 0 ° (FIG. 1A). Subsequently, O ₂ was added to 20
The instantaneous annealing for 30 seconds with a halogen lamp at 710 ° C. in an N ₂ atmosphere controlled to not more than
A monosilicide layer of Ti is formed on the surface, and a TiN layer rich in Ti is formed on the silicon oxide film. Then, when immersed in a mixed aqueous solution of ammonium hydroxide and hydrogen peroxide, Ti
The N layer is removed by etching, leaving a monosilicide layer 19 of Ti only on the surface of the Si.
4 and the impurity layer 17 are self-aligned with the silicide layer 19.
Was formed. Next, as an interlayer insulating film, first, TEOS [ S
i (OC ₂ H ₅ ) ₄ ] and O ₂ in a parallel plate type plasma reactor at 380 ° C. and 9 torr at a silicon oxide film (NS
G: Nondoped Silicate Glass) 20 was grown at 2500 ° C. This NSG film 20 has a growth rate of 8000Å /
In addition to being high enough, there is no oxidation or casping of the silicide layer,
The insulating film had a higher insulating property than the film grown from SiH _4, and the etching rate with respect to the HF aqueous solution was lower, so that a dense film was formed. Subsequently , P (OCH ₃ ) ₃ is added, and a phosphorus glass (PSG) film 21 of 2000 ° is formed under substantially the same conditions as the silicon oxide film.
Was deposited. This PSG film 21 is about 3.5 mol%
And P ₂ O ₅ concentration, was laminated as a getter film in an alkali contamination during the process, rather than NSG film similar Kasupingu, even film growth conditions to the condition of the NSG film by simply adding P (OCH _{3) 3} Since the growth rate and uniformity are not much different, continuous growth is easy in the same reaction chamber.
When SiH ₄ is used, continuous growth is not easy because the growth conditions such as temperature and pressure of the PSG and NSG films must be adjusted. Next, for flattening, a coating glass 22 in which silanol and P ₂ O ₅ were dissolved in ethanol and ethyl acetate was spin-coated, and further annealed in a N ₂ atmosphere at 800 ° C. (FIG. 1B). Subsequently, after patterning the contact region with a photoresist, first, HF and NH ₄ F
The coating glass 22 and the PSG film 21 were isotropically wet-etched with a mixed aqueous solution of the above to taper the holes.
At this time, the PSG film 21 has a wet etching speed 3 to 4 times higher than the NSG film 20 and the coating glass 22 is several times higher than the NSG film 20. As a result, the interlayer film has not only a higher etching throughput but also a smaller hole taper than the NSG single layer. The shape also became a preferable shape for the coverage of the metal wiring. vice versa,
Since the NSG film 20 has a very low wet etching rate, the NSG film 20 after the PSG film 21 is wet-etched is removed.
The reproducibility of the film residue of G is good, and the control of the etching amount in the subsequent dry etching is easy. Continue , CHF
_The remaining NSG film 20 was anisotropically etched with a reactive ion etcher using ₃ and CF ₄ as main gases, contact holes were formed, and the photoresist was peeled off. Next, about 0.8 μm of Al—Cu
The laminated film is patterned to form a metal wiring 23 (FIG. 1C), and a silicon nitride film is deposited as a passivation film by a plasma reaction.
A bonding pad portion for taking out an external electrode was opened in a desired region. In the removal of the photoresist in the previous process, the surface altered layer by dry etching is removed by O ₂ plasma,
Further, the entire surface was peeled off with a heated mixture of sulfuric acid and hydrogen peroxide, but the surface of the Ti silicide layer 19 in the hole was lightly oxidized. It has been effective to continuously sputter the metal wiring material including the barrier material TiN without breaking the vacuum after performing the sputter etching at 200 w for 20 seconds or more. Since this sputter etching can remove the round at the end of the contact hole, it is also effective in improving the wiring coverage. The semiconductor device thus configured can perform the coating glass annealing at a higher temperature than before, and
Problems such as cracks no longer occur. In addition, from the thickness of the interlayer insulating film and the shape of the hole, the coverage of the metal wiring in the contact hole part is improved, and the oxide film which is easily formed on the surface of the salicide layer is controlled.
The hole diameter of 0.8 micron was stabilized to about 3Ω and the yield and reliability were improved. On the other hand, although the conventional problem of gate film destruction due to charge charge in the initial stage of the growth of the silicon oxide film by plasma was concerned, there was no problem in the structure according to the present invention. This is presumably because the charge easily escaped to the Si substrate side via the low-resistance silicide layer. As another embodiment, the present invention was applied to a logic LSI product having a two-layer metal wiring structure using an Al alloy, but the problem was improved as compared with the prior art, and the electrical characteristics, reliability, and yield were improved.

In the embodiment of the present invention, the manufacture of a MOS-LSI having a salicide structure using Ti silicide has been described. However, the gate electrode wiring and the Si impurity layer are separately silicided, or either of them has a silicide structure. The present invention can be applied to a multilayer structure of Poly - Si or silicide. On the other hand, the silicide is not limited to Ti, but can be applied to a high melting point metal such as W, Mo, Co or Cr. In addition to the silicidation of the high melting point metal and Si by annealing, a silicide film may be used alone or in advance.
It is also effective for a polycide gate electrode wiring structure in which an poly-Si film is laminated by sputtering or the like. On the other hand, instead of TEOS, C ₄ H ₁₆ Si ₄ O ₄ or Si ₄
A silicon oxide film obtained by subjecting an organic silane such as O ₄ C ₈ H ₂₄ to a plasma reaction, or P (OC
Use of a PSG film containing phosphorus by introducing H ₃ ) ₃ or PH ₃ or the like; and N ₂ O , C instead of O ₂ as an oxidizing gas
Applications of O ₂ , CO and O ₃ are also possible.

[0012]

As described above, according to the present invention, a semiconductor device
In particular, the interlayer insulating film on the wiring with silicide layer
A first silicide obtained by a plasma reaction between silane and an oxidizing gas;
Con oxide film, containing organic silane, oxidizing gas and phosphorus
A second oxide film obtained by subjecting the compound to a plasma reaction;
By adopting a laminated structure with a semiconductor film, reliability and yield related to electric characteristics and quality are improved, and it is possible to contribute to a stable supply of finer and multifunctional semiconductor devices.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic sectional views showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional view related to a conventional method for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 11 Si substrate 12 field insulating film 13 gate oxide film 14 gate electrode wiring 15 side wall spacer 16 low concentration impurity layer 17 high concentration impurity layer 18 Ti 19 silicide layer 20 NSG film 21 PSG film 22 coating glass 23 metal wiring 31 Silicon oxide film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 27/08 321D 5F140 // C23C 16/40 F term (Reference) 4K030 AA06 AA09 BA44 CA04 CA12 FA01 HA03 4M104 AA01 BB01 BB20 BB24 BB25 BB26 BB28 BB30 CC01 CC05 DD08 DD09 DD16 DD19 DD37 DD45 DD84 EE12 EE14 EE15 FF14 FF18 FF22 GG09 GG10 GG14 HH08 5F033 HH04 HH08 KKH29 KK29 H27H01 KKH MM13 NN06 NN07 NN32 PP03 PP06 PP15 QQ09 QQ10 QQ16 QQ19 QQ21 QQ22 QQ37 QQ70 RR04 RR09 RR14 SS04 SS15 SS22 TT02 VV06 XX01 XX13 XX17 5F048 BDAA01 BF05 BF46 BH04 BJ02 5F140 AA15 AA39 AB03 BA01 BC06 BD05 BF04 BF11 BF18 BG08 BG12 BG28 BG30 BG34 BG37 BG44 BG45 BG56 BH15 BJ01 BJ08 BJ11 BJ16 BJ20 BK02 BK13 BK26 BK29 BK34 BK38 BK39 CA02 CA03 CB01 CC01 CC02 CC03 CC05 CC08 CC13 CC15 CC16 CC19 CE10 CF04

Claims (5)

[Claims] 1. A refractory metal silicide layer is formed on the surface of an impurity layer such as a gate electrode and a source and a drain of a MOS transistor, and at least a first plasma-reacted interlayer insulating film between the silicide layer and the metal wiring is formed. A semiconductor device comprising: a silicon oxide film; a second silicon oxide film formed by a plasma reaction containing phosphorus as an impurity; and a coating glass. A step of forming a silicide layer of a refractory metal on at least a surface of an impurity layer such as a gate electrode and a source and a drain of a MOS transistor; A step of forming a film, a step of forming a second silicon oxide film obtained by adding an impurity containing phosphorus to an organic silane and an oxidizing gas to cause a plasma reaction, a step of spin-coating a coated glass and heat-treating, a contact from an element A method for manufacturing a semiconductor device, comprising a step of forming a hole and providing a metal wiring. 3. The contact hole according to claim 2, wherein at least a desired amount of the coating glass and the second silicon oxide film is tapered by isotropic etching, and further opened by anisotropic etching. A method for manufacturing a semiconductor device. 4. The growth of the metal wiring according to claim 2, wherein at least a contact hole from the element is opened using a photoresist as a mask, the photoresist is peeled off, and then high-frequency sputter etching is performed under vacuum. A method for manufacturing a semiconductor device, wherein sputter growth is further continued. 5. A semiconductor device and a method for manufacturing the same, wherein the refractory metal forming the silicide layer according to claim 1 is Ti.