CN111785694A - Semiconductor device and electronic apparatus - Google Patents

Semiconductor device and electronic apparatus Download PDF

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Publication number
CN111785694A
CN111785694A CN201910271303.XA CN201910271303A CN111785694A CN 111785694 A CN111785694 A CN 111785694A CN 201910271303 A CN201910271303 A CN 201910271303A CN 111785694 A CN111785694 A CN 111785694A
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Prior art keywords
semiconductor device
electrode
substrate
protective film
lateral end
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CN201910271303.XA
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Chinese (zh)
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CN111785694B (en
Inventor
鹿内洋志
鹫谷哲
田中雄季
熊仓弘道
马场良平
山田辽太
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Priority to CN201910271303.XA priority Critical patent/CN111785694B/en
Priority claimed from CN201910271303.XA external-priority patent/CN111785694B/en
Publication of CN111785694A publication Critical patent/CN111785694A/en
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Publication of CN111785694B publication Critical patent/CN111785694B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring

Abstract

An embodiment of the present application provides a semiconductor device and an electronic apparatus, the semiconductor device including: a substrate; an electrode formed on the substrate surface; and a protective film formed on the substrate surface, wherein at least a part of a lateral end of the electrode is overlapped on at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface, and the protective film includes a non-doped silicate glass (NSG) and a phosphosilicate glass (PSG) which are formed by lamination. According to the embodiment of the present application, the reliability of the semiconductor device can be improved.

Description

Semiconductor device and electronic apparatus
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device and an electronic apparatus.
Background
In a semiconductor device, a protective film is generally provided on a surface of a substrate in order to improve reliability of the device. The protective film may be provided on the outer periphery of the active area (active area) or on the outer periphery of the pressure-resistant member, for example.
For example, patent document 1 (japanese patent laid-open publication No. 2017-130590) discloses a silicon carbide (SiC) semiconductor element in which a protective film 70 is provided on an outer peripheral portion of a protective ring 40(Guard ring).
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present application.
Disclosure of Invention
In the related art, the protective film may be any of a silicon oxide film, a silicon nitride film, an undoped silicate glass (NSG) film, a phosphosilicate glass (PSG) film, or the like, for example.
The inventors of the present application have found that in the case of using one material as the protective film, the protective effect of the protective film is limited.
Embodiments of the present application provide a semiconductor device and an electronic apparatus, in which a protective film includes a non-doped silicate glass (NSG) and a phosphosilicate glass (PSG) stacked together, wherein a phosphorus element P in the phosphosilicate glass (PSG) can combine with an external impurity entering the phosphosilicate glass, so as to prevent the external impurity from penetrating through the phosphosilicate glass and invading into a substrate or an electrode of a semiconductor, and the non-doped silicate glass (NSG) can block the phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, so as to prevent the phosphorus element P from corroding the electrode of the semiconductor device. Therefore, the protective film in the semiconductor device of the present embodiment has good protective properties for the substrate and the electrode.
According to an aspect of an embodiment of the present application, there is provided a semiconductor device having:
a substrate;
an electrode formed on the substrate surface; and
and a protective film formed on the substrate surface, wherein at least a part of a lateral end of the electrode is overlapped on at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface, and the protective film includes a non-doped silicate glass (NSG) and a phosphosilicate glass (PSG) which are formed by lamination.
According to another aspect of the embodiments of the present application, wherein in an end portion of the protective film overlapping with a lateral end portion of the electrode, an end portion of the phosphosilicate glass is covered with the undoped silicate glass.
According to another aspect of the embodiment of the present application, the protective film is a lower layer of undoped silicate glass, phosphosilicate glass, and an upper layer of undoped silicate glass in this order from the substrate surface.
According to another aspect of an embodiment of the present application, wherein, in a direction parallel to the substrate surface, a lateral end portion of an outer side of the lower layer of undoped silicate glass extends further away from the electrode than a lateral end portion of an outer side of the phosphosilicate glass.
According to another aspect of the embodiments of the present application, wherein the lateral end portion of the outer side of the upper layer of undoped silicate glass laterally covers the lateral end portion of the outer side of the phosphosilicate glass in a direction parallel to the substrate surface.
According to another aspect of the embodiments of the present application, wherein the semiconductor device further has: a guard ring formed within the substrate,
wherein, in a direction parallel to the substrate surface and away from the electrode, a lateral end of an outer side of the phosphosilicate glass does not exceed a lateral end of the guard ring.
According to another aspect of embodiments of the present application, there is provided an electronic apparatus having the semiconductor device according to any one of the above-described embodiments.
The beneficial effect of this application lies in: the phosphosilicate glass (PSG) of the protective film can effectively prevent external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, and the undoped silicate glass (NSG) of the protective film can block phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, so as to avoid the phosphorus element P from corroding the electrode of the semiconductor device.
Specific embodiments of the present application are disclosed in detail with reference to the following description and drawings, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the present application are not so limited in scope. The embodiments of the application include many variations, modifications and equivalents within the spirit and scope of the appended claims.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic view of a semiconductor device according to embodiment 1 of the present application;
fig. 2 is another schematic view of a semiconductor device according to embodiment 1 of the present application.
Detailed Description
The foregoing and other features of the present application will become apparent from the following description, taken in conjunction with the accompanying drawings. In the description and drawings, particular embodiments of the application are disclosed in detail as being indicative of some of the embodiments in which the principles of the application may be employed, it being understood that the application is not limited to the described embodiments, but, on the contrary, is intended to cover all modifications, variations, and equivalents falling within the scope of the appended claims.
In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing different elements by reference, but do not denote a spatial arrangement, a temporal order, or the like of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprising," "including," "having," and the like, refer to the presence of stated features, elements, components, and do not preclude the presence or addition of one or more other features, elements, components, and elements.
In the embodiments of the present application, the singular forms "a", "an", and the like include the plural forms and are to be construed broadly as "a" or "an" and not limited to the meaning of "a" or "an"; furthermore, the term "the" should be understood to include both the singular and the plural, unless the context clearly dictates otherwise. Further, the term "according to" should be understood as "at least partially according to … …," and the term "based on" should be understood as "based at least partially on … …," unless the context clearly dictates otherwise.
In addition, in the following description of the embodiments of the present application, a direction parallel to a substrate surface of a semiconductor device is referred to as a "lateral direction" for convenience of description; in the "lateral direction", a side of each member directed from the outside of the electrode to the direction of the electrode is referred to as "inside", and a side directed from the electrode to the outside of the electrode is referred to as "outside"; a direction perpendicular to a substrate surface of the semiconductor device is referred to as a "longitudinal direction"; in the "longitudinal direction", a direction pointing from the substrate surface of the semiconductor device to the electrode is referred to as an "upper" direction, and a direction opposite to the "upper" direction is a "lower" direction; the dimension in the "longitudinal direction" is referred to as the "thickness" or "depth".
Example 1
Embodiment 1 of the present application provides a semiconductor device.
Fig. 1 is a schematic view of the semiconductor device of the present embodiment, and as shown in fig. 1, the semiconductor device 1 may have a substrate 11, an electrode 12, and a protective film 13.
In the present embodiment, the substrate 11 may be a semiconductor material, such as silicon, germanium, or a compound semiconductor material. In one embodiment, the semiconductor material may be silicon carbide (SiC).
As shown in fig. 1, the substrate 11 may have: an underlayer 111, and an active layer (active layer)112 formed over the underlayer 111.
The substrate layer 111 may be an N-type doped layer, the active layer 112 may also be an N-type doped layer, and the doping concentration of the active layer 112 may be different from that of the substrate layer 111. For example, the active layer 112 may be a drift layer or the like. In addition, the doping type and the doping concentration of the substrate layer 111 and the active layer 112 may not be limited thereto, for example, the doping type of the substrate layer 111 and the active layer 112 may be different, and for example, the active layer 112 may include a plurality of doping regions distributed in a lateral direction and the like having different doping types.
In the present embodiment, the electrode 12 may be formed on the surface 11a of the substrate 11, and an electrical contact may be formed between the electrode 12 and the active layer 112, and the electrical contact may be, for example, an ohmic contact, a schottky contact, or the like. For example, in fig. 1, the electrode 12 makes electrical contact with the active layer 112, which is a drift layer.
In the present embodiment, the protective film 13 may be formed on the surface 11a of the substrate 11. At least a part of the lateral end 121 of the electrode 12 is disposed to overlap at least a part of the lateral end 131 of the protective film 13 in a direction perpendicular to the surface 11a of the substrate 11.
As shown in fig. 1, the protective film 13 may include a stack of Non-doped silicate Glass (NSG)132 and phosphosilicate Glass (PSG) 133. Wherein phosphorus element P in phosphosilicate glass (PSG)133 can combine with an external impurity such as water molecule or the like entering into the phosphosilicate glass 133, thereby preventing the external impurity from penetrating through the phosphosilicate glass 133 and invading into the substrate 11 or the electrode 12 of the semiconductor device; the undoped silicate glass (NSG)132 can prevent phosphorus element P in the phosphosilicate glass (PSG)133 from diffusing to the outside, thereby preventing the phosphorus element P from corroding the electrode 12 or the substrate 11 of the semiconductor device.
According to the present embodiment, by providing the protective film 13 as a laminate of the undoped silicate glass (NSG)132 and the phosphosilicate glass (PSG)133, the protective performance of the protective film 13 for the substrate 11 and the electrode 12 of the semiconductor device 1 can be improved, and the reliability of the semiconductor device 1 can be improved.
In the present embodiment, as shown in fig. 1, the protective film 13 may have 3 stacked layers, for example, a lower undoped silicate glass 1321, a phosphosilicate glass 133, and an upper undoped silicate glass 1322 in this order from the surface 11a of the substrate 11, wherein the lower undoped silicate glass 1321 and the upper undoped silicate glass 1322 are configured as the undoped silicate glass (NSG)132 described above. In addition, the structure of the stacked layer of the protective film 13 in the present embodiment is not limited to this, for example, the protective film 13 may not have the lower undoped silicate glass 1321, and for example, a stacked layer of phosphosilicate glass and undoped silicate glass may be formed on the upper surface of the upper undoped silicate glass 1322 in this order from bottom to top.
In the embodiment, the thickness of the lower layer of undoped silicate glass 1321 may be, for example, 0.1 to 10 microns, the thickness of the phosphosilicate glass 133 may be, for example, 0.1 to 10 microns, and the thickness of the upper layer of undoped silicate glass 1322 may be, for example, 0.1 to 10 microns. In addition, the present embodiment is not limited to this, and the thickness of each layer may be other values.
According to the present embodiment, the lower undoped silicate glass 1321 and the upper undoped silicate glass 1322 sandwich the phosphosilicate glass 133 from the lower surface and the upper surface, respectively, thereby blocking diffusion of the phosphorus element P in the phosphosilicate glass 133 and preventing the phosphorus element P from entering the substrate 11 and the electrode 12.
As shown in fig. 1, the outer lateral end 1321a of the lower undoped silicate glass 1321 extends further away from the electrode 12 than the outer lateral end 133a of the phosphosilicate glass 133 in the direction parallel to the surface 11a of the substrate 11, whereby the barrier effect of the lower undoped silicate glass 1321 against the phosphorus element P can be ensured.
As shown in fig. 1, the lateral end 1322a of the upper undoped silicate glass 1322 covers the lateral end 133a of the phosphosilicate glass 133 in the lateral direction in the direction parallel to the surface 11a of the substrate 11, whereby the external impurities can be prevented from entering the phosphosilicate glass 133 from the lateral end 133 a.
Fig. 2 is another schematic view of the semiconductor device of the present embodiment. Fig. 2 differs from fig. 1 in that, in fig. 2, in the end portion 131 of the protective film 13 overlapping with the lateral end portion 121 of the electrode 12, the end portion 133b of the phosphosilicate glass 133 is covered with the undoped silicate glass 132, whereas, in fig. 1, the end portion 133b of the phosphosilicate glass 133 is covered with the undoped silicate glass 132.
For example, in fig. 2, the end 1322b of the upper undoped silicate glass 1322 in the undoped silicate glass 132 may extend downward so as to cover the end 133b of the phosphosilicate glass 133 in the lateral direction.
According to fig. 2 of the present embodiment, due to the barrier of the undoped silicate glass 132, the phosphorus element P in the phosphosilicate glass 133 can be prevented from entering the electrode 12 from the end portion 133b, thereby further protecting the electrode 12 from corrosion by the phosphorus element P.
In the present embodiment, as shown in fig. 1 and 2, the semiconductor device 1 may further have a voltage-resistant protection portion 14, the voltage-resistant protection portion 14 may be formed in the substrate 11 below the lateral end portion 121 of the electrode 12, and the voltage-resistant protection portion 14 may be, for example, a P-type doped region. The voltage-resistant protection portion 14 serves to mitigate electric field concentration at the lateral end portion 121 of the electrode 12, thereby preventing destruction of the semiconductor device 1 due to electric field concentration.
In the present embodiment, the voltage-resistant protection portion 14 may not exceed the range of the lateral end portion 121 of the electrode 12 in the lateral direction. The lateral width and the longitudinal depth of the voltage-proof protection portion 14 may be set according to the structure of the semiconductor device 1 and the requirement of the voltage-proof value.
In fig. 1 and 2, the lateral end 131 of the protective film 13 may cover at least a part of the voltage-resistant protection portion 14, thereby protecting the voltage-resistant protection portion 14.
As shown in fig. 1 and 2, the semiconductor device 1 may further have a guard ring 15, and the guard ring 15 may be formed in the substrate 11. In the lateral direction, the guard ring 15 may be located farther from the electrode 12 than the voltage-resistant protection portion 14. The guard ring 15 may include a plurality of doped regions 151, such as P-type doped regions. The guard Ring 15 may be called a Field Limiting Ring (FLR) for further reducing a change in an electric Field outside the voltage-resistant protection portion 14, thereby suppressing a decrease in the voltage resistance of the semiconductor device 1.
In the present embodiment, as shown in fig. 1 and 2, the protective film 13 is located above the guard ring 15, whereby the protective film 13 can protect the guard ring 15.
In the present embodiment, the end 133a of the outer side of the phosphosilicate glass 133 does not exceed the lateral end 15a of the guard ring 15 in the direction parallel to the substrate surface 11a and away from the electrode 12. Thus, on the one hand, the phosphosilicate glass 133 has sufficient lateral dimensions to enable effective protection of the guard ring 15; on the other hand, the lateral dimension of the phosphosilicate glass 133 can be controlled so as not to be set excessively large, so that the diffusion amount of the phosphorus element P in the phosphosilicate glass 133 can be controlled.
As shown in fig. 1 and 2, the semiconductor device 1 may further include a back surface electrode 16. The present embodiment does not limit the structure and function of the back electrode 16.
In the above description of the present embodiment, the electrodes and the protective film of the semiconductor device are described with emphasis, and in addition to the above description, the semiconductor device may have other characteristics, and thus the semiconductor device may have corresponding electrical characteristics, for example, the semiconductor device may be a diode, an Insulated Gate Bipolar Transistor (IGBT), or the like.
According to the semiconductor device of the embodiment, the protective film comprises non-doped silicate glass (NSG) and phosphosilicate glass (PSG), wherein the phosphorus element P in the phosphosilicate glass (PSG) can combine with the external impurities entering the phosphosilicate glass, so as to prevent the external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, and the non-doped silicate glass (NSG) can block the phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, so as to prevent the phosphorus element P from corroding the electrode of the semiconductor device and diffusing into the substrate. Therefore, the protective film in the semiconductor device of the present embodiment has good protective properties for the substrate and the electrode, and the reliability of the semiconductor device is improved.
Example 2
Embodiment 2 of the present application provides an electronic device having the semiconductor device described in embodiment 1. Since the structure of the semiconductor device has been described in detail in embodiment 1, the contents thereof are incorporated herein, and the description thereof is omitted here.
According to the present embodiment, the phosphosilicate glass (PSG) in the protective film of the semiconductor device can prevent external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, and the undoped silicate glass (NSG) can block phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, so that the protective film has good protective properties for the substrate and the electrode, and the reliability of the semiconductor device is improved; further, the reliability of an electronic device having the semiconductor device is improved.
The present application has been described in conjunction with specific embodiments, but it should be understood by those skilled in the art that these descriptions are intended to be illustrative, and not limiting. Various modifications and adaptations of the present application may occur to those skilled in the art based on the spirit and principles of the application and are within the scope of the application.

Claims (7)

1. A semiconductor device, comprising:
a substrate;
an electrode formed on the substrate surface; and
a protective film formed on the surface of the substrate,
wherein at least a part of a lateral end of the electrode is disposed to be overlapped on at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface,
the protective film includes a non-doped silicate glass (NSG) and a phosphosilicate glass (PSG) which are laminated.
2. The semiconductor device according to claim 1,
in an end portion of the protective film overlapping with a lateral end portion of the electrode, an end portion of the phosphosilicate glass is covered with the undoped silicate glass.
3. The semiconductor device according to claim 1,
the protective film comprises lower non-doped silicate glass, phosphosilicate glass and upper non-doped silicate glass in sequence from the surface of the substrate.
4. The semiconductor device according to claim 3,
the lateral end portion of the outer side of the lower layer of undoped silicate glass extends further away from the electrode than the lateral end portion of the outer side of the phosphosilicate glass in a direction parallel to the substrate surface.
5. The semiconductor device according to claim 3,
the lateral end of the outer side of the upper layer of undoped silicate glass laterally overlaps the lateral end of the outer side of the phosphosilicate glass in a direction parallel to the substrate surface.
6. The semiconductor device according to claim 1,
the semiconductor device further includes: a guard ring formed within the substrate,
wherein, in a direction parallel to the substrate surface and away from the electrode, a lateral end of an outer side of the phosphosilicate glass does not exceed a lateral end of the guard ring.
7. An electronic device characterized in that the electronic device has the semiconductor device according to any one of claims 1 to 6.
CN201910271303.XA 2019-04-04 Semiconductor device and electronic apparatus Active CN111785694B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910271303.XA CN111785694B (en) 2019-04-04 Semiconductor device and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910271303.XA CN111785694B (en) 2019-04-04 Semiconductor device and electronic apparatus

Publications (2)

Publication Number Publication Date
CN111785694A true CN111785694A (en) 2020-10-16
CN111785694B CN111785694B (en) 2024-04-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540222A (en) * 2021-07-13 2021-10-22 弘大芯源(深圳)半导体有限公司 High-voltage bipolar transistor

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Publication number Priority date Publication date Assignee Title
JPH09213903A (en) * 1996-01-31 1997-08-15 Sanyo Electric Co Ltd Manufacture of semiconductor storage device
JP2002124673A (en) * 2001-07-30 2002-04-26 Seiko Epson Corp Semiconductor device
US20020102841A1 (en) * 2001-01-26 2002-08-01 Sanken Electric Co., Ltd. Method of forming low-resistance contact electrodes in semiconductor devices
JP2017130590A (en) * 2016-01-22 2017-07-27 サンケン電気株式会社 Semiconductor device and manufacturing method of the same
CN107768316A (en) * 2016-08-15 2018-03-06 Abb瑞士股份有限公司 Power semiconductor arrangement and the method for manufacturing this power semiconductor arrangement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213903A (en) * 1996-01-31 1997-08-15 Sanyo Electric Co Ltd Manufacture of semiconductor storage device
US20020102841A1 (en) * 2001-01-26 2002-08-01 Sanken Electric Co., Ltd. Method of forming low-resistance contact electrodes in semiconductor devices
JP2002124673A (en) * 2001-07-30 2002-04-26 Seiko Epson Corp Semiconductor device
JP2017130590A (en) * 2016-01-22 2017-07-27 サンケン電気株式会社 Semiconductor device and manufacturing method of the same
CN107768316A (en) * 2016-08-15 2018-03-06 Abb瑞士股份有限公司 Power semiconductor arrangement and the method for manufacturing this power semiconductor arrangement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540222A (en) * 2021-07-13 2021-10-22 弘大芯源(深圳)半导体有限公司 High-voltage bipolar transistor
CN113540222B (en) * 2021-07-13 2022-10-21 弘大芯源(深圳)半导体有限公司 High-voltage bipolar transistor

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