CN111785693A - Semiconductor device and electronic apparatus - Google Patents
Semiconductor device and electronic apparatus Download PDFInfo
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- CN111785693A CN111785693A CN201910270551.2A CN201910270551A CN111785693A CN 111785693 A CN111785693 A CN 111785693A CN 201910270551 A CN201910270551 A CN 201910270551A CN 111785693 A CN111785693 A CN 111785693A
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- silicate glass
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 239000005360 phosphosilicate glass Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 230000001681 protective effect Effects 0.000 claims abstract description 57
- 239000005368 silicate glass Substances 0.000 claims abstract description 46
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 18
- 229910052698 phosphorus Inorganic materials 0.000 description 18
- 239000011574 phosphorus Substances 0.000 description 18
- 239000012535 impurity Substances 0.000 description 8
- 230000000149 penetrating effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Abstract
An embodiment of the present application provides a semiconductor device and an electronic apparatus, the semiconductor device including: a substrate; an electrode formed on the substrate surface; and a protective film formed on the substrate surface, wherein at least a part of a lateral end of the electrode is overlapped on at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface, and the protective film includes an oxide film, phosphosilicate glass (PSG), and first undoped silicate glass (NSG) which are stacked in this order from the substrate surface. According to the embodiment of the present application, the reliability of the semiconductor device can be improved.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device and an electronic apparatus.
Background
In a semiconductor device, a protective film is generally provided on a surface of a substrate in order to improve reliability of the device. The protective film may be provided on the outer periphery of the active area (active area) or on the outer periphery of the pressure-resistant member, for example.
For example, patent document 1 (japanese patent laid-open publication No. 2017-130590) discloses a silicon carbide (SiC) semiconductor element in which a protective film 70 is provided on an outer peripheral portion of a protective ring 40(Guard ring).
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present application.
Disclosure of Invention
In the related art, the protective film may be any of a silicon oxide film, a silicon nitride film, an undoped silicate glass (NSG) film, a phosphosilicate glass (PSG) film, or the like, for example.
The inventors of the present application have found that in the case of using one material as the protective film, the protective effect of the protective film is limited.
The embodiment of the application provides a semiconductor device and an electronic device, wherein a protective film comprises an oxide film, phosphosilicate glass (PSG) and non-doped silicate glass (NSG) which are arranged in a stacked mode, phosphorus element P in the phosphosilicate glass (PSG) can be combined with external impurities entering the phosphosilicate glass, therefore, the external impurities are prevented from penetrating through the phosphosilicate glass and entering a substrate or an electrode of a semiconductor, the non-doped silicate glass (NSG) can prevent the phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, therefore, the phosphorus element P is prevented from corroding the electrode of the semiconductor device, the oxide film is compact, and the phosphorus element P can be better prevented from diffusing to the substrate. Therefore, the protective film in the semiconductor device of the present embodiment has good protective properties for the substrate and the electrode, and thus the semiconductor device has high reliability.
According to an aspect of an embodiment of the present application, there is provided a semiconductor device having:
a substrate;
an electrode formed on the substrate surface; and
a protective film formed on the substrate surface, wherein at least a part of a lateral end of the electrode is disposed to overlap at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface,
the protective film includes an oxide film, phosphosilicate glass (PSG), and first undoped silicate glass (NSG) stacked in this order from the surface of the substrate.
According to another aspect of the embodiments of the present application, wherein the semiconductor device further has:
a second undoped silicate glass (NSG) disposed to cover the lateral ends of the electrodes.
According to another aspect of an embodiment of the present application, wherein the second non-doped silicate glass (NSG) further covers an upper surface of the first non-doped silicate glass (NSG).
According to another aspect of an embodiment of the present application, wherein the second undoped silicate glass (NSG) further laterally covers lateral ends of an outer side of the phosphosilicate glass (PSG) in a direction parallel to the substrate surface.
According to another aspect of the embodiments of the present application, wherein the semiconductor device further has:
and an outer protective Film (PI) arranged on the surface of the second non-doped silicate glass.
According to another aspect of the embodiments of the present application, wherein a corner portion of the outer protective film near the electrode has a concave portion that is concave toward the substrate direction in a direction parallel to the substrate surface.
According to another aspect of the embodiment of the present application, wherein the electrode is formed in a shape in which a widthwise central portion is thicker than widthwise end portions.
According to another aspect of the embodiments of the present application, wherein the first undoped silicate glass covers an end portion of the phosphosilicate glass in an end portion of the protective film overlapping with a lateral end portion of the electrode.
According to another aspect of embodiments of the present application, there is provided an electronic apparatus having the semiconductor device according to any one of the above-described embodiments.
At least one beneficial effect of this application lies in: the phosphosilicate glass (PSG) of the protective film can effectively prevent external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, the undoped silicate glass (NSG) of the protective film can prevent phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, so that the phosphorus element P is prevented from corroding the electrode of the semiconductor device, and the oxide film in the protective film can better prevent the phosphorus element P from diffusing to the substrate, so that the protective film in the semiconductor device of the embodiment has good protective performance for the substrate and the electrode.
Specific embodiments of the present application are disclosed in detail with reference to the following description and drawings, indicating the manner in which the principles of the application may be employed. It should be understood that the embodiments of the present application are not so limited in scope. The embodiments of the application include many variations, modifications and equivalents within the spirit and scope of the appended claims.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic view of a semiconductor device according to embodiment 1 of the present application;
fig. 2 is another schematic view of a semiconductor device according to embodiment 1 of the present application;
fig. 3 is another schematic view of the semiconductor device according to embodiment 1 of the present application;
fig. 4 is another schematic view of the semiconductor device according to embodiment 1 of the present application.
Detailed Description
The foregoing and other features of the present application will become apparent from the following description, taken in conjunction with the accompanying drawings. In the description and drawings, particular embodiments of the application are disclosed in detail as being indicative of some of the embodiments in which the principles of the application may be employed, it being understood that the application is not limited to the described embodiments, but, on the contrary, is intended to cover all modifications, variations, and equivalents falling within the scope of the appended claims.
In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing different elements by reference, but do not denote a spatial arrangement, a temporal order, or the like of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprising," "including," "having," and the like, refer to the presence of stated features, elements, components, and do not preclude the presence or addition of one or more other features, elements, components, and elements.
In the embodiments of the present application, the singular forms "a", "an", and the like include the plural forms and are to be construed broadly as "a" or "an" and not limited to the meaning of "a" or "an"; furthermore, the term "the" should be understood to include both the singular and the plural, unless the context clearly dictates otherwise. Further, the term "according to" should be understood as "at least partially according to … …," and the term "based on" should be understood as "based at least partially on … …," unless the context clearly dictates otherwise.
In addition, in the following description of the embodiments of the present application, a direction parallel to a substrate surface of a semiconductor device is referred to as a "lateral direction" for convenience of description; in the "lateral direction", a side of each member directed from the outside of the electrode to the direction of the electrode is referred to as "inside", and a side directed from the electrode to the outside of the electrode is referred to as "outside"; a direction perpendicular to a substrate surface of the semiconductor device is referred to as a "longitudinal direction"; in the "longitudinal direction", a direction pointing from the substrate surface of the semiconductor device to the electrode is referred to as an "upper" direction, and a direction opposite to the "upper" direction is a "lower" direction; the dimension in the "longitudinal direction" is referred to as the "thickness" or "depth".
Example 1
Fig. 1 is a schematic view of the semiconductor device of the present embodiment, and as shown in fig. 1, the semiconductor device 1 may have a substrate 11, an electrode 12, and a protective film 13.
In the present embodiment, the substrate 11 may be a semiconductor material, such as silicon, germanium, or a compound semiconductor material. In one embodiment, the semiconductor material may be silicon carbide (SiC).
As shown in fig. 1, the substrate 11 may have: an underlayer 111, and an active layer (active layer)112 formed over the underlayer 111.
The substrate layer 111 may be an N-type doped layer, the active layer 112 may also be an N-type doped layer, and the doping concentration of the active layer 112 may be different from that of the substrate layer 111. For example, the active layer 112 may be a drift layer or the like. In addition, the doping type and the doping concentration of the substrate layer 111 and the active layer 112 may not be limited thereto, for example, the doping type of the substrate layer 111 and the active layer 112 may be different, and for example, the active layer 112 may include a plurality of doping regions distributed in a lateral direction and the like having different doping types.
In the present embodiment, the electrode 12 may be formed on the surface 11a of the substrate 11, and an electrical contact may be formed between the electrode 12 and the active layer 112, and the electrical contact may be, for example, an ohmic contact, a schottky contact, or the like. For example, in fig. 1, the electrode 12 makes electrical contact with the active layer 112, which is a drift layer.
In the present embodiment, the protective film 13 may be formed on the surface 11a of the substrate 11. At least a part of the lateral end 121 of the electrode 12 is disposed to overlap at least a part of the lateral end 131 of the protective film 13 in a direction perpendicular to the surface 11a of the substrate 11.
As shown in fig. 1, the protective film 13 may include, stacked in order from the surface 11a of the substrate 11: an oxide film 1321, phosphosilicate Glass (PSG)133, and a first undoped Silicate Glass (NSG) 1322. Wherein phosphorus element P in phosphosilicate glass (PSG)133 can combine with an external impurity such as water molecule or the like entering into the phosphosilicate glass 133, thereby preventing the external impurity from penetrating through the phosphosilicate glass 133 and invading into the substrate 11 or the electrode 12 of the semiconductor device; the first undoped silicate glass (NSG)1322 can block phosphorus element P in the phosphosilicate glass (PSG)133 from diffusing to the outside, thereby preventing the phosphorus element P from corroding the electrode 12 or the substrate 11 of the semiconductor device; the oxide film 1321 has good crystal characteristics, is dense, and can block diffusion of the phosphorus element P in the phosphosilicate glass (PSG)133 to the substrate, and the oxide film 1321 may be, for example, silicon oxide, and in one embodiment, the oxide film 1321 may be formed by a thermal oxidation method in order to make the oxide film 1321 have high density.
According to the present embodiment, by providing the protective film 13 as a stack of an oxide film, phosphosilicate glass (PSG), and undoped silicate glass (NSG)1322, the protective performance of the protective film 13 with respect to the substrate 11 and the electrode 12 of the semiconductor device 1 can be improved, and the reliability of the semiconductor device 1 can be improved.
In this embodiment, as shown in fig. 1, there may be 3 stacked layers of the protective film 13, but the structure of the stacked layers of the protective film 13 in this embodiment is not limited thereto, and for example, a stack of phosphosilicate glass and undoped silicate glass may be formed on the upper surface of the first undoped silicate glass 1322 in this order from bottom to top.
In the embodiment, the thickness of the oxide film 1321 may be, for example, 1.0 to 1000 angstroms, the thickness of the phosphosilicate glass 133 may be, for example, 0.1 to 10 micrometers, and the thickness of the first undoped silicate glass 1322 may be, for example, 0.1 to 10 micrometers. In addition, the present embodiment is not limited to this, and the thickness of each layer may be other values.
According to the present embodiment, the oxide film 1321 and the first undoped silicate glass 1322 sandwich the phosphosilicate glass 133 from the lower surface and the upper surface, respectively, thereby blocking diffusion of the phosphorus element P in the phosphosilicate glass 133 and preventing the phosphorus element P from entering the substrate 11 and the electrode 12.
In the present embodiment, as shown in fig. 1, the semiconductor device 1 further has a second undoped silicate glass (NSG)17, the second undoped silicate glass (NSG)17 being disposed so as to cover the lateral end portions 121 of the electrodes 12, for example, the second undoped silicate glass (NSG)17 may cover the lateral end portions 121 of the electrodes 12 in the longitudinal direction and in the lateral direction. The second undoped silicate glass (NSG)17 provides better protection to the lateral ends 121 of the electrodes 12 due to its better insulating properties.
In the present embodiment, the second undoped silicate glass (NSG)17 may also extend in the lateral direction so as to cover the upper surface of the protective film 13. For example, as shown in fig. 1, the second undoped silicate glass (NSG)17 may also cover the upper surface of the first undoped silicate glass (NSG) 1322.
In the present embodiment, as shown in fig. 1, the semiconductor device 1 may further include: an outer protective film 18. The outer protective film 18 may be disposed on the surface of the second non-doped silicate glass (NSG) 17. The outer protective Film 18 may be, for example, a Polyimide Film (PI). The outer protective film 18 has good ductility and electrical insulation properties, and can protect the second non-doped silicate glass (NSG) 17.
In the present embodiment, as shown in fig. 1, the corner portion 181 of the outer protective film 18 near the electrode 12 has a recessed portion 1811 recessed toward the substrate 11 in a direction parallel to the surface of the substrate 11. The concave portion 1811 forms the corner portion 181 in a stepped shape, whereby the lead has more space to move near the electrode 12 when the lead is connected to the electrode 12, and therefore, it is convenient to perform an operation of connecting the lead to the electrode 12.
Fig. 2 is another schematic diagram of the semiconductor device 1 of the present embodiment. Fig. 2 differs from fig. 1 in that, in fig. 2, a second undoped silicate glass (NSG)17 laterally covers lateral end portions 133a of the outer sides of phosphosilicate glasses (PSG)133 in a direction parallel to the surface 11a of the substrate 11. Thereby, the lateral end 133a of the phosphosilicate glass (PSG)133 is prevented from being exposed to the outside.
As shown in fig. 2, the second undoped silicate glass (NSG)17 may laterally cover the lateral end portions of the outside of the oxide film 1321 and the lateral end portions of the outside of the first undoped silicate glass 1322.
As shown in fig. 2, the outer protective film 18 may cover the outer lateral end of the second undoped silicate glass (NSG)17, thereby protecting the second undoped silicate glass (NSG)17 more reliably.
Fig. 3 is another schematic diagram of the semiconductor device 1 of the present embodiment. Fig. 3 differs from fig. 1 in that in fig. 3, the electrode 12 is formed in a shape in which a lateral central portion 122 is thicker than lateral end portions 121.
This can prevent the end of the electrode 12 from forming a sharp shape, thereby suppressing discharge when a voltage is applied to the electrode 12; moreover, the end portion 121 of the electrode 12 is thin, and the stress applied to the substrate 11 below the end portion 121 is small, so that the electrical characteristics of the semiconductor device 1 can be ensured to be stable; further, since the central portion 122 of the electrode 12 is relatively thick, damage to the central portion 122 of the electrode 12 can be suppressed when a lead is connected to the central portion 122 of the electrode 12 using an ultrasonic method or the like.
Fig. 4 is another schematic diagram of the semiconductor device 1 of the present embodiment. Fig. 4 differs from fig. 1 in that, in fig. 4, in the end portion 131 of the protective film 13 overlapping with the lateral end portion 121 of the electrode 12, the end portion 1322b on the inner side of the first undoped silicate glass 1322 extends downward and covers the end portion 133b on the inner side of the phosphosilicate glass 133 in the lateral direction, whereby the end portion 133b of the phosphosilicate glass 133 can be prevented from contacting the electrode 12, thereby preventing the phosphorus element in the phosphosilicate glass 133 from diffusing into the electrode 12.
In this embodiment, the differences from fig. 2, 3, 4 and 1 can be combined. For example, the end 1322b of the first undoped silicate glass 1322 shown in fig. 4 may be provided in fig. 2 or 3; and/or, in fig. 3 or fig. 4, the second undoped silicate glass (NSG)17 may also laterally cover the lateral end 133a of the outer side of the phosphosilicate glass (PSG) 133; and/or, in fig. 2 or 4, the electrode 12 may be formed such that the central portion 122 is thicker than the lateral end portions 121.
In addition, the same reference numerals as in fig. 1 in fig. 2, 3, and 4 are not separately described in the present application.
In the present embodiment, as shown in fig. 1, 2, 3 and 4, the semiconductor device 1 may further have a voltage-resistant protection portion 14, the voltage-resistant protection portion 14 may be formed in the substrate 11 below the lateral end portion 121 of the electrode 12, and the voltage-resistant protection portion 14 may be, for example, a P-type doped region. The voltage-resistant protection portion 14 serves to mitigate electric field concentration at the lateral end portion 121 of the electrode 12, thereby preventing destruction of the semiconductor device 1 due to electric field concentration.
In the present embodiment, the voltage-resistant protection portion 14 may not exceed the range of the lateral end portion 121 of the electrode 12 in the lateral direction. The lateral width and the longitudinal depth of the voltage-proof protection portion 14 may be set according to the structure of the semiconductor device 1 and the requirement of the voltage-proof value.
As shown in fig. 1, 2, 3, and 4, the lateral end 131 of the protective film 13 may cover at least a portion of the voltage-resistant protection portion 14, thereby protecting the voltage-resistant protection portion 14.
As shown in fig. 1, 2, 3, and 4, the semiconductor device 1 may further have a guard ring 15, and the guard ring 15 may be formed in the substrate 11. In the lateral direction, the guard ring 15 may be located farther from the electrode 12 than the voltage-resistant protection portion 14. The guard ring 15 may include a plurality of doped regions 151, such as P-type doped regions. The guard Ring 15 may be called a Field Limiting Ring (FLR) for further reducing a change in an electric Field outside the voltage-resistant protection portion 14, thereby suppressing a decrease in the voltage resistance of the semiconductor device 1.
In the present embodiment, as shown in fig. 1, 2, 3, and 4, the protective film 13 is located above the guard ring 15, and thus the protective film 13 can protect the guard ring 15.
As shown in fig. 1, 2, 3, and 4, the semiconductor device 1 may further include a back surface electrode 16.
In addition to the above description of the present embodiment, the semiconductor device may have other features, so that the semiconductor device may have corresponding electrical characteristics, for example, the semiconductor device may be a diode, an Insulated Gate Bipolar Transistor (IGBT), or the like.
According to the semiconductor device of the present embodiment, the protective film includes an oxide film, phosphosilicate glass (PSG), and undoped silicate glass (NSG) formed by stacking, wherein phosphorus element P in the phosphosilicate glass (PSG) can combine with external impurities entering the phosphosilicate glass, thereby preventing the external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, and the oxide film and the undoped silicate glass (NSG) can block the phosphorus element P in the phosphosilicate glass (PSG) from diffusing to the outside, thereby preventing the phosphorus element P from corroding the electrode of the semiconductor device and from diffusing into the substrate. Therefore, the protective film in the semiconductor device of the present embodiment has good protective properties for the substrate and the electrode, and the reliability of the semiconductor device is improved.
Example 2
According to the present embodiment, the phosphosilicate glass (PSG) in the protective film of the semiconductor device can prevent external impurities from penetrating through the phosphosilicate glass and invading into the substrate or the electrode of the semiconductor, and the oxide film and the undoped silicate glass (NSG) can block phosphorus P in the phosphosilicate glass (PSG) from diffusing to the outside, so that the protective film has good protective properties for the substrate and the electrode, and the reliability of the semiconductor device is improved; further, the reliability of an electronic device having the semiconductor device is improved.
The present application has been described in conjunction with specific embodiments, but it should be understood by those skilled in the art that these descriptions are intended to be illustrative, and not limiting. Various modifications and adaptations of the present application may occur to those skilled in the art based on the spirit and principles of the application and are within the scope of the application.
Claims (9)
1. A semiconductor device, comprising:
a substrate;
an electrode formed on the substrate surface; and
a protective film formed on the substrate surface, wherein at least a part of a lateral end of the electrode is disposed to overlap at least a part of a lateral end of the protective film in a direction perpendicular to the substrate surface,
the protective film includes an oxide film, phosphosilicate glass (PSG), and first undoped silicate glass (NSG) stacked in this order from the surface of the substrate.
2. The semiconductor device according to claim 1, further comprising:
a second undoped silicate glass (NSG) disposed to cover the lateral ends of the electrodes.
3. The semiconductor device according to claim 2,
the second undoped silicate glass (NSG) also covers an upper surface of the first undoped silicate glass (NSG).
4. The semiconductor device according to claim 3,
the second undoped silicate glass (NSG) also laterally covers lateral ends of an outer side of the phosphosilicate glass (PSG) in a direction parallel to the substrate surface.
5. The semiconductor device according to claim 2, further comprising:
an outer protective film (PI) disposed on a surface of the second undoped silicate glass.
6. The semiconductor device according to claim 5,
the corner portion of the outer protective film, which is close to the electrode, has a concave portion that is concave toward the substrate in a direction parallel to the substrate surface.
7. The semiconductor device according to claim 1,
the electrode is formed in a shape in which a widthwise central portion is thicker than widthwise end portions.
8. The semiconductor device according to claim 1,
in an end portion of the protective film overlapping with a lateral end portion of the electrode, the first undoped silicate glass covers an end portion of the phosphosilicate glass.
9. An electronic device characterized in that the electronic device has the semiconductor device according to any one of claims 1 to 8.
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| CN201910270551.2A CN111785693A (en) | 2019-04-04 | 2019-04-04 | Semiconductor device and electronic apparatus |
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| CN201910270551.2A CN111785693A (en) | 2019-04-04 | 2019-04-04 | Semiconductor device and electronic apparatus |
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