JP2018195845A - Semiconductor device - Google Patents

Abstract

To improve electromigration resistance of an electrode.SOLUTION: A semiconductor device has a drain electrode DE which is partially embedded in a side face DSF of a drain pad DP. In this case, the drain electrode DE is coupled with the drain pad DP and extends from the side face DSF in a first direction (y direction) in plan view. In a region overlapping the drain electrode DE in plan view, a recess DRE is located. In the recess DRE, at least a part of the drain electrode DE is embedded. A side face (side face RDS) of the recess DRE, which faces the drain pad DP is fitted in the drain pad DP when viewed in the first direction (y direction).SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and is a technique applicable to, for example, a power device.

  A transistor using a nitride semiconductor layer may be used for the power device. Patent Document 1 describes an example of such a transistor. In the transistor described in Patent Document 1, an interlayer insulating film is formed on a nitride semiconductor layer. On the interlayer insulating film, a drain pad and a source pad, and a drain electrode and a source electrode are provided. The drain electrode is provided in a comb shape on the drain pad. Similarly, the source electrode is provided in a comb shape on the source pad. In this case, the drain electrode and the source electrode are arranged so as to mesh with each other.

  Further, in Patent Document 1, the drain electrode includes a concave portion formed in the interlayer insulating film on the inner side in a plan view. A part of the drain electrode is embedded in the recess. The drain electrode is electrically connected to the nitride semiconductor layer through the recess. Similarly, the source electrode includes a recess formed in the interlayer insulating film on the inner side in a plan view. A part of the source electrode is embedded in the recess. The source electrode is electrically connected to the nitride semiconductor layer through the recess.

JP 2014-22413 A

  In general, electromigration tends to occur in a region where the width of the current path becomes narrower in the direction of current flow (current concentration region). In particular, a large current may flow through the electrode connected to the nitride semiconductor layer. For this reason, when a current concentration region is formed in the electrode connected to the nitride semiconductor layer, a structure for realizing high electromigration resistance is required. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the interlayer insulating film is located on the nitride semiconductor layer. A wiring is located on the interlayer insulating film. An electrode is partially formed on the first side surface of the wiring. The electrode is integral with the wiring and extends in the first direction from the first side surface in plan view. A recess is formed in the interlayer insulating film. The recess is located in a region overlapping the electrode in plan view. At least a part of the electrode is embedded in the recess. A barrier metal film is formed along the bottom and side surfaces of the recess, the bottom surface of the wiring, and the bottom surface of the electrode. The wiring and the electrode contain aluminum. The barrier metal film contains titanium. The side surface facing the wiring in the recess reaches the first side surface of the wiring or enters the wiring when viewed in the first direction.

  According to the one embodiment, the electrode has high electromigration resistance.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. It is AA 'sectional drawing of FIG. It is BB 'sectional drawing of FIG. It is the figure which expanded the area | region enclosed with the broken line (alpha) of FIG. It is the figure which expanded the area | region enclosed with the broken line (beta) of FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is a top view which shows the structure of the semiconductor device which concerns on a comparative example. It is a graph which shows the electromigration characteristic of the layout which concerns on 1st Embodiment, and the electromigration characteristic of the layout which concerns on a comparative example. It is a figure which shows the 1st modification of FIG. It is a figure which shows the 2nd modification of FIG. It is a figure which shows the 3rd modification of FIG. It is a figure which shows the 4th modification of FIG. It is a figure which shows the 5th modification of FIG. It is a figure which shows the 6th modification of FIG. It is a top view which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is the figure which expanded the area | region enclosed with the broken line (alpha) of FIG. It is the figure which expanded the area | region enclosed with the broken line (beta) of FIG. It is a top view which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is the figure which expanded the area | region enclosed with the broken line (alpha) of FIG. It is the figure which expanded the area | region enclosed with the broken line (beta) of FIG. It is a figure which shows the modification of FIG. It is the figure which expanded the area | region enclosed with the broken line (alpha) of FIG. It is the figure which expanded the area | region enclosed with the broken line (beta) of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device SD according to the first embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. 2 and 3, the semiconductor device SD includes a semiconductor substrate SMS, a buffer layer BUF, a nitride semiconductor layer NSL (first nitride semiconductor layer NSL1 and second nitride semiconductor layer NSL2), and a protective insulating layer PIL. (For example, a silicon nitride film (SiN)) and an interlayer insulating film ILD (for example, a silicon oxide film (SiO ₂ )). The semiconductor substrate SMS, the buffer layer BUF, the first nitride semiconductor layer NSL1, the second nitride semiconductor layer NSL2, the protective insulating layer PIL, and the interlayer insulating film ILD are stacked in this order.

  A planar layout of the semiconductor device SD will be described with reference to FIG. As shown in the figure, the semiconductor device SD includes a plurality of transistors TR, a drain pad DP (wiring), a source pad SP (wiring), a gate pad GP, a plurality of drain electrodes DE, a plurality of source electrodes SE, and a plurality of gates. An electrode GE and a gate wiring GL are provided.

  Each transistor TR has a gate electrode GE and has a drain and a source in the nitride semiconductor layer NSL (FIGS. 2 and 3). As will be described later, the gate electrode GE extends in the first direction (y direction). A drain electrode DE and a source electrode SE are electrically connected to the drain and the source, respectively. In this case, in each transistor TR, a drain (drain electrode DE), a gate electrode GE, and a source (source electrode SE) are arranged in this order in a second direction (x direction) orthogonal to the first direction (y direction). It is out.

  In the example shown in this drawing, a plurality of transistors TR are arranged in the second direction (x direction). Specifically, the gate electrodes GE of the plurality of transistors TR are arranged in the second direction (x direction). In the example shown in the drawing, the drain electrode DE, the gate electrode GE, the source electrode SE, and the gate electrode GE are repeatedly arranged in this order in the second direction (x direction). In this case, the transistors TR adjacent to each other via the drain electrode DE have their drains electrically connected to the same drain electrode DE. Similarly, the transistors TR adjacent to each other via the source electrode SE are electrically connected to the same source electrode SE.

  The drain pad DP and the source pad SP are opposed to each other via the transistor TR in the first direction (y direction) in plan view. The drain pad DP and the source pad SP extend in the second direction (x direction). More specifically, the drain pad DP and the source pad SP have a rectangular shape in which the planar shape has a longitudinal direction in the second direction (x direction).

  The plurality of drain electrodes DE are formed in a comb-teeth shape on the drain pad DP. In this case, the plurality of drain electrodes DE are formed integrally with the drain pad DP. Similarly, the plurality of source electrodes SE are formed in a comb shape on the source pad SP. In this case, the plurality of source electrodes SE are formed integrally with the source pad SP. The drain electrode DE and the source electrode SE are arranged so as to mesh with each other.

  More specifically, the drain pad DP has a plurality of drain electrodes DE on a side surface (side surface DSF: first side surface) facing the source pad SP. In this case, each drain electrode DE is partially formed on the side surface DSF of the drain pad DP. Further, each drain electrode DE extends in the first direction (y direction) from the drain pad DP side toward the source pad SP side. Similarly, the source pad SP has a plurality of source electrodes SE on the side surface (side surface SSF: first side surface) facing the drain pad DP. In this case, each source electrode SE is partially formed on the side surface SSF of the source pad SP. Further, each source electrode SE extends in the first direction (y direction) from the source pad SP side toward the drain pad DP side. The source electrode SE and the drain electrode DE are repeatedly arranged in this order in the second direction (x direction).

  In the example shown in this figure, the widths of the drain electrodes DE are equal. However, the width of each drain electrode DE may be different from each other. Similarly, in the example shown in this drawing, the widths of the source electrodes SE are equal. However, the widths of the source electrodes SE may be different from each other.

  As will be described later with reference to FIGS. 2 and 3, a recess REC is formed in the interlayer insulating film ILD (FIGS. 2 and 3). The planar shape of the recess REC will be described with reference to FIG. A plurality of recesses REC are provided in plan view. Each recess REC is provided in each drain electrode DE and each source electrode SE in plan view.

  Specifically, the recess REC (recess DRE) provided in the drain electrode DE is located in a region overlapping the drain electrode DE in plan view. Similarly, the recess REC (recess SRE) provided in the source electrode SE is located in a region overlapping the source electrode SE in plan view. Furthermore, in the example shown in this drawing, the recess DRE extends along the extending direction (y direction) of the drain electrode DE. Similarly, the recess SRE extends along the extending direction (y direction) of the source electrode SE.

  In the example shown in this figure, the length in the first direction (y direction) of the portion of the recess DRE that overlaps the drain electrode DE in plan view is the length in the first direction (y direction) of the drain electrode DE. On the other hand, it is 75% or more and less than 100%, for example. Similarly, the length of the portion of the recess SRE that overlaps the source electrode SE in plan view in the first direction (y direction) is, for example, 75% of the length of the source electrode SE in the first direction (y direction). It is less than 100%. However, the lengths of the recess DRE and the recess SRE are not limited to the above example.

  Further, in plan view, the recess DRE is sandwiched between the gate electrodes GE adjacent to each other via the drain electrode DE. Similarly, in plan view, the recess SRE is sandwiched between the gate electrodes GE adjacent to each other via the source electrode SE. Each gate electrode GE extends in the first direction (y direction) from the gate line GL.

  The gate line GL is located closer to the source pad SP than the drain electrode DE in plan view. In this case, the gate line GL extends in the second direction (x direction). In the example shown in this figure, the gate wiring GL has one end connected to one gate pad GP and the other end connected to another gate pad GP. Further, a plurality of gate electrodes GE are formed in a comb shape on the gate wiring GL. In this case, the gate electrode GE is formed integrally with the gate wiring GL.

  In the example shown in this drawing, the width of the recess DRE in the second direction (x direction) is narrower than the width of the drain electrode DE in the second direction (x direction). Similarly, the width of the recess SRE in the second direction (x direction) is narrower than the width of the source electrode SE in the second direction (x direction). In this case, as will be described later, the drain electrode DE is embedded in the recess REC in the region where the recess REC is formed, and on the interlayer insulating film ILD (FIGS. 2 and 3) in the region where the recess REC is not formed. To position. Similarly, the source electrode SE is buried in the recess REC in the region where the recess REC is formed, and is located on the interlayer insulating film ILD (FIGS. 2 and 3) in the region where the recess REC is not formed.

  Note that the width of the recess DRE in the second direction (x direction) may be equal to the width of the drain electrode DE in the second direction (x direction). In this case, the entire drain electrode DE is embedded in the recess DRE in the second direction (x direction). Similarly, the width of the recess SRE in the second direction (x direction) may be equal to the width of the source electrode SE in the second direction (x direction). In this case, the entire source electrode SE is embedded in the recess SRE in the second direction (x direction).

  FIG. 4 is an enlarged view of a region surrounded by a broken line α in FIG. As shown in the figure, the side surface (side surface RDS) facing the drain pad DP in the recess DRE enters the drain pad DP when viewed in the first direction (y direction). In this case, a part of the drain pad DP is embedded in the recess DRE.

  The length of the portion of the recess DRE entering the drain pad DP when viewed in the first direction (y direction) can be set to, for example, 300 nm. In this case, the recess DRE can surely enter the drain pad DP. Specifically, even when the recess DRE and the drain pad DP are designed so that a part of the recess DRE enters the drain pad DP, the position of the recess DRE may be shifted from the design due to, for example, a lithography error. Even in such a case, when the recess DRE satisfies the above-described example in the actually manufactured layout, the recess DRE can surely enter the drain pad DP.

  FIG. 5 is an enlarged view of a region surrounded by a broken line β in FIG. As shown in the figure, the side surface (side surface RSS) facing the source pad SP in the recess SRE enters the source pad SP when viewed in the first direction (y direction). In this case, a part of the source pad SP is embedded in the recess SRE. Note that the length of the portion of the recess SRE that enters the source pad SP when viewed in the first direction (y direction) can be the same as, for example, the above-described example of the recess DRE.

  Further, in the example shown in this drawing, the gate wiring GL, the side surface SSF (the side surface of the source pad SP where the source electrode SE is formed), and the source electrode SE are arranged in this order in the first direction (y direction). . As a result, the recess SRE can enter the source pad SP when viewed in the first direction (y direction). As will be described later, the recess SRE is formed in the interlayer insulating film ILD (FIGS. 2 and 3). On the other hand, the gate wiring GL is buried in the interlayer insulating film ILD (FIG. 3). For this reason, the recess SRE cannot be formed in a region overlapping the gate wiring GL in plan view. Therefore, in the example shown in this figure, the gate line GL is inserted into the source pad SP as viewed in the first direction (y direction). In this case, as described above, the recess SRE can enter the source pad SP when viewed in the first direction (y direction).

  Next, a cross-sectional structure of the semiconductor device SD will be described with reference to FIGS. The semiconductor substrate SMS is, for example, a silicon substrate, an SOI (Silicon On Insulator) substrate, a GaN substrate, or a SiC substrate. However, the semiconductor substrate SMS is not limited to these. Note that, for example, a sapphire substrate may be used instead of the semiconductor substrate SMS.

  In the nitride semiconductor layer NSL, the first nitride semiconductor layer NSL1 and the second nitride semiconductor layer NSL2 form a heterojunction. Thus, the first nitride semiconductor layer NSL1 forms a two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) on the second nitride semiconductor layer NSL2 side. The first nitride semiconductor layer NSL1 and the second nitride semiconductor layer NSL2 are formed by epitaxial growth, for example, a GaN layer (first nitride semiconductor layer NSL1) and an AlGaN layer (second nitride semiconductor layer NSL2), respectively. ). However, the materials of the first nitride semiconductor layer NSL1 and the second nitride semiconductor layer NSL2 are not limited to this example.

  In the example shown in this drawing, a buffer layer BUF is formed between the semiconductor substrate SMS and the nitride semiconductor layer NSL (first nitride semiconductor layer NSL1). The buffer layer BUF has, for example, an AlN / AlGaN superlattice structure. The buffer layer BUF suppresses occurrence of cracks in the semiconductor substrate SMS (for example, cracks caused by a difference in lattice constant between the semiconductor substrate SMS and the first nitride semiconductor layer NSL1).

As shown in FIG. 2, a recess GRE is formed in the protective insulating layer PIL. In the example shown in this drawing, the recess GRE has a lower end reaching the upper surface of the nitride semiconductor layer NSL (second nitride semiconductor layer NSL2). A gate insulating film GI (for example, a silicon oxide film (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or hafnium oxide (HfO ₂ )) is formed along the bottom and side surfaces of the recess GRE. Further, a gate electrode GE is formed on the gate insulating film GI. Thereby, the recess GRE is filled with the gate electrode GE. Further, the gate electrode GE is covered with an interlayer insulating film ILD. Note that the gate electrode GE is formed of, for example, polysilicon or metal (for example, aluminum).

  In the example shown in this drawing, the gate insulating film GI and the gate electrode GE are also formed around the recess GRE. In this case, the gate insulating film GI and the gate electrode GE are embedded in the recess GRE in the region where the recess GRE is formed. On the other hand, the gate insulating film GI and the gate electrode GE are located on the protective insulating layer PIL in a region where the recess GRE is not formed.

  Recesses REC (recesses DRE and recesses SRE) are formed in the interlayer insulating film ILD. In the example shown in the drawing, the lower end of the recess REC reaches the upper surface of the nitride semiconductor layer NSL (second nitride semiconductor layer NSL2). A barrier metal film BM (barrier metal film DBM) is formed along the bottom and side surfaces of the recess DRE. Similarly, a barrier metal film BM (barrier metal film SBM) is formed along the bottom and side surfaces of the recess SRE. A drain electrode DE is formed on the barrier metal film DBM. Thereby, the recess DRE is filled with the drain electrode DE. Similarly, a source electrode SE is formed on the barrier metal film SBM. Thereby, the recess SRE is filled with the source electrode SE.

  In the example shown in this drawing, the barrier metal film BM and the drain electrode DE (source electrode SE) are also formed around the recess REC. In this case, the barrier metal film BM and the drain electrode DE (source electrode SE) are embedded in the recess REC in the region where the recess REC is formed. On the other hand, the barrier metal film BM and the drain electrode DE (source electrode SE) are located on the interlayer insulating film ILD in the region where the recess REC is not formed.

  In the example shown in this figure, the barrier metal film BM is a single layer film made of titanium (Ti). The drain electrode DE and the source electrode SE are formed of an aluminum alloy (AlCu) containing copper. In this case, in the example shown in this drawing, a film (barrier film) that suppresses the reaction between titanium and aluminum is not formed between the barrier metal film BM and the drain electrode DE (source electrode SE). In other words, the barrier metal film BM is directly connected to the drain electrode DE (source electrode SE). The barrier film is a film made of, for example, titanium nitride (TiN). As will be described in detail later, in the example shown in this drawing, titanium (Ti) contained in the barrier metal film BM and aluminum (Al) contained in the drain electrode DE (source electrode SE) can be provided without providing a barrier film. The reaction can be suppressed.

  Further, when the barrier film is a film made of titanium nitride (TiN), a high-temperature thermal process for forming an ohmic junction between the drain electrode DE (source electrode SE) and the nitride semiconductor layer NSL becomes unnecessary. Specifically, the drain electrode DE (source electrode SE) and the nitride semiconductor layer NSL need to be electrically connected to each other through an ohmic junction. In this case, when a film made of titanium nitride (TiN) is included between the barrier metal film BM and the drain electrode DE (source electrode SE), a high-temperature thermal process is required. On the other hand, in the example shown in this figure, such a heat process becomes unnecessary.

  However, the barrier metal film BM may be, for example, a titanium nitride / titanium (TiN / Ti) laminated film. Even in this case, the drain electrode DE (source electrode SE) and the nitride semiconductor layer NSL can be electrically connected by an ohmic junction if the above-described thermal process is performed. Furthermore, the barrier metal film BM is not limited to the above example as long as it is a film containing titanium (Ti).

  Furthermore, the material of the drain electrode DE (source electrode SE) is not limited to the above example (AlCu). The drain electrode DE (source electrode SE) is formed of a film containing aluminum (Al). For example, the drain electrode DE (source electrode SE) is a single layer film made of aluminum (Al). As another example, the drain electrode DE (source electrode SE) is an aluminum alloy (AlSiCu) containing silicon (Si) and copper (Cu).

  As shown in FIG. 3, the gate wiring GL is provided on the protective insulating layer PIL. The gate wiring GL is covered with an interlayer insulating film ILD. Further, the source pad SP is located above the gate wiring GL via the interlayer insulating film ILD.

  As shown in the figure, the source pad SP and the source electrode SE are integrally formed. Further, a barrier metal film BM is formed along the bottom and side surfaces of the recess SRE and the bottom surface of the source pad SP. As described above, the side surface RSS of the recess SRE enters the source pad SP in the first direction (y direction). Thus, the side surface RSS, the side surface SSF (the side surface of the source pad SP where the source electrode SE is formed), and the source electrode SE are arranged in this order in the first direction (y direction).

  In the example shown in this figure, the nitride semiconductor layer NSL, the barrier metal film BM, and the source pad SP are arranged in this order (z direction) between the side surface RSS and the side surface SSF in the first direction (y direction). ) Will be positioned. In other words, the interface between the interlayer insulating film ILD and the barrier metal film BM (barrier metal film SBM) is not formed in the thickness direction (z direction) between the side surface RSS and the side surface SSF in the first direction (y direction). . In this case, as will be described in detail later, the electromigration resistance of the source electrode SE is high.

  6 to 12 are sectional views showing a method for manufacturing the semiconductor device SD shown in FIGS. 1 to 3 and correspond to FIG. First, as shown in FIG. 6, the buffer layer BUF is formed on the semiconductor substrate SMS by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Next, the nitride semiconductor layer NSL (the first nitride semiconductor layer NSL1 and the second nitride semiconductor layer NSL2) is formed on the buffer layer BUF, for example, by epitaxial growth. Next, the protective insulating layer PIL is formed over the nitride semiconductor layer NSL.

  Next, as shown in FIG. 7, a recess GRE is formed in the protective insulating layer PIL. In the example shown in this figure, the recess GRE penetrates the protective insulating layer PIL. The lower end of the recess GRE reaches the upper surface of the nitride semiconductor layer NSL (second nitride semiconductor layer NSL2).

  Next, as shown in FIG. 8, the insulating film GI1 and the conductive film GE1 are stacked in this order on the protective insulating layer PIL. The insulating film GI1 is an insulating film that becomes the gate insulating film GI. The conductive film GE1 is a conductive film that becomes the gate electrode GE and the gate wiring GL. In the example shown in this figure, a part of the insulating film GI1 and a part of the conductive film GE1 are embedded in the recess GRE.

  Next, as shown in FIG. 9, the insulating film GI1 and the conductive film GE1 (FIG. 8) are patterned. Thereby, the gate insulating film GI and the gate electrode GE are formed. In this step, the gate wiring GL (FIGS. 1 and 3) is also formed together with the gate electrode GE.

  Next, as shown in FIG. 10, an interlayer insulating film ILD is formed on the protective insulating layer PIL and the gate electrode GE by, for example, CVD (Chemical Vapor Deposition). Thereby, the protective insulating layer PIL and the gate electrode GE are covered with the interlayer insulating film ILD.

  Next, as shown in FIG. 11, recesses REC (recesses DRE and recesses SRE) are formed in the interlayer insulating film ILD by lithography. In this case, the recess REC penetrates the interlayer insulating film ILD and the protective insulating layer PIL. The lower end of the recess REC reaches the upper surface of the nitride semiconductor layer NSL (second nitride semiconductor layer NSL2).

  Next, as shown in FIG. 12, a metal film BM1 is formed on the interlayer insulating film ILD, for example, by sputtering. The metal film BM1 is a metal film that becomes the barrier metal film BM. Next, a metal film MF is formed on the metal film BM1, for example, by sputtering. The metal film MF is a metal film that becomes the drain pad DP and the source pad SP, and the drain electrode DE and the source electrode SE. In the example shown in the drawing, the metal film BM1 is formed along the bottom and side surfaces of the recess REC and the top surface of the interlayer insulating film ILD. On the other hand, the metal film MF is partially embedded in the recess REC.

  Next, the metal film MF and the metal film BM1 are patterned. Thereby, the drain pad DP and the source pad SP, the drain electrode DE and the source electrode SE are formed, and the barrier metal film BM is formed. In this way, the semiconductor device SD shown in FIGS. 1 to 3 is manufactured.

  FIG. 13 is a plan view showing the configuration of the semiconductor device SD according to the comparative example, and corresponds to FIG. 1 of the present embodiment. The semiconductor device SD according to the comparative example has the same configuration as the semiconductor device SD according to the present embodiment except for the following points.

  As shown in the figure, the recess DRE has a side surface RDS on the drain pad DP side in the same manner as in the present embodiment. Similarly, the recess SRE has a side surface RSS on the source pad SP side. In the example shown in this figure, the side surface RDS is positioned on the opposite side of the drain pad DP in the first direction (y direction) via the side surface DSF (the side surface of the drain pad DP on which the drain electrode DE is formed). ing. Similarly, the side surface RSS is located on the opposite side of the source pad SP via the side surface SSF (the side surface of the source pad SP where the source electrode SE is formed) in the first direction (y direction). In other words, the side surface RDS enters the inside of the drain electrode DE in the first direction (y direction). Similarly, the side surface RSS enters the inside of the source electrode SE in the first direction (y direction).

  FIG. 14 is a graph showing the electromigration characteristics of the layout according to the present embodiment and the electromigration characteristics of the layout according to the comparative example. In this figure, 1000 [a. u. ] And 2000 [a. u. ] Are broken lines. This broken line indicates the end time of the test.

  In this figure, the inventors used a TEG (Test Element Group) according to the present embodiment and a TEG according to the comparative example. Specifically, in the TEG according to the present embodiment, the drain pad DP has one drain electrode DE, and the source pad SP has one source electrode SE. Similarly, in the TEG according to the comparative example, the drain pad DP has one drain electrode DE, and the source pad SP has one source electrode SE.

  As shown in this figure, the electromigration lifetime of the layout according to the present embodiment is about 2.4 times the electromigration lifetime of the layout according to the comparative example. Thus, this embodiment has better electromigration resistance than the comparative example. The reason will be described below.

  In general, electromigration is a phenomenon in which a wiring metal moves using a momentum exchange due to collision with electrons as a driving force. For this reason, it is likely to occur in a region having a high current density (current concentration region). In this embodiment and the comparative example, the current concentration region corresponds to a region from the drain pad DP to the drain electrode DE (FIGS. 1 and 13) and a region from the source pad SP to the source electrode SE (FIGS. 1 and 13). To do.

In this embodiment and the comparative example, Al ₃ Ti can cause electromigration. As described above, the drain electrode DE (source electrode SE) contains aluminum. On the other hand, the barrier metal film BM contains titanium. The drain electrode DE (source electrode SE) and the barrier metal film BM are in contact with each other. For this reason, aluminum contained in the drain electrode DE (source electrode SE) and titanium contained in the barrier metal film BM may react with each other. In this case, Al ₃ Ti is generated at the interface between the drain electrode DE (source electrode SE) and the barrier metal film BM. In this case, a high-speed diffusion path can be formed at the interface between Al ₃ Ti and the surrounding area. The fast diffusion path causes electromigration.

  In the present embodiment, as shown in FIG. 1, the side surface RDS of the recess DRE and the side surface RSS of the recess SRE enter the drain pad DP and the source pad SP, respectively, in the first direction (y direction). On the other hand, in the comparative example, as shown in FIG. 13, the side surface RDS of the recess DRE and the side surface RSS of the recess SRE are inside the drain electrode DE and inside the source electrode SE in the first direction (y direction), respectively. It has entered. As is clear from this comparison, the recess DRE is located at the end of the drain electrode DE on the drain pad DP side (the recess SRE is located at the end of the source electrode SE on the source pad SP side). It is suggested that this has led to an improvement in migration resistance.

  As a result of studies by the present inventors, it has been clarified that when the recess REC is located at the above-described end, it is highly likely that the high-speed diffusion path is suppressed from being formed in the current concentration region. . Specifically, in the present embodiment, the recess REC is located at the above-described end. In this case, the stacked structure at this end is drain electrode DE (source electrode SE) / barrier metal film BM / nitride semiconductor layer NSL (for example, FIG. 3). On the other hand, in the comparative example, the recess REC is not located at the above-described end. In this case, the laminated structure at this end is drain electrode DE (source electrode SE) / barrier metal film BM / interlayer insulating film ILD. As is clear from this comparison, it is suggested that the above-described stacked structure of this embodiment can effectively suppress the formation of a high-speed diffusion path as compared with the above-described stacked structure of the comparative example.

  The present inventors have observed the following two cross-sectional structures using TEM (Transmission Electron Microscope). As a result, the inventors examined the reason why the above-described stacked structure of the present embodiment can effectively suppress the formation of the high-speed diffusion path as compared with the above-described stacked structure of the comparative example.

  First, a cross section of a structure (Al / Ti / GaN) in which a GaN film, a Ti film, and an Al film were laminated in this order was observed. This structure corresponds to the above-described laminated structure of the present embodiment. As a result of observation, it was revealed that the Al film has a high (111) orientation. This is because the Al film may be formed on the GaN film. In other words, there is a high possibility that the Al film inherits the high orientation of the GaN film. In other words, there is a possibility that the Al film is epitaxially grown with the GaN film as a base.

Second, the cross section of the structure (Al / Ti / SiO ₂ ) in which the SiO ₂ film, Ti film, and Al film were laminated in this order was observed. This structure corresponds to the above-described laminated structure of the comparative example. As a result of observation, it was revealed that the Al film has a low (111) orientation. This is because the Al film may be formed on the SiO ₂ film.

According to the result of the observation described above, in the present embodiment, even if Al ₃ Ti is formed, the region around Al ₃ Ti has high orientation. Thereby, formation of a high-speed diffusion path may be suppressed. On the other hand, in the comparative example, the orientation of the region around Al ₃ Ti is low. Thereby, when Al ₃ Ti is formed, a high-speed diffusion path may be easily formed at the interface between Al ₃ Ti and the surrounding region. In this way, this embodiment has better electromigration resistance than the comparative example.

  As described above, according to the present embodiment, the recess DRE is formed in the region overlapping the drain electrode DE in plan view. Similarly, a recess SRE is formed in a region overlapping the source electrode SE in plan view. In plan view, a part of the recess DRE enters the drain pad DP. Similarly, a part of the recess SRE enters the source pad SP in plan view. Thereby, the electromigration resistance of the drain electrode DE and the electromigration resistance of the source electrode SE become high.

  FIG. 15 is a diagram showing a first modification of FIG. As shown in the drawing, the lower end of the recess REC (the recess DRE and the recess SRE) may penetrate the second nitride semiconductor layer NSL2. In the example shown in the drawing, the lower end of the recess REC reaches the upper surface of the first nitride semiconductor layer NSL1. Also in the example shown in this figure, the same effect as this embodiment is acquired.

  FIG. 16 is a diagram showing a second modification of FIG. 2, and this modification corresponds to the modification of FIG. As shown in the drawing, the lower end of the recess REC may enter the first nitride semiconductor layer NSL1. In this case, the lower end of the recess REC does not penetrate the first nitride semiconductor layer NSL1. Also in the example shown in this figure, the same effect as this embodiment is acquired.

  FIG. 17 is a diagram showing a third modification of FIG. 2, and this modification corresponds to the modification of FIG. As shown in the figure, the lower end of the recess GRE may enter the second nitride semiconductor layer NSL2. In this case, the lower end of the recess GRE does not penetrate the second nitride semiconductor layer NSL2. Also in the example shown in this figure, the same effect as this embodiment is acquired.

  FIG. 18 is a diagram illustrating a fourth modification of FIG. As shown in the drawing, a cap layer CL may be provided between the second nitride semiconductor layer NSL2 and the protective insulating layer PIL. The cap layer CL is a nitride semiconductor layer, more specifically, for example, an undoped GaN film. The lower end of the recess GRE penetrates the protective insulating layer PIL and reaches the upper surface of the cap layer CL. The lower end of the recess REC reaches the upper surface of the nitride semiconductor layer NSL (second nitride semiconductor layer NSL2) through the interlayer insulating film ILD, the protective insulating layer PIL, and the cap layer CL.

  Also in the example shown in this figure, the same effect as this embodiment is acquired. Furthermore, in the example shown in this drawing, the upper surface of the second nitride semiconductor layer NSL2 is covered with the cap layer CL. In this case, the second nitride semiconductor layer NSL2 is protected by the cap layer CL. In particular, the cap layer CL functions effectively when the second nitride semiconductor layer NSL2 is formed of AlGaN. Al contained in AlGaN is easily oxidized. According to the example shown in the figure, the oxidation of Al can be suppressed by the cap layer CL.

  FIG. 19 is a diagram illustrating a fifth modification of FIG. 2, and this modification corresponds to the modification of FIG. As shown in the drawing, the lower end of the recess REC (the recess DRE and the recess SRE) may penetrate the second nitride semiconductor layer NSL2. In the example shown in the drawing, the lower end of the recess REC reaches the upper surface of the first nitride semiconductor layer NSL1. Also in the example shown in this figure, the same effect as this embodiment is acquired.

  FIG. 20 is a diagram showing a sixth modification of FIG. 2, and this modification corresponds to the modification of FIG. As shown in the drawing, the lower end of the recess REC may enter the first nitride semiconductor layer NSL1. In this case, the lower end of the recess REC does not penetrate the first nitride semiconductor layer NSL1. Also in the example shown in this figure, the same effect as this embodiment is acquired.

(Second Embodiment)
FIG. 21 is a plan view showing the configuration of the semiconductor device SD according to the second embodiment, and corresponds to FIG. 1 of the first embodiment. The semiconductor device SD according to the present embodiment has the same configuration as the semiconductor device SD according to the first embodiment except for the following points.

  As shown in this figure, in this embodiment as well, as in the first embodiment (FIG. 1), a recess DRE is formed in a region overlapping the drain electrode DE in plan view. Similarly, a recess SRE is formed in a region overlapping the source electrode SE in plan view.

  FIG. 22 is an enlarged view of a region surrounded by a broken line α in FIG. 21 and corresponds to FIG. 4 of the first embodiment. As shown in this figure, the side surface RDS of the recess DRE (the side surface of the recess DRE facing the drain pad DP) is viewed in the first direction (y direction), and the side surface DSF of the drain pad DP (the drain electrode DE is formed). Has been reached).

  FIG. 23 is an enlarged view of a region surrounded by a broken line β in FIG. 21, and corresponds to FIG. 5 of the first embodiment. As shown in this figure, the side surface RSS (the side surface of the recess SRE facing the source pad SP) of the recess SRE is viewed in the first direction (y direction), and the side surface SSF (source electrode SE is formed) of the source pad SP. Has been reached).

  In the present embodiment, the recesses REC (the recesses DRE and the recesses SRE) do not enter the pads (the drain pad DP and the source pad SP) in plan view. Even in this case, the recess DRE is located at the end of the drain electrode DE on the drain pad DP side. Similarly, a recess SRE is located at the end of the source electrode SE on the source pad SP side. For this reason, also in this embodiment, the effect similar to 1st Embodiment is acquired.

(Third embodiment)
FIG. 24 is a plan view showing the configuration of the semiconductor device SD according to the third embodiment, and corresponds to FIG. 1 of the first embodiment. The semiconductor device SD according to the present embodiment has the same configuration as the semiconductor device SD according to the first embodiment except for the following points.

  As shown in this figure, also in this embodiment, similarly to the first embodiment (FIG. 1), the drain electrode DE and the source electrode SE are repeatedly arranged in this order in the second direction (x direction). In the present embodiment, the width of the source electrode SE is wider than the width of the drain electrode DE. In this case, the current concentration from the source pad SP to the source electrode SE can be made smaller than that in the first embodiment. As a result, as will be described in detail later, it is not necessary to position the recess SRE at the end of the source electrode SE on the source pad SP side.

  In the example shown in the drawing, the source electrode SE overlaps at least a part of the gate electrode GE adjacent to the source electrode SE in plan view. Specifically, the recess SRE is located in a region overlapping the source electrode SE in plan view. The gate electrode GE is located on both sides of the recess SRE in the second direction (x direction). In this case, the source electrode SE includes these gate electrodes GE inside in the width direction (x direction). In this case, the portion of the source electrode SE that covers the gate electrode GE functions as a field plate. Thereby, the electric field concentration at the gate electrode GE can be relaxed.

  In the example shown in this figure, the distance between the centers of the gate electrode GE and the drain electrode DE is larger than the distance between the centers of the gate electrode GE and the source electrode SE. Thereby, in each transistor TR, the distance between the gate and the drain becomes larger than the distance between the gate and the source. As a result, the breakdown voltage between the gate and the drain can be increased.

  FIG. 25 is an enlarged view of a region surrounded by a broken line α in FIG. 24, and corresponds to FIG. 4 of the first embodiment. As shown in this figure, also in this embodiment, as in the first embodiment (FIG. 4), the side surface (side surface RDS) facing the drain pad DP in the recess DRE is in the first direction (y direction). As seen, it enters the drain pad DP. Furthermore, as described above, at least a part of the gate electrode GE overlaps the source electrode SE in plan view. In the example shown in this figure, the tip of the gate electrode GE is positioned on the drain pad DP side in the first direction (y direction) as compared to the tip of the source electrode SE.

  FIG. 26 is an enlarged view of a region surrounded by a broken line β in FIG. 24, and corresponds to FIG. 5 of the first embodiment. In the example shown in this drawing, the side surface RSS of the recess SRE does not reach the side surface SSF of the source pad SP when viewed in the first direction (y direction), and does not enter the source pad SP. Specifically, the gate wiring GL is located on the drain pad DP side as compared with the source pad SP in plan view. Accordingly, the recess SRE is located on the drain pad DP side as compared with the side surface SSF of the source pad SP.

  Also in this embodiment, the same effect as the first embodiment can be obtained. Specifically, as shown in FIG. 24, the width of the source electrode SE is wider than the width of the drain electrode DE. Thereby, current concentration from the source pad SP to the source electrode SE can be reduced. For this reason, even if the side surface RSS of the recess SRE enters the inside of the source electrode SE in the first direction (y direction) (FIG. 26), the electromigration resistance of the source electrode SE can be increased.

  As described above, in this embodiment, it is not necessary to locate the recess SRE at the end of the source electrode SE on the source pad SP side (FIGS. 24 and 26). In this case, even if the position where the recess SRE is actually formed is shifted to the drain pad DP side in the first direction (y direction) as compared with the design, the electromigration resistance of the source electrode SE can be increased. it can.

  Specifically, in order to increase the electromigration resistance of the source electrode SE in the layout of the first embodiment (FIG. 1), the recess SRE needs to enter the source pad SP in plan view. In this case, if the position where the recess SRE is actually formed is shifted to the drain pad DP side in the first direction (y direction) as compared with the design, the source electrode SE may not be able to obtain the desired electromigration resistance. There is sex. On the other hand, in this embodiment, such a situation is prevented from occurring.

(Modification)
FIG. 27 is a diagram showing a modification of FIG. As shown in the figure, a plurality of recesses DRE may be arranged along the drain electrode DE. Similarly, a plurality of recesses SRE may be arranged along the source electrode SE. In other words, the recess DRE may not extend along the drain electrode DE. Similarly, the recess SRE may not extend along the source electrode SE. In the example shown in the figure, the planar shape of the recess REC (the recess DRE and the recess SRE) is a rectangle. However, the planar shape of the recess REC is not limited to the example shown in this figure.

  In the example shown in this figure, in the drain electrode DE and the source electrode SE adjacent to each other, the centers of the recesses DRE and the recesses SRE are alternately arranged in the first direction (y direction). However, the planar layout of the recess DRE and the recess SRE is not limited to the example shown in this figure. For example, in the drain electrode DE and the source electrode SE that are adjacent to each other, the recess DRE and the recess SRE may have the same planar shape, and the centers may be aligned in the first direction (y direction).

  FIG. 28 is an enlarged view of a region surrounded by a broken line α in FIG. 27, and corresponds to FIG. 4 of the first embodiment. In the example shown in this figure, one recess DRE on the drain pad DP side enters the drain pad DP in plan view. Specifically, the recess DRE has a side surface (side surface RDS) facing the drain pad DP. The side surface RDS enters the drain pad DP in the first direction (y direction). However, the side surface RDS may not enter the drain pad DP. For example, the side surface RDS may only reach the side surface DSF of the drain pad DP in the first direction (y direction).

  FIG. 29 is an enlarged view of a region surrounded by a broken line β in FIG. 27, and corresponds to FIG. 5 of the first embodiment. In the example shown in this figure, one recess SRE on the source pad SP side enters the source pad SP in plan view. Specifically, the recess SRE has a side surface (side surface RSS) facing the source pad SP. The side surface RSS enters the source pad SP in the first direction (y direction). However, the side surface RSS may not enter the source pad SP. For example, the side surface RSS may only reach the side surface SSF of the source pad SP in the first direction (y direction).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BM Barrier metal film BM1 Metal film BUF Buffer layer CL Cap layer DBM Barrier metal film DE Drain electrode DP Drain pad DRE Recess DSF Side surface GE Gate electrode GE1 Conductive film GI Gate insulating film GI1 Insulating film GL Gate wiring GP Gate pad GRE Recess ILD Interlayer Insulating film MF Metal film NSL Nitride semiconductor layer NSL1 First nitride semiconductor layer NSL2 Second nitride semiconductor layer PIL Protective insulating layer RDS Side surface REC Recessed portion RSS Side surface SBM Barrier metal film SD Semiconductor device SE Source electrode SMS Semiconductor substrate SP Source pad SRE Recessed SSF Side TR Transistor

Claims (12)

Semiconductor devices including:
A nitride semiconductor layer;
A gate electrode located on the nitride semiconductor layer and extending along the first direction in plan view;
An interlayer insulating film located on the gate electrode and the nitride semiconductor layer;
A source pad located on the interlayer insulating film and extending along a second direction orthogonal to the first direction in plan view;
A drain pad located on the interlayer insulating film and extending along the second direction in plan view, the drain pad being spaced apart from the source pad;
A source electrode extending along the first direction in plan view and connected to the source pad; and a drain electrode extending along the first direction in plan view and connected to the drain pad;
Here, the interlayer insulating film has a first recess extending along the first direction in plan view.
Here, the first recess extends in the source electrode and the source pad in a plan view.
Here, the source electrode and a part of the source pad are connected to the nitride semiconductor layer through the first recess.
Here, the source electrode and the source pad are formed on the interlayer insulating film via a first barrier metal film. The semiconductor device according to claim 1,
Here, the interlayer insulating film has a second recess extending along the first direction in plan view.
Here, the second recess extends in the drain electrode and the drain pad in a plan view.
Here, the drain electrode and a part of the drain pad are connected to the nitride semiconductor layer through the second recess. The semiconductor device according to claim 1,
Here, the drain electrode and the drain pad are formed on the interlayer insulating film via a second barrier metal film. The semiconductor device according to claim 1,
Here, the first barrier metal film includes a titanium film. The semiconductor device according to claim 3,
Here, the second barrier metal film includes a titanium film. The semiconductor device according to claim 1,
Here, the first recess is located in a region overlapping the source electrode and the source pad in plan view. The semiconductor device according to claim 2,
Here, the second recess is located in a region overlapping the drain electrode and the drain pad in plan view. The semiconductor device according to claim 1,
Here, the source electrode is integrated with the source pad. The semiconductor device according to claim 1,
Here, the drain electrode is integrated with the drain pad. The semiconductor device according to claim 1,
Here, the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device according to claim 1,
Here, the first recess is formed in the interlayer insulating film, and the bottom of the first recess reaches the nitride semiconductor layer.
Here, at least a part of the source electrode and the source pad is embedded in the first recess. The semiconductor device according to claim 2,
Here, the second recess is formed in the interlayer insulating film, and the bottom of the second recess reaches the nitride semiconductor layer.
Here, at least a part of the drain electrode and the drain pad is embedded in the second recess.

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