JPH08255766A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent shortcircuiting between a gate and a diffusion layer caused by creeping up of a silicide layer during heat treatment. CONSTITUTION: In a first process of Fig. (a), a poly-Si layer 3 and an offset film 4 are laminated on a surface of an Si board 1 one by one and the lamination body is patterned to a gate 5. In a second process of Fig. (b), a sidewall 7 formed of an insulation material different from the offset film 4 in etching velocity is formed on the side wall part of the gate 5. In a third process of Fig. (c), an S/D diffusion layer 8 is formed on the Si board 1 and in a fourth process of Fig. (d), the offset film 4 is removed. In a fifth process of Fig. (e), after a layer 9 of high melting point metal is formed, a silicide layer 10 is formed by silicide reaction between each of the Si board 1 in a position of the S/D diffusion layer 8 and the poly-Si layer 3 and the layer 9 [Fig. (f)]. The layer 9 of high melting point metal not subjected to salicide reaction is removed in the sixth process, Fig. (g).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device applied to a salicide process.

[0002]

2. Description of the Related Art One of the important processes for achieving miniaturization of semiconductor devices is on the gate and source / drain (hereinafter, referred to as
There is a so-called salicide process of forming a silicide on the diffusion layer in a self-aligned manner (referred to as S / D).

In the conventional salicide process, first, referring to FIG.
As shown in (a), on a silicon (Si) substrate 50,
Gate oxide film 51 and polysilicon (Poly-Si) layer 52
A gate 53 is formed by sequentially stacking and. After this,
Depositing a silicon oxide on the Si substrate 50 in the state of covering the gate 53 (SiO ₂₎ (not shown), followed by SiO ₂ on the side wall of the gate 53 by an etch-back by RIE
A sidewall 54 made of is formed. Then, the S / D diffusion layers 55 are formed on both sides of the sidewall 54 of the Si substrate 50 by the ion implantation method.

Next, as shown in FIG. 3B, Poly-Si
A titanium (Ti) layer 57 is formed on the Si substrate 50 in a state of covering the surface of the layer 52 and the sidewalls 54, and then a first heat treatment (annealing treatment) is performed. As a result, the Poly-Si layer 52, the Ti layer 57, the S / D diffusion layer 5
The Si substrate 50 and the Ti layer 57 at the 5th position are silicidized to each other, and the poly-Si layer 52, that is, the gate 5 is formed.
3 and the S / D diffusion layer 55 on the titanium silicide (Ti
A salicide layer 58 made of Si ₂ ) is formed.

Then, as shown in FIG. 3C, the Ti layer 57 on the surface of the sidewall 54 is selectively etched and removed, and a second heat treatment is performed to perform salicide layer 5 removal.
8 to lower the resistance. After that, a usual process such as formation of an interlayer insulating film (not shown) is performed.

[0006]

However, in the above-described method for manufacturing a semiconductor device, during the heat treatment for the silicidation reaction, it is formed on the surface of the sidewall 54 as shown by the arrow in FIG. 4 (a). A phenomenon called so-called creeping up of the salicide layer 58 occurs in which the Ti layer 57 absorbs Si of the Poly-Si layer 52 and Si of the Si substrate 50 to form the salicide layer 58 on the surface of the sidewall 54.

Si at the position of the gate 53 and the S / D diffusion layer 55
Since the substrate 50 is separated from the outer surface of the sidewall 54 by a short distance, and when such creeping occurs, the salicide layer on the Si substrate 50 is formed as shown in FIG. 4B. 58 and the salicide layer 58 on the Poly-Si layer 52 are continuous, and the Ti layer 57 after that.
In the etching process, the continuous salicide layer 58 remains without being removed, and the Poly-Si layer is not removed during operation of the semiconductor device.
The layer 52 and the S / D diffusion layer 55 may be short-circuited. The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device capable of preventing a short circuit between a gate and a diffusion layer due to creeping up of a salicide layer during heat treatment. There is.

[0008]

In the method of manufacturing a semiconductor device according to the present invention, first, in a first step, a silicon-based material layer and an offset film are sequentially laminated on the surface of a substrate made of a silicon-based material, and then this lamination is performed. Pattern the body into a gate. Next, in a second step, a layer of an insulating material having a different etching rate from the offset film is formed on the substrate so as to cover the gate, and then a sidewall made of the above insulating material is formed on the side wall of the gate by etching. Subsequently, in a third step, source / drain diffusion layers are formed at positions on both sides of the side wall of the substrate, and the offset film is removed by etching in a fourth step. In the fifth step, after forming a refractory metal layer or refractory metal compound layer on the substrate at the source / drain diffusion layer position in a state of covering the sidewall surface and the silicon-based material layer, the source / drain is formed. The silicidation reaction is performed between the substrate at the position of the diffusion layer and the silicon-based material layer and the layer of the refractory metal or the layer of the refractory metal compound. Then, in a sixth step, the layer of the refractory metal or the layer of the refractory metal compound which has not undergone the silicidation reaction in the fifth step is removed to obtain a semiconductor device.

According to this method, when forming the layer of the refractory metal or the layer of the refractory metal compound, the bulge which is made of the refractory metal or the refractory metal compound and bulges outward at the upper end of the sidewall. It is preferable to form a part.

[0010]

In the present invention, since the gate is raised by forming the offset film on the silicon-based material layer, the sidewall is formed higher than the silicon-based material layer on the side wall of the gate. Moreover, in order to remove the offset film,
The surface area of the sidewall is increased as compared with the conventional case. That is, the distance from the silicon-based material layer to the substrate at the diffusion layer position becomes longer because the height of the sidewall is increased and the height of the portion where the offset film is removed is added. Therefore, even if a creeping phenomenon of the formed salicide layer occurs when heat treatment for silicidizing the substrate and the silicon-based material layer with the refractory metal layer occurs,
The salicide layer on the substrate and the salicide layer on the silicon-based material layer are prevented from being continuous with each other.

Further, if a bulging portion made of a high melting point metal or a high melting point metal compound and bulging outward and having a large volume of the high melting point metal or the high melting point metal compound is formed at the upper end portion of the sidewall, even if the sidewall is formed, Even if the refractory metal layer formed in the offset film removed portion of the device absorbs a large amount of silicon in the silicon-based material layer, this silicon reacts with the refractory metal or refractory metal compound in the bulge and is consumed. . Therefore, the creeping up of the salicide layer is stopped by the bulging portion.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. 1A to 1G are explanatory views showing an embodiment of the present invention in the order of steps. Here, a silicon (Si) substrate is used as a substrate in the present invention. First, in the first step shown in FIG. 1A, the gate oxide film 2 is formed on the surface of the silicon substrate 1 by the thermal oxidation method.

Then, by a CVD method, a polysilicon (Poly-Si) layer 3 to be a silicon-based material layer of the present invention and a phosphosilicate glass (PSG) are formed on the Si substrate 1 via the gate oxide film 2. And the offset film 4 to be sequentially laminated. At this time, the film thickness of the Poly-Si layer 3 is 10
The thickness of the offset film 4 is set to about 200 nm.

Next, after forming a resist pattern (not shown) on the offset film 4, the offset film 4 and the Poly- film are formed by etching using the resist pattern as a mask.
The Si layer 3 is formed in the pattern of the gate 5. Then, the LDD (Lightly-Dope) is formed on the Si substrate 1 by the ion implantation method.
d Drain) The diffusion layer 6 is formed.

Next, in a second step, S is performed by a CVD method with a layer (not shown) made of an insulating material covering the gate 5.
It is formed on the i substrate 1. Here, as the layer made of the insulating material, the etching rate (3%) of the offset film 4 in wet etching using diluted hydrofluoric acid described later is used.
A silicon oxide (SiO ₂ ) layer (etching rate: 10 nm / min) having an etching rate different from 0 nm / min) is formed. Next, as shown in FIG. 1B, a sidewall 7 made of SiO ₂ and having a height of about 300 to 400 nm is formed on the sidewall of the gate 5 by etching back by RIE.

Next, in the third step shown in FIG. 1C, the sidewall 7 on the Si substrate 1 is formed by ion implantation.
Source / drain (hereinafter referred to as S / D) diffusion layers 8 are formed on both sides of the. At this time, the Si substrate 1
Ions are not implanted into the portion immediately below the side wall 7 of the above, so that the portion finally becomes the LDD diffusion layer 6.
Subsequently, in a fourth step shown in FIG. 1D, the offset film 4 is selectively removed by wet etching using diluted hydrofluoric acid.

Then, in the fifth step shown in FIG. 1 (e),
The Si substrate 1 is covered with the surface of the side wall 7 and the top of the Poly-Si layer 3 by the CVD method or the sputtering method.
A refractory metal layer 9 made of, for example, titanium (Ti) is formed thereon. At the same time, a bulging portion 9a made of Ti is formed at the upper end of the sidewall 7 so as to bulge outward. Examples of respective conditions when the refractory metal layer 9 and the bulging portion 9a are formed by the sputtering method and the CVD method are shown below.

Sputtering method: Sputtering gas: Argon (Ar) gas Gas flow rate: 0.4 Pa Sputtering power: 5 kW Si substrate temperature: 200 ° C. CVD method; Reaction gas: TiCl ₄ / H ₂ / Ar gas flow rate: TiCl ₄ / H ₂ / Ar = 3/10
0 / 170sccm Microwave power: 2.8kW Si substrate temperature: 460 ° C

Then, a heat treatment (annealing treatment) is performed at 650 ° C. for about 30 seconds in a nitrogen atmosphere, and as shown in FIG. 1 (f), the Si substrate 1 at the position of the S / D diffusion layer 7, Poly-S.
Each of the i layers 3 and the refractory metal layer 9 are silicidized. As a result, titanium silicide (Ti) is formed on the Poly-Si layer 3, that is, on the gate 5 and on the S / D diffusion layer 8.
The salicide layer 10 made of Si ₂ ) is formed.

Then, in a sixth step shown in FIG. 1 (g), ammonia-hydrogen peroxide mixture (NH ₃ : H ₂ O ₂ : H ₂ O = 1: 2:
By wet etching using 7), the refractory metal layer 9 on the surface of the side wall 7 which has not undergone the silicidation reaction is selectively removed, and then in a nitrogen atmosphere at 800 ° C.
The salicide layer 10 is annealed for about 30 seconds.
To lower the resistance.

In the method of manufacturing a semiconductor device described above, the Poly
Since the gate 5 is raised by forming the offset film 4 on the -Si layer 3, the sidewall 7 is formed higher than the Poly-Si layer 3 on the side wall of the gate 5. Moreover, since the offset film 4 is selectively removed, the surface area of the sidewall 7 increases. That is, as shown in the enlarged view of the main part of FIG. 2, the distance from the Poly-Si layer 3 to the Si substrate 1 at the position of the S / D diffusion layer 8 is higher in the sidewall 7 than in the conventional example shown in FIG. In addition, the height of the rising portion a from which the offset film 4 is removed is further added to increase the length.

Therefore, the salicide layer 10 formed when the heat treatment for siliciding the Si substrate 1 and the Poly-Si layer 3 with the refractory metal layer 9 is performed.
Even if the creeping phenomenon occurs, the salicide layer 10 on the Si substrate 1 and the salicide layer 10 on the Poly-Si layer 3 are prevented from being continuous with each other. Therefore, after the step of removing the unreacted refractory metal layer 9 on the surface of the sidewall 7 by etching, the salicide layer 10 on the Si substrate 1 is removed.
Since the salicide layer 10 on the Poly-Si layer 3 is completely separated, the Poly-Si layer 3 at the time of operating the semiconductor device.
And the S / D diffusion layer 8 are prevented from being short-circuited.

Since the refractory metal layer 9 formed on the sidewall 7 is formed particularly thin at the rising portion a of the sidewall 7, the refractory metal layer 9 at the rising portion a is the Poly-Si layer 3. Si absorbed from
Therefore, the degree of creeping up of the salicide layer 10 is small. Further, since the bulging portion 9a having a large volume of Ti is formed at the upper end portion of the sidewall 7, even if the refractory metal layer 9 at the rising portion a absorbs a large amount of Si of the Poly-Si layer 3, this Si Is consumed by reacting with Ti in the bulging portion 9a. Therefore, the creeping up of the salicide layer 10 is stopped by the bulging portion 9a.

Therefore, according to this embodiment, the Si substrate 1
Since the salicide layer 10 on the upper side and the salicide layer 10 on the Poly-Si layer 3 are prevented from continuing due to the creeping up, the gate 5 and the S 5 at the time of operation of the semiconductor device are prevented.
Since a short circuit with the / D diffusion layer 8 can be surely prevented, a fine semiconductor device having high electrical performance can be manufactured.

In the above embodiments, the case where the refractory metal of the present invention is made of Ti has been described, but other refractory metals can be used. Further, instead of the refractory metal, a refractory metal compound such as Ti _x N _y can be used, and in this case, the same effect as that of the above embodiment can be obtained.

In the above embodiment, the offset film of the present invention is made of PSG and the sidewall is made of Si.
The case of O _{2 has} been described, but the combination is not limited to this combination as long as the etching rate of the sidewall is different from that of the offset film, that is, the etching selection ratio between the offset film and the sidewall can be obtained. For example, the offset film is PSG, the sidewall is silicon nitride (Si
N) and the offset film is formed of SiO.
_{2. The} sidewall can be formed of SiN.
Further, although the offset film 4 is removed by wet etching in the above-mentioned embodiment, it may be removed by dry etching if the offset film 4 is selectively removed.

[0027]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the sidewall higher than the silicon-based material layer is formed on the side wall of the gate, and the offset film is removed to remove the source from the silicon-based material layer. The distance to the substrate at the drain diffusion layer position is made longer by adding the height of the portion where the offset film is removed to the height of the sidewall. Therefore, even if the formed salicide layer creeps up during the heat treatment for the silicidation reaction, the salicide layer on the substrate and the salicide layer on the silicon-based material layer are prevented from being continuous with each other. Therefore, it is possible to obtain a semiconductor device in which a short circuit between the gate and the source / drain diffusion layer does not occur.

Further, when a bulging portion having a large volume made of a refractory metal or a refractory metal compound is formed at the upper end portion of the sidewall, the refractory metal layer formed at the offset film removed portion of the sidewall is not formed. Even if a large amount of silicon in the silicon-based material layer is absorbed, this silicon reacts with the refractory metal or refractory metal compound in the bulging portion and is consumed, so the creeping up of the salicide layer can be reliably performed in the bulging portion. Can be stopped. Therefore, according to the present invention, a fine semiconductor device having high electrical performance can be manufactured.

[Brief description of drawings]

1A to 1G are explanatory views showing an embodiment of the present invention in the order of steps.

FIG. 2 is an enlarged view of an essential part showing a crawled state of a salicide layer.

3A to 3C are explanatory views showing a conventional salicide process in the order of steps.

FIG. 4 is a diagram illustrating a creeping phenomenon of a salicide layer.

[Explanation of symbols]

1 Si Substrate (Base) 3 Poly-Si Layer (Silicon Material Layer) 4 Offset Film 5 Gate 7 Sidewall 8 S / D Diffusion Layer 9 Refractory Metal Layer 9a Swelling Part 10 Salicide Layer

Claims (2)

[Claims] 1. A first step of sequentially stacking a silicon-based material layer and an offset film on a surface of a substrate made of a silicon-based material, and then patterning the stacked body into a gate, wherein the offset film has a different etching rate. A second step of forming a layer of a different insulating material on the base so as to cover the gate, and then forming a sidewall made of the insulating material on a side wall portion of the gate by etching; and both sides of the side wall of the base. Third step of forming source / drain diffusion layers at respective positions, fourth step of removing the offset film by etching, and the source / drain diffusion in a state of covering the sidewall surface and the silicon-based material layer. After forming a layer of refractory metal or a layer of refractory metal compound on the substrate at the layer position, the source / drain A fifth step of performing a silicidation reaction between the substrate at the scattered layer position, the silicon-based material layer, and the layer of the high-melting point metal or the layer of the high-melting point metal compound, and a high step that does not cause the silicidation reaction in the fifth step. And a sixth step of removing the layer of the melting point metal or the layer of the refractory metal compound. 2. When the layer of refractory metal or the layer of refractory metal compound is formed, the sidewall is made of the refractory metal or refractory metal compound and bulges outward. The method of manufacturing a semiconductor device according to claim 1, wherein the bulge portion is formed.