JP2002124043A - Phase-modulated decode clock generating circuit, phase inversion detecting circuit, phase inversion pattern detecting circuit, decode circuit, and phase-modulated signal reproducing device for recording medium having phase-modulated signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase-modulated decode clock generating circuit which can be easily integrated in a simple configuration of a digital circuit. SOLUTION: As shown in Figure 2, a signal waveform (g) which dulles the waveform of a phase inversion part is binarized as a 'zero level' threshold, and a phase-modulated decode clock is generated on the basis of the binarized signal (h). A phase inversion signal decode clock (k) obtained as a logical add of a pulse string corresponding to the rising and falling of the binarized signal (i) and a phase inversion detected pulse (j) which is a pulse generator operating only when the binarized signal is in a H level (E in Figure 2) and which is generated when its length is between the one period length (A in Figure 2) and the half period length of a wobble signal in which the H level length of the binarized signal is not phase-inversed, is generated. Accordingly, a PLL circuit required conventionally is unnecessary, and a simple phase-modulated decode clock generating circuit can be easily integrated in a small size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk medium for recording and reproducing digital information, and more particularly to a rewritable medium, and more particularly to a decoding circuit configuration for a phase modulation signal proposed in + RW4.7 GB standard. The present invention relates to a phase modulation decode clock generation circuit, a phase inversion detection circuit, a phase inversion pattern detection circuit, a decoding circuit, and an apparatus for reproducing a phase modulation signal of a recording medium equipped with a phase modulation signal.

[0002]

2. Description of the Related Art In recent years, DVD-ROMs, DVD-Rs, DVD-RAMs, and the like have attracted attention as large-capacity optical disk media. In order to increase the storage capacity, increasingly smaller pitches and smaller pits, an L / G format in which both land portions / groove portions are used as information tracks, and multi-layered information surfaces of optical disks are being studied. .
Under such circumstances, +
RW (4.7 GB).

In this medium, CD ± R / R
Like W and DVD-RW, meandering (wobble) grooves are formed along the tracks, and block addresses are written in advance. However, unlike the other media, the address writing method is formed by a wobble phase inversion pattern.

For example, Japanese Patent Application Laid-Open No. 10-069646 discloses a conventional technique that multiplies a phase-modulated wobble signal by a signal obtained by delaying the wobble signal and demodulates data from a low-pass filter output of the multiplied signal. "Optical disk medium and optical disk apparatus" disclosed in the official gazette
There is.

According to the above-mentioned "optical disk medium and optical disk apparatus", the phase of the wobble signal is inverted only in response to the occurrence of "1" which is one of the two predetermined values of the address information. For a phase modulation in which the phase of the wobble signal is not inverted even when "0" occurs, a delay circuit for delaying the wobble signal by a predetermined time and a multiplication circuit for multiplying the undelayed wobble signal by the delay signal A decoder circuit configuration including a low-pass filter for smoothing a multiplication signal is shown.

FIG. 11 shows an example of a wobble phase modulation signal pattern. For example, (a) shows SYNC
(Synchronization) pattern, (b) a pattern corresponding to bit data "0", (c) a pattern corresponding to bit data "1", and so on.

In an optical disk, these patterns are arranged in a tracking groove in a meandering (wobble) manner and are arranged discretely at a certain period in synchronization with a sector forming area to form a block address.

When recording or reproducing user data from or to this optical disk, a phase modulation signal corresponding to the wobble groove obtained from the return light is taken out while tracking the reproduction light in the meandering guide groove, and the phase inversion is detected. And read out the preset address information from this,
Write or read user data to or from an arbitrary address.

As a phase inversion detection method using such phase modulation, there is a decoding method as shown in FIG. In FIG. 12, a sine wave (b) synchronized with a normal wobble phase is generated, multiplied by a wobble signal (a) (with phase inverted data superimposed thereon) (c), and the multiplied signal waveform is integrated for each wobble cycle. (D) and sample and hold (e). By processing the phase inversion signal in this way, phase inversion can be detected. This makes it possible to decode and reproduce the phase-modulated data.

[0010]

However, according to the method described above, there is a problem that many analog circuits such as a PLL circuit, a sine wave generation circuit, a multiplication circuit, an integration circuit, and a sample hold circuit are required. There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has a simple digital circuit configuration and does not require a conventionally required "PLL circuit" for generating a decode clock. A first object is to provide a phase modulation detection clock generation circuit for a phase modulation signal which is easy to integrate, and to provide a phase modulation decode clock generation circuit.

Also, the present invention has a simple digital circuit configuration, eliminates the need for a conventionally required "PLL circuit" for generating a decode clock, and facilitates integration of phase modulation of a plurality of carrier frequencies. A second object is to provide a phase inversion detection clock generation circuit that can generate a phase inversion detection clock for a signal, and to provide a phase modulation decode clock generation circuit.

Further, the present invention has a simple digital circuit configuration, eliminates the need for a conventionally required "PLL circuit" for generating a decode clock, and provides a continuously changing carrier frequency which is easy to integrate. Or a phase inversion detection clock generation circuit that adaptively generates a phase inversion detection clock in a wide carrier frequency region for a phase modulation signal having a carrier frequency fluctuation and a phase modulation decode clock generation circuit And a third purpose.

Further, the present invention has a simple digital circuit configuration, eliminates the need for a sine wave generation circuit, a multiplication circuit, an integration circuit, and a sample and hold circuit, which are required in the past, is easy to integrate, and provides a phase modulation signal. It is a fourth object of the present invention to provide a phase inversion detection circuit that can flexibly adapt to changes and variations in carrier frequency.

Further, the present invention uses a phase inversion detection circuit which is digitally formed and can flexibly adapt to changes and fluctuations in the carrier frequency of a phase modulation signal. It is a fifth object of the present invention to perform good phase inversion pattern detection with respect to the above) and fluctuations (fluctuations in carrier frequency due to uneven rotation of the disk).

The present invention further provides a digital circuit,
It is a sixth object of the present invention to provide a phase modulation signal pattern detection circuit that is integrated and miniaturized, and to achieve a good reproduction operation of a phase modulation signal reproduced from a recording medium and to reduce the power consumption of the reproduction apparatus.

However, the main object of the present invention is to decode the address information and the like formed by the discrete arrangement of the phase inversion patterns as shown in FIG. The present invention can be similarly applied to a phase modulation method as described in the above.

[0018]

According to a first aspect of the present invention, there is provided a decode clock generating circuit for generating a decode clock for detecting a phase inversion of a phase-modulated wobble signal waveform. The decode clock receives a phase-modulated wobble signal waveform, a band-pass filter circuit, a binarization circuit for binarizing an output from the band-pass filter circuit, and a binarization circuit output from the binarization circuit. Clock pulses corresponding to the rising and falling positions of the binarized signal, and the positive (H) of the binarized signal
Is formed by a phase inversion detection pulse that is generated when the length of the portion is one half to one cycle of the wobble cycle.

According to a second aspect of the present invention, in the first aspect of the present invention, the phase modulation decode clock generation circuit is capable of arbitrarily setting a generation count position of a phase inversion detection pulse.

The invention according to claim 3 is the invention according to claim 1 or 2
In the invention described above, the phase modulation decode clock generation circuit sets the generation count value of the phase change detection pulse based on the average period of the binary signal of the wobble signal waveform.

According to a fourth aspect of the present invention, there is provided a decode clock generating circuit according to any one of the first to third aspects, a band-pass filter circuit for inputting a phase-modulated wobble signal waveform, and an output from the band-pass filter. , And a binarization signal output from the binarization circuit is latched and decoded clock generation circuit sequentially converts the binary
A shift register circuit for shifting the digitized data by one clock, a first latch circuit for latching the binary signal at the rising edge of the output signal of the shift register, a first inverting circuit for inverting the shift register output, A second inverting circuit for inverting the binarized signal at the rise of the inverting circuit output signal from the first inverting circuit, and a second inverting circuit for latching the inverted binarized signal output from the second inverting circuit. And an OR circuit that generates a logical sum signal of the latch signal of the binary signal and the inverted binary signal latch signal.

According to a fifth aspect of the present invention, there is provided the phase modulation decode clock generating circuit according to any one of the first to third aspects and the phase inversion detection circuit according to the fourth aspect, wherein the phase inversion detection signal is stored in a shift register. The shift register is set to detect a match between "1" and "0" patterns on the shift register.

According to a sixth aspect of the present invention, there is provided a phase inversion pattern detecting circuit according to the fifth aspect.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a phase modulation decode clock generation circuit, a phase inversion detection circuit, a phase inversion pattern detection circuit, a decoding circuit and a phase modulation signal according to an embodiment of the present invention will be described with reference to the accompanying drawings. A device for reproducing a phase modulation signal of a recording medium will be described in detail.

The phase modulation signal as shown in FIG.
Usually, the frequency band required to reproduce such a signal waveform is limited, that is, the inverted portion is made to look like the phase modulation signal waveform shown in FIG. 1 by passing through a BPF (the inverted signal level position is set to the signal level of the signal level). (Moving far from the average value (0 level)).

In the present invention, as shown in FIG. 2, the signal waveform (g) obtained by blunting the waveform of the phase inversion section is binarized by setting "0 level" as a threshold value (h). The phase modulation decode clock generation circuit according to the embodiment of the present invention is generated based on the binary signal (h). A pulse generator (i) corresponding to the rise and fall of the binarized signal and a pulse generator that operates only when the binarized signal is at H level (region E in FIG. 2). Of the phase inversion detection pulse (j) generated when the H level length of the wobble signal has a length from one half cycle length or more to one cycle length (range A in FIG. 2) of the phase-inverted wobble signal. A phase inverted signal decode clock (k) obtained as a sum is generated.

The generation of the phase inversion detection pulse is performed by counting the counter value (X) preset at the head of the H level of the binary signal.
Count up or down according to
Outputting a pulse when the count value reaches a predetermined value is easily configured using a counter circuit.

FIG. 3 shows a configuration example of the phase inversion signal decode clock generation circuit. The phase inversion can occur on the plus side and the minus side of the “0 level” as can be seen from the signal waveform of FIG. Therefore, in FIG. 3, the phase inversion detection pulse generation circuits 33 and 35 for the inversion signal of the binary signal are added to detect the phase inversion occurring on the minus side.

The present invention also relates to the above-described phase inversion detection pulse generation circuit, and stores the phase inversion detection pulse generation count value (X) in an external device (such as a system controller).
Can be set arbitrarily. Although the configuration is omitted, it is preferable to prepare a register for storing the count value (X) and configure the register to be a preset value of the counter.

Further, the present invention relates to the above-described phase inversion detection pulse generation circuit, wherein the value of the phase inversion detection pulse generation count value (X) is adaptively determined from the average period length of the wobble obtained from the binarized signal. To be generated. FIG. 4 shows an example of the configuration.

In FIG. 4, the wobble counter 41 is
The binary signal is counted by a predetermined number, and when the predetermined number is reached, a signal is output. The required time at this time is used as a counter value operated by a clock (CLK) having a frequency sufficiently higher than the wobble period, and the value is latched. Set to 43. Thereafter, the value of the counter 42 is preset, and this operation is continuously repeated. (The counter preset signal is omitted.)

The ROM circuit 44 previously stores a phase inversion detection pulse generation count value for generating a phase inversion detection pulse in the area A in FIG. 2 according to the latched count value at this time. Therefore, even if the frequency of the wobble signal changes or changes, the phase inversion detection pulse generation count value (X) can be generated in the area A.

The value of X is approximately 0.7 with respect to a normal wobble cycle (wobble cycle without phase inversion).
It is better to set it for five periods. By setting in this way, it is possible to make the configuration strong against the jitter component of the signal. Further, it is preferable that the count number of the wobble counter is set to a value large enough to prevent the influence of the binary signal of the phase inversion unit from appearing. Also, it is preferable to set a value smaller than the period of the fluctuation of the carrier frequency (the fluctuation corresponding to the rotation period of the disk in the case of reproducing the optical disk medium). By doing so, a phase inversion detection pulse generation that is not affected by the rotation fluctuation is tried, and as a result, a favorable phase modulation pattern detection operation can be achieved.

The present invention also relates to a circuit configuration for detecting a phase inversion from a phase modulation signal using a phase inversion signal decode clock generation circuit configured using the above-described phase inversion detection clock generation circuit. FIGS. 5 and 6 show examples of the phase inversion detection circuit, and FIGS. 8 to 10 show the state of each signal of the phase inversion detection circuit with respect to the phase modulation signal shown in FIG. The operation of the phase inversion detection circuit shown in FIG. 5 will be described with reference to the signals in FIGS.

8 to 10 correspond to signals at the same position of the phase inversion detection circuit. The signal is the signal waveform of the phase modulated signal after passing through the BPF.
The digitized signal is the phase inverted signal decode clock (DCLK) described in claims 1 to 3. In the drawing, a bold clock corresponds to a phase inversion detection pulse. Is a shift register (1 clock shift) output using DCLK as a shift clock for the binarized signal obtained in. At the rise of the output signal of the one-clock shift register, the binary signal () is latched by a latch circuit, whereby the phase inversion on the plus side of the phase inversion wobble signal is detected as a plus side phase inversion detection signal shown in FIG. You. Regarding the phase inversion detection on the minus side, the inverted binary signal () obtained by inverting the binary signal ()
Similarly, at the rising edge of the output () of the shift register (1 clock shift) using DCLK as the shift clock, the inverted binary signal () is latched in the latch circuit, thereby the phase on the minus side of the phase inverted wobble signal is latched. The inversion is detected as a minus side phase inversion detection signal shown in FIG. By generating a logical sum signal of the plus side and minus side phase inversion detection signals, a phase inversion detection signal () is obtained.

The phase inversion detection circuit shown in FIG. 6 converts the output signal of one clock shift register on the minus side into the signal on the plus side.
The configuration is obtained by inverting the output signal of the clock shift register. Other operations are the same as those in FIG.

Further, the present invention, as shown in FIG.
The above-mentioned phase inversion detection signal () is sequentially shifted and stored in the shift register 71 using the above-mentioned phase inversion signal decode clock (DCLK), and the data sequence (for example, the phase inversion data sequence shown in FIGS. 8 to 10) The pattern detection circuit 72 detects the phase modulation pattern.

Further, according to the present invention, it is possible to demodulate address information and the like formed in advance by phase modulation using bit information and the like obtained by the above-described phase modulation pattern detection method. The phase modulation pattern detection circuit and the decoding circuit for address information and the like can all be implemented as digital circuits, and have a small power-saving device configuration.

As a reproducing apparatus, a decoder for a phase modulation signal, a drive for reproducing an optical disk medium loaded with phase modulated data, an optical disk medium loaded with phase modulated data or a glass membrane disk in the manufacturing process thereof, and evaluation of various stampers There are devices, and these devices can be mounted on them to form a small power-saving device.

[0040]

As is apparent from the above description, according to the first aspect of the present invention, a "PLL circuit" for generating a decode clock conventionally required with a simple digital circuit configuration is provided. Since this is unnecessary, it is possible to provide a phase modulation decode clock generation circuit which can be easily integrated in a small size.

According to the second aspect of the present invention, in the first aspect of the present invention, since the phase inversion detection pulse generation position can be set arbitrarily, the same circuit can be used for phase modulation signals having different carrier frequencies. A phase modulation decode clock generation circuit can be provided.

According to the third aspect of the present invention, in the first or second aspect of the present invention, the generation position of the phase shift detection pulse is changed adaptively with respect to a change in carrier frequency or a change in carrier frequency. Therefore, it is possible to provide a good phase modulation decode clock over a wide range of the carrier frequency and also with respect to the fluctuation of the carrier frequency.

According to the fourth aspect of the present invention, many analog circuits such as a "PLL circuit, a sine wave generating circuit, a multiplying circuit, an integrating circuit, and a sample-and-hold circuit" which have conventionally been required with a simple digital circuit structure. Since a circuit is not required, a phase inversion detection circuit that can be easily integrated in a small size can be provided.

According to the fifth aspect of the present invention, the first to fifth aspects are provided.
4. A phase modulation decode clock generation circuit according to claim 3,
Used with the described phase inversion detection circuit, it is possible to detect the phase modulation pattern with a simple digitalized configuration,
It is possible to provide a phase modulation pattern detection circuit that can be easily integrated in a small size.

According to a sixth aspect of the present invention, there is provided a decoding circuit equipped with the phase modulation pattern detection circuit according to the fifth aspect of the present invention, which is compactly integrated, and an apparatus for reproducing a phase modulation signal of a recording medium having a phase modulation signal. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing a phase modulation waveform after passing through a bandpass filter.

FIG. 2 is a diagram showing a phase inversion signal decode clock.

FIG. 3 is a block diagram showing a configuration of a phase shift signal decode clock generation circuit.

FIG. 4 is a block diagram illustrating a configuration of a phase inversion detection clock generation circuit.

FIG. 5 is a block diagram illustrating a first configuration example of a phase inversion detection circuit.

FIG. 6 is a block diagram showing a second configuration example of the phase inversion detection circuit.

FIG. 7 is a block diagram illustrating a configuration of a phase modulation pattern detection circuit.

FIG. 8 is a diagram illustrating an example of SYNC detection.

FIG. 9 is a diagram illustrating an example of detection of bit 0;

FIG. 10 is a diagram illustrating an example of detection of bit 1;

FIG. 11 is a diagram illustrating an example of a phase modulation pattern.

FIG. 12 is a diagram for explaining conventional phase inversion detection.

[Explanation of symbols]

 31 NOT circuit 32, 34 Rising pulse 33, 35 Phase inversion detection pulse 36 OR circuit 41 Walb counter 42 Counter 43 Latch circuit 44 ROM 51 BPF (bandpass filter) 52 Binarization circuit 53 DCLK generation circuit 54, 57 T ( Shift register) 55, 58 latch circuit 56 NOT circuit 59 OR circuit 61 BPF (bandpass filter) 62 binarization circuit 63 DCLK generation circuit 64 T (shift register) 65, 68 latch circuit 66, 67 NOT circuit 69 OR circuit

Claims (6)

[Claims] 1. A phase modulation decode clock generation circuit for generating a decode clock for detecting a phase inversion of a phase-modulated wobble signal waveform, wherein the decode clock is a band for inputting the phase-modulated wobble signal waveform. A pass filter circuit, a binarization circuit for binarizing an output from the band pass filter circuit, a clock pulse corresponding to a rising and falling position of the binarization signal output from the binarization circuit, A phase modulation decode clock generation circuit, which is formed by a phase inversion detection pulse generated when a positive (H) portion of the binary signal has a length from one half to one cycle of a wobble cycle. . 2. The phase modulation decode clock generation circuit according to claim 1, wherein said phase modulation decode clock generation circuit can arbitrarily set a generation count position of said phase inversion detection pulse. 3. The phase modulation decode clock generation circuit sets an occurrence count value of the phase shift detection pulse based on an average period of a binarized signal of a wobble signal waveform. A phase modulation decode clock generation circuit as described in the above. 4. The decode clock generation circuit according to claim 1, a band-pass filter circuit for inputting the phase-modulated wobble signal waveform, and a binary output from the band-pass filter. A shift register circuit that latches a binarized signal output from the binarization circuit and sequentially shifts the binarized data by one clock by the decode clock generation circuit; A first latch circuit that latches the binary signal at a rising edge of a register output signal, a first inverting circuit that inverts the shift register output, and a rising edge of an inverted circuit output signal from the first inverting circuit A second inverting circuit for inverting the binarized signal, and latching an inverted binarized signal which is an output of the inverting circuit from the second inverting circuit. Phase inversion detecting circuit and having a second latch circuit, and a OR circuit that generates a logical sum signal of the latch signal of the binary signal and the inverted binary signal latch signal. 5. The phase inversion detection signal is set in the shift register, using the phase modulation decode clock generation circuit according to claim 1 and the phase inversion detection circuit according to claim 4. "1" on the shift register
A phase inversion pattern detection circuit for detecting coincidence of a "0" pattern. 6. A phase modulation signal reproducing apparatus for a recording medium on which a decoding circuit and a phase modulation signal are mounted, wherein the phase inversion pattern detection circuit according to claim 5 is mounted.