JP2006134394A - Address information detection circuit for optical disk drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable address information detection circuit for an optical disk drive device, capable of quickly and accurately reproducing the address information of ADIP employed by a DVD+RW system. <P>SOLUTION: When phase demodulation is carried out for a reproduced wobbling signal WBLIN read from a DVD+RW, for the reproduce wobbling signal, the numbers of times of detecting ADIP zero bit patterns and ADIP one bit patterns are counted. Based on these counting results, threshold values THD1 and THD2 supplied to comparators 314 and 316, and the clock phase of a clock signal PLLCK supplied to an SR F/F322 are controlled to assure detection of the phase inversion part of the reproduced wobbling signal. Thus, stable address information reproduction is realized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an address information detection circuit of an optical disk drive device for recording data on a DVD + RW (Digital Versatile Disc + ReWritable) optical disk.

  In an information recording medium such as an optical disk, a magneto-optical disk, or a magnetic disk, it is used to control the rotation of the information recording medium such as address information and a synchronization signal or wobbling signal necessary for position search when recording the recording information of the image information. Pre-information including rotation control information to be used is recorded in advance. A CD-R (CD-Recordable), which is an optical disk having a recording capacity comparable to that of a compact disk (CD), is known as a recording medium on which recording information based on this pre-information can be additionally recorded.

  In this CD-R, an information track (groove track or land track) on which recording information is recorded in advance at the pre-format stage at the time of manufacture is waved at a frequency with respect to a signal obtained by previously modulating the pre-information to be recorded by FM (Frequency Modulation). Pre-information is recorded by wobbling the mold. When recording information on a conventional CD-R, the wobbling frequency of the wobbling track is detected, and a reference clock for controlling the rotation of the CD-R is extracted based on the detected wobbling frequency. To do. Further, it generates a drive signal for controlling the rotation of the spindle motor that rotates the CD-R based on the extracted reference clock, and also generates a recording clock signal that includes timing information synchronized with the rotation of the CD-R. is doing.

  Further, in CD-R, the address information indicating the address on the CD-R necessary for recording the record information should be recorded based on the reproduced pre-information by reproducing the pre-information when recording the record information. The position is detected, and the record information is recorded at the detected position.

  On the other hand, in recent years, a high-density recording medium such as a DVD (Digital Versatile Disk) whose recording density has been dramatically improved as compared with a conventional CD has been put into practical use. Among various high-density recording media represented by DVD, in DVD-R (DVD-Recordable) and DVD + RW (DVD + Rewritable), which are recordable recording media, an information track (for example, a groove track) is used as a reference clock. Wobbling at a frequency based on

  In particular, in DVD + RW optical discs, address information called ADIP (Address in Pre-groove) may be preformatted on a recording medium in advance. When data is recorded on the DVD + RW, the preformatted ADIP is reproduced to grasp the address information, and the data is written from an appropriate address position using the address information. The ADIP address information performs the same function as address information called ATIP (Absolute Time in Pre-groove) in a CD-R / RW optical disc.

  However, the ADIP modulation scheme and physical format are completely different from those of ATIP. Therefore, the ATIP modulation scheme and the circuit corresponding to the modulation scheme cannot be directly used in the ADIP reproduction process. In particular, recently, there is a demand for the construction of a mechanism for quickly and accurately reproducing ADIP address information in the DVD + RW format.

  For example, Patent Document 1 below discloses a technique for providing a highly reliable reproduction circuit for the above-described ADIP address information. According to the technique disclosed in Patent Document 1, bit synchronization in ADIP performed by a WBL counter that detects a bit pattern and counts wobble, and word synchronization of ADIP that is performed by detection of a word synchronization pattern and a word counter, respectively. When the bit synchronization pattern is detected independently and continuously detected at a predetermined time interval, window detection using only a predetermined timing as a window is performed. Hereinafter, the address information detection circuit of the optical disk drive disclosed in Patent Document 1 will be described.

  FIG. 15 shows an information recording / reproducing apparatus 60 described in Patent Document 1. As will be described later, also in the present invention, the information recording / reproducing apparatus 60 shown in FIG. 15 can be used.

  In the information recording apparatus 60 shown in FIG. 15, light emitted from a light source 61 such as a semiconductor laser is transmitted on a DVD + RW 67 by a coupling lens 62, a beam splitter 63, a quarter wavelength plate 64, and an objective lens 65 in an optical system 66. Focused on the recording surface. The reflected light from the recording surface on the DVD + RW 67 returns to the optical system 66 again, passes through the beam splitter 63, is condensed on the light receiving element 69 by the condenser lens 68, and is converted into an electric signal.

  The output of the light receiving element 69 is usually converted from current to voltage by the I / V amplifier 70 and various calculations are performed. Normally, the light receiving element 69 and the I / V amplifier 70 are divided into a plurality of parts, and a focus error signal indicating the distance between the media surface and the light spot focus, a track on the recording surface on the DVD + RW 67 and the light spot. Calculations such as a track error signal indicating the position and the RF signal for detecting information recorded on the recording surface of the DVD + RW disc 67 are performed. In FIG. 15, the focus error signal and the track error signal are calculated by the servo circuit 71, and the mechanism system 72 is driven from the position data to move the light spot to the target position. Further, information on the recording surface of the DVD + RW disc 67 is calculated into an RF signal by the reproduction circuit 73 and sent to signal processing (not shown) in the subsequent stage.

  Note that the phase modulation signal can be obtained from the reproduction signal. This phase modulation signal has a different detection method depending on the division shape of the light receiving element 69. The simplest detection method is a push which is one of the track error signals obtained from the difference between the left and right of the light receiving element dividing line along the track. There is a method of detecting from the pull signal. In this case, for example, the demodulation circuit 75 can operate based on the push-pull signal output from the servo circuit 71. The demodulating circuit 75 outputs data obtained by demodulating the wobbling signal WBLIN input via the servo circuit 71.

  On the other hand, FIG. 16 shows an example of the structure of a DVD + RW disc 67. A DVD + RW disc 67 shown in FIG. 16 is a dye-type DVD + RW disc provided with the dye film 5. On the surface of the DVD + RW disc 67, a groove track 2 as an information track and a land track 3 forming an adjacent track for guiding the light beam B of a laser beam as reproduction light or recording light to the groove track 2 are formed. Has been.

  Further, the DVD + RW disc 67 includes a gold vapor deposition surface 6 for reflecting the light beam B when reproducing recorded information, and a protective film 7 for protecting the groove track 2, land track 3, and dye film 5. It has.

  In such a configuration, when recording image information other than pre-information and rotation control information on the DVD + RW disc 67, the information recording / reproducing device 60 detects rotation control information by detecting wobbling of the groove track 2. Obtaining and controlling the rotation of the DVD + RW disc 67 at a predetermined rotational speed, and obtaining pre-information. The information recording / reproducing apparatus 60 sets the optimum output of the light beam B as recording light based on the pre-information acquired in this way, and addresses information related to the position on the DVD + RW disc 67 where information is to be recorded. Etc., and information is recorded at the corresponding recording position based on the acquired address information.

  Further, the information recording / reproducing apparatus 60 irradiates the light beam B so that the center of the light beam B coincides with the center of the groove track 2 at the time of information recording, and records information bits corresponding to the recording information on the groove track 2. Recording information is formed by forming. At this time, the size of the light spot SP is set so that a part thereof is irradiated not only on the groove track 2 but also on the land track 3.

  The information recording / reproducing apparatus 60 detects the wobbling signal from the groove track 2 using the reflected light of the light spot SP irradiated to the land track 3 and the groove track 2, and acquires the clock signal for rotation control.

  Further, the ADIP format and modulation rules used in the DVD + RW disc 67 will be described with reference to FIGS. As shown in FIG. 17, in ADIP, the standard defines that a total of 93 wobbles of 8 wobble ADIP units and 85 wobble monotone wobbles (85 monotone wobbles) are represented as “1 ADIP bit”. Yes.

Further, as shown in FIGS. 18 (1) to (3), there are three patterns of ADIP bits in the 8-wobble ADIP unit. That is, the ADIP unit indicates “ADIP word sync” (see FIG. 18 (1)) indicating the break of the ADIP word, “ADIP zero bit” (refer to FIG. 18 (2)) indicating ADIP = 0, and ADIP = 1. There are three patterns of “ADIP one bit” (see FIG. 18 (3)). Further, as shown in FIG. 19, the ADIP word is represented by a total of 52 bits of these ADIP bits. Also, as shown in FIG. 20, bits 0 to 23 are address information.
Japanese Patent Laying-Open No. 2003-85749 (FIGS. 1 and 4) JP 2001-176069 A (FIG. 6)

  As described above, the ADIP address information reproduction process cannot use the conventional circuit for performing the ATIP address information reproduction process as it is, and a technique related to a new reproduction process for ADIP address information. Is required. Moreover, the ADIP address information is important information indicating the address position of the recorded information, and needs to be reproduced quickly and accurately.

  In view of the above problems, the present invention provides a highly reliable optical disc drive capable of quickly and accurately reproducing ADIP address information employed in the DVD + RW system using a technique different from the conventional technique. An object of the present invention is to provide an address information detection circuit for a device.

In order to achieve the above object, according to the present invention, data recording is performed on an optical disc on which a data recording track is formed by wobbling address information and a frequency pattern obtained by phase-modulating a bit pattern for synchronization according to a predetermined rule. And in the address information detection circuit of the optical disk drive device that performs reproduction,
A phase demodulation circuit for phase demodulating the wobbling component of the data recording track extracted from the optical disc;
From the phase demodulation result in the phase demodulation circuit, a bit pattern detection circuit for detecting the bit pattern;
A counter that counts the number of the bit patterns detected in a predetermined period by the bit pattern detection circuit;
A comparator used for detection of a phase inversion unit of a signal related to the wobbling component in the phase demodulating circuit based on a count result by the counter;
A control circuit for controlling a threshold value of the comparator;
An address information detection circuit for an optical disc drive apparatus is provided.

  Further, in addition to the above invention, the control circuit may be configured to provide a flip-flop that latches the detection result of the phase inversion unit of the signal related to the wobbling component in the phase demodulation circuit based on the count result of the counter. An address information detection circuit for an optical disk drive device configured to control a phase relationship between a signal input supplied from the comparator and a clock signal used as a timing reference for the flip-flop to latch the signal input. Is provided.

  The address information detection circuit in the optical disc drive apparatus according to the present invention has the above-described configuration, and has the effect that ADIP address information employed in the DVD + RW system can be reproduced quickly and accurately. Have. In addition, the address information detection circuit in the optical disc drive apparatus according to the present invention particularly includes a threshold value used when binarizing a value related to the input reproduction wobbling signal WBLIN and a clock signal for sampling the binarized signal. The function of always optimizing the phase of an image is realized by a simple circuit, and it has the effect of being able to stably acquire ADIP address information even when a disc with a poor reproduction state is reproduced. .

  Hereinafter, first to third embodiments of the present invention will be described with reference to the drawings. In the present invention, the mechanism for reading the wobbling signal (reproduction wobbling signal) WBLIN from the DVD + RW can use the information recording / reproducing apparatus shown in FIG. The present invention has a novel feature in, for example, an address information detection circuit for acquiring address information from a reproduction wobbling signal WBLIN, which can be arranged in the demodulation circuit 75 shown in FIG.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 4 is a diagram showing an example of an address information detection circuit for reproducing address information from the phase-modulated reproduction wobbling signal WBLIN according to the first embodiment of the present invention. It is a figure which shows an example of PM (Phase Modulation: phase modulation) demodulation circuit which demodulates an ADIP signal from the phase-modulated wobbling signal WBLIN in the first embodiment. The PM demodulation circuit 12 shown in FIG. 1 corresponds to the PM demodulation circuit 12 of the address information detection circuit 10 shown in FIG.

  First, the reproduction wobbling signal WBLIN read from the DVD + RW is supplied to the PM demodulation circuit 12 of the address information detection circuit 10. In the PM demodulation circuit 12 of FIG. 1, the supplied reproduction wobbling signal WBLIN is applied to the first terminal of the capacitor 302. On the other hand, the second terminal of the capacitor 302 is connected to the first terminal of the inductor 304 and the first terminal of the inductor 306. The second terminal of the inductor 304 is connected to GND. In addition, the second terminal of the inductor 306 is connected to the first terminal of the resistor 308, the second terminal of the resistor 308 is connected to the first terminal of the capacitor 310, and the second terminal of the capacitor 310 is Connected to GND. With this configuration, the analog signal SIGA is output from the second terminal of the resistor 308 in accordance with the reproduction wobbling signal WBLIN applied to the first terminal of the capacitor 302.

  On the other hand, the second terminal of the resistor 308 is connected to each of the non-inverting input of the comparator 312, the non-inverting input of the comparator 314, and the inverting input of the comparator 316. The inverting input of the comparator 312 is connected to GND, and the comparator 312 outputs a binary digital signal CMPOUT1 indicating that the analog signal SIGA has a positive value. The digital signal CMPOUT1 is connected to an input terminal of a PLL (Phase Locked Loop) circuit 318.

  The output THD1 of the first D / A converter (first DAC) 324 is connected to the inverting input of the comparator 314, and the output of the second D / A converter (second DAC) 326 is connected to the non-inverting input of the comparator 316. THD2 is connected. The first D / A converter 324 and the second D / A converter 326 are supplied with data from the control circuit (the control circuit 102 shown in FIG. 4), respectively, and the first D / A converter 324 and the second D / A converter 326 are supplied. From each of the converters 326, outputs THD1 and THD2 corresponding to the supplied data are output. As a result, the comparison results between the analog signal SIGA and the threshold values THD1 and THD2 are output from the comparators 314 and 316 as binary digital signals CMPOUT2 and CMPOUT3, respectively.

  The output of the PLL circuit 318 is connected to the input of the phase shift circuit 320. Note that the phase shift amount of the phase shift circuit 320 changes according to data from the control circuit 102. The output signal PLLCK of the phase shift circuit 320 is connected to a clock terminal of an SR F / F (set / reset flip-flop) 322. On the other hand, the output signal CMPOUT2 of the comparator 314 is connected to the R input of the SR F / F 322, and the output signal CMPOUT3 of the comparator 316 is connected to the S input of the SR F / F 322. The output signal from the SR F / F 322 is PMOUT is output. Note that the values of the capacitors 302 and 310, the inductors 304 and 306, and the resistor 308 minimize the low frequency and high frequency noise, and the values of the capacitor 310, the inductor 306, and the resistor 308 have a natural frequency slightly lower than the wobble frequency. It is desirable to be selected to have.

  Here, with reference to FIG. 2, signals of respective parts in FIG. 1 are schematically shown. FIG. 2 schematically shows signals WBLIN, SIGA, CMPOUT1, CMPOUT3, CMPOUT2, PLLCK, and PMOUT of each part in the PM demodulation circuit 12 of FIG. With respect to the reproduction wobbling signal WBLIN shown in FIG. 2, the waveform of the analog signal SIGA is as shown in FIG. Strictly speaking, a delay occurs, but here it is assumed that there is no delay for simplicity. Further, since the comparator 312 compares the analog signal SIGA with the GND level, the output signal CMPOUT1 becomes binary data indicating the positive value of the analog signal SIGA. Further, since the comparator 316 compares the analog signal SIGA with the output level THD2 of the second D / A converter 326, the output signal CMPOUT3 becomes binary data indicating that the analog signal SIGA is equal to or less than the threshold value THD2. Further, since the comparator 314 compares the analog signal SIGA with the output level THD1 of the first D / A converter 324, the output signal CMPOUT2 becomes binary data indicating that the analog signal SIGA is equal to or higher than the threshold value THD1.

  Further, the phase of the clock signal supplied from the PLL circuit 318 is controlled by the data from the control circuit 102 so that the output signal PLLCK of the phase shift circuit 320 is appropriate for the signals CMPOUT3 and CMPOUT2 as shown in FIG. This is a phase signal. Further, the SR F / F 322 outputs the output data “1” and holds “1” therein if the S input (signal CMPOUT3) is “1” at the rising edge of the input clock signal PLLCK. If the input (signal CMPOUT2) is “1”, output data “0” is output and “0” is held internally. As a result, the output signal PMOUT becomes “1” during the phase inversion period of the reproduction wobbling signal WBLIN and becomes “0” otherwise.

  Next, the address information detection circuit 10 that reproduces the ADIP signal according to the ADIP format from the PM demodulation result in the PM demodulation circuit 12 of FIG. 1 will be described with reference to FIG. As described above, the signals PMOUT and PLLCK are output from the PM demodulation circuit 12 shown in FIG. The signal PLLCK is supplied to each unit as a clock signal for the address information detection circuit 10 (not shown). On the other hand, the signal PMOUT is input to the shift register 104 and the second counter 118.

  The shift register 104 sequentially takes in the signal PMOUT by the clock signal PLLCK, and holds, for example, the latest 10 clocks while shifting. The data for 10 clocks is supplied to each of the word sync detection circuit 106, the zero bit detection circuit 108, and the one bit detection circuit 110 as parallel data.

  The word sync detection circuit 106 performs pattern matching of “0111100000”. This corresponds to the ADIP word sync shown in (1) of FIG. The word sync detection circuit 106 outputs “1” if the patterns match, and “0” otherwise. An output from the word sync detection circuit 106 is supplied to the synchronization protection circuit 112.

  Further, the zero bit detection circuit 108 performs pattern collation of “0100000110”. This corresponds to the ADIP zero bit shown in (2) of FIG. Then, “1” is output when the patterns match, and “0” is output in other cases. The output from the zero bit detection circuit 108 is supplied to the synchronization protection circuit 112 and the first counter 116.

  Further, the one-bit detection circuit 110 performs pattern collation of “0100011000”. This corresponds to the ADIP one bit shown in (3) of FIG. Then, “1” is output when the patterns match, and “0” is output in other cases. An output from the one-bit detection circuit 110 is supplied to the synchronization protection circuit 112 and the first counter 116.

  The synchronization protection circuit 112 performs ADIP bit synchronization detection / protection and ADIP word synchronization detection / protection based on the inputs from the word sync detection circuit 106, the zero bit detection circuit 108, and the one bit detection circuit 110, thereby providing an ADIP word. And the ADIP word is output to the error correction circuit 114 in the subsequent stage together with the ADIP word synchronization timing signal.

  As described with reference to FIGS. 17 to 20, the 1 · ADIP bit is composed of 93 wobbles. Therefore, if the reproduction state is good, the signal input from any one of the word sync detection circuit 106, the zero bit detection circuit 108, and the one bit detection circuit 110 becomes “1” every 93 clocks. On the other hand, when the reproduction state is not good, “1” at the position where it should be may disappear, or “1” may appear at a position where it should not exist. The synchronization protection circuit 112 has a built-in counter (not shown) that counts 93 clocks (1 · ADIP bits), and performs bit synchronization protection by a well-known method. Specifically, for example, when “1” is supplied every 93 clocks in succession three times, the inertial operation state is entered, and the input of “1” at a place other than the inertia position is ignored, and the inertia position is set. Even when “1” is not input, a method of outputting a dummy ADIP bit signal is considered as if “1” was input at that position.

  As described with reference to FIGS. 17 to 20, one ADIP word is composed of 52 · ADIP bits, and a word sync is arranged at the head thereof. Therefore, if the reproduction state is good, the signal input from the word sync detection circuit 106 becomes “1” every 93 × 52 clocks. On the other hand, when the reproduction state is not good, “1” at the position where it should be may disappear, or “1” may appear at a position where it should not exist. The synchronization protection circuit 112 has a built-in counter (not shown) for counting 52 · ADIP bits, and performs word bit synchronization protection by a well-known method. Specifically, for example, when “1” is supplied every 93 × 52 clocks in succession three times, the inertial operation state is entered, the input of “1” in places other than the inertia position is ignored, Even when “1” is not input at a position, a method of outputting a dummy ADIP word synchronization timing signal is considered as if “1” was input at that position.

  As the error correction circuit 114, for example, a conventional error correction circuit as disclosed in Patent Document 2 above may be used.

  Next, a threshold value using the first counter 116 that counts the outputs from the zero-bit detection circuit 108 and the one-bit detection circuit 110 and the second counter 118 that counts the output from the PM demodulation circuit 12, which are features of the present invention. And timing control will be described.

  The first counter 116 shown in FIG. 4 is a counter that counts up when the output from the zero bit detection circuit 108 is “1” or the output from the one bit detection circuit is “1”. Further, the count value of the first counter 116 is cleared by a reset signal reset from the control circuit 102.

  On the other hand, the second counter 118 is a counter that counts up when the output signal PMOUT from the PM demodulation circuit 12 is “1”. Also for the second counter, the count value is cleared by the reset signal reset from the control circuit 102.

  Next, signals of the respective units in FIG. 4 and counter values of the first counter 116 and the second counter 118 will be described with reference to FIG. 3 shows a clock signal PLLCK output from the PM demodulation circuit 12 in the address information detection circuit 10 of FIG. 4, a reset signal reset output from the control circuit 102, an output signal PMOUT from the PM demodulation circuit 12, and one-bit detection. An output signal from the circuit 110 and counter values of the first counter 116 and the second counter 118 are schematically shown. The first counter 116 is cleared by the reset signal reset, and counts up when the output of the one-bit detection circuit 110 is “1”. The second counter 118 is cleared by the reset signal reset, and counts up when the output signal PMOUT from the PM demodulation circuit 12 is “1”.

  The control circuit 102 sets a predetermined initial value for the first D / A converter 324 of the PM demodulation circuit 12 shown in FIG. Further, a value obtained by multiplying the initial value by −1 is set for the second D / A converter 326. As a result, the outputs of the first D / A converter 324 and the second D / A converter 326 become threshold values THD1 and THD2, respectively. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116 and the second counter 118, and then the value of the first counter 116 and the second counter at an appropriate timing (for example, after 9300 clocks). Take 118 values and save them.

  Next, the control circuit 102 sets a value obtained by adding a predetermined value to a predetermined initial value for the first D / A converter 324 of the PM demodulation circuit 12. Further, a value obtained by multiplying that value by −1 is set for the second D / A converter 326. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116 and the second counter 118, and thereafter, the value of the first counter 116 and the second counter at an appropriate timing (for example, after 9300 clocks). Take 118 values and save them.

By repeating the above operation a plurality of times, the control circuit 102 measures the correspondence relationship between the values of the threshold value THD1 and the threshold value THD2, the count value of the first counter 116, and the count value of the second counter 118. 5 and 6 show an example of the measurement result. When the threshold value THD1 is A to G, the count value of the first counter 116 and the count value of the second counter 118 are, for example,
THD1 first counter 116 second counter 118
A 0 580
B 1 450
C 93 400
D 95 340
E 94 310
F 50 260
G 5 140
It becomes.

  The control circuit 102 examines the measurement result, and the count value of the first counter 116 is larger than that before and after the threshold value THD1 is C to E, and the count value of the second counter 118 is the threshold value. When THD1 is C to E, the case of E is the smallest, and even in that case, it is grasped that there are 300 or more, and as a result, the value of E is selected as the threshold value THD1. This is because 100 ADIP bits are included in 9300 clocks, and when the reproduction state is good, if the threshold values THD1, THD2 are ideal values, the value of the first counter is 98, The reason is that the value of the second counter is considered to be 302. Although the value of E is selected as the threshold value THD1 here, the present invention is not limited to this, and other values (for example, the value of D) may be selected as the threshold value THD1.

  Further, as can be seen from FIG. 2, from the relationship between the analog signal SIGA and the threshold values THD1 and THD2, if the absolute values of the threshold values THD1 and THD2 are too large, the phase inversion part of the reproduction wobbling signal WBLIN cannot be detected. , "1" of signal CMPOUT3 or signal CMPOUT2 is not output. In such a case, the SR F / F 322 is not set and reset, and the PMOUT signal output from the SR F / F 322 is also “0”, and acquisition of address information is not performed correctly. In addition, when the absolute values of the threshold THD1 and the threshold THD2 are too small, the threshold THD1 and the threshold THD2 are exceeded in other than the phase inversion unit, and “1” of the signal CMPOUT3 and the signal CMPOUT2 is output in other than the phase inversion unit, The SR F / F 322 is set and reset. As a result, the signal PMOUT is set to “1” at an irregular place, and the pattern “0100000110” or “0100011000” appears at an irregular position, resulting in disturbing bit synchronization. From the above, the threshold values THD1 and THD2 need to be set appropriately.

  Next, the control circuit 102 sets a predetermined initial value for the phase shift circuit 320 of the PM demodulation circuit 12 shown in FIG. The phase shift circuit 320 delays the output clock of the PLL circuit 318 by a value corresponding to the initial value and outputs it as a clock signal PLLCK. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116, and then captures and stores the value of the first counter 116 at an appropriate timing (for example, after 9300 clocks). Next, the control circuit 102 sets a value obtained by adding a predetermined value to a predetermined initial value in the phase shift circuit 320. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116, and then captures and stores the value of the first counter 116 at an appropriate timing (for example, after 9300 clocks).

By repeating the above operation a plurality of times, the control circuit 102 measures the correspondence relationship between the phase shift amount and the count value of the first counter 116. FIG. 7 shows an example of the measurement result. The count value of the first counter 116 when the amount of phase shift is J to P is, for example,
Phase shift amount first counter 116
J 45
K 71
L 95
M 95
N 94
O 75
P 35
It becomes.

  The control circuit 102 examines the measurement result, and the count value of the first counter 116 is larger in the case where the phase shift amount is L to N than in other cases, and in each case where the phase shift amount is L to N. Therefore, the value of M, which is the central value of L to N, is selected as the phase shift amount. Here, the value of M is selected as the phase shift amount, but the present invention is not limited to this, and other values (for example, the value of N) may be selected as the phase shift amount.

  As shown in FIGS. 1 and 2, the signal PMOUT is an output of the SR F / F 322, and the SR F / F 322 is output from each of the comparator 314 and the comparator 316 using the rising edge of the clock signal PLLCK. Set or reset the signals CMPOUT2 and CMPOUT3. Therefore, the rising timing of the clock signal PLLCK with respect to the signals CMPOUT2 and CMPOUT3 needs to be set appropriately.

  Further, the control circuit 102 increases or decreases the absolute values of the threshold THD1 and the threshold THD2 in small increments once the values of the threshold THD1 and the threshold THD2 are determined, and as a result, the zero bit detection circuit 108 and the one bit detection circuit It is measured whether the count value related to the output signal from each of 110 increases or decreases compared to before. As a result, if the count value increases, it is desirable to update the threshold values THD1 and THD2 at that time as new threshold values. Note that the control circuit 102 can be realized by a microcomputer having a built-in program for executing the above-described processing.

  In the first embodiment of the present invention, the threshold value THD1, the threshold value THD2, and the phase shift amount of the phase shift circuit 320 are determined by using the value of the second counter 118 together with the value of the first counter 116. For example, the threshold value THD1, the threshold value THD2, and the phase shift amount of the phase shift circuit 320 are determined using only the count value of the first counter 116 without using the count value of the second counter 118. You may do it. In this case, as the threshold value THD1, it is desirable to use a threshold value (the value of D in the example of FIG. 5) that maximizes the value of the first counter 116.

  In the first embodiment of the present invention, the phase shift circuit 320 is an independent circuit, but an offset amount of a phase comparator (not shown) in the PLL circuit 318 is adjusted and output from the PLL circuit 318. The phase of the clock to be adjusted may be adjusted. In this case, the offset amount of the phase comparator in the PLL circuit 318 is supplied from the control circuit 102 to the PLL circuit 318 instead of the control amount of the phase shift circuit 320.

  As described above, according to the first embodiment of the present invention, the threshold value used when binarizing the value related to the input reproduction wobbling signal WBLIN and the binarized signal are sampled. A function that allows the phase of the clock signal to be always optimized can be realized with a simple circuit, and ADIP address information can be stably acquired even during reproduction of a disk having a poor reproduction state. It becomes possible.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 8 is a transition diagram showing the operation of the state holding circuit in the synchronization protection circuit according to the second embodiment of the present invention, and FIG. 9 shows the output from the PM demodulation circuit according to the second embodiment of the present invention. Clock signal PLLCK, output signal from zero bit detection circuit or one bit detection circuit, inertia counter of state holding circuit in synchronization protection circuit, reset signal reset output from control circuit, output signal PMOUT from PM demodulation circuit, It is a figure which shows typically the window period produced based on the count value of an inertia counter.

  In the second embodiment of the present invention, the synchronization protection circuit 112 shown in FIG. 4 includes an ADIP bit synchronization protection state holding circuit (not shown) indicating an inertia state or a search state, and an inertia counter operating in the inertia state. (Not shown) and the ADIP bit synchronization is in the inertia state, the processing related to the count-up of the first counter 116 is limited only to the window period created using the count value of the inertia counter. Is configured to do.

  FIG. 8 schematically shows a transition state held by the state holding circuit for ADIP bit synchronization protection in the synchronization protection circuit 112 shown in FIG. The state holding circuit holds the search state in the initial state. In this search state, for example, the output “1” from the zero bit detection circuit 108 or the output “1” from the one bit detection circuit 110 is input to the synchronization protection circuit 112 three times every 93 clocks. In this case, the state holding circuit shifts to the inertia state and newly holds this inertia state. In this inertia state, when the phenomenon that the output “1” from the zero-bit detection circuit 108 or the output “1” from the one-bit detection circuit 110 is not input together within a window period to be described later, A transition is made to the search state, and this search state is newly held.

  The operation when the state holding circuit is in the inertia state will be described below. When the state holding circuit is in the inertia state, an inertia counter as shown in FIG. 9 is operated. The inertia counter counts up for each clock signal PLLCK and counts when the output “1” from the zero bit detection circuit 108 or the output “1” from the one bit detection circuit 110 is supplied to the synchronization protection circuit 112. A counter whose value is cleared to zero. Further, when the output value “1” from the zero bit detection circuit 108 or the output “1” from the one bit detection circuit 110 is not input at the time when the count value of the inertia counter is counted up to 92, the next clock signal The count value becomes 0 at PLLCK. By decoding the count value of such an inertia counter, a window period in which the count value is “1” between 91, 92, and 0 and “0” in other periods is generated. Here, the window period is between 91, 92, and 0 of the counter value of the inertia counter, but for example, only the period between 90, 91, 92, 0, 1 and 92 is set as the window period. Also good.

  When the state holding circuit is in the inertia state, the first counter 116 shown in FIG. 4 has the above window out of the output “1” from the zero bit detection circuit 108 or the output “1” from the one bit detection circuit 110. Only those that become “1” in the period are counted. The operation of each part other than this is the same as in the first embodiment described above.

  In the inertia state, the output “1” supplied from the zero bit detection circuit 108 or the one bit detection circuit 110 in a period other than the window period has a high probability of being caused by noise, and is considered to be ignored. It is done. Therefore, by allowing the first counter 116 to count up by excluding the output “1” generated due to noise, the count value of the first counter 116 becomes more reliable. As a result, the threshold value THD1 supplied from the first D / A converter 324 to the first counter 116, the threshold value THD2 supplied from the second D / A converter 326 to the second counter 118, and the phase shift amount of the output clock of the PLL circuit 318 are set. An optimum value can be obtained.

  As described above, according to the second embodiment of the present invention, in addition to the first embodiment described above, the window period is set and the zero bit detection circuit 108 and the one bit detection circuit 110 are used. By determining the timing to count the output signal, it is possible to exclude the count related to the output caused by noise, and it is possible to further improve the reliability related to the acquisition of ADIP address information It becomes.

<Third Embodiment>
Next, a third embodiment of the present invention will be described. In the third embodiment of the present invention, the PM demodulation circuit 12 of the address information detection circuit 10 shown in FIG. 4 is configured by a PM demodulation circuit 12 shown in FIG. The operation of each part excluding the control circuit 102 is the same as that in the first embodiment.

  FIG. 10 is a diagram illustrating an example of a PM demodulation circuit that demodulates an ADIP signal from a phase-modulated wobbling signal WBLIN according to the third embodiment of the present invention. First, the reproduction wobbling signal WBLIN read from the DVD + RW is supplied to the PM demodulation circuit 12 of the address information detection circuit 10. The reproduction wobbling signal WBLIN is digitized by an A / D converter (not shown) and then supplied to the PM demodulation circuit 12 shown in FIG. Note that the sampling frequency used for digitization of the reproduction wobbling signal WBLIN has a sufficiently high frequency compared to a signal PLLCK described later.

  In the PM demodulation circuit 12 of FIG. 10, the digitized reproduction wobbling signal WBLIN is applied to an input terminal of a BPF (Band Pass Filter) 402 for digital signal processing. The BPF 402 is a digital filter that uses the frequency of the supplied reproduction wobbling signal WBLIN as a passband frequency, and uses a frequency component lower than the passband frequency and a frequency component higher than the passband frequency as an attenuation band, The BPF 402 removes unnecessary noise components included in the reproduction wobbling signal WBLIN.

  On the other hand, the output terminal of the BPF 402 is connected to the input terminal of the delay circuit (DELAY) 404 and the input terminal of the Hilbert filter (HILBERT) 406. The HILBERT 406 is a digital filter that delays the phase of the input signal by 90 degrees and outputs it. The DELAY 404 takes the input signal by the group delay time of the HILBERT 406 in consideration of the group delay characteristic of the HILBERT 406. This is a digital delay circuit that outputs a delayed signal.

  The output terminal of DELAY 404 and the output terminal of HILBERT 406 are connected to the first input terminal and the second input terminal of divider (DIV) 408, respectively. The DIV 408 is a divider that calculates and outputs the division Q (t) / I (t) between the output signal I (t) of the DELAY 404 and the output signal Q (t) of the HILBERT 406.

  An output terminal of the DIV 408 is connected to an input terminal of an arctangent calculator (ARCTAN) 410, and an output terminal of the Arctan 410 is connected to a first input terminal of the phase comparator 412. The Arctan 410 performs arctan [Q (t) / I (t)] arc tangent operation on the division result Q (t) / I (t) supplied from the DIV 408 and outputs the operation result. Is an arithmetic circuit.

  The output terminal of the phase comparator 412 is connected to the input terminal of the digital signal loop filter 414 and the input terminal of the absolute value conversion circuit 416, and the signal D (t) is output. The output terminal of the loop filter 414 is connected to the input terminal of a digital signal voltage controlled oscillator (VCO) 418.

  Furthermore, the output terminal of the VCO 418 is connected to the input terminal of the binarization circuit 420 and is also connected to the second input terminal of the phase comparator 412 described above. The output terminal of the absolute value conversion circuit 416 is connected to the first input terminal of the comparator 422, and the signal ABS (t) is output. The second input terminal of the comparator 422 is connected to the control circuit 102, and the first control data THD3 is supplied from the control circuit 102. The output terminal of the comparator 422 is connected to the input terminal of a DF / F (D flip-flop) 424, and a signal CMPOUT4 is output.

  The second control data OFFSET from the control circuit 102 is connected to the offset input terminal of the binarization circuit 420, and the output terminal of the binarization circuit 420 is connected to the clock input terminal of the DF / F 424. And supply a clock signal PLLCK. The output terminal of the DF / F 424 outputs demodulated data PMOUT.

  In the PM demodulation circuit 12 shown in FIG. 10 configured as described above, the instantaneous phase of the supplied reproduction wobbling signal WBLIN is calculated by the DELAY 404, HILBERT 406, DIV 408, and ArcTAN 410 circuits. The phase comparator 412, the loop filter 414, and the VCO 418 form a PLL circuit. As a result, the VCO 418 outputs an instantaneous phase. The instantaneous phase output from the VCO 418 is binarized by the binarization circuit 420 and output as the clock signal PLLCK. The binarization circuit 420 outputs “1” in the case of 0 to 180 degrees and “0” in the case of 180 to 360 degrees among the instantaneous phase inputs 0 to 360 degrees supplied from the VCO 418. When the offset amount (second control data) OFFSET is supplied to the offset input terminal of the binarization circuit 420, the binarization circuit 420 adds the OFFSET to the instantaneous phase input (this value is 360 degrees). If it exceeds the value, the value obtained by subtracting 360 degrees is “1” when the angle is 0 to 180 degrees, and “0” is output when the angle is 180 to 360 degrees.

  The absolute value conversion circuit 416 is an arithmetic unit that converts the instantaneous phase output from the VCO 418 from the instantaneous phase output from the arctan 410 by the phase comparator 412 and converts it to an absolute value. The comparator 422 compares the input ABS (t) supplied from the absolute value circuit 416 to the first input terminal and the first control data THD3 supplied to the second input terminal, and ABS (t) ≧ “1” is output in the case of THD3, and “0” is output in other cases.

  Next, signals of each part in FIG. 10 will be described with reference to FIG. FIG. 11 schematically shows signals I (t), Q (t), D (t), ABS (t), CMPOUT4, and PLLCK in each part of FIG. In FIG. 11, the digital signal is represented by an analog signal, but is actually a sampled and quantized digital signal.

  The DELAY 404 outputs a signal I (t) obtained by delaying the reproduction wobbling signal WBLIN supplied to the PM demodulation circuit 12. On the other hand, the HILBERT 406 outputs a signal Q (t) whose phase is delayed by 90 degrees with respect to the signal I (t). That is, when the signal I (t) = A × cos (ω × t), the signal Q (t) = A × sin (ω × t). Here, A is the amplitude of the signals I (t) and Q (t), and ω is the angular frequency. Further, t = n × T (T is a sampling period).

Therefore, by performing a division operation with DIV408,
Q (t) / I (t) = A × sin (ω × t) / A × cos (ω × t) = tan (ω × t)
Is calculated. Furthermore, by performing arc tangent calculation in Arctan 410,
Arctan {tan (ω × t)} = ω × t
Thus, the instantaneous phase is calculated. The reproduction wobbling signal WBLIN is mostly in the same phase, and ADIP address information is modulated in part of the inverted phase.

  Therefore, the instantaneous phase output from the arctan 410 is the instantaneous phase of the signal having the same phase for most of the time, and the PLL circuit configured by the subsequent phase comparator 412, the loop filter 414, and the VCO 418 is locked to this phase. To do. In other words, the signal D (t) output from the phase comparator 412 in the PLL circuit is 0 for most of the time (time for signals having the same phase). On the other hand, in the phase inversion portion, as shown in FIG. 11, the signal D (t) has a non-zero value. Since this non-zero signal D (t) is difficult to handle as it is, the absolute value circuit 416 takes the absolute value and outputs it as a signal ABS (t). The signal ABS (t) is compared with the threshold value THD3 in the comparator 422 and output as the binarized signal CMPOUT4. The signal CMPOUT4 is taken into the DF / F 424 at the rising edge of the clock signal PLLCK, and the signal PMOUT is output from the DF / F 424.

  Next, the first control data THD3 and the second control data OFFSET set by the control circuit 102 will be described. Similar to the first embodiment described above, the control circuit 102 sets the first control data THD3 and the second control data OFFSET using the count value of the first counter 116 and the count value of the second counter 118. .

  The control circuit 102 sets a predetermined initial value as the first control data THD3. This is input to the second input terminal of the comparator 422 in FIG. The first control data THD3 is shown in FIG. 11 as the threshold value THD3. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116 and the second counter 118, and thereafter, the value of the first counter 116 and the second counter at an appropriate timing (for example, after 9300 clocks). Take 118 values and save them.

  Next, the control circuit 102 sets a value obtained by adding a predetermined value to a predetermined initial value as a new threshold value THD3. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116 and the second counter 118, and thereafter, the value of the first counter 116 and the second counter at an appropriate timing (for example, after 9300 clocks). Take 118 values and save them.

By repeating the above operation a plurality of times, the control circuit 102 measures the correspondence between the value of the threshold value THD3, the count value of the first counter 116, and the count value of the second counter 118. An example of the measurement result is shown in FIGS. When the threshold value THD3 is A to F, the count value of the first counter 116 and the count value of the second counter 118 are, for example,
THD1 first counter 116 second counter 118
A 15 580
B 45 500
C 98 380
D 97 370
E 92 360
F 45 210
It becomes.

  The control circuit 102 examines the measurement result, and the count value of the first counter 116 is larger than that before and after the threshold value THD3 is C to E, and the count value of the second counter 118 is the threshold value. When THD3 is C to E, the case of E is the smallest, and even in that case, it is grasped that there are 300 or more, and as a result, the value of E is selected as the threshold value THD3. This is because, like the selection of the threshold value THD1 in the first embodiment described above, 100 ADIP bits are included in 9300 clocks, and when the reproduction state is good, the value of the threshold value THD3 is ideal. It is based on the assumption that the value of the first counter is 98 and the value of the second counter is 302. Here, the value of E is selected as the threshold value THD3, but the present invention is not limited to this, and other values (for example, the value of D) may be selected as the threshold value THD3.

  As can also be seen from FIG. 11, when the absolute value of the threshold value THD3 is too large, the phase inversion part of the reproduction wobbling signal WBLIN cannot be detected, and the signal CMPOUT4 “1” is not output. In such a case, “1” of the signal CMPOUT4 is not input to the DF / F 424, and the PMOUT signal output from the DF / F 424 is also “0”. Not done correctly. When the absolute value of the threshold value THD3 is too small, the threshold value THD3 is exceeded even in a portion other than the phase inversion unit, and “1” of the signal CMPOUT4 is output in other than the phase inversion unit and “1” to the DF / F 424. Input will be made. As a result, the signal PMOUT is set to “1” at an irregular place, and the pattern “0100000110” or “0100011000” appears at an irregular position, resulting in disturbing bit synchronization. From the above, the value of the threshold value THD3 needs to be set appropriately.

  Next, the control circuit 102 sets a predetermined initial value as the second control data OFFSET. This is input to the offset input terminal of the binarization circuit 420 in FIG. As described above, the binarization circuit 420 performs binarization processing on the sum of the instantaneous phase output from the VCO 418 and the second control data OFFSET that is an offset input. Therefore, the phase of the clock signal PLLCK, which is the output of the binarization circuit 420, is changed according to the second control data OFFSET with respect to the instantaneous phase output from the VCO 418.

  Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116, and then captures and stores the value of the first counter 116 at an appropriate timing (for example, after 9300 clocks). Next, the control circuit 102 sets a value obtained by adding a predetermined value to a predetermined initial value as the second control data OFFSET. Thereafter, the control circuit 102 outputs a reset signal reset to the first counter 116, and then captures and stores the value of the first counter 116 at an appropriate timing (for example, after 9300 clocks).

By repeating the above operation a plurality of times, the control circuit 102 measures the correspondence between the value of the second control data OFFSET and the count value of the first counter 116. FIG. 14 shows an example of the measurement result. The count value of the first counter 116 when the value of the second control data OFFSET is J to O is, for example,
OFFSET first counter 116
J 50
K 75
L 97
M 95
N 78
O 55
It becomes.

  The control circuit 102 examines the measurement result, and the count value of the first counter 116 selects a value of L as the second control data OFFSET because the offset value is larger when the offset amount is L than the other cases. The DF / F 424 in FIG. 10 takes in the output signal CMPOUT4 from the comparator 422 at the rising edge of the clock signal PLLCK. At this time, as shown in FIG. 11, if the clock signal PLLCK rises at an appropriate timing with respect to the signal CMPOUT4, the signal CMPOUT4 can be stably captured and output as the signal PMOUT. Therefore, the offset input of the binarization circuit 420 needs to be corrected appropriately.

  In addition, after the control circuit 102 once determines the value of the threshold value THD3, the control circuit 102 increases or decreases the threshold value THD3 in small increments, and counts related to output signals from the zero bit detection circuit 108 and the one bit detection circuit 110, respectively. Measure whether the value increases or decreases compared to before. As a result, if the count value increases, it is desirable to update and use the threshold value THD3 at that time as a new threshold value. Note that the control circuit 102 can be realized by a microcomputer having a built-in program for executing the above-described processing.

  In the third embodiment of the present invention, the threshold value THD3 and the offset amount of the binarization circuit 420 are determined using the value of the second counter 118 together with the value of the first counter 116. However, for example, the threshold value THD3 and the offset amount of the binarization circuit 420 may be determined using only the count value of the first counter 116 without using the count value of the second counter 118. In this case, as the threshold value THD3, it is desirable to use a threshold value (the value of C in the example of FIG. 12) that maximizes the value of the first counter 116.

  As described above, according to the third embodiment of the present invention, the threshold value used when binarizing the value related to the input reproduction wobbling signal WBLIN and the binarized signal are sampled. A function that allows the phase of the clock signal to be always optimized can be realized with a simple circuit, and ADIP address information can be stably acquired even during reproduction of a disk having a poor reproduction state. It becomes possible.

  The address information detection circuit in the optical disc drive apparatus according to the present invention has the above-described configuration, and has the effect that ADIP address information employed in the DVD + RW system can be reproduced quickly and accurately. The present invention is applicable to a technique in an address information detection circuit of an optical disk drive device that records data on a DVD + RW optical disk.

It is a figure which shows an example of PM demodulation circuit which demodulates an ADIP signal from the wobbling signal WBLIN by which the phase modulation was carried out in the 1st Embodiment of this invention. It is a figure which shows typically the signal WBLIN, SIGA, CMPOUT1, CMPOUT3, CMPOUT2, PLLCK, and PMOUT of each part in the PM demodulation circuit in the 1st Embodiment of this invention. The clock signal PLLCK output from the PM demodulation circuit, the reset signal reset output from the control circuit, the output signal PMOUT from the PM demodulation circuit, the output signal from the one-bit detection circuit, the first signal output from the PM demodulation circuit in the first embodiment of the present invention It is a figure which shows typically the counter value of 1 counter and a 2nd counter. It is a figure which shows an example of the address information detection circuit for reproducing | regenerating address information from the phase-modulated reproduction | regeneration wobbling signal WBLIN in the 1st Embodiment of this invention. It is a figure which shows an example of the count value of a 1st counter in case threshold value THD1 which concerns on the 1st Embodiment of this invention is AG. It is a figure which shows an example of the count value of a 2nd counter in case threshold value THD1 which concerns on the 1st Embodiment of this invention is AG. It is a figure which shows an example of the count value of a 1st counter in case the phase shift amount which concerns on the 1st Embodiment of this invention is JP. It is a transition diagram of a state held by a state holding circuit in the synchronization protection circuit in the second embodiment of the present invention. Clock signal PLLCK output from PM demodulator circuit in second embodiment of the present invention, output signal from zero bit detection circuit or one bit detection circuit, inertia counter of state holding circuit in synchronization protection circuit, output from control circuit It is a figure which shows typically the window period produced based on the reset signal reset, the output signal PMOUT from PM demodulation circuit, and the count value of an inertia counter. It is a figure which shows an example of PM demodulation circuit which demodulates an ADIP signal from the phase-modulated wobbling signal WBLIN in the 3rd Embodiment of this invention. It is a figure which shows typically signal I (t), Q (t), D (t), ABS (t), CMPOUT4, PLLCK of each part in the PM demodulation circuit in the 3rd Embodiment of this invention. It is a figure which shows an example of the count value of a 1st counter in case threshold value THD3 which concerns on the 3rd Embodiment of this invention is AF. It is a figure which shows an example of the count value of a 2nd counter in case threshold value THD3 which concerns on the 3rd Embodiment of this invention is AF. It is a figure which shows an example of the count value of a 1st counter in case the signal OFFSET which concerns on the 3rd Embodiment of this invention is JO. It is a block diagram which shows the structural example of the information recording / reproducing apparatus common to a prior art and this invention. It is a perspective view which shows typically the structural example of DVD + RW in a prior art. It is a figure which shows the relationship between 1 * ADIP bit and a wobble in a prior art. It is a figure which shows the rule of the modulation of ADIP in a prior art, (1) is a figure which shows ADIP word sync, (2) is a figure which shows ADIP zero bit, (3) is a figure which shows ADIP one bit . It is a figure which shows the 1st structural example of the ADIP word in a prior art. It is a figure which shows the 2nd structural example of the ADIP word in a prior art.

Explanation of symbols

2 Groove Track 3 Land Track 5 Dye Film 6 Gold Deposition Surface 7 Protective Film 10 Address Information Detection Circuit 12 PM Demodulation Circuit 60 Information Recording / Reproduction Device 61 Light Source 62 Coupling Lens 63 Beam Splitter 64 1/4 Wave Plate 65 Objective Lens 66 Optical Series 67 DVD + RW
68 condensing lens 69 light receiving element 70 I / V amplifier 71 servo circuit 72 mechanical system 73 reproduction circuit 75 demodulation circuit 102 control circuit 104 shift register 106 word sync detection circuit 108 zero bit detection circuit 110 one bit detection circuit 112 synchronization protection circuit 114 error Correction circuit 116 First counter 118 Second counter 302, 310 Capacitor 304, 306 Inductor 308 Resistor 312, 314, 316 Comparator 318 PLL circuit 320 Phase shift circuit 322 SR F / F (set / reset flip-flop)
324 1st DAC (D / A converter)
326 2nd DAC (D / A converter)
402 BPF (band pass filter)
404 DELAY (delay circuit)
406 HILBERT (Hilbert filter)
408 DIV (divider)
410 Arctan (inverse tangent calculator)
412 Phase comparator 414 Loop filter 416 Absolute value circuit 418 VCO (voltage controlled oscillator)
420 Binary circuit 422 Comparator 424 DF / F (D flip-flop)

Claims (2)

In an address information detection circuit of an optical disk drive device for recording and reproducing data on an optical disk on which a data recording track is formed by wobbling address information and a frequency pattern obtained by phase-modulating a bit pattern for synchronization in accordance with a predetermined rule ,
A phase demodulation circuit for phase demodulating the wobbling component of the data recording track extracted from the optical disc;
From the phase demodulation result in the phase demodulation circuit, a bit pattern detection circuit for detecting the bit pattern;
A counter that counts the number of the bit patterns detected in a predetermined period by the bit pattern detection circuit;
A comparator used for detection of a phase inversion unit of a signal related to the wobbling component in the phase demodulating circuit based on a count result by the counter;
A control circuit for controlling a threshold value of the comparator;
An address information detection circuit of an optical disc drive apparatus having the same. A signal input supplied from the comparator to a flip-flop that latches a detection result of a phase inverting unit of a signal related to the wobbling component in the phase demodulating circuit in the phase demodulating circuit based on a count result by the counter 2. The address information detection circuit of the optical disk drive device according to claim 1, wherein the flip-flop is configured to control a phase relationship between the flip-flop and a clock signal used as a timing reference for latching the signal input.

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