JP2007095156A - Phase synchronizer, method, and, optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase synchronizer equipped with a PLL circuit capable of high speed pull-in. <P>SOLUTION: When a PLL circuit 17 is in an asynchronous state, the maximum sign inversion interval measuring instrument 18 measure the maximum value of the sign inversion interval in identifying data output by a PRML detector 16. Based on the maximum value of the sign inversion interval, a first channel frequency estimator 19 estimates the channel frequency and outputs estimated channel frequency f<SB>det_T</SB>. The PLL circuit 17 sets the center frequency at the estimated channel frequency f<SB>det_T</SB>. Then, a sync interval measuring instrument 20 measures the sync interval from the identifying data. Based on the measured sync interval, a second channel frequency estimator 21 estimates the channel frequency, outputs the estimated channel frequency f<SB>det_S</SB>, and the PLL circuit 17 sets the center frequency at the estimated channel frequency f<SB>det_S</SB>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a phase synchronization apparatus, method, and optical disc apparatus, and more specifically, a phase synchronization apparatus, method, and method for synchronizing a clock signal generated by a PLL circuit with a channel clock of a signal read from an optical disc medium or the like. The present invention relates to an optical disk device.

  In recent years, CD (Compact Disc) for music reproduction and DVD (Digital Versatile Disc) for video reproduction have become widespread as large-capacity information recording media. Recently, HD DVD (High Definition Digital Versatile Disc) and BrD (Blue Ray Disc) have appeared as next-generation optical discs capable of recording HD (High Definition) video for a long time. These optical disc recording media have a spiral recording track, and digital information (user data) such as music data and video data is recorded on the recording track as a minute recording mark row.

  The optical disk apparatus has a laser, an optical element, and an optical head equipped with a mechanism that can operate in a direction perpendicular to the disk surface (focus direction) and a radial direction (track direction). At the time of reproduction, the optical head irradiates the focused laser beam onto the information recording surface of the optical disk whose rotation is controlled by the spindle motor. At this time, the optical head detects the reflected light from the optical disc and controls the focus and tracking actuator so that the focused beam scans the recording mark row.

  The reflected light of the condensed beam irradiated to the recording mark row is detected as an electric signal by the photodetector by the brightness or the polarization. The detected reproduction signal is pulsed at the same time as a synchronous clock is extracted by a PLL (Phase Locked Loop) circuit. Thereafter, music and video information are reproduced by performing error correction processing and the like.

  The focused beam spot is finite, and the smaller the spot diameter, the higher the density of recording / reproduction is possible. Therefore, an optical approach for reducing the beam spot has been advanced. The spot diameter is inversely proportional to the NA (Natural Aperture) of the objective lens and proportional to the laser beam wavelength λ. Therefore, the spot diameter can be reduced by increasing NA and decreasing λ. However, if NA is increased, the depth of focus becomes shallow, and there is a limit because it is necessary to reduce the distance between the disk surface and the lens.

  By the way, although short wavelength lasers have problems of stability of high power transmission and long life, next generation such as infrared laser (λ = 780 nm) for CD, red laser (λ = 650 nm) for DVD, HD DVD, etc. In DVD, the blue laser (λ = 405 nm) and the shortening of the wavelength of the laser beam are gradually progressing. As the wavelength becomes shorter, the diameter of the focused beam has become smaller, but at present, the recording capacity has increased more than the wavelength ratio. This is because technology for improving detection performance has advanced.

  PRML (Partial Response Maximum Likelihood) detection is a technique for reproducing information recorded at high density. This detection method combines maximum likelihood detection with PR equalization, and detects data while performing a kind of error correction. In the maximum likelihood detection, Viterbi decoding is generally used. In PRML, a reproduction signal has a correlation in the time direction by PR equalization, and only a specific state transition appears in a data series obtained by sampling the reproduction signal. By comparing the limited state transition and the data sequence of the actual reproduction signal including noise and selecting the most probable state transition, errors in the detected data can be reduced. In particular, HD DVD is premised on such PRML detection because the reproduction amplitude of the shortest mark decreases and cannot be detected by threshold detection used in CDs and DVDs.

  Here, there are mainly two types of disc rotation control methods in the optical disc apparatus. One method is a CLV (Constant Linear Velocity) control method that keeps the linear velocity constant, and the other method is a CAV (Constant Angular Velocity) control method that makes the rotation angular velocity constant. Comparing the CLV control method with the CAV control method, the spindle rotation speed of the CLV control changes by about 2.4 times on the inner and outer circumferences, so it takes a spindle control waiting time at the time of random access. There is a problem of being consumed. On the other hand, in the CAV control method, since the spindle is rotated at a constant speed, the waiting time of the rotation speed becomes 0 and the accessibility is improved. Therefore, the number of apparatuses adopting the CAV control is increasing. However, when CAV control is performed on a disc recorded by CLV control, the linear velocity changes in proportion to the radius, so the frequency pull-in of the PPL circuit immediately after the jump becomes a bottleneck.

  The PLL circuit of the optical disk apparatus sufficiently follows the disk eccentricity, and the loop gain is kept low so that the lock is not released by noise or the like. Therefore, the capture range of the PLL circuit is narrow, and if the frequency changes greatly, such as immediately after a long seek during CAV, frequency pull-in cannot be performed. In an optical disc having a prefix header such as an optical disc or DVD-RAM, a VFO is inserted in units of several KB, and high-speed pull-in of the PLL circuit can be realized relatively easily. However, DVDs other than DVD-RAM do not have VFO, and HD DVD has VFO only at intervals of 64 KB, and the resolution of the reproduction signal is low, so that high-speed pull-in becomes difficult.

Normally, in an optical disc, special patterns called sync are inserted into recording data at regular intervals. This special pattern is generally used for error propagation prevention and DSV (Digital Sum Value) control. As shown in Table 1 below, the sync pattern is different for each medium, but in order to facilitate detection, the sync pattern has a long pattern longer than the maximum code inversion interval specified by the modulation code rule of each medium. It is included. The numerical values in Table 1 indicate the length of the channel clock period unit. In general, the sync interval is narrower than the VFO interval, but the pattern itself is as short as 2B and cannot be used as it is for the frequency pull-in operation.

  As a technique for shortening the pull-in time of the PLL circuit with respect to a large frequency change, for example, there is a technique described in Patent Document 1. FIG. 6 shows the configuration of the PLL circuit described in Patent Document 1. The reproduction RF signal is binarized by the data comparator 201. The sector mark detector 202 detects a special pattern (sector mark) arranged immediately before the VFO from the binarized reproduction signal. When the sector mark is detected, the pulse generator 203 outputs a prediction gate signal indicating the VFO period expected to follow immediately after the sector mark. With this prediction gate signal, the VFO / VCO selector 204 is switched, and a binary signal in the VFO period is input to the frequency demodulator 205. The output of the frequency demodulator 205 passes through the VFO / VCO clamp 206, the frequency error voltage is held by the frequency error hold circuit 207, and the frequency is added by the mixing amplifier 208. In Patent Document 1, the channel frequency of the reproduction RF signal detected by the VFO is converted into the VCO oscillation frequency input, thereby realizing frequency pull-in and phase synchronization in a short period.

As another example of the prior art, there are techniques described in Patent Documents 2 and 3. In Patent Document 2, a reference frequency is generated by detecting the head position and the spindle rotation speed for an optical disk apparatus controlled by CLV, thereby shortening the access time during seeking. In Patent Document 3, the center frequency and the sweep range are determined, and the PLL circuit is pulled in by frequency sweeping, thereby speeding up the pull-in.
Japanese Patent Laid-Open No. 10-163861 JP-A-8-293155 JP-A-8-116254

  In Patent Document 1, a specific mark such as a sector mark immediately before the VFO is detected in a state where the frequency of the PLL clock is greatly shifted, and the VFO period immediately following the specific mark is specified, and the portion is FM-modulated. The channel frequency is detected by However, it is difficult to accurately detect a specific mark with respect to a reproduction signal whose resolution is reduced so that PRML is essential and in a situation where phase synchronization is not performed. Further, since the VFO area does not exist in DVDs other than CDs and DVD-RAMs, the technique described in Patent Document 1 cannot be applied. Also, in HD DVD, there is no specific mark such as a sector mark at the head of the VFO area, and the VFO area cannot be recognized using the specific mark, and even if the VFO area can be specified. Since the appearance frequency of the VFO area is low, high-speed pull-in is difficult.

  The technique described in Patent Document 2 is premised on CLV control in which the linear velocity is constant. For this reason, the technique described in Patent Document 2 cannot be directly applied to a CAV-controlled optical disc apparatus in which the spindle rotation speed is constant. Although not described in Patent Document 2, a method of detecting the reproduction channel frequency by detecting the head position with a position detector is also conceivable. However, in this case, there is a problem that the cost of the entire optical disc apparatus increases due to the addition of the position detector, and the yield decreases. The technique described in Patent Document 3 has a problem that it takes time to draw even if the sweep frequency range is limited. Further, when a head position estimation error occurs, the center frequency and the sweep frequency range may be set to values different from the correct frequency, and in that case, the pull-in may fail. .

  The present invention provides a phase synchronization apparatus, method, and optical disc apparatus that can solve the above-described problems of the prior art and can synchronize a PLL clock with a channel frequency without adding a new sensor or the like. With the goal.

  The present invention also provides a phase synchronization apparatus, method, and method capable of speeding up the frequency pull-in of the PLL circuit with respect to a large change in channel frequency that occurs during a long seek or the like during CAV operation even when the resolution of the reproduced signal is low. An object of the present invention is to provide an optical disk device.

  In order to solve the above problem, a phase synchronization apparatus according to a first aspect of the present invention is a modulated signal modulated by a run length limit code, and has a predetermined run length equal to or greater than the upper limit of the run length limit code rule. A PLL circuit that generates a clock signal synchronized with the modulation signal from a modulation signal periodically embedded with a special pattern, and a pulse signal that generates a pulse signal by pulsing the modulation signal in synchronization with the clock signal Measures the sign inversion interval of the pulse signal when the generation means and the PLL circuit are out of synchronization, and outputs the maximum value of the code inversion interval within a period longer than the embedding period of the special pattern as the maximum code inversion interval. Maximum code inversion interval measuring means for performing the first channel frequency signal generating means for estimating the first channel frequency based on the maximum code inversion interval, PLL circuit becomes unsynchronized, the center frequency, characterized in that it is set to the first channel frequency.

  An optical disc apparatus according to a first aspect of the present invention is a modulated signal in which concentric or spiral tracks are formed and modulated with a run length limit code on the track, and is equal to or higher than the upper limit of the run length limit code rule. In an optical disc apparatus for reproducing an optical disc medium on which a modulation signal in which a special pattern including a predetermined run length is periodically embedded is recorded, a pickup means for reading the modulation signal recorded on the optical disc medium, and the pickup means The PLL circuit that generates a clock signal that is synchronized with the read modulation signal, the pulse signal generation means that generates a pulse signal by pulsing the modulation signal in synchronization with the clock signal, and the PLL circuit are out of synchronization. Measure the interval of sign inversion of the pulse signal in the A maximum code inversion interval measuring means for outputting the maximum value of the code inversion interval as a maximum code inversion interval; and a first channel frequency signal generating means for estimating a first channel frequency based on the maximum code inversion interval. The PLL circuit is characterized in that, when the PLL circuit is in an asynchronous state, a center frequency is set to the first channel frequency.

  The phase synchronization method according to the first aspect of the present invention is a special pattern including a predetermined run length that is a modulated signal modulated by a run length limit code using a PLL circuit and is equal to or greater than the upper limit of the run length limit code rule. Generating a clock signal in synchronization with the clock signal by generating a clock signal synchronized with the modulation signal from the modulation signal periodically embedded, and generating the pulse signal, and the PLL circuit Measuring a sign inversion interval of the pulse signal in a state of being out of synchronization, measuring a maximum value of the sign inversion interval within a period equal to or longer than the embedding period of the special pattern, and Estimating the first channel frequency based on the maximum value, and when the PLL circuit is in an asynchronous state, the center frequency of the PLL circuit is set to the first frequency. Characterized by a step of setting the channel frequency.

  In the phase synchronization apparatus, method, and optical disc apparatus of the first aspect of the present invention, the maximum value of the code inversion interval (maximum code inversion interval) of the pulse signal is measured, and the reproduction channel frequency is determined based on the maximum code inversion interval. And the center frequency of the PLL circuit is set to the estimated channel frequency (first channel frequency). When the maximum code inversion interval is measured in units of PLL clocks with a period longer than the period of the special pattern embedded in the modulation signal, it corresponds to a run length that is greater than or equal to the upper limit of the run length limit code rule included in the special pattern. Since the measurement value of the maximum code inversion interval and the reproduction channel frequency are substantially proportional to each other, the actual reproduction channel frequency can be estimated from the measurement value even when the reproduction channel frequency is unknown. In the present invention, when the PLL circuit becomes asynchronous, the center frequency of the PLL circuit is set to the first channel frequency estimated in this way, so that the clock frequency can be estimated without using a sensor or the like to estimate the reproduction channel frequency. The frequency of the signal can be brought close to the reproduction channel frequency, and the PLL circuit can be drawn at high speed. Further, the center frequency of the PLL circuit is set to the first channel frequency, and the maximum code inversion interval is measured in this state, the first channel frequency is estimated, and the estimated center frequency of the PLL circuit is the first estimated frequency. By repeating the operation of setting the channel frequency, the error between the frequency of the clock signal and the actual reproduction channel frequency can be reduced and the accuracy can be increased.

  A phase synchronization apparatus and an optical disc apparatus according to a first aspect of the present invention detect the special pattern from the pulse signal in a state where the center frequency of the PLL circuit is set to the first channel frequency, Special pattern interval measuring means for measuring the appearance interval; and second channel frequency signal generating means for estimating the second channel frequency based on the appearance interval of the special pattern, wherein the center frequency of the PLL circuit is It is preferable to employ a configuration in which the second channel frequency estimated by the second channel frequency signal generation unit is set based on the appearance interval of the special pattern. The phase synchronization method according to the first aspect of the present invention is characterized in that, after the step of setting the center frequency of the PLL circuit to the first channel frequency, the modulation signal is pulsed in synchronization with the clock signal. Detecting the special pattern from the measured pulse signal, measuring the appearance interval of the special pattern, estimating the second channel frequency based on the appearance interval of the special pattern, and determining the center frequency of the PLL circuit. Preferably, the method further includes the step of setting the second channel frequency. The special pattern can be detected from the pulse signal by setting the center frequency of the PLL circuit to the first channel frequency estimated based on the maximum code inversion interval and approaching the reproduction channel frequency. The embedding period of the special pattern is longer than the maximum code inversion interval, and by estimating the channel frequency using the appearance interval of the special pattern, the channel frequency is more accurately estimated than the channel frequency estimation using the maximum code inversion interval. Can be estimated. By setting the second channel frequency estimated in this way as the center frequency of the PLL circuit, the frequency of the clock signal can be matched with the reproduction channel frequency with high accuracy.

  The phase synchronization apparatus and the optical disc apparatus according to the first aspect of the present invention input the estimated first and second channel frequencies, select one of the first and second channel frequencies, and A selector that outputs to a PLL circuit; and a sequence unit that controls which one of the first and second channel frequency signals is selected. The sequence unit is configured so that the PLL circuit is in an asynchronous state. , Causing the selector to select a first channel frequency, setting the center frequency of the PLL circuit to the first channel frequency, and then causing the selector to select a second channel frequency, and the center frequency of the PLL circuit to be selected. Can be set to the second channel frequency. As described above, first, the first channel frequency is output from the selector, the center frequency of the PLL circuit is set to the first channel frequency, and the rough frequency drawing is performed. Thereafter, the second channel frequency is output from the selector. By setting the center frequency of the PLL circuit to the second channel frequency and performing high-frequency pull-in, the frequency of the clock signal can be matched with the reproduction channel frequency with high accuracy.

  The phase synchronization apparatus according to the second aspect of the present invention is a modulation signal modulated with a run length limit code, and a special pattern including a predetermined run length that is equal to or greater than the upper limit of the run length limit code rule is periodically embedded. A PLL circuit for generating a clock signal synchronized with the modulation signal from the modulated signal, a pulse signal generating means for generating a pulse signal by pulsing the modulation signal in synchronization with the clock signal, and a PLL circuit Special pattern interval measuring means for detecting the special pattern from the pulse signal in an out-of-synchronization state and measuring the appearance interval of the special pattern, and a channel frequency signal for estimating the channel frequency based on the appearance interval of the special pattern Generating means, and when the PLL circuit is in an asynchronous state, a center frequency is set to the channel frequency.

  An optical disc apparatus according to a second aspect of the present invention is a modulated signal in which concentric or spiral tracks are formed and modulated on a track with a run length limit code, and the upper limit of the run length limit code rule is exceeded. In an optical disc apparatus for reproducing an optical disc medium on which a modulation signal in which a special pattern including a predetermined run length is periodically embedded is recorded, a pickup means for reading the modulation signal recorded on the optical disc medium, and the pickup means The PLL circuit that generates a clock signal that is synchronized with the read modulation signal, the pulse signal generation means that generates a pulse signal by pulsing the modulation signal in synchronization with the clock signal, and the PLL circuit are out of synchronization. The special pattern is detected from the pulse signal in a state where the special pattern is detected, and the appearance interval of the special pattern is measured. Pattern interval measuring means and channel frequency signal generating means for estimating the channel frequency based on the appearance interval of the special pattern, and the PLL circuit is set to the channel frequency when the PLL circuit is in an asynchronous state. It is characterized by.

  The phase synchronization method according to the second aspect of the present invention is a modulated signal modulated by a run length limit code using a PLL circuit, and a special pattern including a run length exceeding the upper limit of the run length limit code rule has a period. In the method of generating a clock signal synchronized with the modulation signal from the modulation signal embedded in the signal, the step of pulsing the modulation signal in synchronization with the clock signal to generate a pulse signal; and Detecting a special pattern and measuring an appearance interval of the special pattern; estimating a channel frequency based on the appearance interval of the special pattern; and when the PLL circuit is in an asynchronous state, a center frequency of the PLL circuit Setting the channel frequency to the channel frequency.

  In the phase synchronization apparatus, method, and optical disc apparatus according to the second aspect of the present invention, a special pattern is detected from the pulse signal, the reproduction channel frequency is estimated based on the detection interval, and the center frequency of the PLL circuit is Set to the estimated channel frequency. In this way, the reproduction channel frequency is estimated from the pulse signal, and the center frequency of the PLL circuit is set to the estimated channel frequency, so that it is possible to estimate the clock signal without estimating the reproduction channel frequency using a sensor or the like. The frequency can be brought close to the reproduction channel frequency, and the PLL circuit can be pulled in at high speed.

  In the phase synchronization apparatus and the optical disc apparatus of the present invention, the pulse signal generation unit may include a maximum likelihood detector that generates the pulse signal from the modulation signal by maximum likelihood detection. In this case, the pulse signal generating means can employ a configuration including an equalizer that equalizes the modulated signal for PR and inputs it to the maximum likelihood detector. The maximum likelihood detector may employ a configuration that performs maximum likelihood detection according to a Viterbi algorithm. The phase synchronization apparatus and the optical disk apparatus according to the present invention can be suitably used for an apparatus that reproduces a high-density medium that requires maximum likelihood detection.

  The phase synchronization apparatus and method according to the first aspect of the present invention measures the maximum value of the code inversion interval (maximum code inversion interval) of the pulse signal and estimates the reproduction channel frequency based on the maximum code inversion interval. By setting the first channel frequency estimated in this way to the center frequency of the PLL circuit, the frequency of the clock signal can be brought close to the reproduction channel frequency without adding a sensor or the like. It can be pulled in at high speed. Further, since the optical disk apparatus according to the first aspect of the present invention can pull in the PLL circuit at a high speed, even when a large change occurs in the reproduction channel frequency due to a long seek or the like during the CAV operation, the phase synchronization state can be quickly obtained. Can be established.

  In the phase synchronization apparatus, method, and optical disc apparatus according to the second aspect of the present invention, a special pattern is detected from the pulse signal, the reproduction channel frequency is estimated based on the detection interval, and the center frequency of the PLL circuit is Set to the estimated channel frequency. By doing so, the frequency of the clock signal can be brought close to the reproduction channel frequency without estimating the reproduction channel frequency using a sensor or the like, and the PLL circuit can be drawn at high speed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of an optical disc apparatus according to an embodiment of the present invention. The optical disk apparatus 100 includes an optical head 12, a servo mechanism 13, an RF amplifier 14, an A / D converter 15, a PRML detector 16, a PLL circuit 17, a maximum sign inversion interval measuring unit 18, a first channel frequency estimator 19, A sync interval measuring device 20, a second channel frequency estimator 21, a selector 22, and a sequencer 23 are provided. On the recording track of the disk medium 11, user data is recorded as a minute mark row modulated in accordance with a run length restriction rule. In the user data, a special pattern (sync pattern) including a run length longer than the longest run length according to the rule of the run length restriction code is periodically embedded.

  The disk medium 11 is rotationally controlled by a spindle motor (not shown). The optical head 12 includes a laser diode, an optical element, and an objective lens drive system, and irradiates a focused track on a groove track (recording track) of the disk medium 11. The optical head 12 detects the positional deviation in the vertical direction and the radial direction with respect to the disk medium 11 based on the reflected light from the disk medium 11, and controls the drive system of the objective lens by the actuator servo mechanism 13. The focused spot is made to accurately follow the recording track with respect to disc surface fluctuation and disc eccentricity.

  The optical head 12 detects the reflected light modulated by the minute mark rows in the recording track by the photo detector. The photodetector outputs a weak received light signal corresponding to the intensity of the reflected light to the RF amplifier 14. The RF amplifier 14 amplifies a weak received light signal and outputs it as a reproduction RF signal. The A / D converter 15 performs A / D conversion on the reproduction RF signal, and inputs the digitized RF signal to a data detection system including the PRML detector 16.

  The PLL circuit 17 extracts a synchronization clock from the digitized reproduction RF signal, and generates operation clocks for the A / D converter 15 and the PRML detector 16. The PLL circuit 17 is configured so that the center frequency of the oscillator can be switched. Although the PLL circuit 17 can be configured with an analog circuit, it is desirable to configure it with a digital circuit because it is necessary to switch the center frequency of the oscillator. The PRML detector 16 PR equalizes the reproduction RF signal and identifies the data series by maximum likelihood detection. By using PR equalization and maximum likelihood detection in the PRML detector 16, it is possible to reduce the error rate even when the resolution of the reproduced RF signal is reduced. The data identified by the PRML detector 16 is reproduced as music data or video data through demodulation of a run length limiting code (not shown) and error correction processing.

The maximum sign inversion interval measuring device 18 measures the time in which “0” or “1” in the identification data continues for each clock signal generated by the PLL circuit 17. Maximum code inversion interval measuring instrument 18 measures the continuous time over a period of more sync interval '0' or '1', the largest of them, and outputs a maximum code inversion interval T _max. As shown in Table 1, the sync pattern includes a pattern (maximum code) greater than or equal to the maximum run length of the run length limit code, and the maximum code inversion interval measuring unit 18 sets the time width of the maximum code. , And output as the maximum sign inversion interval T _max . The first channel frequency estimator 19 calculates an estimated channel frequency f _{det_T} based on the maximum code inversion interval T _max output from the maximum code inversion interval measuring unit 18.

The sync interval measuring device 20 measures the appearance interval (sync interval T _inter ) of the sync pattern from the identification data output from the PRML detector 16. In DVD and HD DVD, as shown in Table 1, since a continuous number longer than “0” or “1” measured outside the sync is measured in the sync, the sync interval measuring device 20 The pulse length of 12 to 15 PLL clock cycles can be regarded as a sync pattern and the interval can be measured. In the case of CD, since the consecutive numbers of “0” or “1” measured inside and outside the sync are equal to each other, it is only necessary to detect a pattern that matches the sync pattern and measure the interval. The second channel frequency estimator 21 calculates an estimated channel frequency f _{det_S} based on the sync interval T _inter measured by the sync interval measuring unit 20.

Selector 22, the estimated channel frequency f _{Det_T} the first channel frequency estimator 19 is calculated, and inputs the estimated channel frequency f _{Det_S} the second channel frequency estimator 21 is calculated. The selector 22 receives the estimated channel frequency f _{det_T} calculated by the first channel frequency estimator 19 or the estimated channel frequency calculated by the second channel frequency estimator 21 according to the selector control signal sel input from the sequencer 23. f _{det_S} is input to the PLL circuit 17 as the estimated channel frequency f _det .

  FIG. 2 shows the configuration of the PLL circuit 17. The PLL circuit 17 includes a phase comparator 71, a loop filter (LPF) 72, an adder 73, a numerically controlled oscillator (NCO) 74, and a selector 75. The phase comparator 71 receives the digitized RF signal and generates phase difference information using this and the RF signal one point before. The loop filter 72 receives the phase difference information output from the phase comparator 71 and performs filtering so that the phase difference information has a desired loop characteristic, thereby generating control frequency information.

The selector 75 receives the estimated channel frequency f _det output from the selector 22 (FIG. 1) and the output of the selector 75 itself. The selector 75 outputs the estimated channel frequency f _det to the adder 73 when the timing control signal test input from the sequencer 23 becomes active. In other periods, the output of the selector 75 is maintained at a constant value. The adder 73 adds the control frequency information output from the loop filter 72 and the output of the selector 75 and inputs the sum to the NCO 74 to control the oscillation frequency of the NCO 74. The output of the NCO 74 becomes an operation clock for the A / D converter 15 and the PRML detector 16 as a PLL clock.

  Returning to FIG. 1, the sequencer 23 is realized by hardware (circuit) or by a CPU and software. The sequencer 23 monitors the synchronization state of the PLL circuit 17. For example, the sequencer 23 monitors the synchronization state using the identification data output from the PRML detector 16. As a reference for the synchronization state, for example, whether or not the sync interval is a value unique to the medium can be used. Alternatively, the PLL circuit 17 itself, for example, the transition state of the phase comparator 71 may detect the loss of synchronization and input this signal to the sequencer 23. When the sequencer 23 detects loss of synchronization, the sequencer 23 starts a frequency pull-in operation. Alternatively, the pull-in operation may be started by inputting a frequency pull-in trigger signal immediately after the operation such as seeking is lost from an external CPU (not shown).

At the start of frequency acquisition, the sequencer 23 inputs a selection signal sel for selecting the output of the first channel frequency estimator 19 to the selector 22, and the maximum sign inversion interval measuring device 18 and the first channel frequency estimator. 19 is used to input the channel frequency f _{det_T} estimated based on the maximum code inversion interval T _max to the PLL circuit 17. In the state where frequency pull-in is started, the PRML detector 16 generates identification data in a state where the oscillation frequency of the PLL circuit 17 does not match the channel frequency of the RF signal. When the maximum code inversion interval T _max is measured from this identification data, for example, in DVD, the time width of 14T (T is a channel clock) within sync is to be measured as the maximum code inversion period, and the PLL clock frequency is the channel frequency. Therefore, a longer or shorter time width is measured as the maximum code inversion interval T _max . Channel frequency estimator 19, the maximum code inversion interval if the PLL clock frequency is synchronized with the channel frequency T _sync1, the oscillation frequency of the PLL circuit 17 at the time of measurement as f _Plls, channel frequency estimated from T _max f _{det_T} is calculated by the following equation (1).
_{f det_T = (T sync1 / T} max) × f pll (1)
Since the calculated channel frequency f _{Det_T} contain an error, performing a plurality of times to calculate the channel frequency, it may be averaged.

The channel frequency f _{det_T} calculated by the first channel frequency estimator 19 is input to the PLL circuit 17 as the estimated channel frequency f _det via the selector 22. The sequencer 23 activates the timing control signal test input to the PLL circuit 17 at a predetermined timing. When the timing control signal test becomes active, the selector 75 selects the output f _{det_t} of the first channel frequency estimator 19, and outputs to the NCO 74 the output of the loop filter 72 and the output f _{det_T of} the first channel frequency estimator 19. The value obtained by adding and is input. As a result, the center frequency of the oscillation frequency of the _{NCO 74} is preset to the frequency f _{det_T} calculated by the first channel frequency estimator 19. By repeating the operation of presetting the frequency f _{det_T} estimated using the maximum code inversion interval T _max as the center frequency of the PLL circuit 17 a plurality of times, the PLL clock frequency f _pll is brought close to the channel frequency of the RF signal. be able to.

The _pull- in using the maximum sign inversion interval T _max will be described in detail. The Viterbi decoder used in the PRML detector 16 performs maximum likelihood detection based on the PR class and the minimum run length constraint. At this time, it is assumed that PLL synchronization has been established, but corresponding pulsing is possible even in an asynchronous state. However, when the operation clock of the Viterbi decoder, that is, the PLL clock frequency is lower than the RF signal channel frequency, the probability of erroneous detection of the minimum run increases. In this case, if the maximum sign inversion interval of the identification data output from the PRML detector 16 is measured, even if the short patterns before and after the sync are read erroneously and averaged, an interval longer than the original is calculated. On the contrary, when the output clock frequency of the PLL circuit 17 is higher than the channel frequency of the RF signal, if the PLL circuit 17 is locked, the waveform fluctuation that can be excluded by the minimum run length rule is identified as a short pattern. However, a run length shorter than the original may be detected. This relationship is shown in FIG.

A PLL clock frequency f _Plls in FIG 3, when the relationship between the measured value T _max of the maximum code inversion interval defined by a function g,
T _max = g (f _pll ) (2)
It can be expressed as. Referring to FIG. 3, the measured value T _max of the maximum code inversion interval and the PLL clock frequency f _pll are substantially proportional to each other, and the first channel frequency estimator 19 calculates the equation (1) from these values. Is used to estimate the channel frequency. From equation (1) and (2), when determining the relationship between the output clock frequency f _Plls of the estimated channel frequency f _{Det_T} and PLL circuit 17,
_{f det_T = (T sync1 / g} (f pll)) × f pll = h (f pll) (3)
It can be expressed as. When Expression (3) is graphed, the graph shown in FIG. 4 is obtained.

In the graph shown in FIG. 4, if the PLL clock across the frequency f possible values of _pll estimated channel frequency f _{Det_T} is long substantially matches the channel frequency of the RF signal, by the measurement of a single maximum code inversion interval, approximately The PLL clock frequency f _pll can be surely matched with the channel frequency of the RF signal. However, in practice, the lower the PLL clock frequency _{fpll, the} greater the error in the measured maximum sign inversion interval, and the estimated channel clock frequency deviates greatly from the channel frequency of the RF signal.

PLL clock frequency f _Plls is the case close to the RF signal channel frequency is estimated channel frequency f _{Det_T} is approximately equal to the RF signal channel frequency. From this relationship, as shown in the following formula (4), the PLL clock frequency f _pll can be made to substantially coincide with the RF signal channel frequency by iteration.
_{f pll (n + 1) =} T sync1 / T max (n) × f pll (n) (4)
N represents the number of iteration cycles.
At the start of the pull-in operation (n = 0), the maximum sign inversion interval T _max (0) at the initial value f _pll (0) of the PLL clock frequency is measured, and the estimated channel frequency f _{det_T} (0) is calculated. _{Is the} next PLL clock frequency f _pll (1). Then, by measuring the maximum code inversion interval T _max (1) in the PLL clock frequency f _Plls (1), to calculate the estimated channel frequency _f det_T (1), which next PLL clock frequency f _Plls (2) And By repeating such an operation, the PLL clock frequency f _pll can be converged to the RF signal channel frequency as shown in FIG.

The sequencer 23 repeats the operation of presetting the frequency f _{det_T} calculated by the first channel frequency estimator 19 as the center frequency of the PLL circuit 17 a predetermined number of times, and selects the output frequency of the PLL circuit 17 close to the RF signal channel frequency. The signal sel is switched, and the channel frequency estimated based on the sync interval using the sync interval measuring device 20 and the second channel frequency estimator 21 is input to the PLL circuit 17. In this state, the output frequency of the PLL circuit 17 is close to the channel frequency of the RF signal, and the PRML detector 16 generates the identification data in a state where the operation clock matches the channel frequency of the RF signal to some extent. The sync pattern can be detected from this identification data.

The sync interval measuring device 20 detects the sync pattern from the identification data output from the PRML detector 16 by using, for example, a sync pattern detector, measures the detection interval with a counter, and sets the sync interval T _{inter in} units of PLL clocks. measure. For example, in DVD, the time width of 1488T (Table 1) should be measured as the sync interval _Tinter , so that the time width longer or shorter than that is due to the PLL clock frequency not completely matching the channel frequency. It is measured as the sync interval _Tinter . Second channel frequency estimator 21, the sync interval in the disk medium 11 T _sync2, the oscillation frequency of the PLL circuit 17 at the time of measurement as f _Plls, deduced from sync interval T _inter that sync interval measuring instrument 20 is measured The channel frequency f _{det_S} is calculated by the following equation (5).
_{f det_S = T sync2 / T inter} × f pll (5)

The channel frequency f _{det_S} calculated by the second channel frequency estimator 21 is input to the PLL circuit 17 through the selector 22 as the estimated channel frequency f _det . The sequencer 23 activates the timing control signal test input to the PLL circuit 17 at a predetermined timing. When the timing control signal test becomes active, the selector 75 in the PLL circuit 17 selects the output f _{det_S} of the second channel frequency estimator 21 and _sends the output of the loop filter 72 and the second channel frequency estimator to the NCO 74. A value obtained by adding 21 outputs f _{det_S} is input. As a result, the center frequency of the oscillation frequency of the _{NCO 74} is preset to the frequency f _{det_S} calculated by the second channel frequency estimator 21. With this operation, if the difference between the PLL clock frequency and the RF signal channel frequency is less than or equal to the capture range of the PLL circuit 17, phase synchronization is completed by a normal phase pull-in operation.

FIG. 5 is a timing chart showing the phase pull-in state. At time t1, when seeking from the state of phase synchronization with the outer track to the inner track, the RF signal is interrupted (a), and the PLL circuit 17 is out of synchronization (b). At this time, the frequency of the RF signal channel frequency changes before and after seeking (c). The sequencer 23 detects that the PLL circuit 17 is out of synchronization, switches the selector control signal sel (e), and starts pulling using the maximum code inversion interval (rough frequency pulling). When the seek ends at time t2 and the RF signal is converted into an identification data string by the PRML detector 16, the maximum code inversion interval measuring unit 18 measures the maximum code inversion period T _max (0), and the first The channel frequency estimator 19 calculates an estimated channel frequency f _{det_T} (0) based on the measured maximum code inversion period T _max (0).

At time t3, the sequencer 23 makes a timing control signal test active (f), PLL circuit 17, the center frequency of the PLL clock frequency f _Plls, set to the estimated channel frequency _{f det_T (0) (d)} . At time t4, when the sequencer 23 again timing control signal test (f) is an active, PLL circuit 17, the center frequency of the PLL clock frequency f _Plls, estimated channel frequency f first channel frequency estimator 19 is calculated _{det_T} Set to (1). After activating the test signal at time t4, the sequencer 23 inverts the selection control signal sel (e) and starts drawing using the sync interval (frequency high-precision drawing).

The PRML detector 16 operates with a PLL clock having a center frequency f _{det_T} (1) and outputs identification data. The sync interval measuring device 20 measures the sync interval from this identification data, and the second channel frequency estimator 21 calculates the estimated channel frequency f _{det_S} based on the measured sync interval. At time t5, when the sequencer 23 is a timing control signal test (f) is an active, PLL circuit 17, the center frequency of the PLL clock frequency f _Plls, estimated channel frequency f _{Det_S} the second channel frequency estimator 21 is calculated (D). Thereafter, the PLL circuit 17 performs a normal pull-in operation to establish phase synchronization at time t6.

  Since the appearance frequency of the sync is relatively high, it is possible to calculate the channel frequency in a wide frequency range. However, since the long mark included in the sync pattern has only a length of several tens of channel clocks, this is the only one. It is difficult to calculate the frequency with high accuracy using. On the other hand, the sync interval is 50 to 100 times as long as the long mark, and by calculating the frequency from the sync interval, highly accurate frequency information can be generated. However, when the deviation of the oscillation frequency of the PLL circuit 17 exceeds a range of about ± 20% with respect to the RF signal channel frequency, the sync pattern cannot be correctly detected from the identification data, and the phase is determined using the sync interval. Cannot be withdrawn.

  In this embodiment, at the start of pull-in, coarse adjustment is performed using the maximum code inversion interval of identification data in a state where the PLL clock is not phase-synchronized to bring the PLL clock frequency close to the RF signal channel frequency, and then the PLL clock Measures the sync interval from the identification data in a state close to the RF signal channel frequency, performs fine adjustment, and synchronizes the PLL clock in phase. In this way, by performing frequency pull-in by two stages of coarse adjustment using the maximum code inversion interval and fine adjustment using the sync interval, even for a low-resolution reproduction signal on the premise of PRML detection, The frequency pull-in can be completed at a higher speed.

  In the optical disc apparatus 100 of the present embodiment, since the PLL circuit 17 can be pulled in at high speed as described above, even when a long seek occurs during random playback of a CLV recorded disc by CAV, playback is possible. Time throughput. In addition, since it is not necessary to add a new sensor or the like, high-speed pull-in can be realized without increasing costs.

  In the above-described embodiment, an example in which the fine adjustment based on the sync interval is performed after the coarse adjustment based on the maximum code inversion interval has been described. However, the fine adjustment may not be performed. For example, when the loop gain of the PLL circuit 17 can be made sufficiently high and phase synchronization is possible with the PLL clock frequency after coarse adjustment, it is not necessary to perform fine adjustment. Further, even when only the coarse adjustment can be used to sufficiently bring the PLL clock frequency close to the RF signal channel frequency, the fine adjustment can be omitted. On the contrary, when the sync pattern can be detected from the identification data, the PLL clock frequency may be synchronized with the reproduction RF signal channel frequency only by fine adjustment based on the sync interval.

  In the above embodiment, when the phase synchronization of the PLL circuit 17 is lost, the PLL circuit frequency is made closer to the RF signal channel frequency by starting from the PLL clock frequency immediately before the phase synchronization is lost with respect to the unknown RF signal channel frequency. Although examples are shown, the present invention is not limited to this. For example, at the start of pull-in, the PLL circuit 17 can be oscillated at a predetermined initial frequency to start coarse adjustment, and the PLL clock frequency can be made closer to the RF channel frequency from the initial frequency. In this case, as shown in FIG. 5, when the PLL clock frequency is higher than the RF signal channel frequency, the error of the estimated channel frequency becomes smaller. Therefore, it is preferable to set a higher frequency as the initial frequency. .

  The PRML detector 16 can be configured to generate identification data with a Viterbi decoder without performing PR equalization when the input channel characteristics substantially match a specific PR class. The maximum likelihood detection is not limited to Viterbi decoding, and other algorithms can be used. When the resolution of the reproduction RF signal is sufficiently high, the identification data may be generated by a pulsing circuit using threshold detection instead of the PRML detector 16.

  Although the present invention has been described based on the preferred embodiments, the phase synchronization apparatus, method, and optical disc apparatus of the present invention are not limited to the above embodiments, and the configuration of the above embodiments. To which various modifications and changes are made within the scope of the present invention.

  The present invention can be used for an optical disk apparatus such as a CD or a DVD, and is particularly suitable for CAV reproduction of an optical disk apparatus recorded with high density.

1 is a block diagram showing a configuration of an optical disc apparatus according to an embodiment of the present invention. The block diagram which shows the structure of a PLL circuit. The graph which shows the relationship between PLL clock frequency and the measured maximum code inversion interval. The graph which shows the relationship between PLL clock frequency and an estimation channel frequency. The timing diagram which shows the mode of operation | movement at the time of phase synchronization. The block diagram which shows the structure of the conventional PLL circuit.

Explanation of symbols

11 Disk medium 12 Optical head 13 Servo mechanism 14 RF amplifier 15 A / D converter 16 PRML detector 17 PLL circuit 18 Maximum sign inversion interval measuring device 19, 21 Channel frequency estimator 20 Sync interval measuring device 22, 75 Selector 23 Sequencer 71 Phase comparator 72 Loop filter 73 Adder 74 Numerically controlled oscillator

Claims (17)

A modulated signal modulated with a run length limited code, and a clock synchronized with the modulated signal from a modulated signal periodically embedded with a special pattern including a predetermined run length equal to or greater than the upper limit of the run length limited code rule A PLL circuit for generating a signal;
Pulse signal generation means for generating a pulse signal by pulsing the modulation signal in synchronization with the clock signal;
Maximum sign inversion that measures the sign inversion interval of the pulse signal when the PLL circuit is out of synchronization and outputs the maximum value of the sign inversion interval as a maximum code inversion interval within a period longer than the embedding period of the special pattern Interval measuring means;
First channel frequency signal generating means for estimating a first channel frequency based on the maximum code inversion interval;
When the PLL circuit is in an asynchronous state, a center frequency is set to the first channel frequency. Special pattern interval measuring means for detecting the special pattern from the pulse signal in a state where the center frequency of the PLL circuit is set to the first channel frequency, and measuring the appearance interval of the special pattern;
A second channel frequency signal generating means for estimating a second channel frequency based on the appearance interval of the special pattern;
2. The phase synchronization apparatus according to claim 1, wherein a center frequency of the PLL circuit is set to a second channel frequency estimated by the second channel frequency signal generation unit based on an appearance interval of the special pattern. A selector that selects one of the estimated first and second channel frequencies and outputs the selected frequency to the PLL circuit;
Sequence means for controlling which of the first and second channel frequency signals is selected;
When the PLL circuit is in an asynchronous state, the sequence means causes the selector to select the first channel frequency, sets the center frequency of the PLL circuit to the first channel frequency, and then causes the selector to select the second channel frequency. The phase synchronization apparatus according to claim 2, wherein the channel frequency is selected and the center frequency of the PLL circuit is set to the second channel frequency. A modulated signal modulated with a run length limited code, and a clock synchronized with the modulated signal from a modulated signal periodically embedded with a special pattern including a predetermined run length equal to or greater than the upper limit of the run length limited code rule A PLL circuit for generating a signal;
Pulse signal generation means for generating a pulse signal by pulsing the modulation signal in synchronization with the clock signal;
Special pattern interval measuring means for detecting the special pattern from the pulse signal in a state where the PLL circuit is out of synchronization and measuring the appearance interval of the special pattern;
Channel frequency signal generating means for estimating a channel frequency based on the appearance interval of the special pattern,
When the PLL circuit is in an asynchronous state, the center frequency is set to the channel frequency.   The phase synchronization apparatus according to claim 1, wherein the pulse signal generation unit includes a maximum likelihood detector that generates the pulse signal from the modulation signal by maximum likelihood detection. The phase synchronization apparatus according to claim 5, wherein the pulse signal generation unit includes an equalizer that performs PR equalization on the modulation signal and inputs the PR signal to the maximum likelihood detector.   The phase synchronization apparatus according to claim 5, wherein the maximum likelihood detector performs maximum likelihood detection according to a Viterbi algorithm. A concentric or spiral track is formed, a modulated signal modulated on the track with a run length limit code, and a special pattern including a predetermined run length that is not less than the upper limit of the run length limit code rule is periodically In an optical disc apparatus for reproducing an optical disc medium in which a modulation signal embedded in is recorded,
Pick-up means for reading the modulation signal recorded on the optical disc medium;
A PLL circuit for generating a clock signal synchronized with the modulation signal read by the pickup means;
Pulse signal generation means for generating a pulse signal by pulsing the modulation signal in synchronization with the clock signal;
Maximum sign inversion which measures the sign inversion interval of the pulse signal in a state where the PLL circuit is out of synchronization and outputs the maximum value of the sign inversion interval in the period longer than the embedding period of the special pattern as the maximum sign inversion interval Interval measuring means;
First channel frequency signal generating means for estimating a first channel frequency based on the maximum code inversion interval;
When the PLL circuit is in an asynchronous state, the center frequency is set to the first channel frequency. Special pattern interval measuring means for detecting the special pattern from the pulse signal in a state where the center frequency of the PLL circuit is set to the first channel frequency, and measuring the appearance interval of the special pattern;
A second channel frequency signal generating means for estimating a second channel frequency based on the appearance interval of the special pattern;
9. The optical disc apparatus according to claim 8, wherein a center frequency of the PLL circuit is set to a second channel frequency estimated by the second channel frequency signal generation unit based on an appearance interval of the special pattern. A selector that selects one of the estimated first and second channel frequencies and outputs the selected frequency to the PLL circuit;
Sequence means for controlling which of the first and second channel frequency signals is selected;
When the PLL circuit is in an asynchronous state, the sequence means causes the selector to select the first channel frequency, sets the center frequency of the PLL circuit to the first channel frequency, and then causes the selector to select the second channel frequency. The optical disk apparatus according to claim 9, wherein the channel frequency is selected and the center frequency of the PLL circuit is set to the second channel frequency. A concentric or spiral track is formed, a modulated signal modulated on the track with a run length limit code, and a special pattern including a predetermined run length that is not less than the upper limit of the run length limit code rule is periodically In an optical disc apparatus for reproducing an optical disc medium in which a modulation signal embedded in is recorded,
Pick-up means for reading the modulation signal recorded on the optical disc medium;
A PLL circuit for generating a clock signal synchronized with the modulation signal read by the pickup means;
Pulse signal generation means for generating a pulse signal by pulsing the modulation signal in synchronization with the clock signal;
Special pattern interval measuring means for detecting the special pattern from the pulse signal in a state where the PLL circuit is out of synchronization and measuring the appearance interval of the special pattern;
Channel frequency signal generating means for estimating a channel frequency based on the appearance interval of the special pattern,
When the PLL circuit is in an asynchronous state, the center frequency is set to the channel frequency.   The optical disc apparatus according to claim 8, wherein the pulse signal generation unit includes a maximum likelihood detector that generates the pulse signal from the modulation signal by maximum likelihood detection.   The optical disc apparatus according to claim 12, wherein the pulse signal generation means includes an equalizer that PR-equalizes the modulated signal and inputs the PR signal to the maximum likelihood detector.   The optical disc apparatus according to claim 12 or 13, wherein the maximum likelihood detector performs maximum likelihood detection according to a Viterbi algorithm. A modulated signal modulated with a run length limited code using a PLL circuit, wherein a special pattern including a predetermined run length equal to or higher than the upper limit of the run length limited code rule is periodically embedded. In a method for generating a clock signal synchronized with a signal,
Pulsing the modulation signal in synchronization with the clock signal to generate a pulse signal;
Measuring a sign inversion interval of the pulse signal in a state where the PLL circuit is out of synchronization, and measuring a maximum value of the sign inversion interval within a period equal to or longer than the embedding period of the special pattern;
Estimating a first channel frequency based on the measured maximum value of the sign inversion interval;
And a step of setting a center frequency of the PLL circuit to the first channel frequency when the PLL circuit is in an asynchronous state. Subsequent to the step of setting the center frequency of the PLL circuit to the first channel frequency, the special pattern is detected from a pulse signal obtained by pulsing the modulation signal in synchronization with the clock signal. Measuring the appearance interval;
Estimating a second channel frequency based on the appearance interval of the special pattern;
The phase synchronization method according to claim 15, further comprising: setting a center frequency of the PLL circuit to the second channel frequency. A modulation signal modulated with a run length limiting code using a PLL circuit, the modulation signal having periodically embedded a special pattern including a predetermined run length equal to or higher than the upper limit of the run length limiting code rule. In a method for generating a clock signal synchronized with a signal,
Pulsing the modulation signal in synchronization with the clock signal to generate a pulse signal;
Detecting the special pattern from the pulse signal in a state where the PLL circuit is out of synchronization, and measuring an appearance interval of the special pattern;
Estimating a channel frequency based on the appearance interval of the special pattern;
And a step of setting a center frequency of the PLL circuit to the channel frequency when the PLL circuit is in an asynchronous state.

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