CN116704087B

CN116704087B - Parameter adjustment method and electronic equipment

Info

Publication number: CN116704087B
Application number: CN202211268392.0A
Authority: CN
Inventors: 郑晓坤; 金永军; 牛翔宇; 刘文方
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-10-17
Filing date: 2022-10-17
Publication date: 2024-02-27
Anticipated expiration: 2042-10-17
Also published as: CN116704087A

Abstract

A parameter adjusting method and an electronic device. Wherein the method comprises the following steps: when the electronic equipment predicts that the task of drawing and rendering the image frame can not be completed in time and frame dropping risk exists, acquiring the task amount of rendering the image frame, determining a first time point based on the task amount, wherein the first time point is earlier than a default frequency-raising time point of a processor, and frequency-raising the processor at the first time point so that the total duration of drawing and rendering the image frame is equal to a vertical synchronization period. In this way, the electronic device can adaptively advance the frequency-increasing time point of the processor according to the task amount of drawing and rendering the image frames, so that the running frequency of the processor is improved earlier, and the total time length of drawing and rendering the image frames is shortened to one vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

Description

Parameter adjustment method and electronic equipment

Technical Field

The present disclosure relates to the field of terminal technologies, and in particular, to a parameter adjustment method and an electronic device.

Background

In electronic devices such as mobile phones and tablet computers, the processes of drawing, rendering, synthesizing, etc. required for generating image frames can be controlled by vertical synchronization signals. For example, the electronic device may draw and render the image layer included in the image frame when the first vertical synchronization signal arrives, and synthesize the rendered image layer when the second vertical synchronization signal arrives, so as to obtain the image frame. However, when the second vertical synchronization signal arrives, if the rendering of the layer is not completed, the electronic device cannot acquire the rendered layer, and thus cannot synthesize and display the image frame, resulting in a frame loss phenomenon.

At present, the electronic device may set a fixed frequency-raising time point between the time when the first vertical synchronization signal arrives and the time when the second vertical synchronization signal arrives, and the frequency-raising time point checks whether the layer rendering is completed, and if the layer rendering is not completed, the operating frequency of the processor is increased to increase the short rendering speed. However, since the frequency-up time point is fixed, the amount of drawing and rendering tasks corresponding to different image frames may be different; therefore, when the number of the drawing and rendering tasks is large, the rendering task may still not be completed when the second vertical signal arrives, so that the frame loss phenomenon still occurs; when the number of rendering and rendering tasks is small, the processor still runs at high frequency after the rendering tasks are completed, resulting in waste of processor resources and power consumption.

Disclosure of Invention

The embodiment of the application provides a parameter adjustment method and electronic equipment, which can effectively avoid frame loss and avoid waste of processor resources and power consumption.

In a first aspect, an embodiment of the present application provides a parameter adjustment method, which may be applied to an electronic device, where the electronic device generates a first vertical synchronization signal and a second vertical synchronization signal according to a preset vertical synchronization period, and draws and renders a new image frame in response to the first vertical synchronization signal at a time when each of the first vertical synchronization signal and the second vertical synchronization signal arrives, and synthesizes a previous image frame in response to the second vertical synchronization signal, where the method includes: acquiring a first time interval, wherein the first time interval is a time interval between a first image frame rendering completion time and a second image frame rendering completion time, the first image frame is a previous image frame of the second image frame, the second image frame is a previous image frame of a third image frame, and the third image frame is an image frame to be currently drawn and rendered by the electronic equipment; if the first time interval is larger than the vertical synchronization period, acquiring a target task amount, wherein the target task amount is the task amount of a processor of the electronic equipment for executing the task of drawing and rendering the second image frame; determining a first time point according to the target task amount, and frequency-boosting the processor at the first time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period; the first time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and is earlier than a default frequency-raising time point of the processor.

According to the method, when the tasks of drawing and rendering the image frames cannot be completed in time due to the fact that the estimated frequency-raising time point is too late, and the frame dropping risk exists, the frequency-raising time point of the processor can be adaptively moved forward according to the task quantity of drawing and rendering the image frames, so that the running frequency of the processor is improved earlier, and the total time length of drawing and rendering the image frames is shortened to be a vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, determining a target frequency-raising time point according to a target task amount, and frequency-raising the processor at the target frequency-raising time point includes: determining a first duration of operation of the processor at a first frequency and a second duration of operation at a second frequency when the total duration is equal to the vertical synchronization period according to the target task amount; the first frequency is the operating frequency before the processor frequency is increased, the second frequency is the default operating frequency after the processor frequency is increased, and the sum of the first duration and the second duration is equal to the vertical synchronization period; and determining a first time point according to the first time length or the second time length, and raising the operating frequency of the processor to the second frequency at the first time point.

Based on the implementation mode, when the image frame has the frame dropping risk, the running frequency of the processor can be improved earlier only by adopting a mode of advancing the frequency-raising time point of the processor, so that the total time length for drawing and rendering the image frame is shortened to one vertical synchronization period. Therefore, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, determining a target frequency-raising time point according to a target task amount, and frequency-raising the processor at the target frequency-raising time point includes: determining a third time length of running at the first frequency and a fourth time length of running at the third frequency when the total time length is equal to the vertical synchronization period according to the target task quantity; the first frequency is the operating frequency before the processor frequency raising, the third frequency is the operating frequency after the processor frequency raising, the third frequency is larger than the second frequency, the second frequency is the default operating frequency after the processor frequency raising, and the sum of the third duration and the fourth duration is equal to the vertical synchronization period; and determining a first time point according to the third time period or the fourth time period, and raising the operating frequency of the processor to a third frequency at the first time point.

Based on the implementation mode, when the image frame has the frame dropping risk, the method can shorten the total time length of drawing and rendering the image frame to one vertical synchronization period by adopting a mode of advancing the frequency raising time point of the processor and improving the frequency raising amplitude of the processor. Therefore, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, the method further comprises: if the first time interval is larger than the vertical synchronization period, acquiring a target task quantity; determining a second time point according to the target task quantity, and frequency-boosting the processor at the second time point so as to ensure that the total duration is equal to the vertical synchronization period; the second time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and the second time point is later than a default frequency-raising time point of the processor.

Based on the implementation mode, when the task of drawing and rendering the image frames is completed too early and the waste of processor resources and power consumption is caused due to the fact that the frequency-increasing time point is estimated too early, the frequency-increasing time point of the processor can be adaptively moved backwards according to the task amount of drawing and rendering the image frames, so that the speed of drawing and rendering the image frames is reduced, and the total time length of drawing and rendering the image frames is increased to one vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, determining a second time point according to the target task amount, and frequency-boosting the processor at the second time point includes: determining a fifth time length of running at a first frequency and a sixth time length of running at a second frequency when the total time length is equal to the vertical synchronization period according to the target task quantity; the first frequency is the operating frequency before the processor frequency is increased, the second frequency is the default operating frequency after the processor frequency is increased, and the sum of the fifth time length and the sixth time length is equal to the vertical synchronization period; and determining a second time point according to the fifth time period or the sixth time period, and increasing the operating frequency of the processor to a second frequency at the second time point.

By adopting the implementation mode, when the frequency-increasing time point is estimated to be too early, the running frequency of the processor can be increased later only by adopting a mode of moving the frequency-increasing time point of the processor backwards, so that the total time length for drawing and rendering the image frames is increased to one vertical synchronization period. Therefore, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, determining a second time point according to the target task amount, and frequency-boosting the processor at the second time point includes: determining a seventh time length of the processor running at the first frequency and an eighth time length of the processor running at the fourth frequency when the total time length is equal to the vertical synchronization period according to the target task amount; the first frequency is the operating frequency before the processor frequency raising, the fourth frequency is the operating frequency after the processor frequency raising, the fourth frequency is greater than the first frequency and smaller than the second frequency, the second frequency is the operating frequency after the default processor frequency raising, and the sum of the seventh time length and the eighth time length is equal to the vertical synchronization period; and determining a second time point according to the seventh time period or the eighth time period, and increasing the operating frequency of the processor to the fourth frequency at the second time point.

Based on the implementation mode, when the frequency-raising time point is estimated to be too early, the mode of moving the frequency-raising time point of the processor backwards and reducing the frequency-raising amplitude of the processor can be adopted, so that the total time length for drawing and rendering the image frames is increased to one vertical synchronization period. Therefore, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, determining a second time point according to the target task amount, and frequency-boosting the processor at the second time point includes: determining a fifth time length of running at a first frequency and a sixth time length of running at a second frequency when the total time length is equal to the vertical synchronization period according to the target task quantity; the first frequency is the operating frequency before the processor frequency is increased, the second frequency is the default operating frequency after the processor frequency is increased, and the sum of the fifth time length and the sixth time length is equal to the vertical synchronization period; determining a first candidate time point according to the fifth time period or the sixth time period, and calculating first power consumption required by the processor for drawing and rendering a third image frame when the operating frequency of the processor is increased to a second frequency at the first candidate time point; determining a seventh time length of the processor running at the first frequency and an eighth time length of the processor running at the fourth frequency when the total time length is equal to the vertical synchronization period according to the target task amount; the fourth frequency is the running frequency after the frequency is increased by the processor with the aim of the fourth frequency, the fourth frequency is larger than the first frequency and smaller than the second frequency, and the sum of the seventh time length and the eighth time length is equal to the vertical synchronization period; determining a second candidate time point according to the seventh time period or the eighth time period, and calculating second power consumption required by the processor for drawing and rendering the third image frame when the operating frequency of the processor is increased to the fourth frequency at the second candidate time point; if the first power consumption is smaller than the second power consumption, determining the first candidate time point as a second time point, and increasing the operating frequency of the processor to a second frequency at the second time point; if the first power consumption is greater than the second power consumption, determining the second candidate point in time as a second point in time, and increasing the operating frequency of the processor to a fourth frequency at the second point in time.

By adopting the implementation mode, when the estimated frequency raising time point is too early, a frequency raising strategy with lower power consumption can be selected so as to reduce the power consumption of the equipment.

In one implementation, the method further comprises: if the first power consumption is equal to the second power consumption, the first candidate time point is determined as a second time point, and the operating frequency of the processor is increased to a second frequency at the second time point, or the second candidate time point is determined as a second time point, and the operating frequency of the processor is increased to a fourth frequency at the second time point.

In one implementation, the third frequency is determined by increasing at least one gear based on the second frequency.

In one implementation, the fourth frequency is determined by reducing at least one gear based on the second frequency.

In one implementation, frequency boosting a processor at a first point in time includes: starting a timer which times out at a first time point; and when the timer is overtime, triggering the frequency regulator of the processor to execute the frequency raising operation.

In a second aspect, an embodiment of the present application provides a parameter adjustment apparatus, including: the first acquisition module is used for acquiring a first time interval, wherein the first time interval is a time interval between the rendering completion time of a first image frame and the rendering completion time of a second image frame, the first image frame is the previous image frame of the second image frame, the second image frame is the previous image frame of a third image frame, and the third image frame is the image frame to be currently drawn and rendered by the electronic equipment; the second acquisition module is used for acquiring a target task amount if the first time interval is larger than the vertical synchronization period, wherein the target task amount is the task amount of a task for executing drawing and rendering a second image frame by a processor of the electronic equipment; the execution module is used for determining a first time point according to the target task quantity, and frequency-boosting the processor at the first time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period; the first time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and is earlier than a default frequency-raising time point of the processor.

In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, and a display screen; the memory stores program instructions that, when executed by the processor, cause the electronic device to perform the methods of the above aspects and their various implementations.

In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium having instructions stored therein, which when run on a computer, cause the computer to perform the methods of the above aspects and implementations thereof.

In a fifth aspect, embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods of the above aspects and their respective implementations.

In a sixth aspect, embodiments of the present application further provide a chip system, where the chip system includes a processor, and is configured to support the terminal device to implement the functions involved in the foregoing aspects, for example, generate or process information involved in the foregoing methods.

Drawings

FIG. 1 is a flow chart of an electronic device provided by an embodiment of the present application generating and displaying an image frame;

fig. 2 is a flowchart of generating an image frame by the electronic device according to the embodiment of the present application based on a vertical synchronization signal;

FIG. 3 is a schematic diagram showing the effect of the frequency boosting mode adopted to avoid frame loss at present;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 5 is a flowchart of a parameter adjustment method according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an electronic device drawing, rendering, and compositing a first image frame, a second image frame, and a third image frame;

FIG. 7a is a scene graph showing a second image frame without frame loss according to an embodiment of the present application;

FIG. 7b is a scene graph showing a second image frame loss according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a target task volume shown in an embodiment of the present application;

FIG. 9 is a schematic diagram of an electronic device determining a first point in time according to an embodiment of the present application;

fig. 10 is another schematic diagram of an electronic device according to an embodiment of the present application determining a first time point;

FIG. 11 is another flowchart of a parameter adjustment method according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of an electronic device determining a second point in time according to an embodiment of the present application;

FIG. 13 is another schematic diagram of an electronic device determining a second point in time provided in an embodiment of the present application;

fig. 14 is a schematic structural diagram of a mobile phone according to an embodiment of the present application.

Detailed Description

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

Electronic devices such as mobile phones, tablet computers, large-screen devices and the like can display content in a display screen, such as playing videos, playing man-machine interaction animations, displaying game pictures and the like. In general, contents displayed by an electronic device for a period of time are formed by constantly switching still images one by one. Where each still image is referred to as an image frame, the number of image frames that the display screen switches per second may be referred to as the refresh rate of the display screen, for example: a display screen with a refresh rate of 60Hz can play 60 image frames per second.

In general, each image frame needs to undergo drawing, rendering, compositing, and rendering of layers from generation to display. As shown in fig. 1, the electronic device may include: a UI thread 10 (e.g., UI thread), a rendering thread 20 (e.g., render thread), a composition process 30 (e.g., surface flinger), and a hardware display module 40.

The process of generating and displaying an image frame by the electronic device may include the following steps (1) -step (5):

step (1): UI thread 10 draws one or more layers contained in an image frame in preparation for rendering the required data.

Step (2): rendering thread 20 renders the layer drawn by UI thread 10, and after rendering is completed, the rendered layer is put into buffer queue.

Step (3): the composition process 30 obtains the rendered layer from the buffer queue, and composes the rendered layer to obtain an image frame, and sends the image frame to the hardware display module 40.

Step (4): the display panel drive of the hardware display module 40, such as an OLED drive, receives the image frames and sends the image frames to the display screen for display.

In the generation of each frame image, the drawing, rendering, and composition of the layers may be performed at a specified point in time, which may be controlled by a vertical synchronization signal. For example, the electronic device of the Android system may include a hardware synthesis (Hardware Composer, HWC) module in its hardware abstraction layer (Hardware Abstraction Layer, HAL). The HWC module is a hardware module, which is usually implemented by a device manufacturer, and is used to provide hardware support for a surface flinger process, so as to implement functions of layer synthesis, image frame display, and the like. For example, the HWC module may generate a vertical synchronization event (e.g., a Vsync event), generate at least one vertical synchronization signal based on the vertical synchronization event, e.g., such as: a first vertical synchronization signal and a second vertical synchronization signal. The first vertical synchronization signal may be, for example, a Vsync-APP signal, for controlling the timing of drawing and rendering of the layer; the second vertical synchronization signal may be, for example, a Vsync-sf signal, for controlling the timing of the composition of the layers.

The first vertical synchronization signal and the second vertical synchronization signal may be periodic signals. For example: the HWC module may initiate Vsync events once every one vertical synchronization period T by means of a timer interrupt and pass the Vsync events to the vertical synchronization DispSync thread. The DispSync thread may process the Vsync event to divide it into a first vertical synchronization signal and a second vertical synchronization signal, and thus, the vertical synchronization periods and phases of the first and second vertical synchronization signals may be the same. For example, at time t0, the DispSync thread generates a first vertical synchronization signal and a second vertical synchronization signal; after a vertical synchronization period T, at time T1, the DispSync thread generates a first vertical synchronization signal and a second vertical synchronization signal again; after a vertical synchronization period T, at time T2, the DispSync thread generates a first vertical synchronization signal and a second vertical synchronization signal again; and so on.

The vertical synchronization period T may be determined from the refresh rate of the display screen of the electronic device, typically the inverse of the refresh rate of the display screen. The screen refresh rate of the display screen of the electronic device may be any value of 1 hertz (Hz), 10Hz, 30Hz, 60Hz, 90Hz, 120Hz, etc. Taking the refresh rate of 60Hz as an example, the above synchronization period t=1/60=0.01667 seconds(s) = 16.667 milliseconds (ms).

It should be noted that the vertical synchronization signal may be named differently in different systems or architectures. For example, in some systems or architectures, the name of the vertical synchronization signal (i.e., the first vertical synchronization signal) used to trigger the drawing and rendering of a layer described above may not be Vsync-APP. However, no matter what the name of the vertical synchronization signal is, as long as the synchronization signal has similar functions, the method conforms to the technical idea of the method provided by the embodiment of the application, and the method is covered in the protection scope of the application.

As shown in fig. 2, at time t1, a first vertical synchronization signal arrives and the UI thread begins drawing one or more layers contained in the image frame in preparation for rendering the required data. Then, the rendering thread can render the layer drawn by the UI thread, and after the rendering is completed, the rendered layer is put into a buffer queue. Wherein the layers and rendering tasks may be performed by a processor (e.g., a central processing unit CPU) of the electronic device, invoking UI threads and rendering threads, and specific rendering and rendering tasks may be performed by the UI threads and rendering threads invoking a graphics processor GPU.

After the first vertical synchronization signal arrives, a synchronization period T is passed, and at the time T2, the second vertical synchronization signal arrives, the synthesis process obtains the rendered image layer from the buffer queue, synthesizes the rendered image layer to obtain an image frame, and sends the image frame to display. The synthesis task of the layer can be completed by the synthesis process preferentially calling the HWC module, and if the HWC module cannot complete the synthesis task, the synthesis process calls the GPU to complete the synthesis task.

It should be noted that, in the embodiment of the present application, the first vertical synchronization signal and the second vertical synchronization signal may be periodic discrete signals. Thus, the arrival of a vertical synchronization signal (e.g., the arrival of a first vertical synchronization signal or the arrival of a second vertical synchronization signal) refers to the arrival of a rising edge of the vertical synchronization signal.

It will be appreciated that a certain time is required from when the UI thread starts drawing the layer to when the rendering thread finishes rendering the layer, and therefore, the rendering thread may have finished rendering the layer when the second vertical synchronization signal arrives, and put the layer after rendering into the buffer queue BufferQueue, or may not finish rendering the layer when the second vertical synchronization signal arrives, and thus, not put the layer after rendering into the buffer queue BufferQueue. If the rendering thread has put the rendered image layer into the buffer queue when the second vertical synchronization signal arrives, the synthesizing thread can successfully acquire the rendered image layer from the buffer queue and complete the image layer synthesis and the image frame sending task, so that the image frame can be displayed in the display screen without frame loss. If the rendering thread does not put the rendered image layer into the buffer queue when the second vertical synchronization signal arrives, the composition thread cannot acquire the rendered image layer from the buffer queue, so that subsequent image frame composition and display task cannot be completed, and the image frame cannot be displayed in the display screen, so that the frame loss phenomenon occurs.

In general, the length of the drawing and rendering of a layer is related to the amount of drawing and rendering tasks and the speed of drawing and rendering, which is related to the operating frequency of the processor. Generally, for any one of the tasks of drawing and rendering, the higher the running frequency of the processor, the faster the drawing and rendering speed, the shorter the drawing and rendering duration, whereas the lower the running frequency of the processor, the slower the drawing and rendering speed, the longer the drawing and rendering duration.

In order to enable the rendering thread to complete rendering of the layer before the second vertical synchronization signal arrives, the composition process can buffer the layer of which the rendering is completed in the queue buffer queue, so that frame loss is avoided. At present, a frequency raising time point is set between a time t1 when a first vertical synchronous signal arrives and a time t2 when a second vertical synchronous signal arrives, and the electronic equipment can judge whether the layer rendering is completed or not at the frequency raising time point, if the layer rendering is not completed, the operating frequency of the processor is increased, for example, the working efficiency of the processor is increased from the original frequency F1 to the frequency F2, so that the drawing and rendering speeds are increased, and the drawing and rendering time is shortened.

Generally, for a certain vertical synchronization period, the corresponding frequency-up time point is fixed, and may be referred to as a default frequency-up time point. For example, when the vertical synchronization period is 16.667ms, the interval between the default frequency-raising time point and the first vertical synchronization signal is 12.667ms, and the interval between the default frequency-raising time point and the second vertical synchronization signal is 4ms.

Because the default frequency-raising time point is fixed, and the corresponding drawing and rendering task amounts of different image frames are possibly different, the frequency-raising mode currently has the problems of poor effect of avoiding frame loss and waste of power consumption. As shown in fig. 3, one case may be that the electronic device is at the default frequency-raising time point t _c The running frequency of the processor is increased from the frequency F1 to the frequency F2, but due to the fact that the residual task amount is large, the rendering thread still does not complete the rendering task when the second vertical synchronous signal arrives, so that the frame loss situation still occurs, and the effect of avoiding the frame loss is poor. Another case may be that the electronic device is at the default frequency raising time point t _c The operation frequency of the processor is increased from the frequency F1 to the frequency F2, and the rendering thread finishes the rendering task in advance before the second vertical synchronous signal arrives due to the small amount of the residual tasks, however, the processor still operates at a high frequency point after the rendering thread finishes the rendering task, so that the processor resource and the power consumption are wasted.

The embodiment of the application provides a parameter adjustment method which can be applied to electronic equipment.

The electronic device in the embodiment of the present application may be a mobile phone, a large-screen display device (such as an intelligent television), a mobile phone, a tablet computer, a desktop, a laptop, a handheld computer, a notebook, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a PDA (personal digital assistant), an augmented reality (augmented reality, AR) \virtual reality (VR) device, or an electronic device including a display screen, and the specific form of the electronic device is not particularly limited.

As shown in fig. 4, the electronic device 100 may include a processor 110, a memory 120, a universal serial bus (universal serial bus, USB) interface 130, a radio frequency circuit 140, a mobile communication module 150, a wireless communication module 160, a camera 170, a display 180, a touch sensor 190, an air pressure sensor 210, keys 220, and the like.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. The different processing units may be separate devices or may be integrated in one or more processors, for example, in a system on a chip (SoC). A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

Memory 120 may be used to store computer-executable program code that includes instructions. The memory 120 may include a stored program area and a stored data area. The storage program area may store an operating system, application programs (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. The storage data area may store data created during use of the electronic device 100 (e.g., audio data, phonebook, etc.), and so on. Further, the memory 120 may include one or more memory units, for example, may include volatile memory (volatile memory), such as: dynamic random access memory (dynamic random access memory, DRAM), static random access memory (static random access memory, SRAM), etc.; non-volatile memory (NVM) may also be included, such as: read-only memory (ROM), flash memory (flash memory), and the like. The processor 110 performs various functional applications and data processing of the electronic device 100 by executing instructions stored in the memory 120 and/or instructions stored in a memory provided in the processor.

It should be noted that, the operating system referred to in the embodiments of the present application includes, but is not limited to, an Android operating system, an IOS operating system, an iPad OS operating system, a Windows operating system, a Linux operating system, a MAC OS operating system, an embedded system, and the like.

The wireless communication functions of the electronic device 100 may be implemented by the radio frequency circuit 140, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The radio frequency circuit 140 may include at least one antenna 141 for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. In some embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G applications on the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 150 may receive electromagnetic waves from the antenna 141, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 may amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 141 to radiate the electromagnetic waves. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be provided in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (including but not limited to speakers, headphones, etc.) or displays images or video through the display 180. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 150 or other functional module, independent of the processor 110.

The wireless communication module 160 may include a wireless fidelity (wireless fidelity, wi-Fi) module, a Bluetooth (BT) module, a GNSS module, a near field communication technology (near field communication, NFC) module, an Infrared (IR) module, and the like. The wireless communication module 160 may be one or more devices integrating at least one of the modules described above. The wireless communication module 160 receives electromagnetic waves via the antenna 141, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 141.

In the embodiment of the present application, the wireless communication functions of the electronic device 100 may include, for example, functions of the global system for mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), fifth generation mobile communication technology new air interface (5th generation mobile networks new radio,5G NR), BT, GNSS, WLAN, NFC, FM, and/or IR. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The camera 170 is used to capture still images or video. The camera 170 includes a lens and a photosensitive element, and an object is projected to the photosensitive element by generating an optical image through the lens. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, RYYB, or the like format. In some embodiments, the electronic device 100 may include 1 or N cameras 170, N being a positive integer greater than 1.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent awareness of the electronic device 100 may be implemented by the NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.

The display 180 is used to display images, videos, and the like. The display 180 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), miniLED, microLED, micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the electronic device 100 may include 1 or N display screens 180, N being a positive integer greater than 1.

The touch sensor 190 is also referred to as a "touch device". The touch sensor 190 may be disposed on the display screen 180, and the touch sensor 190 and the display screen 180 form a touch screen, which is also referred to as a "touch screen". The touch sensor 190 is used to detect a touch operation acting thereon or thereabout. The touch sensor may communicate the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations may be provided through the display 180. In other embodiments, the touch sensor 190 may also be disposed on a surface of the electronic device 100 at a different location than the display 180.

The air pressure sensor 210 is used to measure air pressure. In some embodiments, the electronic device 100 calculates altitude from barometric pressure values measured by the barometric pressure sensor 210, aiding in positioning and navigation.

The keys 220 include a power-on key, a volume key, etc. The key 220 may be a mechanical key. Or may be a touch key. The electronic device 100 may receive key inputs, generating key signal inputs related to user settings and function controls of the electronic device 100.

It is to be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The embodiment of the application provides a parameter adjustment method, which can effectively avoid the frame loss phenomenon of electronic equipment when displaying images, and can not cause the waste of processor resources and power consumption.

As shown in fig. 5, the parameter adjustment method may include the steps of:

in step S101, the electronic device obtains a first time interval, where the first time interval is a time interval between a time when the rendering of the first image frame is completed and a time when the rendering of the second image frame is completed, the first image frame is a previous image frame of the second image frame, the second image frame is a previous image frame of a third image frame, and the third image frame is an image frame currently drawn and rendered by the electronic device.

It should be noted that, in the embodiment of the present application, a drawing image frame may be understood as one or more image layers included in the drawing image frame, a rendering image frame may be understood as rendering one or more image layers of the image frame, and a synthesizing image frame may be understood as synthesizing one or more image layers of the rendered image frame. In the following embodiments, one or more layers of the rendering-completed image frame may also be simply referred to as the rendering-completed image frame. The task of drawing the image frames can be realized by a processor calling a UI thread, the task of rendering the image frames can be realized by a processor calling a rendering thread, and the task of synthesizing the image frames can be realized by a processor calling a rendering process.

The manner of determining the "first image frame rendering completion time", the "second image frame rendering completion time", and the "first time interval" will be specifically described below with reference to fig. 6.

As shown in fig. 6, the electronic device may generate a vertical synchronization signal according to a preset vertical synchronization period T, for example: a first vertical synchronization signal and a second vertical synchronization signal. For example, at a first time T1, the electronic device generates a first vertical synchronization signal and a second vertical synchronization signal, and after one vertical synchronization period T, at a second time T2, the electronic device generates the first vertical synchronization signal and the second vertical synchronization signal again; after a further vertical synchronization period T, at a third time T3, the electronic device generates the first vertical synchronization signal and the second vertical synchronization signal again. The third time t3 may be the current time.

Wherein at the time of arrival of each of the first vertical synchronization signal and the second vertical synchronization signal, the electronic device may render and render a new image frame in response to the first vertical synchronization signal and synthesize a previous image frame in response to the second vertical synchronization signal. For example:

at a first time t1, the electronic device begins drawing and rendering a first image frame in response to a first vertical synchronization signal. Wherein, from the first time t1, after a period of time, the first image frame is rendered at a time after the first time t1, and the rendered first image frame is stored in the buffer queue, and the electronic device can record the time as t _qend1 ，t _qend1 I.e., the "first image frame rendering completion time".

At a second time t2, the electronic device fetches the rendered first image frame from the buffer queue BufferQueue in response to the second vertical synchronization signal and starts to compose the first image frame, and starts to draw and render the second image frame in response to the first vertical synchronization signal. Wherein, from the second time t2, after a period of drawing and rendering, the second image frame is rendered at a time after the second time t2, and the rendered second image frame is stored in the buffer queue, and the electronic device can record the time as t _qend2 ，t _qend2 I.e. "second image frame rendering completion time".

At a third time t3, the electronic device fetches the rendered second image frame from the buffer queue BufferQueue in response to the second vertical synchronization signal and starts synthesizing the second image frame, and starts drawing and rendering the third image frame in response to the first vertical synchronization signal.

Thus, for a first time interval Δqend, there is:

Δqend＝t _qend2 -t _qend1

in step S102, the electronic device determines whether the first time interval is greater than the vertical synchronization period.

In this embodiment of the present application, the electronic device may determine whether frame loss occurs in the second image frame according to the numerical relationship between the first time interval and the vertical synchronization period T; if the first time interval is greater than the vertical synchronization period T, the electronic device can consider that the second image frame is lost; if the first time interval is less than or equal to the vertical synchronization period T, the electronic device may consider that no frame loss occurs in the second image frame. The occurrence of frame loss of the second image frame refers to that the electronic device fails to acquire the rendered second image frame from the buffer queue at the third time t3, so that the second image frame cannot be synthesized, and finally the second image frame cannot be displayed in the display screen.

Fig. 7a is a scene graph showing that no frame loss occurs in the second image frame according to the embodiment of the present application.

Fig. 7b is a scene graph of a second image frame loss according to an embodiment of the present application.

The following specifically describes a technical principle of determining whether the second image frame is lost according to a numerical relationship between the first time interval and the vertical synchronization period T by the electronic device with reference to fig. 7a and fig. 7 b.

As shown in fig. 7a, at a first time t1, the electronic device starts drawing and rendering a first image frame in response to a first vertical synchronization signal, at a second time t2 or t before the second time t2 _qend1 And finishing rendering the first image frame at the moment, and storing the rendered first image frame into a buffer queue before the second moment t2 or the second moment t 2.

At a second time t2, the electronic device responds to the second vertical synchronization signal and fetches the first image frame which is completely rendered from the buffer queue BufferQueue. At the second time t2, the rendered first image frame is already stored in the buffer queue, so that the electronic device can successfully acquire the rendered second image frame, perform the combining and display task, and the first image frame cannot be lost.

At a second time t2, the electronic device also starts drawing and rendering a second image frame in response to the first vertical synchronization signal, at a third time t3 or t before the third time t3 _qend2 And finishing rendering the second image frame at the moment, and storing the rendered second image frame into a buffer queue before the third moment t3 or the third moment t3. At this time, t _qend2 Time and t _qend1 The duration between moments is less than or equal to the vertical synchronization period T.

At a third time t3, the electronic device responds to the second vertical synchronization signal and fetches the second image frame which is completely rendered from the buffer queue BufferQueue. At the third time t3, the rendered second image frame is already stored in the buffer queue, so that the electronic device can successfully acquire the rendered second image frame and execute the tasks of combining and transmitting and displaying, and the second image frame cannot be lost.

It can be appreciated that since the first time T1 and the second time T2 differ by one vertical synchronization period T, T _qend1 The moment is equal to or earlier than the second moment t2, and therefore, when t _qend2 Time and t _qend1 When the time length between the moments is less than or equal to the vertical synchronization period T, T _qend2 The moment is necessarily earlier than or equal to the third moment t3. It can be seen that as long as t _qend2 Time and t _qend1 The time length between the moments is smaller than or equal to the vertical synchronization period T, and the electronic device can store the rendered second image frame into the buffer queue before the third moment T3 or the third moment T3, so that the second image frame is ensured not to be lost.

As shown in fig. 7b, at a first time t1, the electronic device starts drawing and rendering a first image frame in response to a first vertical synchronization signal, at a second time t2 or t before the second time t2 _qend1 Rendering the first image frame is completed at the moment, and at the second moment t2 or the second momentAnd storing the rendered first image frame into a buffer queue before t 2.

At a second time t2, the electronic device also begins drawing and rendering a second image frame in response to the first vertical synchronization signal, at t _qend2 Rendering the second image frame is completed at the moment. Wherein, when t _qend2 Time and t _qend1 When the time length between the moments is longer than the vertical synchronization period T, T _qend2 The moment may be later than the third moment t3. That is, the electronic device has not completed rendering the second image frame at the third time t3, in which case, the electronic device cannot store the rendered second image frame in the buffer queue BufferQueue before the third time t3 or before the third time t3.

At a third time t3, the electronic device responds to the second vertical synchronization signal to execute an action of fetching the rendered second image frame from the buffer queue BufferQueue. At the third time t3, the rendered second image frame is not stored in the buffer queue, so the electronic device cannot acquire the rendered second image frame, and further cannot synthesize the second image frame, which results in frame loss of the second image frame.

Based on the discussion of fig. 7a and 7b above, it can be concluded that: in the case that the first image frame is not lost, when t _qend2 Time and t _qend1 When the time length between the moments is less than or equal to the vertical synchronization period T, the second image frame will not lose frame, when T _qend2 Time and t _qend1 When the duration between the moments is longer than the vertical synchronization period T, frame loss may occur in the second image frame. Thus, embodiments of the present application may convert t _qend2 Time and t _qend1 The duration between the moments (i.e., the first time interval) is compared with the vertical synchronization period T to determine whether a frame loss of the second image frame occurs.

Step S103, if the first time interval is greater than the vertical synchronization period, the electronic device obtains a target task amount, where the target task amount is a task amount of the processor of the electronic device for executing the task of drawing and rendering the second image frame.

Generally, for adjacent image frames, such as the second image frame and the third image frame, the task amounts of drawing and rendering are substantially the same, and thus, the target task amount may also be the estimated task amount of the processor performing the task of drawing and rendering the third image frame.

The manner in which the electronic device obtains the target task amount is exemplarily described below with reference to the accompanying drawings.

As shown in fig. 8, at a second time t2, the processor begins to call the UI thread and the rendering thread to draw and render a second image frame, at which point the processor initially operates at the first frequency F1. The processor operates at a first frequency F1 for a duration DeltaT ₁ After that, the frequency-boosting time point is reached. At this time, if the rendering task is not completed, the processor performs an frequency up operation to increase the operating frequency from the first frequency F1 to the second frequency F2. The processor operates at the second frequency F2 for a further period of time DeltaT ₂ Thereafter, the rendering task is completed. The first frequency F1 is an operating frequency before the processor frequency is increased, and the second frequency F2 is a default operating frequency after the processor frequency is increased.

Wherein the total time length T consumed for drawing and rendering the second image frame _qend Is a known quantity, is the rendering completion time t for the second image frame _qend2 The difference from the second instant t2, namely: t (T) _qend ＝t _qend2 -t2。

At the same time T _qend Is also equal to delta T ₁ And DeltaT ₂ The sum is that:

T _qend ＝ΔT ₁ +ΔT ₂ formula (1)

The frequency-raising time point can be a fixed default frequency-raising time point t _c For example: when the vertical synchronization period T is 16.667ms,determining the time 4ms before the third time t3 as a default frequency-raising time point t _c At this time, deltaT ₁ T-4 ms= 12.667ms. In addition, if the electronic device has previously performed the method according to the embodiments of the present application, the frequency-raising time point may also be a previously determined time point, for example, the first time point t _u1 Second time point t _u2 Etc. At determining DeltaT ₁ Then, Δt can be determined based on equation (1) ₂ 。

Wherein the amount of tasks that the processor performs over a period of time may be represented by the product of the time period and the frequency. Then, the calculation formula of the target Task amount Task may be:

Task＝ΔT ₁ ×F1+ΔT ₂ XF 2 formula (2)

Step S104, the electronic device determines a first time point according to the target task amount, and frequency-increases the processor at the first time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period, wherein the first time point is a time point after the third image frame starts to be drawn and before the third image frame finishes being rendered, and the first time point is earlier than a default frequency-increasing time point of the processor.

Fig. 9 is a schematic diagram of determining a first time point by the electronic device according to the embodiment of the present application.

As shown in fig. 9, in one implementation, the electronic device may determine a first point in time t based on the target Task amount Task, the first frequency F1, and the second frequency F2 _u1 And a first time point t _u1 Earlier than the default frequency-raising time point t of the processor _c The total time length of drawing and rendering the third image frames is reduced by only advancing the frequency raising time point of the processor under the condition that the frequency raising amplitude of the processor is not changed, so that the total time length of drawing and rendering the third image frames is equal to the vertical synchronization period T, the rendering thread just completes the rendering at the moment when the next second vertical synchronization signal arrives (namely, the fourth moment T4), and the rendered third image frames are stored in the buffer queue, so that the synthesizing process can successfully acquire the rendered third image frames from the buffer queue, and the synthesizing task is executed, thereby avoiding And the third image frame is lost.

To achieve this effect, it should be: at a third time t3, the processor begins to call the UI thread and the rendering thread to draw and render a third image frame, at which point the processor initially operates at the first frequency F1. The processor operates at a first frequency F1 for a duration DeltaT ₁ After' reaching the first time point t _u1 . At this time, the processor performs an frequency raising operation to raise the operating frequency from the first frequency F1 to the second frequency F2. The processor operates at the second frequency F2 for a further period of time DeltaT ₂ After' a fourth time t4 (i.e. the time when the next vertical synchronization signal arrives) is reached, the rendering task is completed.

Then, for the target Task amount Task, there should be:

Task＝ΔT ₁ ’×F1+ΔT ₂ ' x F2 formula (3)

For the vertical synchronization period T, there should be:

T＝ΔT ₁ ’+ΔT ₂ ' formula (4)

Wherein the target Task amount Task, the first frequency F1 and the second frequency F2 are all known amounts, then the simultaneous equations (3) (4) can determine DeltaT ₁ ' and DeltaT ₂ ' value, thereby determining a first point in time t _u1 。

For example, the time period DeltaT may be based ₁ ' determining a first time point t _u1 The method comprises the following steps:

t _u1 ＝t3+ΔT ₁ ’

alternatively, the time duration DeltaT may be based ₂ ' determining a first time point t _u1 The method comprises the following steps:

t _u1 ＝t4-ΔT ₂ ’

compared with the traditional scheme that the operating frequency of the processor is increased at the fixed frequency increasing time point, the method of the embodiment of the application can adaptively advance the frequency increasing time point of the processor according to the task quantity of drawing and rendering the image frames when the tasks of drawing and rendering the image frames cannot be completed in time and the frame dropping risk exists due to the fact that the frequency increasing time point is too late, so that the operating frequency of the processor is increased earlier, and the total duration of drawing and rendering the image frames is shortened to be a vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

Fig. 10 is another schematic diagram of determining a first time point by using the electronic device according to the embodiment of the present application.

As shown in fig. 10, in one implementation, the electronic device may determine a third frequency F3 based on the second frequency F2, and use the third frequency F3 as the operating frequency after the frequency is raised by the processor. Wherein the third frequency F3 is greater than the second frequency F2. For example, the electronic device may set a plurality of gears for the operating frequency of the processor, such as 250MHz, 500MHz, 750MHz, 1000MHz, 1250MHz, 1500MHz, 1750MHz, 2000MHz, and the like. The first frequency F1 and the second frequency F2 may be frequencies in any of the above gears. In this case, the second frequency F2 may be increased by one or more shift steps as the third frequency F3. For example: when the first frequency F1 is 500MHz and the second frequency F2 is 1500MHz, the second frequency F2 may be increased by one gear, and the third frequency F3 is 1750MHz.

In one example, the electronic device may increase the second frequency F3 by a certain proportion to obtain the third frequency F3. For example, the second frequency F2 is increased by 10%, 20%, or the like, which is not particularly limited in the embodiment of the present application.

In one implementation, for drawing and rendering tasks of image frames, the electronic device may set an upper threshold for the operating frequency of the processor, and when the second frequency F2 is below the upper threshold, the processor may determine a third frequency F3, and the third frequency F3 is not above the upper threshold to ensure that the processor does not heat up due to the operating frequency being too high.

Next, the electronic device may determine a first point in time t based on the target Task amount Task, the first frequency F1, and the third frequency F3 _u1 And a first time point t _u1 Earlier than the default frequency-raising time point t of the processor _c The total time length for drawing and rendering the third image frame is reduced by increasing the frequency increasing amplitude of the processor and advancing the frequency increasing time point of the processor, so that the drawing and the rendering are performedThe total duration of the third image frame is equal to the vertical synchronization period T.

To achieve this, it should be: at a third time t3, the processor begins to call the UI thread and the rendering thread to draw and render a third image frame, at which point the processor initially operates at the first frequency F1. The processor operates at a first frequency F1 for a duration DeltaT ₃ After' reaching the first time point t _u1 . At this time, the processor performs an frequency boosting operation to boost the operating frequency from the first frequency F1 to the third frequency F3. The processor operates again at a third frequency F3 for a further period of time deltat ₄ After' a fourth time t4 is reached, the rendering task is completed.

Then, for the target Task amount Task, there should be:

Task＝ΔT ₃ ’×F1+ΔT ₄ ' x F3 formula (5)

For the vertical synchronization period T, there should be:

T＝ΔT ₃ ’+ΔT ₄ ' formula (6)

Wherein the target Task amount Task, the first frequency F1 and the third frequency F3 are all known amounts, then the simultaneous equations (5) (6) can determine DeltaT ₃ ' and DeltaT ₄ ' value, thereby determining a first point in time t _u1 。

For example, the time period DeltaT may be based ₃ ' determining a first time point t _u1 The method comprises the following steps:

t _u1 ＝t3+ΔT ₃ ’

alternatively, the time duration DeltaT may be based ₄ ' determining a first time point t _u1 The method comprises the following steps:

t _u1 ＝t4-ΔT ₄ ’

compared with the traditional scheme that the operating frequency of the processor is increased at the fixed frequency increasing time point, the method of the embodiment of the application can adaptively advance the frequency increasing time point of the processor according to the task quantity of drawing and rendering the image frames when the frame dropping risk exists because the task of drawing and rendering the image frames cannot be completed in time due to the fact that the frequency increasing time point is too late, so that the operating frequency of the processor is increased earlier, the frequency increasing amplitude of the processor is increased, and the total duration of drawing and rendering the image frames is shortened to be a vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In the above embodiments, the processing manner in which the third image frame has the frame dropping risk, that is, the first time interval is greater than the vertical synchronization period is described. It will be appreciated that when the first time interval is less than or equal to the vertical synchronization period, the third image frame may not be lost, but processor resources and power consumption may be wasted. The following are specific examples of several cases:

as shown in FIG. 7b, if t _qend Time 1 is equal to or earlier than the second time T2 and the first time interval deltaqend is smaller than the vertical synchronization period T, then T _qend2 The instant will be earlier than the third instant t3. In this case, the processor is in _tqend2 Although the rendering thread is not called to execute the rendering task between the time and the third time t3, the rendering thread still runs at the frequency after frequency boosting, so that the waste of processor resources and power consumption is caused.

In order to avoid the waste of processor resources and power consumption, as shown in fig. 11, the embodiment of the present application provides a parameter adjustment method, after step S102, further includes the following steps S105-S106.

In step S105, if the first time interval is less than or equal to the vertical synchronization period, the electronic device obtains the target task amount.

Due to the first frequency F1, the second frequency F2, and the duration DeltaT ₁ And duration DeltaT ₂ The target task amount is also calculated based on the formulas (1) and (2) when the first time interval is less than or equal to the vertical synchronization period T, and will not be described here.

Step S106, the electronic device determines a second time point according to the target task amount, and frequency-increases the processor at the second time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period, wherein the second time point is a time point after the third image frame starts to be drawn and before the third image frame finishes being rendered, and the second time point is later than the default frequency-increasing time point of the processor.

Fig. 12 is a schematic diagram of an electronic device according to an embodiment of the present application determining a second time point.

As shown in fig. 12, in one implementation, the electronic device may determine a second point in time t based on the target Task amount Task, the first frequency F1, and the second frequency F2 _u2 And a second time point t _u2 Later than the default frequency-raising time point t of the processor _c The total duration of drawing and rendering the third image frame is equal to the vertical synchronization period T by increasing the total duration of drawing and rendering the third image frame only by moving the frequency-raising time point of the processor backwards under the condition that the frequency-raising amplitude of the processor is not changed.

To achieve this, it should be: at a third time t3, the processor begins to call the UI thread and the rendering thread to draw and render a third image frame, at which point the processor initially operates at the first frequency F1. The processor operates at a first frequency F1 for a duration DeltaT ₅ After' reaching the second point in time t _u2 . At this time, the processor performs an frequency raising operation to raise the operating frequency from the first frequency F1 to the second frequency F2. The processor operates at the second frequency F2 for a further period of time DeltaT ₆ After' a fourth time t4 is reached, the rendering task is completed.

Then, for the target Task amount Task, there should be:

Task＝ΔT ₅ ’×F1+ΔT ₆ ' x F2 formula (7)

For the vertical synchronization period T, there should be:

T＝ΔT ₅ ’+ΔT ₆ ' formula (8)

Wherein the target Task amount Task, the first frequency F1 and the second frequency F2 are all known amounts, then the simultaneous equations (7) (8) can determine DeltaT ₅ ' and DeltaT ₆ ' value, thereby determining a second point in time t _u2 。

For example, the time period DeltaT may be based ₅ ' determining the second time point t _u2 The method comprises the following steps:

t _u2 ＝t3+ΔT ₅ ’

alternatively, time-basedLong delta T ₆ ' determining the second time point t _u2 The method comprises the following steps:

t _u2 ＝t4-ΔT ₆ ’

compared with the traditional scheme that the operating frequency of the processor is increased at the fixed frequency increasing time point, the method provided by the embodiment of the application has the advantages that when the frequency increasing time point is estimated to be too early, the task of drawing and rendering the image frames is completed too early, and the waste of processor resources and power consumption is caused, the frequency increasing time point of the processor can be adaptively moved backwards according to the task quantity of drawing and rendering the image frames, so that the speed of drawing and rendering the image frames is reduced, and the total duration of drawing and rendering the image frames is increased to a vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

Fig. 13 is another schematic diagram of an electronic device according to an embodiment of the present application to determine a second time point.

As shown in fig. 13, in one implementation, the electronic device may determine a fourth frequency F4 based on the second frequency F2, and use the fourth frequency F4 as the operating frequency after the frequency boosting by the processor. The fourth frequency F4 is greater than the first frequency F1 and less than the second frequency F2. For example, the electronic device may set a plurality of gears for the operating frequency of the processor, such as 250MHz, 500MHz, 750MHz, 1000MHz, 1250MHz, 1500MHz, 1750MHz, 2000MHz, and the like. The first frequency F1 and the second frequency F2 may be frequencies in any of the above gears. In this case, the second frequency F2 may be lowered by one or more shift steps as the fourth frequency F4. For example: when the first frequency F1 is 500MHz and the second frequency F2 is 1500MHz, the second frequency F2 may be lowered by one gear, and the fourth frequency F4 may be determined to be 1250MHz.

In one example, the electronic device may reduce the second frequency F2 by a certain proportion to obtain a fourth frequency F4. For example, the second frequency F2 is reduced by 10%, 20%, or the like, which is not particularly limited in the embodiment of the present application.

Next, the electronic device may determine a second point in time t based on the target Task amount Task, the first frequency F1, and the fourth frequency F4 _u2 And a second time point t _u2 Later than the default frequency-raising time point t of the processor _c The total duration of drawing and rendering the third image frame is increased in a mode of reducing the frequency increasing amplitude of the processor and moving the frequency increasing time point of the processor backwards, so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period T.

To achieve this, it should be: at a third time t3, the processor begins to call the UI thread and the rendering thread to draw and render a third image frame, at which point the processor initially operates at the first frequency F1. The processor operates at a first frequency F1 for a duration DeltaT ₇ After' reaching the second point in time t _u2 . At this time, the processor performs an frequency raising operation to raise the operating frequency from the first frequency F1 to the fourth frequency F4. The processor operates at a fourth frequency F4 for a further duration deltat ₈ After' a fourth time t4 is reached, the rendering task is completed.

Then, for the target Task amount Task, there should be:

Task＝ΔT ₇ ’×F1+ΔT ₈ ' x F4 formula (9)

For the vertical synchronization period T, there should be:

T＝ΔT ₇ ’+ΔT ₈ ' formula r

Wherein the target Task amount Task, the first frequency F1 and the fourth frequency F4 are all known amounts, and then the delta T can be determined by the simultaneous expression (9) d ₇ ' and DeltaT ₈ ' value, thereby determining a second point in time t _u2 。

For example, the time period DeltaT may be based ₇ ' determining the second time point t _u2 The method comprises the following steps:

t _u2 ＝t3+ΔT ₇ ’

alternatively, the time duration DeltaT may be based ₈ ' determining the second time point t _u2 The method comprises the following steps:

t _u2 ＝t4-ΔT ₈ ’

compared with the traditional scheme that the operating frequency of the processor is increased at the fixed frequency increasing time point, the method provided by the embodiment of the application has the advantages that when the frequency increasing time point is estimated to be too early, the task of drawing and rendering the image frames is completed too early, and the waste of processor resources and power consumption is caused, the frequency increasing time point of the processor can be adaptively moved backwards according to the task quantity of drawing and rendering the image frames, the frequency increasing amplitude of the processor is reduced, the speed of drawing and rendering the image frames is reduced, and the total duration of drawing and rendering the image frames is increased to be one vertical synchronization period. Thus, the frame loss phenomenon is effectively avoided, and the waste of processor resources and power consumption is avoided.

In one implementation, the electronic device may determine the second time point t using a method corresponding to fig. 13 _u2 Taking it as a first candidate point in time and calculating a first power consumption P1 consumed by the processor for drawing and rendering the third image frame when the operating frequency of the processor is raised to the second frequency at the first candidate point in time F2. In addition, the electronic device may determine the second time point t by using a method corresponding to fig. 14 _u2 Taking it as a second candidate point in time and calculating a second power consumption P2 consumed by the processor for drawing and rendering the third image frame when the operating frequency of the processor is raised to the fourth frequency at the second candidate point in time F4.

Next, the electronic device may compare the first power consumption P1 and the second power consumption P2, and perform processor frequency boosting at a frequency boosting time point corresponding to the lower power consumption. For example: if the first power consumption P1 is smaller than the second power consumption P2, determining the first candidate time point as the second time point t _u2 And at a second point in time t _u2 The operating frequency of the processor is raised to a second frequency F2. If the first power consumption P1 is greater than the second power consumption P2, determining a second candidate time point as a second time point t _u2 And at a second point in time t _u2 The operating frequency of the processor is raised to a fourth frequency F4. If the first power consumption P1 is smaller than the second power consumption P2, the first candidate time point can be determined as the second time point t _u2 And at a second point in time t _u2 The operating frequency of the processor is increased to a second frequency F2, and a second candidate time point can be determined as a second time point t _u2 And at a second point in time t _u2 The operating frequency of the processor is raised to a fourth frequency F4.

In one implementation, after determining the first time point or the second time point, the electronic device may start a timer that times out at the first time point or the second time point at a third time point (i.e., a time point when the UI thread starts drawing the third image frame in response to the first vertical synchronization signal). Thus, when the frequency boosting time point arrives, the timer times out, and a frequency regulator (such as a CPU (Central processing Unit)) of the processor is triggered to execute the frequency boosting operation. In addition, the electronic device may also use the rendering completion time t of the second image frame _qend2 As a starting point, determining the duration of the timer and at time t _qend2 The timer is started, and the frequency raising operation of the processor can be triggered when the timer is overtime.

The above description has been made mainly from the point of view of the electronic device. It will be appreciated that the electronic device, in order to achieve the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that a parameter tuning method step of the examples described in connection with the embodiments disclosed herein may be implemented as hardware or a combination of hardware and computer software. Whether a function is implemented as hardware or electronic device software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the present application may divide the functional modules or functional units of the electronic device according to the above method examples, for example, each functional module or functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware, or in software functional modules or functional units. The division of the modules or units in the embodiments of the present application is merely a logic function division, and other division manners may be implemented in practice.

Other embodiments of the present application provide an electronic device, which may be, for example, a mobile phone. As shown in fig. 14, the electronic device may include: a display 1001, a memory 1002, a processor 1003, and a communication module 1004. The devices described above may be connected by one or more communication buses 1005. The display screen 1001 may include a display panel 10011 and a touch sensor 10012, wherein the display panel 10011 is configured to display an image and the touch sensor 10012 may communicate a detected touch operation to an application processor to determine a touch event type and provide visual output related to the touch operation through the display panel 10011. The processor 1003 may include one or more processing units, such as: the processor 1003 may include an application processor, a modem processor, a graphics processor, an image signal processor, a controller, a video codec, a digital signal processor, a baseband processor, and/or a neural network processor, etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. Memory 1002 is coupled to processor 1003 for storing various software programs and/or computer instructions, and memory 1002 may include volatile memory and/or non-volatile memory. When the processor executes the computer instructions, the electronic device may perform the functions or steps performed by the mobile phone in the above-described method embodiments.

The embodiment of the application provides a parameter adjusting device. The device comprises: the first acquisition module is used for acquiring a first time interval, wherein the first time interval is a time interval between the rendering completion time of a first image frame and the rendering completion time of a second image frame, the first image frame is the previous image frame of the second image frame, the second image frame is the previous image frame of a third image frame, and the third image frame is the image frame to be currently drawn and rendered by the electronic equipment; the second acquisition module is used for acquiring a target task amount if the first time interval is larger than the vertical synchronization period, wherein the target task amount is the task amount of a task for executing drawing and rendering a second image frame by a processor of the electronic equipment; the execution module is used for determining a first time point according to the target task quantity, and frequency-boosting the processor at the first time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period; the first time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and is earlier than a default frequency-raising time point of the processor.

Embodiments of the present application also provide a chip system including at least one processor and at least one interface circuit. The processors and interface circuits may be interconnected by wires. For example, the interface circuit may be used to receive signals from other devices (e.g., a memory of an electronic apparatus). For another example, the interface circuit may be used to send signals to other devices. The interface circuit may, for example, read instructions stored in the memory and send the instructions to the processor. The instructions, when executed by the processor, may cause the electronic device to perform the various steps of the embodiments described above. Of course, the chip system may also include other discrete devices, which are not specifically limited in this embodiment of the present application.

Embodiments of the present application also provide a computer-readable storage medium that includes computer instructions that, when executed on an electronic device (e.g., the electronic device 100 shown in fig. 4), cause the electronic device to perform the functions or steps performed by the mobile phone in the method embodiments described above.

The embodiment of the application also provides a computer program product, which when run on a computer, causes the computer to execute the functions or steps executed by the mobile phone in the embodiment of the method.

It will be apparent to those skilled in the art from this description that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another apparatus, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and the parts shown as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a device (may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a specific embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A parameter adjustment method applied to an electronic device that generates a first vertical synchronization signal and a second vertical synchronization signal in a preset vertical synchronization period, and draws and renders a new image frame in response to the first vertical synchronization signal and synthesizes a previous image frame in response to the second vertical synchronization signal at a timing when each of the first vertical synchronization signal and the second vertical synchronization signal arrives, the method comprising:

acquiring a first time interval, wherein the first time interval is a time interval between a first image frame rendering completion time and a second image frame rendering completion time, the first image frame is a previous image frame of the second image frame, the second image frame is a previous image frame of a third image frame, and the third image frame is an image frame to be currently drawn and rendered by the electronic equipment;

If the first time interval is greater than the vertical synchronization period, acquiring a target task amount, wherein the target task amount is the task amount of the processor of the electronic equipment for executing the task of drawing and rendering the second image frame;

determining a first time point according to the target task amount, and frequency-boosting the processor at the first time point so that the total duration of drawing and rendering the third image frame is equal to the vertical synchronization period; the first time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and is earlier than a default frequency-increasing time point of the processor.

2. The method of claim 1, wherein determining a target frequency-boosting time point according to the target task amount, and frequency-boosting the processor at the target frequency-boosting time point, comprises:

determining a first duration of operation of the processor at a first frequency and a second duration of operation at a second frequency when the total duration is equal to the vertical synchronization period according to the target task amount; the first frequency is the operating frequency before the processor frequency is increased, the second frequency is the default operating frequency after the processor frequency is increased, and the sum of the first duration and the second duration is equal to the vertical synchronization period;

And determining the first time point according to the first time length or the second time length, and raising the operating frequency of the processor to the second frequency at the first time point.

3. The method of claim 1, wherein determining a target frequency-boosting time point according to the target task amount, and frequency-boosting the processor at the target frequency-boosting time point, comprises:

determining a third duration of operation of the processor at the first frequency and a fourth duration of operation at the third frequency when the total duration is equal to the vertical synchronization period according to the target task amount; the first frequency is an operation frequency before the processor frequency is increased, the third frequency is an operation frequency after the processor frequency is increased, the third frequency is larger than the second frequency, the second frequency is a default operation frequency after the processor frequency is increased, and the sum of the third duration and the fourth duration is equal to the vertical synchronization period;

and determining the first time point according to the third time period or the fourth time period, and raising the operating frequency of the processor to the third frequency at the first time point.

4. A method according to any one of claims 1-3, wherein the method further comprises:

if the first time interval is larger than the vertical synchronization period, acquiring the target task quantity;

determining a second time point according to the target task quantity, and frequency-boosting the processor at the second time point so that the total duration is equal to the vertical synchronization period; the second time point is a time point after the third image frame starts to be drawn and before the third image frame is completely rendered, and is later than a default frequency-raising time point of the processor.

5. The method of claim 4, wherein determining a second point in time based on the target task volume and frequency boosting the processor at the second point in time comprises:

determining a fifth time period for the processor to operate at a first frequency and a sixth time period for the processor to operate at a second frequency when the total time period is equal to the vertical synchronization period according to the target task amount; the first frequency is an operation frequency before the processor frequency is increased, the second frequency is a default operation frequency after the processor frequency is increased, and the sum of the fifth duration and the sixth duration is equal to the vertical synchronization period;

And determining the second time point according to the fifth time period or the sixth time period, and increasing the operating frequency of the processor to the second frequency at the second time point.

6. The method of claim 4, wherein determining a second point in time based on the target task volume and frequency boosting the processor at the second point in time comprises:

determining a seventh time period for the processor to operate at a first frequency and an eighth time period for the processor to operate at a fourth frequency when the total time period is equal to the vertical synchronization period according to the target task amount; the first frequency is an operation frequency before the processor frequency raising, the fourth frequency is an operation frequency after the processor frequency raising, the fourth frequency is larger than the first frequency and smaller than a second frequency, the second frequency is a default operation frequency after the processor frequency raising, and the sum of the seventh time length and the eighth time length is equal to the vertical synchronization period;

and determining the second time point according to the seventh time period or the eighth time period, and increasing the operating frequency of the processor to the fourth frequency at the second time point.

7. The method of claim 4, wherein determining a second point in time based on the target task volume and frequency boosting the processor at the second point in time comprises:

determining a first candidate time point according to the fifth time length or the sixth time length, and calculating first power consumption required by the processor for drawing and rendering the third image frame when the operating frequency of the processor is increased to the second frequency at the first candidate time point;

determining a seventh time period for the processor to operate at a first frequency and an eighth time period for the processor to operate at a fourth frequency when the total time period is equal to the vertical synchronization period according to the target task amount; the fourth frequency is the running frequency of the processor after frequency boosting, the fourth frequency is larger than the first frequency and smaller than the second frequency, and the sum of the seventh duration and the eighth duration is equal to the vertical synchronization period;

Determining a second candidate time point according to the seventh time length or the eighth time length, and calculating a second power consumption required by the processor to draw and render the third image frame when the operating frequency of the processor is increased to the fourth frequency at the second candidate time point;

determining the first candidate point in time as the second point in time if the first power consumption is less than the second power consumption, and increasing the operating frequency of the processor to the second frequency at the second point in time;

and if the first power consumption is greater than the second power consumption, determining the second candidate time point as the second time point, and increasing the operating frequency of the processor to the fourth frequency at the second time point.

8. The method of claim 7, wherein the method further comprises:

and if the first power consumption is equal to the second power consumption, determining the first candidate time point as the second time point, and increasing the operating frequency of the processor to the second frequency at the second time point, or determining the second candidate time point as the second time point, and increasing the operating frequency of the processor to the fourth frequency at the second time point.

9. A method according to claim 3, wherein the third frequency is determined by increasing at least one gear on the basis of the second frequency.

10. The method of claim 6, wherein the fourth frequency is determined by reducing at least one gear based on the second frequency.

11. A method according to any one of claims 1-3, wherein said frequency boosting the processor at the first point in time comprises:

starting a timer which times out at the first time point;

and triggering a frequency regulator of the processor to execute frequency raising operation when the timer times out.

12. A method according to any of claims 1-3, wherein the target task volume is a sum of a product of a duration of operation of the processor at a first frequency and a product of a duration of operation of the processor at a second frequency and a second frequency when drawing and rendering the second image frame.

13. An electronic device, comprising: the device comprises a processor, a memory and a display screen; the memory stores program instructions that, when executed by the processor, cause the electronic device to perform the method of any of claims 1-12.

14. A computer readable storage medium having instructions stored therein which, when executed on a computer, cause the computer to perform the method of any of claims 1-12.