JP2001126412A - Decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately decode the data of address information or the like from frequency modulated signals recorded in an optical disk with easy constitution even when the rotation number of a spindle motor is substantially changed. SOLUTION: This decoder for frequency demodulating the frequency modulated signals (ADIP signals) and reading the data is provided with a demodulation means 108 for frequency demodulating the frequency modulate signals and a read means 109 for reading the data from the signals after frequency demodulation at a timing corresponding to the cycle of an FM carrier waves. The read means 109 extracts a clock by a cross detection means 105 for detecting the cross point of the ADIP signals and a threshold and outputting pulse signals and a pulse counting means 106 for counting the pulse signals. Thus, for the change of the revolution number of the spindle motor, follow-up ability is improved and accurate decoding is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device for demodulating an FM signal recorded on an optical disk or the like and reading data from the demodulated signal.

[0002]

2. Description of the Related Art Recently, data such as an address signal of an optical disk which is FM-modulated and recorded on the optical disk has recently become popular. In order to demodulate such an FM signal and read data such as address data, a timing signal for reading data must be extracted from the signal after the FM demodulation. The timing signal extracted to read this data is called a clock or an extracted clock, and generating a clock is called clock extraction.

In the prior art, this clock extraction has been performed by a method using a PLL (Phase Locked Loop). A conventional decoding device using a PLL will be described below with reference to the drawings.

[0004] FIG. 7 shows an ADIP (ADdress In Pregr) in which address data is biphase-modulated in an MD (Mini Disc: Mini Disc) player, which is an optical disk apparatus, and the bi-phase modulated signal is further subjected to FM modulation.
oove) is a block diagram of a decoding device for decoding original address data from a signal called a signal.

In FIG. 7, an ADIP signal is input, demodulated by a demodulation means 707, and a biphase signal is output.
The demodulating means 707 includes a binarizing means 701 and a counting means 7
02, low-pass filter 703 and data slicing means 7
04. The bi-phase signal is read by the reading unit 708
And is decoded into address data. The reading means 708 is
It has a PLL unit 705 and a decoding unit 706.

FIG. 8 is a waveform chart in the decoding apparatus.
(T) is an input ADIP signal, (u) is an output signal of the binarizing means 701, (v) is an output signal of the counting means 702, (w) is an output signal of the low-pass filter 703, ( x) is the output signal of the data slicing means 704;
(Y) is an output signal of the PLL means 705.

The ADIP signal (t) is previously recorded on the optical disk by meandering the track groove of the MD, which is the optical disk, and is output from an optical head or the like for reproducing the optical disk, and is output from the decoding device of FIG. Value conversion means 70
1 is input.

[0008] The binarizing means 701 performs ADI at a predetermined threshold value.
The P signal (t) is compared with a binary signal of a logic H and a logic L. When the ADIP signal (t) is larger than a predetermined threshold, the signal is set to a logic H, and when the ADIP signal (t) is smaller, a logic L is set to 2
The coded signal (u) is output.

The counting means 702 includes a binarizing means 701
Counts the rising edge or falling edge of the binarized signal (u) output by the counter clock, and outputs the counter value, that is, the periodic data of the ADIP signal, every rising edge or every falling edge. . This output counter value (v) is FM
This is a demodulated signal.

[0010] The low-pass filter 703 receives the counter value (v) output from the counting means 702 and removes quantization noise generated by the counting means 702 and high-frequency noise included in the ADIP signal (t). The reduced and smoothed signal (w) is output.

The data slicing means 704 compares the smoothed FM demodulated signal (w) to a logic H and a logic L at a predetermined threshold value. If it is smaller, the value (x) is output as logic L.

The binarized FM demodulated signal (x) output from the data slicing means 704 is a signal obtained by bi-phase modulation of address data, and is called a bi-phase signal.

The PLL means 705 extracts a clock (y) for reading the bi-phase signal (x).

In the biphase signal, if the period of the clock to be extracted is T, the interval between the rising edge and the falling edge is always 1 of the clock period T.
Double, double or triple. That is, the interval between the rising edge and the falling edge of the biphase signal has information on the clock to be extracted.

The PLL means 705 compares the phases of the rising edge and the falling edge of the input bi-phase signal (x) with the rising edge of the output clock (y) so that the phase difference becomes zero. The clock (y) is extracted from the bi-phase signal (x) by adjusting the period of the clock (y).

The decoding means 706 receives the bi-phase signal (x) and the extracted clock (y), detects the falling edge of the extracted clock (y), and at the same time, extracts the data of the bi-phase signal (x). Address data is read out by bi-phase demodulation of the data sequence, and the address data is output.

With the conventional decoding device having the above configuration, a clock included in a biphase signal obtained by FM demodulation of an ADIP signal can be extracted using a PLL, and address data can be decoded.

[0018]

A PL according to the prior art
In a decoding device using L, A
Address data cannot be read from the ADIP signal only when the FM carrier frequency of the DIP signal is within a range of about ± 10% of a predetermined design target value.

This is because the PLL performs a phase comparison.
This is based on the premise that the input signal cycle substantially coincides with a predetermined design target value. In a normal PLL, the signal cycle needs to be within a range of about ± 10% of the design target value. is there.

The FM carrier frequency of the ADIP signal is proportional to the rotation speed of the optical disk to be reproduced, and does not immediately rise from the time when the spindle motor is stopped or at a low rotation speed to the rotation speed at which address data can be read. It takes time to retrieve data from the optical disk, and it is necessary to provide a high-performance spindle motor control circuit in the optical disk device in order to keep the number of rotations of the spindle motor within the range in which reproduction operation is possible. was there.

An object of the present invention is to provide a decoding apparatus which can improve the follow-up performance with respect to a change in the number of revolutions of a spindle motor and can perform accurate decoding.

[0022]

In order to solve the above-mentioned problems, a decoding apparatus according to the present invention comprises a demodulating means for FM-modulating an FM-modulated signal, and demodulation at a timing corresponding to a period of the FM-modulated signal. From the signal after FM demodulation of the output of the means,
Reading means for reading data.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first invention of the present invention is a decoding device for reading data by FM-demodulating an FM-modulated signal, comprising: demodulation means for FM-demodulating the FM-modulated signal; Reading means for reading data from the signal after the FM demodulation at a timing corresponding to the cycle of the FM-modulated signal.

According to a second aspect of the present invention, in the first aspect, the reading means includes an average cycle detecting means for detecting an average cycle of the FM-modulated signal, and at a timing corresponding to the average cycle. Data is read from a signal after FM demodulation.

According to a third aspect of the present invention, in the second aspect, the time constant of the average period detecting means is switched based on the average period of the FM-modulated signal.

According to a fourth aspect of the present invention, in the above-mentioned invention, the signal after the FM demodulation is binarized by comparing the signal with a predetermined threshold, and the timing for reading data from the signal after the FM demodulation is binary. It is characterized by resetting according to the inversion of the converted data.

Thus, even if the FM carrier frequency changes due to a change in the number of revolutions of the spindle motor, etc.
High followability can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of a decoding apparatus according to Embodiment 1 of the present invention.

As shown in the figure, the decoding apparatus according to the present embodiment includes a demodulating means 108 comprising a binarizing means 101, a counting means 102, a low-pass filter 103 and a data slicing means 104; a cross detecting means 105; A reading means 109 comprising a counting means 106 and a decoding means 107 is provided.

FIG. 2 is a signal waveform diagram showing signals of respective sections for explaining the operation of the decoding apparatus according to the present embodiment.
FIG. 2A shows the ADI input to the cross detection means 105.
P signal, (b) is a predetermined threshold used by the cross detecting means 105, (c) is a pulse signal output from the cross detecting means 105, (d) is a counter value inside the pulse counting means 106, and (e) is a clock. This is the extracted clock.

The binarizing means 101, the counting means 102,
The low-pass filter 103, the data slicing unit 104, and the decoding unit 107 perform the same operations as those of the decoding device according to the related art, and a description thereof will be omitted.

The operation of the cross detecting means 105 and the pulse counting means 106 will now be described in detail.

The cross detecting means 105 receives the input AD.
The magnitude of the IP signal (a) is compared with a predetermined threshold (b),
At the moment when the magnitude relation is reversed, a pulse signal (c) having a certain time width is output. As described above, the cross detecting means 105 compares the ADIP signal (a) with an appropriate threshold (b), thereby obtaining a pulse signal (c) having a cycle equivalent to a half cycle of the input ADIP signal (a). Is output.

The pulse counting means 106 includes a counter. Every time a pulse signal (c) is input from the cross detecting means 105, the value of the counter is incremented by one and a counter value (d) is output. .

However, when the value (d) of the counter is equal to the value N (N = 7 in the present embodiment) and the pulse signal (c) is input from the cross detecting means 105, The counter value (d) is reset to 1. That is, the counter provided in the pulse counting means 106 is a counter that repeats the operation of incrementing the counter value (d) from 1 to N in accordance with the input pulse signal (c).

Further, the pulse counting means 106 generates a signal (e) having a logic H during a period when the counter value (d) is equal to N, and a logic L during a period when the counter value (d) is not equal to N. Output.

The frequency of the clock included in the biphase signal is proportional to the FM carrier frequency of the ADIP signal, and the ratio is fixed. In other words, F
If the M carrier frequency is known, a clock can be extracted based on the FM carrier frequency.

Therefore, in order to extract the clock included in the bi-phase signal, the clock is not directly extracted from the bi-phase signal, but an ADIP signal reproduced directly from the optical disk, that is, the FM modulation is applied to the bi-phase signal. A clock can be generated by detecting the FM carrier frequency from the signal subjected to the above.

Here, as a method of easily detecting the FM carrier frequency, a cross cycle between an ADIP signal corresponding to a half cycle of the FM carrier cycle and a predetermined threshold is detected, and a clock is extracted based on the cross cycle.

Since the ADIP signal itself is FM-modulated, even if the FM carrier frequency is constant, the ADI
The frequency of the P signal fluctuates within a range of ± several% with respect to the FM carrier frequency. That is, by detecting the period of the ADIP signal, the FM carrier period can be detected within an error range of ± several%, and similarly, the clock period can be generated within the error range of ± several%. .

When an MD is reproduced at a normal linear velocity,
The FM carrier frequency in the FM modulation of the ADIP signal is 22.05 kHz, the frequency deviation is ± 1 kHz, and the frequency of the clock to be extracted from the biphase signal is 6.3.
kHz.

That is, the clock cycle is 3.5 times (22.05 / 6.3) the FM carrier cycle, and the ADIP
It can be seen that this is equivalent to 7 times (3.5 × 2) of the signal crossing period.
Then, the clock can be extracted from the ADIP signal.

The error of the FM carrier cycle which can be detected from the ADIP signal is about ± 4.5%, and the error of the clock cycle is also about ± 4.5%.

As described above, according to the present embodiment, 2
A demodulating means 108 comprising a value converting means 101, a counting means 102, a low-pass filter 103 and a data slicing means 104, and a reading means 10 comprising a cross detecting means 105, a pulse counting means 106 and a decoding means 107.
9, the clock included in the biphase signal can be easily extracted from the ADIP signal.

It should be noted that the cross detecting means 105
Although a pulse signal is generated by detecting a half cycle of the signal, a similar effect can be obtained by detecting one cycle of the ADIP signal and generating a pulse signal.

In the pulse counting means 106, the clock is set to logic H during the period when the counter value is equal to N, but is set to logic H at the moment when the counter value reaches N.
Then, the same effect can be obtained even if the logic H is held for a certain period of time and then changed to the logic L.

(Embodiment 2) A decoding apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. 3, 4, and 9. FIG. FIG. 3 is a block diagram showing a schematic configuration of the decoding device according to the present embodiment.

As shown in the figure, the decoding apparatus according to the present embodiment includes a demodulating means 309 comprising a binarizing means 301, a counting means 302, a low-pass filter 303 and a data slicing means 304, an average period detecting means 305, A reading unit 310 including a pulse generating unit 306, a pulse counting unit 307, and a decoding unit 308 is provided.

FIG. 4 shows signal waveforms of respective sections for explaining the operation of the decoding apparatus according to the present embodiment. In FIG. 4, (g) is a signal obtained by dividing the average period data of the ADIP signal output from the average period detection unit 305 by 2, (h) is a counter value 1 of a counter included in the pulse generation unit 306, (i) ) Is a pulse signal output according to the counter value 1 (h), (j) is a counter value 2 of the counter provided in the pulse counting means 307, and (k) is an extraction clock output from the pulse counting means 307. .

FIG. 9 is a signal waveform diagram showing an input signal 901 and an output signal 902 for explaining the operation of the average period detecting means 305 of this embodiment.

The binarizing means 301, the counting means 302,
Low-pass filter 303, data slicing means 304,
The pulse counting unit 307 and the decoding unit 308 perform the same operations as those of the decoding device according to the related art and the decoding device according to the first embodiment, and a description thereof will be omitted.

Therefore, here, the average period detecting means 305
And the operation of the pulse generation means 306 will be described in detail.

A signal 901 input to the average period detecting means 305 is an AD signal output from the low-pass filter 303.
This is data of the cycle count of the IP signal, and has, as main frequency components, a high-frequency component due to a cycle deviation included in the ADIP signal and a low-frequency component due to a variation in FM carrier frequency.

The average period detecting means 305 is a low-pass filter that passes a frequency component sufficiently lower than the FM carrier period. The high frequency component due to the period deviation of the input signal 901 is removed, and the average period detecting unit 305 detects a change in the FM carrier period. A signal 902 having only low frequency components is output. Therefore, the average period detecting unit 305 detects the average period data of the FM carrier.

The pulse generating means 306 receives the data output from the average period detecting means 305 as an input and includes a counter therein. Counting is continued until the data output from the means 305 becomes equal to a value (g) obtained by dividing by two. Here, a counter clock having the same frequency as the counter clock used in the counting means 302 is used.

When the counter value 1 (h) of the pulse generation means 306 becomes equal to the value (g) obtained by dividing the data output from the average period detection means 305 by 2, a pulse signal (i) is output. , The counter value 1 (h) is reset to 1, and the counting by the counting clock is repeated again.

With the above operation, the pulse generating means 306
Can generate a pulse signal having a half cycle of the average cycle of the ADIP signal.

The pulse signal (i) is input to the pulse counting means 307 to extract the clock (k), but the description is omitted because it is the same as in the first embodiment.

As described above, the demodulating means 309 comprising the binarizing means 301, the counting means 302, the low-pass filter 303 and the data slicing means 304, the average period detecting means 305, the pulse generating means 306, and the pulse counting means 307 And reading means 3 comprising decoding means 308
10 can easily extract the clock included in the biphase signal from the ADIP signal.

In the decoding device according to the first embodiment of the present invention, since the pulse signal is generated by detecting a half cycle of the ADIP signal, the cycle of the pulse signal is changed to a high frequency jitter by the cycle deviation included in the ADIP signal. And the clock extracted by counting the pulse signal also has jitter. Further, when a reproduction signal from the optical disk is temporarily lost due to a defect such as a defect or dust on the optical disk, a half cycle of the ADIP signal cannot be detected, and clock extraction becomes impossible.

Due to these factors, in the decoding device according to the first embodiment, there is a possibility that the decoding means 107 cannot read an accurate address.

However, in the case of the decoding device according to the second embodiment of the present invention, the method of generating the pulse signal is not detected from the period of the ADIP signal, but is detected from the average period of the ADIP signal. The pulse signal can be generated without being affected by the jitter due to the period deviation, and the clock is not affected by the jitter.

Further, even if the ADIP signal is temporarily lost, the clock can be extracted from the average period data of the ADIP signal, so that the possibility that the decoding unit 308 cannot read an accurate address can be reduced. .

The same effect can be obtained even if the counter clock used in the pulse generating means 306 does not have the same frequency as the counter clock used in the counting means 302.

The same effect can be obtained even if the low-pass filter of the average period detecting means 305 can be switched to a plurality of time constants by the data of the average period of the output ADIP signal.

(Embodiment 3) A decoding apparatus according to Embodiment 3 of the present invention will be described with reference to FIGS.
FIG. 5 is a block diagram showing a schematic configuration of the decoding device according to the present embodiment.

As shown in the figure, the decoding apparatus according to the present embodiment includes a demodulating means 509 comprising a binarizing means 501, a counting means 502, a low-pass filter 503 and a data slicing means 504, an average period detecting means 505, A reading unit 510 including a pulse generating unit 506, a pulse counting unit 507, and a decoding unit 508 is provided.

FIG. 6 is a signal waveform diagram showing signals for explaining the operation of the present embodiment. In FIG. 6, (m) is a signal obtained by dividing the average period data of the ADIP signal output from the average period detection unit 505 by 2, (n) is a counter value 1 of a counter provided in the pulse generation unit 506,
(O) is a pulse signal output according to the counter value 1 (n), (p) is a biphase signal output from the data slicing means 504, and (q) is a pulse counting means 50.
The counter value 2 of the counter provided in 7, (r) is an extraction clock output from the pulse counting means 507.

The binarizing means 501, the counting means 502,
A low-pass filter 503, a data slice unit 504,
The average period detecting unit 505, the pulse generating unit 506, and the decoding unit 508 perform the same operations as those of the decoding device according to the related art and the decoding devices according to the first and second embodiments, and thus description thereof will be omitted. .

The pulse counting means 507 has a counter, and when the pulse signal (o) is input from the pulse generating means 506, increments the counter value 2 (q) by one. When the counter value 2 (q) is in a state equal to the predetermined value N, the pulse generation unit 506
Resets the counter value 2 (q) to 1 when the pulse signal (o) is input from the.

When the rising edge or the falling edge of the biphase signal (p) input from the data slicing means 504 is detected, the counter value 2
(Q) is reset to N / 2.

That is, the counter provided in the pulse count 2 means 507 has a reset function by detecting the rising edge and the falling edge of the biphase signal, and increments and repeats the values from 1 to N according to the pulse signal. It is a counter.

One cycle of the extracted clock from the edge of the bi-phase signal is a section indicating one channel bit data, and when it is desired to accurately read the channel bit data at the falling edge of the clock, the period of the channel bit data section is A falling edge of the clock must occur near the center.

Therefore, when the edge of the biphase signal is detected, a desired clock can be generated by resetting the value of the counter to N / 2.

Further, the pulse count 2 means 507 generates a signal (r) having a logic H during a period when the counter value 2 (q) is equal to N, and a logic L during a period when the counter value 2 (q) is not equal to N. Output. This signal (r) is input to the decoding device 508 together with the biphase signal (p) as an extraction clock, and is decoded into data such as an address.

As described above, the demodulating means 509 including the binarizing means 501, the counting means 502, the low-pass filter 503 and the data slicing means 504, the average period detecting means 505, the pulse generating means 506, and the pulse counting means 507 And reading means 5 comprising decoding means 508
10 can easily extract the clock included in the biphase signal from the ADIP signal.

In the case of the decoding device according to the second embodiment of the present invention, the phase relationship between the biphase signal and the extracted clock is not uniquely determined, and there is a possibility that an accurate address cannot be read by the decoding means.

However, in the case of the decoding device according to the third embodiment of the present invention, the counter provided in pulse counting means 507 is reset at the rising edge and the falling edge of the biphase signal. The phase relationship with the edge can be kept constant, and the possibility that the decoding unit 508 cannot read an accurate address can be further reduced.

Although the counter value is reset to N / 2 by detecting the edge of the bi-phase signal by the pulse generation means 506, the same effect can be obtained by resetting the counter value to a value near N / 2.

[0081]

As described above, according to the decoding apparatus of the present invention, a demodulating means for FM-demodulating an FM-modulated signal;
Reading means for reading data from the signal after the FM demodulation at a timing corresponding to the cycle of the M-modulated signal, so that even if the frequency of the FM-modulated signal changes over a wide range, The clock can be extracted from the bi-phase signal at a timing corresponding to the period of the data, so that the data can be read.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a decoding device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the decoding apparatus.

FIG. 3 is a block diagram showing a configuration of a decoding device according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram for explaining the operation of the decoding apparatus.

FIG. 5 is a block diagram showing a configuration of a decoding device according to a third embodiment of the present invention.

FIG. 6 is a signal waveform diagram for explaining the operation of the decoding apparatus.

FIG. 7 is a block diagram showing a configuration of a conventional decoding device.

FIG. 8 is a signal waveform diagram illustrating an operation of a conventional decoding device.

FIG. 9 is a signal waveform diagram illustrating an operation of an average period detecting unit of the decoding device according to the second and third embodiments of the present invention.

[Explanation of symbols]

 101, 301, 501, 701 Binarizing means 102, 302, 502, 702 Counting means 103, 303, 503, 703 Low-pass filter 104, 304, 504, 704 Data slicing means 105 Cross detecting means 106, 307, 507 Pulse counting means 107, 308, 508, 706 Decoding means 108, 309, 509, 707 Demodulation means 109, 310, 510, 708 Reading means 305, 505 Average period detecting means 306, 506 Pulse generating means

Continued on the front page (72) Inventor Takashi Inoue 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Masanobu Shimizu 1006 Odaka Kadoma, Kadoma City, Osaka Pref. Katsumi Sumida 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture, Japan Matsushita Electric Industrial Co., Ltd. (72) Inventor Kazuhiro Teshiroki 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 1006 Oaza Kadoma Matsushita Electric Industrial Co., Ltd. F-term (reference) 5D044 BC06 CC04 DE32 DE38 GL36 GM14 5D075 AA03 BB05 CC24 DD05 DD06 5D090 AA01 BB10 CC04 DD03 DD05 EE14 FF07 FF24 GG23 GG28 HH03

Claims (5)

[Claims] 1. A decoding device for reading data by FM-demodulating an FM-modulated signal, comprising: demodulation means for FM-demodulating the FM-modulated signal; and timing according to a cycle of the FM-modulated signal. In FM
A decoding device for reading data from the demodulated signal; 2. A decoding device for reading data by FM-demodulating a signal obtained by FM-modulating digital data modulated by a predetermined modulation method, comprising: demodulation means for FM-demodulating the FM-modulated signal; FM at a timing corresponding to the cycle of the FM-modulated signal
A decoding device for reading data from the demodulated signal; 3. A reading means comprising an average period detecting means for detecting an average period of an FM-modulated signal, and reading data from the signal after the FM demodulation at a timing according to the average period. Item 3. The decoding device according to item 1 or 2. 4. The decoding device according to claim 3, wherein the time constant of the average period detecting means is switched based on the average period of the FM-modulated signal. 5. The reading means binarizes a signal after FM demodulation with a predetermined threshold value, and sets a timing of reading data from the signal after FM demodulation in accordance with inversion of the binarized data. The decoding device according to claim 1, wherein the decoding device is reset.