JP2000057701A - Digital information reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase comparator having an expanded phase comparison range and a frequency detector utilizing a preamble pattern so that a pull-in time for an initial phase is improved, and switch a frequency control in accordance with a signal quality of a medium so that a reliable data reproducing operation is performed at high speed. SOLUTION: This phase error detecting circuit 18 detects a phase error while exceeding a phase comparison range in which a phase of a reproduced signal and a phase of an oscillation output of a VCO(voltage-controlled type oscillator) are ±180 degrees. A VFO (preamble pattern) frequency error detecting circuit of this digital information reproducing apparatus compares an edge count value with an initial set value so as to detect an amount of frequency error. A disk controller performs a frequency control of the VCO based on the amount of frequency error output from the VFO frequency detecting circuit 22 until the next read operation is to be performed. In addition, in the digital information reproducing apparatus, the disk controller 28 selects either a frequency error signal from the VFO frequency detecting circuit or a frequency error signal from a wobble frequency detecting circuit 25 to control an oscillating frequency of the VCO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing apparatus for reproducing original digital information from an analog signal reproduced from a recording medium.

[0002]

2. Description of the Related Art In reproducing original digital information recorded on a medium, self-clock reproduction is often used. To perform the self-clock reproduction, a PLL (Phase Locked Loop) circuit is usually used, and a synchronous clock is extracted from the reproduced signal. In recent years, PRML combining partial response equalization and Viterbi decoding has been developed as a method for reproducing original digital information recorded on a medium.
Signal processing is used. Partial response equalization can improve S / N compared to conventional Nyquist equalization by giving known intersymbol interference to a reproduced signal.
Viterbi decoding is effective when there is a correlation before and after the code, and is effective in combination with partial response equalization. A read channel combining the above-described self-clock reproduction and PRML signal processing has been developed. As shown in FIG. 1, such a read channel detects a phase error from a waveform equalization circuit 1 having a low-pass filter and an equalizing function, an A / D converter 2, an FIR filter 3, a Viterbi decoder 4, and a quantized reproduction signal. A phase comparator 5 for detecting, and a digital loop filter (D
LF) 6, a D / A converter (DAC) 7, and a voltage controlled oscillator (VCO) 8. In the conventional example of FIG. 1, a method of detecting a phase error from an output signal of the A / D converter 2 has been described. However, a method of obtaining a phase error from a determination result of the FIR filter 3 or the Viterbi decoder 4 is also used.

[0003] A medium having a sector structure is provided with a preamble pattern (VFO) for initial phase pull-in. The PLL increases the gain in the VFO, decreases the gain in the data area, and performs the initial phase pull-in as soon as possible. The gain is switched so that it can be realized. A medium having a continuous groove for tracking of an optical head is subjected to a predetermined modulation method called so-called wobbling or physical processing for meandering the groove in a single cycle, so that a so-called wobble is continuously generated from a reproduced signal. A method of reproducing the signal and detecting the address or the frequency is used. With such a medium, the address or frequency can be detected even when the rotation speed of the disk motor is not constant.

[0004]

In the above-described read channel, a multistage digital circuit exists from the A / D converter 2 to the control voltage of the VCO 8 and the circuit delay is large, so that the gain of the loop filter cannot be increased. . Therefore, there is a problem that it takes much time to pull in the initial phase because the capture range is narrow. The digital information reproducing apparatus of the present invention is provided with a phase comparator having a wide phase comparison range and a frequency detector based on a preamble pattern to improve the initial phase pull-in time.

In a disk having the above-mentioned continuous groove structure, the wobbled signal depends on the forming process of the medium.
The reproduction signal quality varies. For this reason, there is a problem that it is difficult to accurately detect the address or the frequency depending on the medium. A digital information reproducing apparatus according to the present invention includes a frequency detector based on a wobble signal and a frequency detector based on a preamble pattern, and switches frequency control depending on the signal quality of a medium to achieve high-speed and reliable data reproduction processing.

[0006]

SUMMARY OF THE INVENTION A digital information reproducing apparatus according to the present invention includes a comparator for judging the amplitude of a reproduction signal from a recording medium and a reference signal, and a reproducing signal from the output signal from the comparator. Frequency detecting means 1 for detecting a frequency, A / D converting means for converting a reproduction signal from the recording medium into quantized data,
Decoding means for decoding original digital information from the quantized data output from the D converter conversion means, phase comparison means for detecting phase error information from the quantized data output from the A / D converter conversion means, Frequency detecting means 2 for detecting frequency error information from the quantized data output from the A / D converter converting means, phase error information output from the phase comparing means and the frequency detecting means 1 or the frequency detecting means A from the frequency error information output from
In a digital information reproducing apparatus comprising a timing signal extracting means for producing a timing signal used for / D conversion means and a control means for controlling the signal switching means, the control means controls the frequency detection means based on a decoding result of the decoding means. The present invention is characterized in that the timing signal extracting means is controlled by switching the frequency error information of the frequency detecting means 1 and the frequency error information of the frequency detecting means 2.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital information reproducing apparatus according to the present invention will be described. FIG. 2 shows a configuration diagram.

The optical disk 9 has a sector structure and a single-period wobbling groove.
6) The case where modulation is used is shown. A reproduction signal from the optical head 10 passes through a preamplifier 11, and an RF signal, which is a sum of photodetectors, and a TE signal of a difference signal indicating a tracking error.
A signal is output. The RF signal is subjected to waveform shaping by the waveform equalization circuit 12 so as to remove high-frequency noise components and open the eye pattern of the reproduced signal. The waveform equalization output signal is A
It is quantized by the / D converter 13 at the reproduction clock rate. The quantized reproduction signal is adaptively equalized by the FIR filter 14 so as to achieve a predetermined partial response (PR) equalization. The Viterbi decoder 15 outputs the most probable binary data from the predetermined PR equalized data sequence based on the 8-16 modulation rule and the state transition of FIG. 3 determined by PR equalization. The binary data is converted into binary data by the (8-16) demodulator 16, and the error correction circuit 17 performs an error correction process.

The quantized data sampled by the A / D converter 13 is input to a phase comparator 18.
The phase comparator 18 detects a phase error of the recovered clock.
A digital loop filter (DLF) 19 extracts a signal component to be followed by the VCO 21 from the detected phase error.

[0010] The phase DAC 20 converts the output data of the DLF 19 into an analog signal. A / D converter 1
The quantized data sampled at 3 is input to the VFO frequency detector 22.

The VFO frequency detector 22 detects a frequency during an initial phase pull-in operation (at the time of an acquisition operation). On the other hand, the TE signal output from the preamplifier is output as a single signal by the band-pass filter 23. The comparator 24 converts the single signal into a square wave. The rectangular wave of the wobble signal is input to the wobble frequency detection circuit 25.
Since the interval between the edges of the rectangular wave ideally indicates a constant value, the wobble frequency detection circuit 25 compares the interval between the edges with the ideal value and outputs the difference to the DLF 26 as a frequency error. The DLF 26 detects a signal component to be followed by the VCO 21 from the detected wobble frequency error. The frequency DAC 27 converts the detected frequency error into an analog signal. The signals output from the phase DAC 20 and the frequency DAC 27 are added and input to the VCO 21 as a control signal. The disk controller 28 selects a frequency error signal from the VFO frequency detection circuit 18 and the wobble frequency detection circuit 25, and controls the oscillation frequency of the VCO 21.
For example, if the wobbling groove is insufficiently formed depending on the quality of the optical disc 9 and the detection of the wobble frequency is incomplete and data cannot be reproduced, the disc controller 28 repeats the retry operation, but the VFO frequency detection circuit 22 The oscillation frequency of the VCO 21 is controlled based on the frequency error from

Next, an embodiment of the phase error detecting circuit 18 of the digital information reproducing apparatus according to the present invention will be described in detail.
FIG. 4 shows the phase error detection circuit 18 during the initial phase pull-in operation.
3 shows a time chart of the principle of phase error detection. FIG.
It is assumed that the zero-phase start signal of (b) is input from the disk controller 28 and the VCO oscillates as shown in FIG. As shown in FIG. 4A, a preamble pattern is formed at a frequency of 1/8 of the recording clock in the VFO section of the medium, and is output as a reproduced signal. It is assumed that quantized data (FIG. 4D) as shown in FIG. 4A is obtained from the A / D converter by the clock output from the VCO. The quantized data obtained after the zero-phase start signal becomes Hi level is defined as St (t is an integer of 0 or more). FIG. 5 shows a configuration diagram of the VFO phase error detection circuit. The zero-phase start signal input from the disk controller resets the counter 29. The counter 29 counts the clock of the VCO.
FIG. 4E shows the count value of the counter. The quantized data yt input from the A / D converter is input to the flip-flop 30, and outputs the quantized data yt and a signal -yt whose sign is inverted to the selector 31. FIG. 4D shows the quantized data input to the flip-flop 30. Since the preamble pattern is formed in the VFO section at a frequency of 1/8 of the recording clock, the selector 31
Is the input count value (3 bits of LSB of the counter)
Count value is 8m + 3 (m is an integer of 0 or more)
If so, select -yt. If the count value is 8m + 7, select yt. Otherwise, select the output signal of flip-flop 32.
Output to It is output from the flip-flop 32 as a phase error signal as shown in FIG. A signal for switching between an initial phase pull-in operation (acquisition operation) and a phase following operation (tracking operation) is generated based on the counter value of the counter 29. When the phase of the sampling clock of the A / D converter is earlier than the phase detected from the VFO pattern, the phase error takes a negative value, and when late, it takes a positive value. Therefore, the phase of the reproduction signal and VC
Even if the phase of the O oscillation output exceeds the phase comparison range of ± 180 degrees, a phase error can be detected. In the present embodiment, the preamble pattern of the VFO unit has a frequency of 1/8 of the recording clock as an example. However, in general, the configuration of the selector circuit 31 is changed even if the preamble pattern has a frequency of 1 / n of the recording clock. By doing so, a similar effect can be obtained.

Next, an embodiment of the VFO frequency detecting circuit 25 of the digital information reproducing apparatus according to the present invention will be described in detail. FIG. 6 is a time chart illustrating the principle of detecting the frequency error of the VFO frequency detection circuit 25 during the initial phase pull-in operation. The zero-phase start signal shown in FIG. 6B is input from the disk controller, and the VCO shown in FIG.
Oscillates and the VFO section of the recording medium
It is assumed that a preamble pattern is formed at a frequency that is one eighth of the recording clock as shown in FIG. A is determined by the clock output from the VCO.
The quantized data as shown in FIG. 6A is obtained from the / D converter. A / is determined by the clock output from the VCO.
Quantized data (FIG. 6D) as shown in FIG. 6A is obtained from the D converter. FIG. 7 shows a configuration diagram of the VFO frequency error detection circuit. A zero-phase start signal is output from the read gate input from the disk controller 28. Counter 2 by the zero phase start signal
9 and the edge counter 33 are reset. The sign bit of the quantized data input from the A / D converter is input to the flip-flop.

The sign bit of the quantized data is as shown in FIG. The zero cross edge of the reproduced signal of the VFO unit is detected from the exclusive OR 36 of the sign bit delayed by one clock of the flip-flop 35 and the sign bit of the flip-flop 34. The detected zero crossing edge is shown in FIG.
A pulse signal as shown in FIG. This is counted by the edge counter 33. The counter output is as shown in FIG. For example, if the phase pull-in operation is switched from the acquisition operation to the tracking operation at the timing of the 320 channel clock, the counter 29
After the CO 37 starts oscillating, the 320 channel clock (8
A mode signal indicating that the operation is switched from the acquisition operation to the tracking operation is output at (−16 modulation, 20 bytes long). If the oscillation frequency of VCO 37 is correct, 3
During the 20 channel clock, 40 preamble patterns should be included and 80 zero-crossing edges should be detected.

Therefore, the comparator 38 compares the edge count result with the initial setting value (initial setting value 79). If the edge count value matches the initial setting, it is determined that the phase pull-in in the VFO unit is completed. If the edge count value is larger than the initial setting value, it indicates that the phase pull-in in the VFO unit was incomplete because the oscillation frequency of the VCO 37 was too small, and if the edge count value was smaller than the initial setting value. , The oscillation frequency of the VCO was too high, and the phase pull-in at the VFO section was incomplete. The result of comparison between the edge count value and the initial setting value indicates the frequency error amount. The disk controller 28 controls the frequency of the VCO based on the frequency error amount output from the VFO frequency detection circuit until the next read operation, and can reliably realize the phase pull-in operation. In the above-described VFO frequency detection circuit, a case has been described where a preamble pattern having a frequency of 1/8 of the recording clock is included in the initial phase pull-in period 320 channel clocks. The same effect can be obtained even with the frequency of 1.

[0016]

According to the digital information reproducing apparatus of the present invention, the disk controller selects the frequency error signals from the VFO frequency detection circuit and the wobble frequency detection circuit,
It is possible to control the oscillation frequency of the VCO, select a more accurate frequency error amount, and realize a reliable phase pull-in operation. Further, the phase error detection circuit of the digital information reproducing apparatus of the present invention is arranged such that the phase of the reproduced signal and the phase of the oscillation output of the VCO are within ± 1.
The phase error can be detected even if it exceeds the phase comparison range of 80 degrees. In addition, V of the digital information reproducing apparatus
The FO frequency error detection circuit detects the more accurate frequency error amount by comparing the edge count value of the VFO unit with the initial setting value, and can reliably realize the phase pull-in operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional read channel using a PRML method.

FIG. 2 is a block diagram of a digital information reproducing apparatus according to the present invention.

FIG. 3 is a state transition diagram of the embodiment of the digital information reproducing apparatus of the present invention.

FIG. 4 is a time chart of a principle of detecting a phase error of a phase error detection circuit at the time of a phase pull-in operation;

FIG. 5 is a configuration diagram of a VFO phase error detection circuit of the digital information reproducing apparatus of the present invention.

FIG. 6 is a time chart of a frequency error detection principle of a VFO frequency error detection circuit during an initial phase pull-in operation;

FIG. 7 is a configuration diagram of a VFO frequency error detection circuit of the digital information reproducing apparatus of the present invention.

[Explanation of symbols]

 Reference Signs List 1,12 Waveform equalization circuit 2,13 A / D converter 3,14 FIR filter 4,15 Viterbi decoder 5 Phase comparator 6 Digital loop filter (DLF) 7 D / A converter (DAC) 8 Voltage controlled oscillator ( VCO) 9 optical disk 10 optical head 11 preamplifier 16 8-16 demodulator 17 error correction circuit 18 phase error detection circuit 19, 26 DLF 20 phase DAC 21, 37 VCO 22 VFO frequency detection circuit 23 bandpass filter 24 comparator 25 wobble frequency detection Circuit 27 Frequency DAC 28 Disk controller 29 Counter 30, 32, 34, 35 Flip-flop 31 Selector 33 Edge counter 36 Exclusive OR 38 Comparator

Claims (6)

[Claims] A comparator for comparing the amplitude of a reproduced signal from a recording medium with a reference signal; a frequency detector for detecting a frequency of the reproduced signal from an output signal from the comparator; A / D conversion means for converting a reproduction signal from the A / D into quantized data;
Decoding means for decoding original digital information from the quantized data output from the D converter conversion means, phase comparison means for detecting phase error information from the quantized data output from the A / D converter conversion means, Frequency detecting means 2 for detecting frequency error information from the quantized data output from the A / D converter converting means, phase error information output from the phase comparing means and the frequency detecting means 1 or the frequency detecting means A from the frequency error information output from
In a digital information reproducing apparatus comprising a timing signal extracting means for producing a timing signal used for / D conversion means and a control means for controlling the signal switching means, the control means controls the frequency detection means based on a decoding result of the decoding means. A digital information reproducing apparatus for controlling the timing signal extracting means by switching between the frequency error information of the frequency detecting means 1 and the frequency error information of the frequency detecting means 2; 2. The control means controls the control means to select a frequency detection means from a decoding result decoded by the decoding means, and to perform a retry operation until original digital information satisfying reliability is reproduced. 2. The digital information reproducing apparatus according to claim 1, wherein: 3. A timing signal extracting means for generating a timing signal at a preset center frequency in synchronism with a moment when a reproduction signal reaches a preset threshold value when a gate signal indicating a signal processing start timing becomes valid. A digital information reproducing apparatus comprising: a frequency detection unit that detects a frequency of a signal from an intermittent single signal included in a reproduction signal and controls a frequency of a timing signal of the timing signal extraction unit. A digital information reproducing apparatus, wherein a detecting means detects a frequency error based on the fact that the frequency of an intermittent single signal included in a reproduced signal is 1 / n of the frequency of a timing signal. 4. A timing signal extracting means for generating a timing signal at a preset center frequency at a moment when a reproduction signal reaches a preset threshold value when a gate signal indicating a signal processing start timing becomes valid. A digital information reproducing apparatus comprising: a phase comparison unit that detects a frequency of a signal from an intermittent single signal included in a reproduction signal and controls a frequency of a timing signal of the timing signal extraction unit. A digital information reproducing apparatus, wherein the comparing means detects a phase error based on the fact that the frequency of an intermittent single signal included in the reproduced signal is 1 / n of the frequency of the timing signal. 5. The digital information reproducing apparatus according to claim 3, wherein the timing signal extracting means switches and sets the center frequency from a plurality of center frequencies according to an external control signal. 6. The digital information reproducing apparatus according to claim 3, wherein the timing signal extracting means detects the frequency of the intermittent single signal continuously by an external control signal.