KR100606711B1 - apparatus for decoding of ADdress In Pre-groove signal - Google Patents

Abstract

The present invention is to provide a device for simplifying the complexity of the phase demodulator in the ADIP decoding device, overcoming wrong information demodulated in an unstable wobble signal, and correcting the ADIP decoding. A PLL for following a phase of a wobble signal to a phase demodulator, a control signal generator for generating a cumulative start control signal and a discriminant control signal through the wobble signal following the PLL, and inputting the result to the phase demodulator; A first bit detector for discriminating the ADIP data based on the result determined as 0 or 1 of the demodulated data, and the phase demodulator is incompletely demodulated by the deteriorated wobble signal, and the first bit detector is not discriminated. A second bit for determining ADIP data using the cumulative result of the corresponding wobble of the phase demodulator And a wobble counter indicating a phase modulation section according to the wobble using the ADIP data detected by the first bit detector or the second bit detector.

ADIP, PLL, Wobble, Bit Detector, DVD + R / RW

Description

ADP signal decoding device {apparatus for decoding of ADdress In Pre-groove signal}

1 is a diagram showing a wobble signal formed on a typical DVD + R / RW disc.

2 is a block diagram of a general ADIP decoding apparatus.

3 is a block diagram of an ADIP decoding circuit according to the present invention;

4 is a signal timing diagram of a phase demodulator in the ADIP decoding apparatus according to the present invention;

5 is a signal timing diagram of a primary bit detector in an ADIP decoding apparatus according to the present invention;

6 is a signal timing diagram of a secondary bit detector in the ADIP decoding apparatus according to the present invention;

* Explanation of symbols for main parts of the drawings

100: AD converter 200: phase demodulator

210, 400, 500: Adder (ACC) 220: Register

230: control signal generator 240: discriminator (latch)

300: shift register 600: bit detector

700: Wobble Counter 800: PLL

The present invention relates to an apparatus for detecting ADIP (ADdress In Pre-groove) information formed on a disc in a DVD + R / RW recorder.

DVD + R (R: Recordable) is a recordable medium, and once recorded, the contents cannot be modified like CD-R (Compact Disk-R). Also, recorded DVD + R discs work perfectly with DVD-ROM drivers and DVD video players, so they can be used for distributing large amounts of data, movies, or music. Moreover, once recorded content cannot be modified, it is advantageous for long-term storage or storage of important documents.

On the other hand, DVD + RW (RW: ReWritable) is one of the unrecorded data, audio / video dedicated storage medium, unlike the conventional DVD-Video can only be recorded about 1000 times. DVD + RW has the same capacity of 4.7GB as DVD-Video, and can record high-definition video for two hours up to six hours.

The DVD + R and DVD + RW described above record data on a disc by using the address information of the DVD as an ADIP signal. In general, the ADIP signal in DVD + R and DVD + RW inverts the phase of the wobble by 180 ° according to sync or data '1' or '0' in a specific section of the wobble when generating a wobble signal on the disc. The phase information is recorded by performing phase modulation.

That is, a DVD + R / RW disc, which is a recording medium, is produced by artificially forming a track in a recording area in a sinusoidal form, which is called a wobble.

This wobble makes it possible to generate a recording clock that matches the disk rotation speed, and expresses the positional information and characteristic information of the disk. In addition, by multiplying the extracted wobble signal by 32, the data can be recorded at a recording clock that perfectly matches the disk rotation speed, and this information is called ADIP (ADdress In Pre-groove).

Since the wobble signal is generated by the shape of the track of the recording area, it can be extracted regardless of whether the disc is recorded or not. However, since the quality of the extracted wobble signal may be degraded in the once-recorded area, there is a need for a demodulation apparatus and method capable of overcoming this.

1 shows a wobble signal formed on a DVD + R / RW disc.

As shown in FIG. 1, a phase modulation section appears for every 93 wobbles, and the length of the section corresponds to eight wobbles. The hatched portion in the figure indicates that the phase of the wobble is inverted by 180 degrees, and according to the inverted position, the ADIP Sync, the ADIP Zero bit, and the ADIP One bit can be distinguished.

2 is a block diagram of a general ADIP decoding apparatus.

Referring to FIG. 2, the ADIP decoding apparatus includes an AD converter 10, a control signal generator 40, a sine wave generator 30, a register 60, and a discriminator 70. And a demodulator, a PLL circuit 20 and an ADIP discriminator 80.

Referring to the operation of the ADIP decoding device configured as described above, first, the analog wobble signal input through the AD converter 10 is quantized to obtain a digital wobble signal. When the digital wobble signal is removed using a high-pass filter or the like, the signal is multiplied by a sine wave having the same frequency as the wobble signal at the current rotation speed and accumulated through the register 60. In this case, since the phase is inverted, the positive value is obtained, and in the inverted phase, the negative value is used to determine whether the phase is reversed.

By looking at the pattern of the demodulated data value in the discriminator 70, the ADIP discriminator 80 distinguishes between ADIP Sync, ADIP Zero bit, and ADIP One bit.

At this time, in order for the phase demodulator to operate well, the synchronization of the input analog wobble signal, the accumulated time control signal, the discrimination control signal, and the generated sine wave must coincide. For this purpose, a PLL circuit 20 that follows the phase of the input wobble signal is used.

This general phase demodulator has the disadvantage of requiring complex hardware, such as a sine wave generator 30 and a multiplier. Also, if the incoming wobble signal is very degraded, the phase of the wobble signal is not clear, so that the demodulation result may not be perfect. The problem becomes possible.

Accordingly, an object of the present invention is to provide a device for simplifying the complexity of a phase demodulator in an ADIP decoding device, overcoming wrong information demodulated in an unstable wobble signal, and correct ADIP decoding. have.

A feature of the ADIP signal decoding apparatus according to the present invention for achieving the above object is a phase demodulator for processing a phase-modulated wobble signal, a PLL for following the phase of the wobble signal to the phase demodulator, and the following A control signal generator which generates a cumulative start control signal and a discrimination control signal through a wobble signal and inputs them to the phase demodulator, and discriminates ADIP data based on a result determined as 0 or 1 of data demodulated by the phase demodulator. Determining the ADIP data by using the cumulative result of the wobble of the phase demodulator when the phase demodulator is incompletely demodulated by the first bit detector and the decoded wobble signal is not discriminated by the first bit detector. By using the second bit detector and the ADIP data detected by the first bit detector or the second bit detector There is composed, including a wobble counter indicating the phase modulating sections in accordance with the per wobble.

In this case, the PLL may receive a phase modulation section signal from the wobble counter and control whether phase tracking is performed according to the phase modulation section.

And a phase demodulator having a phase difference of 180 degrees and an input phase modulated wobble waveform added to perform an add function for half a period and a subtract function for the other half period according to the subtracted control signal of the PLL, and generating the control signal. A register for continuously increasing and outputting a phase-modulated wobble waveform output from the adder in a positive direction or a negative direction according to a phase through a cumulative start control signal input from a negative part, and a decrement control signal input to the adder Is preferably composed of a discriminator for discriminating the result of latching the register value at the time of transitioning from 1 to 0 and the phase modulation result by the sign value of the wobble.

In addition, it is preferable that the primary bit detector inputs a code value of the phase demodulator into a shift register to determine ADIP data by comparing the similarity between the shift register value and the ADIP data.

In addition, the wobble counter preferably counters the phase modulation interval according to the wobble by increasing the counter value by 1 for each wobble at the time the ADIP data is detected by the primary bit detector.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of the ADIP signal decoding apparatus according to the present invention will be described below with reference to the accompanying drawings.

3 is a block diagram of an ADIP decoding circuit according to the present invention.

Referring to FIG. 3, the ADIP decoding circuit includes a phase demodulator 100 for processing a phase modulated wobble signal, a PLL 800 for inputting a control signal to the phase demodulator 100, and a control signal generator ( 230, a bit detector 600 for discriminating ADIP Sync, ADIP Zero bit, and ADIP One bit which are ADIP data from the phase demodulated data, and a wobble counter 700 for indicating a phase modulation section.

The PLL 800 is a circuit that follows a phase of a wobble signal input to an ADIP decoding circuit, and performs a function of generating a clock signal having a 50% duty ratio that is in phase with a frequency of the wobble signal. At this time, since the phase modulation section signal is input from the wobble counter 700 to stop the phase tracking, the output signal of the PLL 800 is stably generated even in the phase modulation section.

The phase demodulator 200 refers to a part consisting of the ACC1 210 and the register 220 in FIG. 3, and the operation of this part is shown in FIG. 4.

As shown in FIG. 4A, the phase-modulated wobble waveform has a phase difference of 180 degrees, and the output signal of the PLL 800 that follows the phase of the wobble signal input with the phase difference is controlled by the ACC1 210. As a signal, as shown in (b) of FIG. 4, the addition function is performed during the half cycle and the subtraction function is performed during the remaining half cycle.

The accumulated signal continues to increase in the positive direction in the PW having a zero degree phase and in the negative direction in the NW having a 180 degree phase, as shown in the output value of the register 220 shown in FIG. It will continue to increase. Therefore, as shown in Figs. 4 (d) and 4 (e), the result of latching the register value at the moment when the decrement control signal transitions from 1 to 0 and the sign of the result value determine the phase modulation result. To demodulate.

The demodulated result is determined by the two bit detector 600 ADIP Sync, ADIP Zero bit, ADIP One bit.

First, the primary bit detector 610 inputs a code value of the phase demodulator 200 to the shift register 300 to determine corresponding ADIP data through similarity between the value of the shift register 300 and the ADIP data. .

5 is a diagram illustrating a signal of a primary bit detector according to the present invention.

In this case, assuming that the case of perfect phase demodulation is described with reference to FIG.

As shown in FIG. 5 (a), the shift register value in the case of ADIP Sync has a pattern of 110 0001 1111 as shown in FIG. 5 (b), and when it is an ADIP zero bit as shown in FIG. As shown in FIG. 5 (e), when 1101111 1001 is used, as shown in FIG. 5 (f), it becomes 110 1110 0111.

Therefore, when the output of the shift register 300 has a value similar to the above three patterns, the primary bit detector 610 can obtain the corresponding data.

In other words, if a sign bit shift register stores a pattern similar to 110 0001 1111, ADIP Word Sync is detected. If a sign bit shift register stores a pattern similar to 110 1111 1001, an ADIP Zero pattern is generated. If the shift register of the sign bit stores a pattern similar to 110 1110 0111, it means that the ADIP One pattern is detected.

In this case, when phase demodulation is incomplete and cannot be discriminated by the primary bit detector 610, the secondary bit detector 620 determines.

That is, when the wobble signal is degraded in the phase modulated section as shown in the fourth, fifth, sixth, and seventh wobble waveforms shown in FIG. 6, the ADIP zero bit and the ADIP one bit are used as output values of the shift register 300. May not be able to be determined.

Accordingly, when the secondary bit detector 620 cannot determine the primary bit detector 610 as described above, the accumulated value of the 4th and 5th wobbles (ACC3) 500 and the 6th and 7th wobbles The ADIP zero bit and the ADIP one bit are determined by comparing the accumulated value (ACC2) 400.

At this time, in order for the secondary bit detector 620 to operate normally, it is necessary to know how many wobbles are currently input among 93 units. For this purpose, the wobble counter 700 has an ADIP in the primary bit detector 610. At the moment data is detected, the counter value is initialized to 9, increasing by 1 for each wobble.

When the value of the wobble counter 700 is 92, the next wobble is initialized to 0. From this time, eight wobble sections correspond to a phase modulation section.

By doing so, the secondary bit detector 620 may generate the accumulated control signals of the ACC2 400 and the ACC3 500.

In addition, since the section of the wobble counter 700 has a value of 0 to 7, the phase modulation section may be used as a control signal for preventing the PLL 800 from performing a phase tracking function in this section.

 Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The ADIP signal decoding apparatus according to the present invention as described above has the following effects.                     

First, since the deep decoding is performed using a two-stage bit detector in a DVD + recording system, ADIP decoding can be correctly performed even if the wobble signal is degraded and the phase demodulation is not perfect.

Second, by implementing the phase demodulation function using only the adder and the register, the complexity of the hardware can be reduced.

Third, since the phase modulation section can be predicted using the wobble counter, the PLL can be more stably operated by not operating the PLL phase tracking function in the phase modulation section.

Claims (5)

A phase demodulator for processing a phase modulated wobble signal, A PLL for receiving a phase modulation section signal from the wobble counter to control whether or not phase tracking is performed according to a phase modulation section, and following the phase of the wobble signal to the phase demodulator; A control signal generator for generating a cumulative start control signal and a discrimination control signal through the wobble signal followed by the PLL and inputting the generated control signal to the phase demodulator; A first bit detector for determining ADIP data based on a result determined as 0 or 1 of the phase demodulated data by the phase demodulator; A second bit detector for determining ADIP data by using the cumulative result of the wobble of the phase demodulator when the phase demodulator is incompletely demodulated by the deteriorated wobble signal and is not discriminated by the first bit detector; And a wobble counter indicating a phase modulation period according to the wobble using the ADIP data detected by the first bit detector or the second bit detector. delete The method of claim 1, wherein the phase demodulator An adder for adding a phase-modulated wobble waveform having a phase difference of 180 degrees and performing a subtracting function for a half period and a subtracting function for the remaining half period according to the subtraction control signal of the PLL; A register for continuously increasing and outputting a phase-modulated wobble waveform output from the adder in a positive direction or a negative direction according to a phase through an accumulation start control signal input from the control signal generator; An ADIP signal comprising a result of latching a register value at the moment when a decrement control signal input to the adder transitions from 1 to 0 and a phase modulation result by a code value of the wobble Decoding device. The method of claim 1, wherein the primary bit detector is And inputting a code value of the phase demodulator into a shift register to compare the similarity between the shift register value and the ADIP data to determine ADIP data. The wobble counter of claim 1, wherein And a counter value is incremented by 1 for every wobble at the moment the ADIP data is detected by the primary bit detector to counter the phase modulation interval according to the wobble.

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