JP4794260B2 - Disc player - Google Patents

Description

  The present invention relates to a disk reproducing apparatus capable of reproducing a signal recorded on a disk by constant linear velocity control, and more particularly to a disk reproducing device having a digital PLL (Phase Locked Loop) circuit. It is.

  Conventionally, a reproduction signal processing method based on so-called bit-by-bit determination is known as a reproduction signal processing method for reading pit information recorded on a recording medium such as an optical disk. In the reproduction signal processing method, a signal reproduced from the disc is binarized to generate a binarized signal, and a reproduction clock whose phase is synchronized with rising and falling edges of the binarized signal is generated by a PLL circuit. Then, the reproduction data synchronized with the reproduction clock is generated by making the phase of the binarized signal coincide with the reproduction clock.

  In recent years, signals such as DVD (Digital Versatile Disc) and HD-DVD (High Definition Digital Versatile Disc) have been recorded with high density in order to increase the capacity of the disc. A PRML (Partial Response Maximum Likelihood) signal processing method is known as a reproduction signal processing method for a signal recorded in (1). In the PRML signal processing method, a signal reproduced from a disc is converted into multivalued digital data by an A / D converter, and the digital data after A / D conversion is Viterbi decoded by an adaptive filter.

As a disk reproducing apparatus employing the PRML signal processing method, a disk reproducing apparatus having a VCO (Voltage Controlled Oscillator) for supplying a sampling clock to an A / D converter is known (for example, see Patent Document 1). ). In this type of disc reproducing apparatus, zero-cross data to be zero-crossed is extracted from the data sampled by the A / D converter, and the phase error with the clock component of the reproduction signal is calculated from the extracted zero-cross data. Thereafter, the calculated phase error is integrated, and the oscillation frequency of the VCO is controlled based on the integration result.
However, this type of disk reproducing apparatus has a problem that the output of the VCO varies, a problem that the VCO needs to be calibrated, and a problem that the number of external components increases when the integrated circuit is formed.

Therefore, a disk reproducing apparatus having a digital PLL circuit is known (see, for example, Patent Document 2).
FIG. 16 shows the structure of this type of disk reproducing apparatus, in which the signal recorded on the disk (1) is reproduced by the optical pickup (2), and the reproduced signal is A / It is supplied to the D conversion circuit (3). A fixed clock having a constant frequency is supplied from the outside to the A / D conversion circuit (3), and the reproduction signal is sampled and converted into multi-value digital data D1 at the frequency of the fixed clock. The digital data is supplied to the interpolation circuit (40) and subjected to an interpolation process to be described later in a cycle corresponding to the virtual clock cycle information PH2 supplied from the outside. The interpolation data D2 obtained by the interpolation processing is supplied to the zero-cross extraction circuit (51) of the virtual clock cycle control circuit (5), and the zero-cross data to be zero-crossed from the interpolation data is phased with the clock component of the reproduction signal. It is extracted as error information Δφ. The extracted phase error information Δφ is supplied to the integration circuit (52) and integrated, and the integration result is supplied to the digital oscillator (53). The digital oscillator (53) manages the cycle of the virtual clock in the arithmetic processing, and the phase and frequency of the virtual clock match the phase and frequency of the clock component (channel clock) of the reproduction signal. The period of the virtual clock is controlled according to the integration result. The cycle information PH2 of the virtual clock is supplied to the interpolation circuit (40) and used for interpolation processing. In this way, a digital PLL circuit is formed from the interpolation circuit (40) and the virtual clock cycle control circuit (5).
The interpolation clock (40), the zero cross extraction circuit (51), the integration circuit (52), and the digital oscillator (53) are supplied with the fixed clock from the outside, and the operation is executed based on the fixed clock. .

The operations of the A / D conversion circuit (3), the interpolation circuit (40), and the virtual clock cycle control circuit (5) will be specifically described with reference to FIGS.
FIG. 20 shows sampling data obtained from the A / D conversion circuit (3) and interpolation data obtained from the interpolation circuit (40). In the figure, the hexagonal plot is the sampling data D1 (n), and the circle plot is the interpolation data D2 (n). T1 is the period of the fixed clock, that is, the sampling period of the A / D conversion circuit (3), and T2 is the period of the virtual clock.

In the A / D conversion circuit (3), sampling data D1 (n) is obtained at a cycle T1, as shown in the figure, and the sampling data is supplied to the interpolation circuit (40).
In the interpolation circuit (40), interpolation data D2 (n) is generated by linear interpolation from two adjacent sampling data D1 (n) and D1 (n + 1) in period T2, and the generated interpolation data is controlled by virtual clock period control. It is supplied to the zero cross extraction circuit (51) of the circuit (5).
In the zero-cross extraction circuit (51), zero-cross data D0 (n) to be zero-crossed is extracted as phase error information Δφ with the clock component of the reproduction signal from the plurality of interpolation data supplied from the interpolation circuit (40). Here, since the polarity of the interpolation data changes before and after the zero cross, the zero cross data can be extracted based on the change of the polarity.

The plurality of extracted zero cross data is supplied to the integration circuit (52) and integrated. For example, when the phase of the virtual clock is ahead of the clock component of the reproduction signal, the zero-cross data at the rising portion of the reproduction signal takes a negative value, and the zero-cross data at the falling portion takes a positive value. In this way, the polarity of the zero cross data is inverted between the rising edge and falling edge of the reproduction signal. Therefore, the value of one of the rising and falling edges of the reproduction signal is inverted to rise. The zero-cross data of the part and the falling part are integrated. By integrating the zero-cross data as described above, the frequency of the clock component of the reproduction signal can be obtained.
In the digital oscillator (53), the cycle of the virtual clock is controlled according to the integration result of the integration circuit (52). When the phase of the virtual clock is ahead of the clock component of the playback signal, the virtual clock cycle is changed to a larger value, and when the phase of the virtual clock is behind the clock component of the playback signal, The clock cycle is changed to a smaller value.

  FIG. 21 is a plot of sampling data obtained from the A / D conversion circuit (3) and interpolation data obtained from the interpolation circuit (40), with time on the horizontal axis and absolute phase on the vertical axis. is there. The square plot is sampling data obtained from the A / D conversion circuit (3), and the numbers inside each plot represent the time series order of sampling. On the other hand, the circle plots are interpolation data obtained from the interpolation circuit (40), and the numbers inside each plot represent the time series order of interpolation.

  As described above, the virtual clock period information PH2 output from the digital oscillator (53) represents the period of the fixed clock by a predetermined fixed value PH1, and the relationship between the fixed clock period and the fixed value indicates the second clock signal. It represents the period. If the current value of the phase of sampling performed in synchronization with the fixed clock is PH0, the sampling phase is (PH0 + PH1), (PH0 + 2 · PH1)..., But overflow is prevented in actual interpolation processing. Accordingly, as shown in FIG. 21, when the sampling phase (PH0 + j · PH1) (j is a natural number) becomes larger than the cycle information PH2 of the virtual clock, the cycle information PH2 is subtracted from the sampling phase as an offset value. The interpolation calculation is performed on the linear interpolation calculation lines L1, L2,. For example, the interpolation data 1 is calculated from the sampling data 1 and the sampling data 2 on the linear interpolation calculation line L1, and the interpolation data 2 is calculated from the sampling data 2 and the sampling data 3 on the linear interpolation calculation line L2.

  As shown in FIG. 20, the interpolation data is D2 (n), the immediately preceding sampling data is D1 (n), the immediately following sampling data is D1 (n + 1), the phase of the sampling data D1 (n) and the interpolation data D2 (n). When the phase difference between the phase of the interpolation data D2 (n) and the phase of the sampling data D1 (n + 1) is b, the interpolation data D2 (n) is calculated from the following equation (1). .

(Equation 1)
D2 (n) = {a · D1 (n + 1) + b · D1 (n)} / (a + b)

FIG. 17 shows a specific configuration of the interpolation circuit (40). In the interpolation circuit (40), the sampling data from the A / D conversion circuit (3) is supplied to the first delay element (41), and is held and outputted by the delay element (41) for one period. The sampling data D1 (n) output from the first delay element (41) is input to the first multiplier (43). The first multiplier (43) receives the phase difference b from a first phase difference calculation circuit (42) described later. In the first multiplier (43), the inputted sampling data D1 (n) and the phase difference b are multiplied, and the multiplication result b · D1 (n) is inputted to the adder (46).
The sampling data D1 (n + 1) from the A / D conversion circuit (3) is input to the second multiplier (45), and the second multiplier (45) receives a second phase difference calculation circuit (described later). The phase difference a is input from 44). In the second multiplier (45), the input sampling data D1 (n + 1) and the phase difference a are multiplied, and the multiplication result a · D1 (n + 1) is input to the adder (46).

  In the adder (46), the two multiplication results inputted as described above are added, and the addition result {b · D1 (n) + a · D1 (n + 1)} is inputted to the computing unit (47). The In the arithmetic unit (47), the input addition result is multiplied by the reciprocal of the total value (a + b) of the phase differences a and b, and the multiplication result D2 (n) is supplied to the second delay element (48). After being held for a certain period of time, it is supplied to the virtual clock cycle control circuit (5) shown in FIG.

FIG. 18 shows a specific configuration of the first phase difference calculating circuit (42). The first phase difference calculating circuit (42) stores the first register (421) in which the current value PH0 of the sampling phase is stored. ), A second register (422) storing a fixed value PH1 representing a fixed clock period, and a third register (423) storing virtual clock period information PH2 from the digital oscillator (53). It has.
The current value PH0 of the sampling phase is input from the first register (421) to the first adder (424), and the fixed value PH1 is input from the second register (422) to the first adder (424). The In the first adder (424), the two input values are added, and the addition result (PH0 + PH1) is input to the second adder (425) and the selector (426).

The second adder (425) receives virtual clock cycle information PH2 from the third register (423). In the second adder (425), the virtual clock period information PH2 is subtracted from the addition result input as described above, and the subtraction result (PH0 + PH1-PH2) is input to the selector (426).
In the selector (426), when the addition result (PH0 + PH1) is smaller than the virtual clock cycle information PH2, the addition result (PH0 + PH1) and the subtraction result (PH0 + PH1-PH2) input as described above are the addition results. Selected and output. The addition result output in this way is input to the first register (421), and the current value PH0 of the sampling phase is updated to the addition result.
On the other hand, when the addition result (PH0 + PH1) is larger than the virtual clock cycle information PH2, the subtraction result is selected and output. The subtraction result output in this way is input to the first register (421) so that the current value PH0 of the sampling phase is updated to the subtraction result, and the first multiplier shown in FIG. (43) is input.

FIG. 19 shows a specific configuration of the second phase difference calculation circuit (44). The second phase difference calculation circuit (44) is output from the first phase difference calculation circuit (43). A first register (441) storing the phase difference b and a second register (442) storing the fixed value PH1 are provided.
The phase difference b is input from the first register (441) to the adder (443), and the fixed value PH1 is input from the second register (442) to the adder (443). In the adder (443), the phase difference b is subtracted from the inputted fixed value PH1, and the subtraction result is inputted as the phase difference a to the second multiplier (45) shown in FIG.

By the way, in order to perform the interpolation processing normally, at least one sampling data must exist between two adjacent interpolation data, and the frequency of the fixed clock is the same as or equal to the frequency of the virtual clock. Must be set to a larger value.
When a signal recorded on a disc with constant linear velocity control is reproduced with constant linear velocity control, the frequency of the clock component of the reproduced signal is substantially constant regardless of the reproduction position in the radial direction of the disc. The frequency of becomes substantially constant.
Therefore, in the conventional disk reproducing apparatus, when the signal recorded on the disk by the constant linear velocity control is reproduced by the linear velocity constant control, the frequency of the fixed clock is set in consideration of fluctuation due to eccentricity or the like. The frequency is set to 1.1 to 1.2 times the frequency of the virtual clock.

On the other hand, when the signal recorded on the disc with constant linear velocity control is reproduced with constant angular velocity control, the frequency of the clock component of the reproduction signal obtained when reproducing the outer periphery of the disc is the same as when reproducing the inner periphery of the disc. The frequency of the clock component of the reproduced signal to be obtained is as high as about 2.5 times, and accordingly, the frequency of the virtual clock at the time of reproducing the outer periphery of the disk is higher than that at the time of reproducing the inner peripheral part of the disk.
Therefore, in the conventional disk reproducing apparatus, when the signal recorded on the disk with the constant linear velocity control is reproduced with the constant angular velocity control, the interpolation process is normally performed over the entire area of the disk. The frequency of the fixed clock is set to a value larger than the frequency of the virtual clock at the time of reproducing the outer periphery of the disk. The frequency of the virtual clock when reproducing the outer peripheral portion of the disk is about 25 MHz, the frequency of the virtual clock when reproducing the inner peripheral portion of the disk is about 10 MHz, and the frequency of the fixed clock is set to 30 MHz, for example.

Unexamined-Japanese-Patent No. 2000-311442 [G11B 20/10] JP-A-10-27435 [G11B 20/14]

However, in the conventional disk reproducing apparatus, when the signal recorded on the disk with the constant linear velocity control is reproduced with the constant angular velocity control as described above, the fixed clock frequency is virtually set when reproducing the inner periphery of the disk. Even if the interpolation processing can be normally performed if it is set to about 11 to 12 MHz which is 1.1 to 1.2 times the frequency of the clock, the interpolation processing is normally performed even when reproducing the outer periphery of the disk as described above. Is set to about 30 MHz, which is 1.1 to 1.2 times the frequency of the virtual clock during reproduction of the outer periphery of the disk, so that sampling is performed in synchronization with a fixed clock having a frequency higher than necessary. As a result, there is a problem that wasteful power is consumed.
Accordingly, an object of the present invention is to prevent wasteful power consumption during reproduction of the inner periphery of a disc when a signal recorded on the disc is reproduced with constant linear velocity control. It is to provide a disc reproducing apparatus.

A first disk reproducing apparatus according to the present invention is as follows.
Playback means for playing back signals recorded on the disc;
A digital data generation means for supplying a first clock signal from the outside and performing a sampling process at a frequency corresponding to the frequency of the first clock signal on the signal reproduced from the disc to generate digital data;
The frequency / period information of the virtual second clock signal having a frequency corresponding to the frequency of the clock component of the reproduction signal is supplied from the outside, and the digital data obtained from the digital data generating means corresponds to the frequency / period information. Interpolation means for performing interpolation processing at a frequency to generate interpolation data;
A frequency / period control means for supplying frequency / period information corresponding to the interpolation data obtained from the interpolation means to the interpolation means;
Clock supply means for supplying a first clock signal to the digital data generation means, and the clock supply means changes the frequency of the first clock signal in accordance with the frequency of the clock component of the reproduction signal.

As described above, when a signal recorded on a disc with constant linear velocity control is reproduced with constant angular velocity control, the frequency of the clock component of the reproduced signal increases as the reproduction position moves to the outer periphery of the disc. The frequency of the second clock signal is increased.
Therefore, in the first disc reproducing apparatus according to the present invention, the frequency of the first clock signal supplied to the digital data generating means is changed according to the frequency of the clock component of the reproduced signal. In this way, since the frequency of the first clock signal is changed in accordance with the frequency of the clock component of the reproduction signal, the first clock having a frequency higher than necessary during reproduction of the inner periphery of the disk having a low frequency of the clock component of the reproduction signal. Sampling is not performed based on the signal, and wasteful power can be prevented from being consumed.

  In the first specific configuration, the clock supply means detects the distance from the center of the disc to the reproduction position in the radial direction and the digital data generation means to be supplied to the digital data generation means from the detected distance. Frequency calculating means for calculating the frequency of one clock signal and signal supply means for supplying a first clock signal having the calculated frequency to the digital data generating means.

  The frequency of the clock component of the reproduction signal is proportional to the distance from the center of the disc to the reproduction position in the radial direction. Therefore, in the above specific configuration, the distance from the center of the disk to the reproduction position in the radial direction is detected, and the frequency of the first clock signal is calculated from the detected distance. For example, the frequency of the clock component of the reproduction signal is calculated by multiplying the detected distance by a predetermined value, and the frequency of the first clock signal is calculated from the frequency.

  In the second specific configuration, the track formed on the disk meanders at a constant period, and includes a period detecting means for detecting a meandering period based on a meandering signal obtained from the disk at the time of signal reproduction, A clock supply unit configured to calculate a frequency of a first clock signal to be supplied to the digital data generation unit from the detected meandering period; a first clock signal having the calculated frequency to the digital data generation unit; And a signal supply means for supplying to the signal.

  The frequency of the clock component of the reproduction signal is proportional to the meandering frequency of the track. Therefore, in the above specific configuration, the meander cycle is detected based on the meander signal obtained from the disk, and the frequency of the first clock signal is calculated from the detected meander cycle. As a meander cycle detection method, for example, there is a method in which the meander signal is compared with a predetermined binarization level to generate a binary signal, and the pulse width of the generated binarization signal is detected as a meander cycle. Adopted.

  In the third specific configuration, the tracks formed on the disk meander at a constant period, and the clock supply means generates the first clock signal from the meander signal obtained from the disk during signal reproduction.

  As described above, the frequency of the clock component of the reproduction signal is proportional to the meandering frequency of the track. Therefore, in the above specific configuration, the first clock signal is generated from the meandering signal obtained from the disk.

Specifically, the clock supply means includes
Means for comparing the meandering signal with a predetermined binarization level to generate a binarized signal;
First frequency dividing means for frequency-dividing the frequency of the generated binarized signal by a first frequency division ratio 1 / m (m is an integer of 1 or more);
Second frequency dividing means for frequency-dividing the frequency of the generated first clock signal by a second frequency dividing ratio 1 / n (n is an integer of 1 or more and n>m);
Comparing means for comparing the phase of the first frequency-divided signal obtained from the first frequency-dividing means and the phase of the second frequency-divided signal obtained from the second frequency-dividing means;
Signal generating means for generating a first clock signal having a frequency n / m times the frequency of the meandering signal based on the comparison result of the comparing means;

  In the specific configuration, a first clock signal having a frequency n / m times the frequency of the signal is generated from the meandering signal obtained from the disk.

  According to a fourth specific configuration, the apparatus further comprises period detecting means for detecting a period corresponding to the period of the clock component of the reproduced signal based on the signal reproduced from the disk, and the clock supplying means is detected. A frequency calculating means for calculating the frequency of the first clock signal to be supplied to the digital data generating means from a period; and a signal supplying means for supplying the first clock signal having the calculated frequency to the digital data generating means. It is.

  Specifically, the period detecting unit compares the reproduction signal with a predetermined binarization level to generate a binarized signal, and a pulse width for detecting the pulse width of the generated binarized signal. Detection means and extraction means for extracting the maximum pulse width or the minimum pulse width from the detected pulse width are provided.

Information recorded on the disc is modulated according to a predetermined modulation rule. For example, EFM (Eight to Fourteen Modulation) is applied to CDs, 8/16 modulation is applied to DVDs, and ETM (Eight to Twelve Modulation) is applied to HD-DVDs. The length is specified. The time width of the longest and shortest marks and spaces changes according to the frequency of the clock component of the reproduction signal.
Therefore, in the above specific configuration, a binarized signal is generated from the reproduction signal, the longest pulse width or the shortest pulse width is extracted from the pulse width of the binarized signal, and the extracted longest pulse width or shortest pulse width is extracted. The frequency of the first clock signal is calculated from the pulse width.

A second disk reproducing apparatus according to the present invention is
Playback means for playing back signals recorded on the disc;
A digital data generation means for supplying a first clock signal from the outside and performing a sampling process at a frequency corresponding to the frequency of the first clock signal on the signal reproduced from the disc to generate digital data;
The frequency / period information of the virtual second clock signal having a frequency corresponding to the frequency of the clock component of the reproduction signal is supplied from the outside, and the digital data obtained from the digital data generating means corresponds to the frequency / period information. Interpolation means for performing interpolation processing at a frequency to generate interpolation data;
A frequency / period control means for supplying frequency / period information corresponding to the interpolation data obtained from the interpolation means to the interpolation means;
Clock supply means for supplying a first clock signal to the digital data generating means;
Based on the frequency / period information obtained from the frequency / period control means, the ratio of the period of the second clock signal to the period of the first clock signal or the ratio of the period of the first clock signal to the period of the second clock signal is calculated. The clock supply means controls the frequency of the first clock signal so that the ratio calculated by the ratio calculation means becomes a constant value.

In the second disk reproducing apparatus according to the present invention, the ratio of the period of the second clock signal to the period of the first clock signal or the ratio of the period of the first clock signal to the period of the second clock signal is a constant value. Thus, the frequency of the first clock signal supplied to the digital data generating means is controlled. For example, by controlling the ratio of the period of the second clock signal to the period of the first clock signal to be a constant value greater than 1 or 1, the frequency of the first clock signal is always the same as the frequency of the second clock signal or It can be kept higher than the frequency.
The frequency of the first clock signal is controlled so that the ratio of the period of the second clock signal to the period of the first clock signal or the ratio of the period of the first clock signal to the period of the second clock signal becomes a constant value. Therefore, sampling is not performed based on the first clock signal having a frequency higher than necessary during reproduction of the inner periphery of the disc, and wasteful power consumption can be prevented.

A third disc reproducing apparatus according to the present invention is
Playback means for playing back signals recorded on the disc;
A digital data generation means for supplying a first clock signal from the outside and performing a sampling process at a frequency corresponding to the frequency of the first clock signal on the signal reproduced from the disc to generate digital data;
The frequency / period information of the virtual second clock signal having a frequency corresponding to the frequency of the clock component of the reproduction signal is supplied from the outside, and the digital data obtained from the digital data generating means corresponds to the frequency / period information. Interpolation means for performing interpolation processing at a frequency to generate interpolation data;
A frequency / period control means for supplying frequency / period information corresponding to the interpolation data obtained from the interpolation means to the interpolation means;
Clock supply means for supplying the first clock signal to the digital data generating means, and the frequency / period information represents the frequency or period of the first clock signal as a fixed value, and the second clock based on the fixed value. The clock supply means controls the frequency of the first clock signal so that the frequency / period information obtained from the frequency / period control means becomes a constant value.

In the third disk reproducing apparatus according to the present invention, the frequency of the first clock signal supplied to the digital data generating means is controlled so that the frequency / period information of the second clock signal becomes a constant value. For example, when the frequency / period information represents the period of the second clock signal, the frequency / period information is controlled to be a constant value that is the same as or larger than the fixed value representing the period of the first clock signal. By doing so, the frequency of the first clock signal can always be kept equal to or higher than the frequency of the second clock signal.
Further, by controlling the frequency of the first clock signal so that the frequency / period information of the second clock signal becomes a constant value, the ratio of the frequency of the first clock signal to the frequency of the second clock signal becomes constant. Sampling is not performed based on the first clock signal having a frequency higher than necessary during reproduction of the inner periphery of the disc, and wasteful power consumption can be prevented.

  According to the first to third disk reproducing apparatuses according to the present invention, when a signal recorded on the disk by the constant linear velocity control is reproduced by the constant angular velocity control, wasteful power is consumed at the time of reproducing the inner peripheral portion of the disk. It is possible to prevent consumption.

Hereinafter, embodiments of the present invention will be specifically described based on five examples.
First Embodiment As shown in FIG. 1, the disk reproducing apparatus of the present embodiment has a position sensor (7) for detecting the reproducing position in the radial direction of the disk, and the frequency changes according to the output of the position sensor (7). A variable oscillation circuit (6) for generating a variable clock and supplying the variable clock to the A / D conversion circuit (3);
In the disc reproducing apparatus, a signal recorded on the disc (1) is reproduced by an optical pickup (2), and the reproduced signal is supplied to an A / D conversion circuit (3). In the A / D conversion circuit (3), the reproduction signal is sampled at the frequency of the variable clock supplied from the variable oscillation circuit (6) and converted into multivalued digital data D1. The digital data is supplied to the interpolation circuit (4) and subjected to interpolation processing in a cycle represented by the virtual clock cycle information PH2 supplied from the outside. The configuration and operation of the interpolation circuit (4) are variable in the second register (422) of the first phase difference calculation circuit shown in FIG. 18 and the second register (442) of the second phase difference calculation circuit shown in FIG. This is the same as the conventional disk reproducing apparatus except that a predetermined fixed value PH1 representing the clock period is stored. The interpolation data D2 obtained by the interpolation processing is supplied to the zero-cross extraction circuit (51) of the virtual clock cycle control circuit (5), and the zero-cross data to be zero-crossed from the interpolation data is phased with the clock component of the reproduction signal. It is extracted as error information Δφ. The extracted phase error information Δφ is supplied to the integration circuit (52) and integrated, and the integration result is supplied to the digital oscillator (53). The digital oscillator (53) manages the cycle of the virtual clock in arithmetic processing, and the integration is performed so that the phase and frequency of the virtual clock coincide with the phase and frequency of the clock component (channel clock) of the reproduction signal. The period of the virtual clock is controlled according to the result. The configuration and operation of the digital oscillator (53) are the same as those of the conventional disk reproducing apparatus. The cycle information PH2 of the virtual clock is supplied to the interpolation circuit (4) and used for interpolation processing. In this way, a digital PLL circuit is formed from the interpolation circuit (4) and the virtual clock cycle control circuit (5).
The interpolation circuit (4), the zero cross extraction circuit (51), the integration circuit (52) and the digital oscillator (53) are supplied with a variable clock from the variable oscillation circuit (6). The action is executed.

The variable oscillation circuit (6) calculates the radial distance from the center of the disk to the reproduction position based on the output of the position sensor (7). As a method of calculating the radial distance from the center of the disc to the radial reproduction position, various methods such as a method of calculating based on address information recorded on the disc can be adopted.
After calculating the frequency of the clock component of the reproduction signal by multiplying the calculated distance by the proportionality constant, the frequency of the clock component of the reproduction signal is fch and the proportionality constant is k1. calculate.

(Equation 2)
fs = k1 · fch

  Here, since the frequency of the clock component of the reproduction signal fluctuates about several percent due to the eccentricity of the disk, the proportionality constant k1 of the above formula 2 is set to a value of 1.1 to 1.2.

FIG. 2 shows the relationship between the reproduction position in the radial direction of the disk (1), the frequency of the variable clock, and the frequency of the virtual clock.
Since the frequency of the clock component of the reproduction signal is proportional to the radial distance from the center of the disc to the reproduction position, the frequency of the virtual clock controlled to be equal to the frequency of the clock component of the reproduction signal is a straight line ( As shown by a), it is proportional to the distance and becomes higher as the reproduction position is on the outer peripheral side. Further, since the frequency fs of the variable clock is calculated from the above equation 2, as shown by the straight line (b) in the figure, it is proportional to the radial distance from the center of the disk to the reproduction position, and the reproduction position is on the outer peripheral side. The higher it is, the higher it is. Here, since the proportional constant k1 (= f2 / f1) of the above formula 2 is set to a value of 1.1 to 1.2, the frequency of the variable clock is changed from the radius R1 of the innermost circumference of the disk to the radius of the outermost circumference. It becomes higher than the frequency of the virtual clock over R2. The straight line (c) in the figure represents the change in the frequency of the conventional fixed clock.

In the variable oscillation circuit (6) shown in FIG. 1, a variable clock having the frequency calculated as described above is generated, and the variable clock is supplied to the A / D conversion circuit (3).
In the A / D conversion circuit (3), sampling data is obtained at the cycle of the variable clock supplied from the variable oscillation circuit (6), and the sampling data is supplied to the interpolation circuit (4).
In the interpolation circuit (4), the interpolation data D2 (n) is generated from the two sampling data D1 (n) and D1 (n + 1). Here, since the frequency of the variable clock is always set to a value larger than the frequency of the virtual clock as described above, at least one sampling data always exists between two adjacent interpolation data. Interpolation processing is normally performed.

  In the disk reproducing apparatus of this embodiment, as indicated by the straight line (b) in FIG. 2, the frequency of the variable clock is changed in accordance with the reproducing position in the radial direction of the disk. When playing back a signal with constant angular velocity control, sampling is not performed based on a variable clock with a frequency higher than necessary during playback of the inner periphery of the disc, and wasteful power consumption is prevented. I can do it.

  In the above embodiment, the frequency of the variable clock is calculated from the above formula 2. However, the frequency fs of the variable clock only needs to increase as the frequency fch of the clock component of the reproduction signal increases. It is also possible to calculate from 3.

(Equation 3)
fs = fch + fofs
fofs> 0: offset frequency

Second Embodiment The disk reproducing apparatus of the first embodiment calculates the frequency of the variable clock from the radial distance from the center of the disk to the reproducing position, whereas the disk reproducing apparatus of the present embodiment is The frequency of the variable clock is calculated from the wobble period of the track formed on the disk.

  As shown in FIG. 3, the disk reproducing apparatus of this embodiment includes a period detecting circuit (8) for detecting a wobble period based on a wobble signal obtained from the disk (1) during signal reproduction, and a period detecting circuit (8). A variable oscillation circuit (61) that generates a variable clock whose frequency changes according to the detected wobble period and supplies the variable clock to the A / D conversion circuit (3) is provided. Other configurations are the same as those of the first embodiment, and thus the description thereof is omitted.

  A plurality of tracks are formed on a disk such as a DVD-R, a DVD-RW, or a DVD-RAM as shown in FIG. 5, and these tracks meander (wobble) at a constant cycle. As in the first embodiment, the reproduction signal supplied to the A / D conversion circuit (3) shown in FIG. 3 is obtained by collecting and tracing the laser beam on a track on the disk and forming information pits formed on the track. This is an addition signal (SIGA + SIGB) representing all changes in the amount of reflected light obtained by modulation by the so-called RF signal. On the other hand, the wobble signal supplied to the period detection circuit (8) is a so-called differential push-pull signal, which is a differential signal (SIGA-SIGB) of changes in the amount of reflected light on the inner and outer peripheral sides of the track. The modulated signal due to the information pit is removed from the signal by differential processing.

FIG. 4 shows the configuration of the period detection circuit (8). The wobble signal obtained from the disk (1) is supplied to the binarization circuit (81), and a predetermined dotted line shown in FIG. 6 (a). The binarized signal shown in FIG. 4 (b) is generated by comparing with the binarized level. Here, the binarization level is set to a value at which the ratio of the values “0” and “1” constituting the binarized signal is substantially equal.
The generated binarized signal is supplied to the period counter (82). The period counter 82 is supplied with a fixed clock having a constant frequency shown in FIG. 6C from the outside, and the number of fixed clocks supplied between the edges of the binarized signal is shown in FIG. It counts as follows. The count result is supplied to the variable oscillation circuit 61 shown in FIG. 3 as wobble cycle information shown in FIG.
By the way, at the time of signal recording, a clock having a frequency that is a predetermined multiple of the wobble frequency is generated and a signal is recorded at that clock frequency. Therefore, the frequency of the clock component of the reproduced signal is proportional to the wobble frequency. Therefore, the frequency of the virtual clock controlled to be equal to the frequency of the clock component of the reproduction signal is proportional to the wobble frequency.
Therefore, the variable oscillation circuit 61 calculates the frequency of the variable clock by multiplying the inverse of the wobble period, that is, the wobble frequency by a proportional constant k2 (k2> 1). Here, the proportional constant k2 is set to a value at which the frequency of the variable clock is 1.1 to 1.2 times the frequency of the virtual clock.

FIG. 7 shows the relationship between the wobble frequency, the variable clock frequency, and the virtual clock frequency.
The frequency of the virtual clock is proportional to the wobble frequency as indicated by the alternate long and short dash line in the figure, and increases as the wobble frequency increases. Further, since the frequency of the variable clock is calculated by multiplying the wobble frequency by the proportional constant k2 as described above, it is proportional to the wobble frequency as indicated by the broken line in the figure, and increases as the wobble frequency increases. Here, since the proportional constant k2 is set to a value at which the frequency of the variable clock is 1.1 to 1.2 times the frequency of the virtual clock, the frequency of the variable clock is always virtual regardless of the wobble frequency. It becomes higher than the clock frequency.

In the variable oscillation circuit (61) shown in FIG. 3, a variable clock having the frequency calculated as described above is generated, and the variable clock is supplied to the A / D conversion circuit (3).
In the A / D conversion circuit (3), sampling data is obtained at the cycle of the variable clock supplied from the variable oscillation circuit (61), and the sampling data is supplied to the interpolation circuit (4).
In the interpolation circuit (4), the interpolation data D2 (n) is generated from the two sampling data D1 (n) and D1 (n + 1). Here, since the frequency of the variable clock is always set to a value larger than the frequency of the virtual clock as described above, at least one sampling data always exists between two adjacent interpolation data. Interpolation processing is normally performed.

  In the disk reproducing apparatus of the present embodiment, the frequency of the variable clock is changed according to the wobble frequency as described above. Therefore, when the signal recorded on the disk by the constant linear velocity control is reproduced by the constant angular velocity control, the variable clock frequency is variable. The frequency of the clock changes according to the frequency of the clock component of the reproduction signal. Therefore, sampling is not performed based on a variable clock having a frequency higher than necessary during reproduction of the inner periphery of the disc, and wasteful power consumption can be prevented.

  In the above embodiment, the frequency of the variable clock is continuously changed according to the wobble frequency as shown by the broken line in FIG. 7, but can be changed stepwise as shown by the solid line in FIG. It is. In a configuration in which the frequency of the variable clock is changed stepwise, when a disc having a plurality of zones formed in the radial direction of the disc, such as a DVD-RAM, is played, the playback position moves between the zones. It is desirable to change the frequency of the variable clock.

  Further, as shown in FIG. 8, a frequency divider (83) is provided between the binarization circuit (81) of the period detection circuit (80) and the period counter (82), and the binarization circuit (81) The obtained binarized signal can be divided by the frequency divider (83), and the number of clocks between edges of the binarized signal after the frequency division can be counted by the period counter (82). According to this configuration, the wobble cycle can be detected with high accuracy.

Third Embodiment The disc reproducing apparatus of the second embodiment detects the wobble period based on the wobble signal obtained from the disc, and calculates the frequency of the variable clock based on the detection result. The disc reproducing apparatus of the embodiment generates a variable clock from a wobble signal obtained from a disc.

  As shown in FIG. 9, the disk reproducing apparatus of this embodiment generates a variable clock from a wobble signal obtained from the disk (1) during signal reproduction and supplies it to an A / D converter circuit (3). ). Other configurations are the same as those of the first embodiment, and thus the description thereof is omitted.

FIG. 10 shows the configuration of the variable oscillation circuit (9). The wobble signal obtained from the disk (1) is supplied to the binarization circuit (91) and compared with a predetermined binarization level to obtain a binary value. A generated signal is generated. Here, the binarization level is set to a value at which the ratio of the values “0” and “1” constituting the binarized signal is substantially equal.
The generated binarized signal is supplied to the first frequency divider (92) and divided by a frequency division ratio of 1 / m (m ≧ 1), and a clock obtained thereby is input to the phase comparator (93). Is done. Further, the variable clock output from the VCO (96) is supplied to the second frequency divider (97) and is divided by a frequency division ratio of 1 / n (n ≧ 1 and n> m), and thus obtained. A clock is input to the phase comparator (93). In the phase comparator (93), the phases of the two input clocks are compared to generate a phase error signal, which is supplied to the charge pump (94). A current having a magnitude corresponding to the phase error signal is supplied from the charge pump (94) to the loop filter (95), integrated by the loop filter (95), and then converted into a voltage. The output voltage of the loop filter (95) is input to the VCO (96), and the output frequency of the VCO (96) is controlled. In this way, a feedback loop is formed to match the frequency 1 / m times the wobble signal with the frequency 1 / n times the variable clock output from the VCO (96). A variable clock having a frequency of n / m times is output. Here, as described above, since the frequency of the virtual clock is proportional to the wobble frequency, the ratio of the frequency of the variable clock to the frequency of the virtual clock is constant. Therefore, the frequency division ratios 1 / m and 1 / n are set to values at which the ratio is 1.1 to 1.2.

The variable clock output from the VCO (96) is supplied to the A / D conversion circuit (3) shown in FIG.
In the A / D conversion circuit (3), sampling data is obtained at the cycle of the variable clock supplied from the variable oscillation circuit (9), and the sampling data is supplied to the interpolation circuit (4).
In the interpolation circuit (4), interpolation data D2 (n) is generated from the two sampling data D1 (n) and D1 (n + 1) by linear interpolation calculation. Here, the frequency division ratios 1 / m and 1 / n are set to values at which the ratio of the frequency of the variable clock to the frequency of the virtual clock is 1.1 to 1.2 as described above. At least one sampling data always exists between two adjacent interpolation data, and the interpolation process is normally performed.

  In the disk reproducing apparatus of this embodiment, as described above, a variable clock having a frequency n / m times the frequency of the signal is generated from the wobble signal, so that the signal recorded on the disk with constant linear velocity control can be obtained. When reproduction is performed with constant angular velocity control, the frequency of the variable clock changes in accordance with the frequency of the clock component of the reproduction signal. Therefore, sampling is not performed based on a variable clock having a frequency higher than necessary during reproduction of the inner periphery of the disc, and wasteful power consumption can be prevented.

Fourth Embodiment The disk reproducing apparatus of the second embodiment calculates the frequency of the variable clock based on the wobble signal, whereas the disk reproducing apparatus of the present embodiment is based on the reproduction signal (RF signal). Thus, the frequency of the variable clock is calculated.

  As shown in FIG. 11, the disk reproducing apparatus of the present embodiment is a period detection circuit that detects a period corresponding to the period of the clock component of the reproduced signal based on the signal (RF signal) reproduced from the disk (1). 84) and a variable oscillation circuit (62) that generates a variable clock whose frequency changes according to the period detected by the period detection circuit (84) and supplies the variable clock to the A / D conversion circuit (3). . Other configurations are the same as those of the first embodiment, and thus the description thereof is omitted.

FIG. 12 shows a configuration of the period detection circuit (84). A signal reproduced from the disk (1) is supplied to the binarization circuit (841), and a predetermined line indicated by a broken line in FIG. 13 (a). Compared with the binarization level, the binarization signal shown in FIG. Here, the binarization level is set to a value at which the ratio of the values “0” and “1” constituting the binarized signal is substantially equal.
The generated binarized signal is supplied to the edge interval detection circuit (842). Further, the fixed interval clock shown in FIG. 13C is externally supplied to the edge interval detection circuit 842, and the number of fixed clocks supplied between the edges of the binarized signal is shown in FIG. It is counted as in d). Then, those count values are supplied to the maximum value extraction circuit (843).

By the way, the information recorded on the disc is modulated according to a predetermined modulation rule. For example, EFM is applied to CDs, 8/16 modulation is applied to DVDs, and ETM is applied to HD-DVDs. The maximum run length and the minimum run length are defined by the modulation rule. The time width of the longest and shortest marks and spaces changes according to the frequency of the clock component of the reproduction signal.
Therefore, in the maximum value extraction circuit (843), the maximum count value, that is, the count value at the longest mark or the longest space is extracted from the supplied count values, and the extracted maximum count value is the variable oscillation shown in FIG. It is supplied to the circuit (62).
The variable oscillation circuit (62) calculates the frequency of the variable clock by multiplying the maximum count value by a proportional constant k3 (k3> 1). Here, the proportionality constant k3 is set to a value in which the frequency of the variable clock is 1.1 to 1.2 times the frequency of the clock component of the reproduction signal estimated from the maximum count value. As described above, since the frequency of the virtual clock is controlled to be equal to the frequency of the clock component of the reproduced signal, the frequency of the variable clock is always 1.1 to 1.2 times the frequency of the virtual clock.

In the variable oscillation circuit (62), a variable clock having the frequency calculated as described above is generated, and the variable clock is supplied to the A / D conversion circuit (3).
In the A / D conversion circuit (3), sampling data is obtained at the cycle of the variable clock supplied from the variable oscillation circuit (62), and the sampling data is supplied to the interpolation circuit (4).
In the interpolation circuit (4), interpolation data D2 (n) is generated from the two sampling data D1 (n) and D1 (n + 1) by linear interpolation calculation. Here, since the frequency of the variable clock is always 1.1 to 1.2 times the frequency of the virtual clock as described above, at least one sampling data always exists between two adjacent interpolation data. Thus, the interpolation process is normally performed.

  In the disc reproducing apparatus of the present embodiment, as described above, the frequency of the variable clock is changed according to the count value in the longest mark or the longest space formed on the disc, so that it is recorded on the disc with constant linear velocity control. When the existing signal is reproduced by the constant angular velocity control, the frequency of the variable clock changes according to the frequency of the clock component of the reproduced signal. Therefore, sampling is not performed based on a variable clock having a frequency higher than necessary during reproduction of the inner periphery of the disc, and wasteful power consumption can be prevented.

  Note that a synchronization pattern that violates the modulation rule is formed at a predetermined period on a disc such as a CD, DVD, or HD-DVD. The appearance interval of the synchronization pattern is counted by a counter, and the variable clock is calculated from the counted value. It is also possible to calculate the frequency.

Fifth Embodiment FIG. 14 shows the configuration of a disk reproducing apparatus according to the present embodiment. As shown in the figure, the disk reproducing apparatus compares a fixed value PH1 representing a variable clock period with virtual clock period information PH2. A value comparison circuit (10) for generating a variable clock whose frequency changes in accordance with a comparison result between the comparison result of the value comparison circuit (10) and a constant value R supplied from the outside, and an A / D conversion circuit And a variable oscillation circuit (63) for supplying to (3). The value comparison circuit (10) performs an operation described later based on the variable clock supplied from the variable oscillation circuit (63). Other configurations are the same as those of the first embodiment, and thus the description thereof is omitted.

  In the value comparison circuit (10), the ratio of the virtual clock period information PH2 to the fixed value PH1 representing the period of the variable clock is calculated, and the calculated ratio PH2 / PH1 is supplied to the variable oscillation circuit (63). In the variable oscillation circuit (63), the frequency of the variable clock is controlled so that the ratio PH2 / PH1 becomes a constant value R. Here, the ratio PH2 / PH1 represents the ratio of the period of the virtual clock to the period of the variable clock, and the constant value R is set to 1.1 to 1.2. As a result, the frequency of the variable clock is always set to 1.1 to 1.2 times that of the virtual clock.

The variable clock obtained from the variable oscillation circuit (63) is supplied to the A / D conversion circuit (3).
In the A / D conversion circuit (3), sampling data is obtained at the cycle of the variable clock supplied from the variable oscillation circuit (63), and the sampling data is supplied to the interpolation circuit (4).
In the interpolation circuit (4), interpolation data D2 (n) is generated from the two sampling data D1 (n) and D1 (n + 1) by linear interpolation calculation. Here, since the frequency of the variable clock is always set to a value larger than the frequency of the virtual clock as described above, at least one sampling data always exists between two adjacent interpolation data. Interpolation processing is normally performed.

In the above disk reproducing apparatus, the frequency of the virtual clock is 100 MHz and the frequency of the variable clock is 1.1 times the frequency of the virtual clock when the signal recorded on the innermost circumference of the disk is reproduced at a single speed. If the optical pickup (2) is moved from this state to the outermost periphery of the disk, the frequency of the variable clock is once 1.1 times the frequency of the virtual clock at the outermost periphery of the disk. It is fixed at 275 MHz. Then, after phase synchronization is established by the digital PLL circuit, frequency control by the variable oscillation circuit (63) is started.
Further, when the signal recorded on the outermost periphery of the disk is reproduced at 2.5 times speed, the frequency of the virtual clock is 250 MHz, and the variable clock frequency is 275 MHz which is 1.1 times the frequency of the virtual clock. Then, when moving the optical pickup (2) from this state to the innermost circumference of the disk, the frequency of the variable clock is once fixed at 110 MHz, which is 1.1 times the frequency of the virtual clock at the innermost circumference of the disk. Is done. Then, after phase synchronization is established by the digital PLL circuit, frequency control by the variable oscillation circuit (63) is started.

  In the disk reproducing apparatus of the present embodiment, the frequency of the variable clock is controlled so that the ratio of the virtual clock period information PH2 to the fixed value PH1 representing the period of the clock becomes a constant value R. When a signal recorded on a disc is played back with constant angular velocity control, sampling is not performed based on a variable clock with a frequency higher than necessary during playback of the inner periphery of the disc, and wasted power is consumed. Can be prevented.

  Instead of the variable oscillation circuit (63) and the value comparison circuit (10) of this embodiment, as shown in FIG. 15, the virtual clock cycle information PH2 is 1.1 to 1.1 of the fixed value PH1 representing the cycle of the variable clock. It is also possible to provide a variable oscillation circuit (64) for controlling the frequency of the variable clock so that the constant value becomes 1.2 times.

  In the first to fifth embodiments, the response speed of the variable oscillation circuits (6) (61) (9) (62) (63) is sufficiently higher than the response speed of the phase locked loop of the digital PLL circuit. It is desirable to set it late.

  In the first to fifth embodiments, a configuration is adopted in which zero-cross data to be zero-crossed is extracted from a plurality of generated interpolation data as phase error information Δφ with the clock component of the reproduction signal. The present invention is not limited to this, and various methods for detecting the phase error from the interpolation data can be employed. For example, depending on the waveform of the reproduction signal, the phase error can be detected from the average value of the interpolation data before and after the zero cross point.

  Further, in the first to fifth embodiments, the digital oscillator 53 controls the cycle of the virtual clock so that the frequency fdo of the virtual clock is equal to the frequency fch of the clock component of the reproduction signal. It is also possible to control the cycle of the virtual clock so that the frequency fdo of the virtual clock is t times the frequency fch of the clock component of the reproduction signal as shown in the following equation 4.

(Equation 4)
fdo = t · fch
t> 1

  In the configuration in which the frequency of the virtual clock is calculated from the above equation 4, the A / D conversion circuit (3) performs sampling at a frequency t times the frequency of the variable clock. Alternatively, the interpolation circuit (4) performs an interpolation process at a frequency of 1 / t times.

It is a block diagram showing the structure of the disc reproducing | regenerating apparatus of 1st Example. It is a graph showing the relationship between the reproduction position in the radial direction of the disk, the frequency of the variable clock, and the frequency of the virtual clock. It is a block diagram showing the structure of the disc reproducing | regenerating apparatus of 2nd Example. It is a block diagram showing the specific structure of the period detection circuit of the said disk reproducing | regenerating apparatus. It is a figure showing the track currently formed in the disc. It is a wave form diagram of various signals obtained in the above-mentioned period detection circuit. It is a graph showing the relationship between the wobble frequency, the frequency of the variable clock, and the frequency of the virtual clock. It is a block diagram showing the modification of the said period detection circuit. It is a block diagram showing the structure of the disc reproducing | regenerating apparatus of 3rd Example. It is a block diagram showing the specific structure of the variable oscillation circuit of the said disk reproducing | regenerating apparatus. It is a block diagram showing the structure of the disc reproducing | regenerating apparatus of 4th Example. It is a block diagram showing the specific structure of the period detection circuit of the said disk reproducing | regenerating apparatus. It is a wave form diagram of various signals obtained in the above-mentioned period detection circuit. It is a block diagram showing the structure of the disc reproducing | regenerating apparatus of 5th Example. It is a block diagram showing the modification of the said disk reproducing | regenerating apparatus. It is a block diagram showing the structure of the conventional disc reproducing | regenerating apparatus. It is a block diagram showing the specific structure of an interpolation circuit. It is a block diagram showing the specific structure of the 1st phase difference calculation circuit of the said interpolation circuit. It is a block diagram showing the specific structure of the 2nd phase difference calculation circuit of the said interpolation circuit. It is a wave form diagram explaining the procedure which calculates | requires a phase error. It is a graph explaining operation | movement of the said interpolation circuit.

Explanation of symbols

(1) Disc
(2) Optical pickup
(3) A / D conversion circuit
(4) Interpolation circuit
(5) Variable clock cycle control circuit
(51) Zero cross extraction circuit
(52) Integration circuit
(53) Digital oscillator
(6) Variable oscillation circuit

Claims (3)

In a disc reproducing apparatus capable of reproducing a signal recorded on a disc with constant linear velocity control with constant angular velocity control,
Reproducing means for reproducing a signal from the disk with constant angular velocity control;
Digital data generating means for receiving the supply of the first clock signal and generating a digital data by subjecting the signal obtained from the reproducing means to sampling processing at a frequency corresponding to the frequency of the first clock signal;
In response to the supply of the frequency / period information of the virtual second clock signal having a frequency corresponding to the frequency of the clock component of the reproduction signal, the digital data obtained from the digital data generating means is responsive to the frequency / period information. Interpolation means for performing interpolation processing at a frequency to generate interpolation data;
A frequency / period control means for supplying frequency / period information corresponding to the interpolation data obtained from the interpolation means to the interpolation means;
Clock supply means for supplying a first clock signal to the digital data generating means;
Based on the frequency / period information obtained from the frequency / period control means, the ratio of the period of the second clock signal to the period of the first clock signal or the ratio of the period of the first clock signal to the period of the second clock signal is calculated. Ratio calculating means for calculating, and the clock supplying means controls the frequency of the first clock signal to supply the digital data generating means with the frequency calculated by the ratio calculating means to be a constant value. A disc player characterized by the above. The frequency / period information represents a period of the first clock signal as a fixed value, and represents a period of the second clock signal with the fixed value as a reference. 2. The disk reproducing apparatus according to claim 1 , wherein the ratio of the period of the second clock signal to the period of the first clock signal is calculated by dividing by the fixed value. In a disc reproducing apparatus capable of reproducing a signal recorded on a disc with constant linear velocity control with constant angular velocity control,
Reproducing means for reproducing a signal from the disk with constant angular velocity control;
Digital data generating means for receiving the supply of the first clock signal and generating a digital data by subjecting the signal obtained from the reproducing means to sampling processing at a frequency corresponding to the frequency of the first clock signal;
In response to the supply of the frequency / period information of the virtual second clock signal having a frequency corresponding to the frequency of the clock component of the reproduction signal, the digital data obtained from the digital data generating means is responsive to the frequency / period information. Interpolation means for performing interpolation processing at a frequency to generate interpolation data;
A frequency / period control means for supplying frequency / period information corresponding to the interpolation data obtained from the interpolation means to the interpolation means;
Clock supply means for supplying the first clock signal to the digital data generating means, and the frequency / period information represents the frequency or period of the first clock signal as a fixed value, and the second clock based on the fixed value. It represents the frequency or period of the signal,
The disk supply means controls the frequency of the first clock signal so that the frequency / period information obtained from the frequency / period control means becomes a constant value, and supplies it to the digital data generation means. apparatus.

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