JP6630917B2 - Phase error detector and optical disk device - Google Patents

Description

  The present disclosure relates to a phase error detector used in a PLL (Phase Locked Loop) circuit, and an optical disc device that performs address detection and recording using a generated clock.

  In recent years, the recording density of optical disks has been steadily increasing. In the field of video, optical disks such as DVD (Digital Versatile Disc) and BD (Blu-ray (registered trademark) Disc) are well known. These optical discs are used not only for recording video but also as external recording media for personal computers. On the other hand, a hard disk, a flash memory, or the like is also used as an external recording medium of a personal computer. Optical discs have the advantages of longer life, higher reliability, and no need for storage power, as compared to those external recording media.

  Because of these advantages, they have also attracted attention as important data archive media such as data centers. However, BD-XL is currently the largest in capacity, and the capacity of one optical disc is 128 GB. Therefore, the optical disk requires a larger storage space as compared with other external recording media, and further higher density of the capacity is demanded.

  There is a land / groove recording technique as a technique for increasing the density of an optical disc. The optical disc is provided with a guide groove called a groove for controlling a light spot on a recording track with high accuracy. In the land / groove recording technique, user data is recorded not only in grooves but also in guide grooves called lands between grooves. As an optical disk using the land-groove recording technique, a DVD-RAM is well known.

  The optical disk is provided with a physical address for specifying a location on the optical disk for recording and reproducing user data. As a method of forming a physical address, there is a pre-pit used in a DVD-RAM. However, since user data cannot be recorded in the pre-pits, the recording capacity is reduced.

  As another method of forming a physical address, there is a wobble address based on a meandering track (hereinafter, wobble). Since the detection of the physical address by the wobble is detected by a method different from the detection of the recording and reproduction of the user data, the recording capacity does not decrease.

  In the method using a wobble address, a PLL is used for a wobble reproduction signal in order to generate a clock for recording data on an optical disc. The PLL has a phase error detector that detects a phase error that is a difference between the phase of the wobble reproduction signal and the phase of the generated recording clock. The PLL controls the phase of the recording clock so that the phase error approaches zero.

  Patent Document 1 discloses a method of generating a recording clock from a wobble signal. When a recording clock is generated from a wobble signal, linear velocity fluctuations occur due to eccentricity, motor fluctuations, and the like, so that a residual error occurs in the PLL, and the phase error may not be sufficiently close to zero. In this case, recording at an accurate position on the optical disc is hindered. The residual can be reduced by increasing the loop gain of the PLL, but this involves an increase in analog circuits such as an increase in the current of a charge pump used in the PLL.

JP 2008-176832 A

  The present disclosure provides a phase error detector and an optical disk device that reduce a residual of a PLL without adding an analog circuit having a large circuit area.

The phase error detector according to the present disclosure divides a first clock by N (N is a natural number) and outputs a signal at a predetermined timing, and a second clock divides the second clock by M (M is a natural number) to a predetermined value. And the phase at which the value of the N counter becomes 0 and M
The phase comparison is performed with the phase when the value of the counter becomes 0, and the phase when the value of the N counter becomes equal to a value obtained by substantially dividing N by a predetermined value and the value of the M counter become a value obtained by substantially dividing M by a predetermined value. A comparator for performing a phase comparison with the phase when they are equal to each other ; and a combining circuit for generating a phase error based on the comparison result of the comparator , wherein the N counter has a value of 0, N / 8, 2N / 8, 3N / 8, N-3N / 8, N-2N / 8, NN / 8, and outputs a signal. The M counter has a value of 0, The comparator outputs signals at timings of M / 8, 2M / 8, 3M / 8, M-3M / 8, M-2M / 8, and MM / 8, and the comparator sets the value of the N counter to 0. Is compared with the phase when the value of the M counter becomes 0, and the N counter During the period from the rising edge of the signal from the M counter to the rising edge of the signal from the M counter, an up pulse is output, and the period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter is a first phase comparator that outputs a down pulse, and a phase comparison between a phase when the value of the N counter becomes N / 8 and a phase when the value of the M counter becomes M / 8, During the period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter, an up pulse is output, and from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter. The second phase comparator that outputs a down pulse during the period and the value of the N counter becomes 2N / 8 Compare the phase with the phase when the value of the M counter becomes 2M / 8, and output an up pulse during the period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter. A third phase comparator that outputs a down pulse during a period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter, and the value of the N counter becomes 3N / 8 And a phase when the value of the M counter becomes 3M / 8. The period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter is an up pulse. And the period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter is a fourth phase comparator for outputting a down pulse, and a phase between a phase when the value of the N counter is N-3N / 8 and a phase when the value of the M counter is M-3M / 8 A comparison is performed, and an up pulse is output during a period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter, and the signal of the signal from the N counter is output from the rising edge of the signal from the M counter. A fifth phase comparator that outputs a down pulse until a rising edge, a phase when the value of the N counter becomes N−2N / 8, and a value of the M counter becomes M−2M / 8 The up pulse is output during the period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter. A sixth phase comparator that outputs a down pulse during a period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter, and the value of the N counter becomes NN / 8 Is compared with the phase when the value of the M counter becomes M−M / 8, and the period from the rising edge of the signal from the N counter to the rising edge of the signal from the M counter is a seventh phase comparator that outputs an up pulse, and outputs a down pulse during a period from a rising edge of a signal from the M counter to a rising edge of a signal from the N counter. When the first phase comparator outputs an up pulse, the down pulse is fixed at 0, and the down pulse of the first phase comparator is Down pulse of the second phase comparator, down pulse of the third phase comparator, down pulse of the fourth phase comparator, down pulse of the fifth phase comparator, the sixth phase comparator Is output as a down pulse, and when the first phase comparator outputs a down pulse, the up pulse is fixed to 0 and the first pulse is fixed to 0. When the phase comparator does not output a down pulse, the up pulse of the first phase comparator, the up pulse of the second phase comparator, the up pulse of the third phase comparator, and the fourth phase comparison The logical sum of the up pulse of the comparator, the up pulse of the fifth phase comparator, the up pulse of the sixth phase comparator, and the up pulse of the seventh comparator is output as an up pulse .

  According to the phase error detector and the optical disk device of the present disclosure, by increasing the gain of the phase error detector, it is possible to reduce the residual of a PLL using the phase error detector.

FIG. 1 is a schematic diagram of an optical disc according to the embodiment. FIG. 2 is a configuration diagram of the address information of the optical disc in the embodiment. FIG. 3 is a block diagram of the optical disc device according to the embodiment. FIG. 4 is a block diagram of a wobble processing circuit of the optical disc device according to the embodiment. FIG. 5 is a block diagram of a phase error detector of the optical disk device according to the embodiment. FIG. 6 is a graph showing a phase error output with respect to a phase difference of the phase error detector according to the embodiment. FIG. 7 is a block diagram of a hold circuit of the optical disk device according to the embodiment. FIG. 8 is a block diagram of a synthesizer of the optical disk device according to the embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, an unnecessary detailed description may be omitted. For example, a detailed description of well-known matters and a repeated description of substantially the same configuration may be omitted. This is to prevent the following description from being unnecessarily redundant and to facilitate understanding of those skilled in the art.

  The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the claimed subject matter.

(Embodiment 1)
[1-1. Configuration of Optical Disk]
First, an optical disk in which the optical disk device of the present embodiment performs recording / reproduction will be described.

  FIG. 1 is a schematic diagram of an optical disk on which recording / reproduction is performed by the optical disk device of the present embodiment. As shown in FIG. 1, the optical disc 101 has a groove track (hereinafter, groove) 102 formed in a spiral shape. A land track (hereinafter, land) 103 is formed between the groove 102 and a portion sandwiched between the groove 102. The optical disc 101 uses the groove 102 and the land 103 as recording tracks.

  The grooves 102 and the lands 103 divide the track radially into seven to form an ADIP (ADless In Pre-Groove) 104. The ADIP 104 has address information indicating a position on the optical disc 101. The ADIP 104 is an address information unit on the optical disc 101. Since the ADIP 104 is radially divided, the length of the ADIP 104 differs depending on the position. Assuming that the radius of the position where the ADIP 104 is arranged is r, the length of the ADIP 104 is 2 × π × r / 7.

  FIG. 2 is a configuration diagram of the ADIP 104, which is address information according to the present embodiment. The ADIP 104 includes a synchronization unit 201 and an address information unit 202. The synchronization unit 201 is used to detect the timing of performing recording / reproduction of the optical disk device. The address information section 202 stores address information. The address information section 202 includes a plurality of ADIP units 203.

  The ADIP unit 203 includes a monotone wobble unit 204 and an address modulation unit 205. The monotone wobble unit 204 has a phase of a cosine wave in the groove 102. Address modulation section 205 performs predetermined modulation based on 1-bit information of address modulation section 205 and has a phase different from that of the cosine wave of monotone wobble section 204. Therefore, the optical disc device can detect the address information by detecting the address modulation section 205 having a different phase from the phase of the monotone wobble section 204.

  Here, at the time of manufacturing the optical disk, the groove 102 is formed by light beam irradiation. The land 103 is defined as an area sandwiched between adjacent grooves 102. In order to stably reproduce the signal of the monotone wobble section 204 of the land 103, the wobbles of the grooves 102 adjacent in the radial direction of the optical disk must have the same phase. For this purpose, wobbles are formed at a certain angle. The reason why the ADIP 104 of the optical disc 101 is divided at a constant angle is to make the phases of the wobbles of the groove 102 uniform.

  In order to make the phases of the adjacent grooves 102 uniform, the length of the monotone wobble section 204 differs for each radius. The optical disk device generates a clock in which the frequency of the monotone wobble unit 204 is multiplied. The synthesizer performs a rational number multiplication (M / N times: M and N are natural numbers) of the clock frequency on the generated clock, and generates a clock having a frequency corresponding to a substantially constant physical length. The optical disk device performs recording at a substantially constant recording density by recording using this clock.

[1-2. Configuration of Optical Disk Device]
Next, the configuration of the optical disk device according to the present embodiment will be described. FIG. 3 is a block diagram of the optical disk device according to the present embodiment.

  The optical disk device 100 includes an optical head 301, a servo control circuit 302, a signal generation circuit 303, a wobble processing circuit 304, an access timing generation circuit 305, a synthesizer 306, a controller 307, an encoder 308, a recording processing circuit 309, a laser drive circuit 310, A processing circuit 311 and a decoder 312 are provided.

  When the optical disk 101 is inserted into the optical disk device 100, a light beam is emitted from the optical head 301 to the optical disk 101. The light beam reflected by the optical disk 101 is photoelectrically converted by a photodetector (not shown) divided into four in a track direction (tangential direction) and a radial direction (radial direction) included in the optical head 301, and is reflected. The information of the light beam is converted into an electric signal.

  The signal generation circuit 303 generates a focus error signal, a tracking error signal, a wobble signal, and a full addition signal from an electric signal output from the four-division photodetector included in the optical head 301.

  The focus error signal is, for example, a signal detected by an astigmatism method. The focus error signal is a signal obtained by adding two sets of two signals on the diagonal of the 4-split photodetector and calculating the difference therebetween.

  The tracking error signal and the wobble signal are signals detected by the push-pull method. Two sets of two signals of the four-segment photodetector arranged in the tangential direction are respectively added to generate a push-pull signal that is a signal obtained by calculating a difference between the two signals. The tracking error signal is generated by extracting a frequency component from 0 Hz to several tens of kHz from the push-pull signal. The wobble signal is generated by extracting a signal component of several tens of kHz to several MHz from the push-pull signal.

  The full addition signal is a signal obtained by adding all the signals output from the four-divided photodetector, and is a signal indicating the reflected light amount itself of the optical disk.

  The servo control circuit 302 drives the objective lens of the optical head 301 up and down so that the focus error signal generated by the signal generation circuit 303 becomes 0, and focuses the light spot on the recording surface. The servo control circuit 302 drives the objective lens in the radial direction so that the tracking error signal generated by the signal generation circuit 303 becomes 0, thereby tracking the light spot to a land or a groove. Whether the tracking is performed on the land or the groove is determined depending on whether the objective lens is driven outward or inward according to the tracking error signal. The direction of this drive is determined in accordance with an instruction from the controller 307 to track the land or the groove.

  The wobble processing circuit 304 generates and outputs a wobble clock obtained by multiplying the reproduction signal of the monotone wobble unit 204 of the optical disc 101 by using the wobble signal generated by the signal generation circuit 303, reproduces and outputs address information, Generate and output an address timing signal. Details of the wobble processing circuit 304 will be described later. The wobble clock is generated so as to have a period equal to a time obtained by dividing the monotone wobble unit 204 by a predetermined amount. Therefore, when the optical disk 101 is scanned at the same linear velocity, the frequency becomes higher toward the inner circumference and becomes lower toward the outer circumference. When the optical disk 101 is scanned at the same rotation speed, the frequency becomes the same from the inner circumference to the outer circumference.

  The synthesizer 306 multiplies the wobble clock generated by the wobble processing circuit 304 by a rational number so that the optical disk 101 scans at a substantially constant physical length from the inner circumference to the outer circumference, that is, the same frequency when scanning at the same linear velocity. Is converted to a recording clock. Specifically, the synthesizer 306 uses the coefficient M and the coefficient N provided from the controller 307 to generate a recording clock such that the frequency is N / M times the frequency of the wobble clock.

  The access timing generation circuit 305 uses the address information, the address timing signal, and the wobble clock generated by the wobble processing circuit 304 to generate a timing signal of a recording target address and a timing signal of a reproduction target address indicating the timing of performing recording and reproduction. I do.

  The reproduction processing circuit 311 extracts binary data as user data from the full addition signal generated by the signal generation circuit 303 according to the timing signal of the reproduction target address generated by the access timing generation circuit 305.

  The decoder 312 demodulates the binary data extracted by the reproduction processing circuit 311 to perform error correction, and outputs the result as reproduction data.

  The encoder 308 receives recording data, which is user data, and adds an error correction code and modulates the data into binary data.

  The recording processing circuit 309 issues a light emission command of the recording power corresponding to the binary data to the laser driving circuit 310 based on the recording clock generated by the synthesizer 306 and the timing signal of the recording target address generated by the access timing generation circuit 305. I do.

  The laser drive circuit 310 drives the optical head 301 in accordance with a recording power emission command of the recording processing circuit 309. As a result, the optical head 301 irradiates the optical disc 101 with a light beam at a recording power stronger than that at the time of reproduction, and recording according to binary data is performed on the optical disc 101.

[1-3. Configuration of Wobble Processing Circuit]
Next, a detailed configuration of the wobble processing circuit 304 will be described. FIG. 4 is a block diagram of the wobble processing circuit 304. The wobble processing circuit 304 includes an ADIP detection circuit 413 and a PLL 414.

  The PLL 414 generates a wobble clock by multiplying the frequency of the wobble signal from the wobble signal. The PLL 414 includes an A / D converter 401, a phase error detector 407, a hold circuit 408, a clock generator 415, and a frequency divider 412.

  The clock generator 415 includes a first charge pump 409, a first filter 410, and a first VCO (Voltage Controlled Oscillator) 411.

  The ADIP detection circuit 413 includes a synchronization detection circuit 402, an ADIP timing generation circuit 406, a hold timing generation circuit 405, and an address detection circuit 403. The ADIP detection circuit 413 generates and outputs address information and an address timing signal from the digital wobble signal.

  The A / D converter 401 digitizes the wobble signal at a sampling cycle based on the wobble clock, and outputs it as a digital wobble signal to the phase error detector 407, the synchronization detection circuit 402 of the ADIP detection circuit 413, and the address detection circuit 403.

  The frequency divider 412 divides the wobble clock by 24, and outputs a frequency-divided phase, which is a signal indicating the phase in one cycle after the frequency division, to the phase error detector 407. The multiplication frequency division phase is a signal which increases by one from -12 to 11 every wobble clock, and returns to -12 after 11. The cycle of the multiplication and division phase is the same as 24 times the cycle of the wobble clock.

  The phase error detector 407 detects and outputs a phase error between a wobble carrier component included in the digital wobble signal output from the A / D converter 401 and the multiplied divided phase.

  The synchronization detection circuit 402 detects the synchronization unit 201 of the optical disc 101 from the digital wobble signal.

  The ADIP timing generation circuit 406 generates an address timing signal for specifying the position of the synchronization unit 201 in the ADIP 104 based on the timing at which the synchronization unit 201 is detected.

  The address detection circuit 403 specifies a timing at which the address modulation section 205 is detected according to the address timing signal generated by the ADIP timing generation circuit 406, and determines whether the address information is “0” or “1”. , Sums up the discrimination results, performs error correction, and outputs the result as address information.

  The hold timing generation circuit 405 outputs, as a hold timing signal, a signal specifying the timing of the address modulation unit 205 in which the wobble is modulated, in accordance with the address timing signal generated by the ADIP timing generation circuit 406. The hold timing signal is a signal that is “1” at the timing of the address modulation unit 205 and “0” otherwise.

  The hold circuit 408 outputs the internally held value as a phase error when the hold timing signal indicates the timing of the address modulation unit 205, and outputs the value from the phase error detector 407 at any other timing. Outputs the phase error.

  The first charge pump 409 injects or sucks current according to the output of the hold circuit 408.

  The first filter 410 smoothes the current injection or suction operation of the first charge pump 409, and outputs the voltage as a voltage.

  The first VCO 411 outputs a wobble clock having a frequency corresponding to the voltage output from the first filter 410.

  Note that the PLL 414 may have a configuration not including the hold circuit 408.

[1-4. Configuration of phase error detector]
Next, a detailed configuration of the phase error detector 407 will be described. FIG. 5 is a block diagram of the phase error detector 407. The phase error detector 407 includes a sine wave generation circuit 501, a first calculation unit 502, a cosine wave generation circuit 503, a second calculation unit 504, and a first selection unit 505.

  The first calculation unit 502 includes a first multiplier 506 and a first integrator 507. The second calculator 504 includes a second multiplier 508 and a second integrator 509. The first selector 505 includes a first comparator 510, a second comparator 511, a first selector 512, a second selector 513, and an amplifier 514.

The sine wave generation circuit 501 generates a sine wave signal based on the input multiplied frequency division phase. Since the multiplication and division phase changes from -12 to 11, as a sine wave signal,
sin (2 × π × multiplied frequency division phase / 24)
Is output.

  First multiplier 506 multiplies the wobble carrier component of the digital wobble signal by the sine wave signal and outputs the result.

  The first integrator 507 performs the first cycle of the multiplication and division phase, that is, the section from the timing at which the multiplication and division phase corresponding to one cycle of wobble (24 cycles of the wobble clock) to -1 to -1. The output of the multiplier 506 is integrated.

These configurations perform phase difference detection by so-called heterodyne detection. Let α be the phase difference between the cosine wave component of the monotone wobble section 204 included in the wobble signal and the multiplied divided phase. At this time, the multiplication of the cosine wave component cos (x) and the sine wave signal sin (x + α) generated by the sine wave generation circuit 501 is
cos (x) × sin (x + α) = (sin (2x + α) + sin (α)) / 2
It becomes. Since the integration result of the sin (2x + α) term becomes 0 by the integration of one cycle by the first integrator 507, only the sin (α) / 2 term remains. Since sin (α) / 2, which is the result of heterodyne detection, is a sine function of the phase difference α, the phase difference α is monotonically increasing with respect to the phase difference α when the phase difference α is in a range of −90 degrees to 90 degrees. In the range from -180 degrees to -90 degrees and from +90 degrees to +180 degrees, the detection result of the phase error is monotonically decreasing.

  The first comparator 510 outputs “1” when the output of the first integrator 507 is positive, and outputs “0” when the output is negative.

  The first selector 512 outputs 0.5 when the output of the first comparator 510 is “1”, and outputs −0.5 when the output of the first comparator 510 is “0”. That is, the first selector 512 outputs 0.5 when the output of the first integrator 507 is positive, and outputs -0.5 when the output of the first integrator 507 is negative.

The cosine wave generation circuit 503 generates a cosine wave signal based on the input multiplied frequency division phase.
cos (2 × π × multiplied frequency division phase / 24)
Is output.

  The second multiplier 508 multiplies the digital wobble signal by the cosine wave signal and outputs the result.

  The second integrator 509 performs the second division for one cycle of the divided frequency phase, that is, for the section from the timing when the multiplied divided phase corresponding to one cycle of the wobble (24 cycles of the wobble clock) to −1 to −1. The output of the multiplier 508 is integrated.

  The second comparator 511 outputs “1” when the output of the second integrator 509 is positive, and outputs “0” when the output is negative.

  The second selector 513 outputs the output of the first integrator 507 when the output of the second comparator 511 is “1”, and outputs the output of the first selector 512 when the output of the second comparator 511 is “0”. Amplifier 514 doubles the input signal and outputs it.

Here, assuming that the phase difference between the cosine wave component of the monotone wobble unit 204 and the multiplied divided phase included in the wobble signal is α, the cosine wave component cos (x) and the cosine wave signal cos generated by the cosine wave generation circuit 503 The multiplication of (x + α) is
cos (x) × cos (x + α) = cos (α) / 2
It becomes. Therefore, the output of the second comparator 511 is "1" when the phase difference is -90 degrees to +90 degrees, and is "0" when the phase difference is -180 degrees to -90 degrees and +90 degrees to +180 degrees.

  The second selector 513 outputs the output of the first integrator 507 when the output of the second comparator 511 is “1”, that is, when the phase difference α is in the range from −90 degrees to 90 degrees. In addition, the second selector 513 determines whether the output of the second comparator 511 is “0” and the output of the first comparator 510 is “0”, that is, the phase difference α is from −180 degrees to −90 degrees. , -0.5. When the output of the second comparator 511 is “0” and the output of the first comparator is “1”, that is, when the phase difference α is from +90 degrees to +180 degrees, the second selector 513 outputs +0. 5 is output. FIG. 6 is a graph showing a phase error output with respect to a phase difference of the phase error detector 407. 6, the phase error with respect to the phase difference in the phase error detector 407 is shown by a solid line, and the phase error with respect to the phase difference of heterodyne detection, that is, the output of the first integrator 507 is shown by a broken line for comparison.

  That is, when the phase difference calculated by the second calculation unit 504 is within a predetermined range, the first selection unit 505 outputs the phase difference calculated by the first calculation unit 502 as a phase error, and outputs the second calculation result. When the phase difference calculated by the unit 504 is out of the predetermined range, a value having the same sign and a predetermined absolute value as the phase difference calculated by the first calculation unit 502 is output as a phase error.

[1-5. Configuration of Hold Circuit]
Next, a detailed configuration of the hold circuit 408 will be described. FIG. 7 is a block diagram of the hold circuit 408. The hold circuit 408 includes an LPF (Low-Pass Filter) 701 and a third selector 702.

  The hold timing signal is a signal that is “1” at the timing of the address modulation unit 205 and “0” otherwise. When the hold timing signal is “0”, the third selector 702 selects a phase error which is an input signal, and outputs it as a phase error. When the hold timing signal is “1”, the third selector 702 selects the output of the LPF 701 and outputs it as a phase error. That is, at the timing of the address modulation unit 205 when the hold timing signal is “1”, the phase error of the phase error detector 407 is almost 0, and the gain decreases. Is not used, and the output of the LPF 701 is used to suppress a decrease in gain.

  The LPF 701 smoothes and outputs the phase error while the hold timing signal is “0”. When the hold timing signal becomes “1”, the LPF 701 holds and outputs the value that has been smoothed and output immediately before. That is, when the hold timing signal is “1”, the third selector 702 continues to output a value obtained by smoothing the phase error immediately before the hold timing signal changes from “0” to “1”. With respect to the phase error smoothed by the LPF 701, a residual equal to or lower than the cutoff frequency of the LPF 701 passes. Therefore, even if the phase error that has passed through the LPF 701 is held and output, the PLL 414 can be operated with the residual error suppressed. Therefore, even if the ratio of the address modulation unit 205 is large and the frequency of holding the PLL 414 is high, it is possible to suppress a decrease in the gain of the PLL 414 in the low frequency range.

[1-6. Configuration of synthesizer]
Next, a detailed configuration of the synthesizer 306 will be described. FIG. 8 is a block diagram of the synthesizer 306. The synthesizer 306 includes a phase error detector 900 and a clock generator 814.

  The phase error detector 900 includes an N counter 801, an M counter 802, a comparator 800, and a combining circuit 810.

  The comparator 800 includes a first phase comparator 803, a second phase comparator 804, a third phase comparator 805, a fourth phase comparator 806, a fifth phase comparator 807, and a sixth phase comparator. 808 and a seventh phase comparator 809.

  The clock generator 814 includes a second charge pump 811, a second filter 812, and a second VCO 813.

  The N counter 801 receives the coefficient N from the controller 307 and counts the wobble clock from 0 to N−1 to divide the frequency by N. At this time, when the counter value is 0, N / 8, 2N / 8, 3N / 8, N-3N / 8, N-2N / 8, NN / 8, a timing signal is output.

  Since the counter value is an integer, each value to be compared also needs to be an integer. However, since each value is obtained by a simple operation by bit shift and addition / subtraction, the fractional part is discarded. Here, it is assumed that the calculation of N / 8 is performed first and then the calculation of an integral multiple is performed. Therefore, for example, when N = 99, N / 8 is 12, 2N / 8 is 24, 3N / 8 is 36, N-3N / 8 is 63, N-2N / 8 is 75, and NN / 8. Is 87.

  Similarly, the M counter 801 receives the coefficient M from the controller 307 and counts the recording clock output from the second VCO 813 from 0 to M−1 to divide the frequency by M. At this time, when the counter value is 0, M / 8, 2M / 8, 3M / 8, M-3M / 8, M-2M / 8, MM / 8, a timing signal is output.

  Like the N counter, the counter value is an integer, so that the respective values to be compared also need to be integers. However, since each value is obtained by a simple operation by bit shift and addition / subtraction, the value after the decimal point is rounded down. Here, it is assumed that the calculation of M / 8 is performed first and then the calculation of an integral multiple is performed.

  The first phase comparator 803 to the seventh phase comparator 809 have different inputs but perform common operations. The first to seventh phase comparators 803 to 809 compare the phase of the timing signal from the N counter 801 with the timing signal from the M counter 802, and generate an up pulse or a down pulse according to the comparison result. Output. That is, when the rising edge of the timing signal from the N counter 801 comes earlier than the rising edge of the timing signal from the M counter 802, the first phase comparator 803 to the seventh phase comparator 809 An up pulse is output in a period from the rising edge of the signal from the signal 801 to the rising edge of the signal from the M counter 802. Conversely, the first to seventh phase comparators 803 to 809 determine whether the rising edge of the timing signal from the M counter 802 comes before the rising edge of the timing signal from the N counter 801. A down pulse is output in a period from the rising edge of the signal from the counter 802 to the rising edge of the signal from the N counter 801.

  Specifically, the first phase comparator 803 performs a phase comparison between a timing signal indicating N counter = 0 and a timing signal indicating M counter = 0. The second phase comparator 804 performs a phase comparison between a timing signal indicating N counter = N / 8 and a timing signal indicating M counter = M / 8. The third phase comparator 805 performs a phase comparison between a timing signal indicating N counter = 2N / 8 and a timing signal indicating M counter = 2M / 8. The fourth phase comparator 806 performs a phase comparison between a timing signal indicating N counter = 3N / 8 and a timing signal indicating M counter = 3M / 8. The fifth phase comparator 807 performs a phase comparison between a timing signal indicating N counter = N−3N / 8 and a timing signal indicating M counter = M−3M / 8. The sixth phase comparator 808 performs a phase comparison between a timing signal indicating N counter = N−2N / 8 and a timing signal indicating M counter = M−2M / 8. The seventh phase comparator 809 performs a phase comparison between a timing signal indicating N counter = N−N / 8 and a timing signal indicating M counter = M−M / 8.

  The first to seventh phase comparators 803 to 809 perform a phase comparison between a phase when the value of the N counter becomes 0 and a phase when the value of the M counter becomes 0. Is compared with the phase when the value of N becomes substantially equal to the value obtained by substantially dividing N and the phase when the value of the M counter becomes equal to the value obtained by substantially dividing M by a predetermined value.

  The combining circuit 810 generates a signal indicating a phase error based on the comparison result of the first to seventh phase comparators 803 to 809. That is, the combining circuit 810 fixes the down pulse to be output to “0” when the first phase comparator 803 outputs an up pulse, and outputs the first phase comparison signal when the first phase comparator 803 does not output the up pulse. The logical sum of the down pulses from the detector 803 to the seventh phase comparator 809 is output as a down pulse. Similarly, when the first phase comparator 803 outputs a down pulse, the output up pulse is fixed to “0”, and when the down pulse is not output, the first phase comparator 803 outputs the down pulse. The logical sum of the up pulses up to the seventh phase comparator 809 is output as an up pulse. If the phases of the N counter 801 and the M counter 802 are significantly different from each other by a predetermined value or more by these phase comparisons, the PLL 414 is locked using the phase comparison result of the first phase comparator 803. On the other hand, if the phase error is small within a predetermined range, the first to seventh phase comparators 803 to 809 are used.

  As long as N and M are not a multiple of 8, N / 8 and M / 8 generate a residual phase error due to a difference after the decimal point in the phase comparison converted into an integer. For example, when N = 99 and M = 98, 99/8 = 12.375 and 98/8 = 12.25. Therefore, the phase comparison is performed when N = 12 and M = 12. For this reason, the phase comparison of 12/99 = about 0.1212 cycle and 12/98 = about 0.1224 cycle is performed, and a residual for 0.1224−0.1212 = 0.0012 cycle is generated. This residual appears as an offset in the loop of the PLL 414. However, in the phase comparison of NN / 8 and MM / 8, an offset of -0.0012 cycle is generated. For this reason, by simultaneously performing the phase comparison of N / 8 and M / 8 and the phase comparison of N−N / 8 and MM / 8, the residual is canceled and the total offset in the entire loop of the PLL 414 is eliminated. Is suppressed.

  The second charge pump 811 injects a current according to the up pulse of the synthesizing circuit 810, and sucks the current according to the down pulse.

  The second filter 812 smoothes the current injection or suction operation of the second charge pump 811 and outputs it as a voltage.

  The second VCO 813 outputs a recording clock having a frequency according to the output voltage of the second filter 812.

  As described above, the synthesizer 306 performs a conventional phase comparison performed only with the phase 0 in a total of seven phases, and injects or draws a current in each phase, thereby performing a charge that involves an increase in circuit scale. The phase comparison gain can be increased seven times without increasing the pump current.

[1-7. Effects etc.]
As described above, the N counter that divides the first clock by N (N is a natural number) and outputs a signal at a predetermined timing, and the N clock that divides the second clock by M (M is a natural number) and outputs a signal at a predetermined timing And a phase comparison between the phase when the value of the N counter becomes 0 and the phase when the value of the M counter becomes 0, and the value of the N counter is a value obtained by substantially dividing N by a predetermined value. A comparator for comparing a phase when the phase becomes equal to the phase when the value of the M counter becomes substantially equal to a value obtained by dividing the M by a predetermined value, and a synthesizing circuit for generating a phase error based on the comparison result of the comparator And.

  This makes it possible to provide a phase error detector that can appropriately detect a phase error even when the phase difference is large.

  The present disclosure is applicable to a recording / reproducing apparatus that extracts a clock from a medium recording a physical address in a track groove. Specifically, the present invention can be applied to an optical disk or optical tape recording / reproducing apparatus.

REFERENCE SIGNS LIST 100 optical disk device 101 optical disk 102 groove 103 land 104 ADIP
201 Synchronization section 202 Address information section 203 ADIP unit 204 Monotone wobble section 205 Address modulation section 301 Optical head 302 Servo control circuit 303 Signal generation circuit 304 Wobble processing circuit 305 Access timing generation circuit 306 Synthesizer 307 Controller 308 Encoder 309 Recording processing circuit 310 Laser Drive circuit 311 Reproduction processing circuit 312 Decoder 401 A / D converter 402 Synchronization detection circuit 403 Address detection circuit 405 Hold timing generation circuit 406 Timing generation circuit 407, 900 Phase error detector 408 Hold circuit 409 Charge pump 410 First filter 411 1 VCO
412 frequency divider 413 ADIP detection circuit 414 PLL
415, 814 Clock generator 501 Sine wave generation circuit 502 First calculation unit 503 Cosine wave generation circuit 504 Second calculation unit 505 First selection unit 506 First multiplier 507 First integrator 508 Second Multiplier 509 Second integrator 510 First comparator 511 Second comparator 512 First selector 513 Second selector 514 Amplifier 701 LPF
702 selector 800 comparator 801 counter 802 counter 803 first phase comparator 804 second phase comparator 805 third phase comparator 806 fourth phase comparator 807 fifth phase comparator 808 sixth phase comparison Device 809 seventh phase comparator 810 synthesis circuit 811 charge pump 812 second filter 813 second VCO

Claims (1)

An N counter for dividing the first clock by N (N is a natural number) and outputting a signal at a predetermined timing;
An M counter that divides the second clock by M (M is a natural number) and outputs a signal at a predetermined timing;
A phase comparison is made between the phase when the value of the N counter becomes 0 and the phase when the value of the M counter becomes 0, and when the value of the N counter becomes equal to a value obtained by substantially dividing N by a predetermined value. And a comparator for comparing the phase of the M counter with the phase when the value of the M counter becomes equal to a value obtained by substantially dividing M by a predetermined value.
A combining circuit that generates a phase error based on the comparison result of the comparator ,
The N counter outputs a signal at a timing when the value of the N counter is 0, N / 8, 2N / 8, 3N / 8, N-3N / 8, N-2N / 8, NN / 8. ,
The M counter outputs a signal at a timing when the value of the M counter is 0, M / 8, 2M / 8, 3M / 8, M-3M / 8, M-2M / 8, MM / 8. ,
The comparator comprises:
A phase comparison is made between the phase when the value of the N counter becomes 0 and the phase when the value of the M counter becomes 0, and the rising of the signal from the M counter from the rising edge of the signal from the N counter. A first phase comparator that outputs an up pulse during a period until an edge, and outputs a down pulse during a period from a rising edge of a signal from the M counter to a rising edge of a signal from the N counter;
A phase comparison is made between the phase when the value of the N counter becomes N / 8 and the phase when the value of the M counter becomes M / 8. From the rising edge of the signal from the N counter, A second phase comparator that outputs an up pulse during a period from the rising edge of the signal from the M counter to a rising edge of the signal from the N counter. When,
The phase when the value of the N counter becomes 2N / 8 and the phase when the value of the M counter becomes 2M / 8 are compared, and from the rising edge of the signal from the N counter, A third phase comparator that outputs an up pulse during a period from the rising edge of the signal from the M counter to a rising edge of the signal from the N counter, and outputs a down pulse during a period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter. When,
A phase comparison is made between the phase when the value of the N counter becomes 3N / 8 and the phase when the value of the M counter becomes 3M / 8, and from the rising edge of the signal from the N counter, A fourth phase comparator that outputs an up pulse during a period from the rising edge of the signal from the M counter to a rising edge of the signal from the N counter. When,
A phase comparison is made between the phase when the value of the N counter becomes N−3N / 8 and the phase when the value of the M counter becomes M−3M / 8, from the rising edge of the signal from the N counter. An up pulse is output during the period from the rising edge of the signal from the M counter, and a down pulse is output during the period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter. And a phase comparator of
A phase comparison is made between the phase when the value of the N counter becomes N-2N / 8 and the phase when the value of the M counter becomes M-2M / 8. From the rising edge of the signal from the N counter, An up pulse is output during the period from the rising edge of the signal from the M counter, and a down pulse is output during the period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter. And a phase comparator of
The phase when the value of the N counter becomes NN / 8 and the phase when the value of the M counter becomes MM / 8 are compared, and from the rising edge of the signal from the N counter, An up pulse is output during the period from the rising edge of the signal from the M counter, and a down pulse is output during the period from the rising edge of the signal from the M counter to the rising edge of the signal from the N counter. And a phase comparator of
The synthesis circuit includes:
When the first phase comparator outputs an up pulse, the down pulse is fixed to 0,
The down pulse of the first phase comparator, the down pulse of the second phase comparator, the down pulse of the third phase comparator, the down pulse of the fourth phase comparator, the fifth phase comparison And outputs the logical sum of the down pulse of the comparator, the down pulse of the sixth phase comparator, and the down pulse of the seventh comparator as a down pulse,
When the first phase comparator outputs a down pulse, the up pulse is fixed to 0,
When the first phase comparator does not output a down pulse, the up pulse of the first phase comparator, the up pulse of the second phase comparator, the up pulse of the third phase comparator, And outputting the logical sum of the up pulse of the phase comparator 4, the up pulse of the fifth phase comparator, the up pulse of the sixth phase comparator, and the up pulse of the seventh comparator as an up pulse.
Phase error detector.

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