JP4188583B2 - Recording clock generator and recording clock generation method - Google Patents

Description

【００３３】
例えば３周期の最初と最後の周期のみでランドプリピットが検出された場合は表の'１０１'の欄にしたがいデコードする。これはデータの「１」を表す。このランドプリピットを１６セクタにわたり集めてデコードすることによりディスク上のアドレスを特定することができる。
またすでに説明したように、プッシュプル信号には隣接トラックのクロストークの影響による波形歪が存在し、内周側のランドプリピット位置と外周側のランドプリピット位置の相対関係もディスク１回転ごとに０．７４×３．１４≒２．３μｍずれていく。
【００３４】
次に本発明の実施の形態１におけるブロック図を図４に示す。図４において、１は光ディスク、２はディスクモータ、３はヘッドであり、ヘッド３は、光ディスクからの反射光を受光し、電気信号に変換する２分割ディテクタを有する。４はＲＦアンプで、２分割ディテクタからの２つの出力を加算した全加算ＲＦ信号をデコーダ５に送る一方、２分割ディテクタからの２つの出力の差であるプッシュプル信号をウォブル信号検出回路６とランドプリピット検出回路２１に送る。装置を動作させるためにはヘッドのフォーカストラッキング制御も必要であるが、本発明の本質とは関係なく公知の技術であるため、ブロック図には記載していない。
【００３５】
５はデコーダでデータの復調を行う。６はウォブル信号検出回路でプッシュプル信号よりウォブル信号を抽出する。７は周期平均化回路でウォブル周期の平均値を求める。８は記録開始位置判定回路でエンコーダ１８より出力される記録ゲート信号を元に記録開始時から一定時間を検出する。記録ゲート信号とは、エンコーダ１８でデータが変調されレーザが記録パワー変調をうけている区間を示す信号である。９は記録終了位置判定回路でエンコーダより出力される記録ゲート信号を元に記録終了時から一定時間を検出する。１０はウォブル欠落検出回路でウォブル信号の欠落を検出する。１１は第１のタイマー制御回路で、タイマー１５に平均周期がロードされるのを抑止しタイマーの出力周期をホールドする。
【００３６】
３０は、ウォブル１６周期毎にタイマー１５にロードされる平均周期を保持する周期保持回路、１２は周期比較回路で周期平均化回路７により求められた平均周期Ｑと、周期保持回路３０で保持された、タイマー１５の前回の矩形波出力の周期Ｔ０を比較し所定値以上の差異があるかどうかを判定する。１３は第２のタイマー制御回路で、周期比較回路１２で所定値以上の周期の差があった場合に、タイマー１５にロードされる平均周期に一定の制限をかける。この詳細は後に説明する。
【００３７】
１４は固定周波数発振器でタイマーを動作させるためのクロックを発生する。固定周波数発振器の発振周波数は、ウォブル信号周期より充分高い周波数に設定する必要がある。１５はタイマーで、周期平均化回路７で求められた平均周期の値がロードされ、平均周期とほぼ同一周期の矩形波を発生する。１６は周波数逓倍ＰＬＬでタイマー出力矩形波に対して周波数を１８６逓倍した記録クロックを発生する。１７はインタフェースでコンピュータとデータの送受信を行う。１８はエンコーダでインタフェース１７から送られる記録データを周波数逓倍ＰＬＬ１６の出力する記録クロックのタイミングにあわせてデータを変調し、パワー制御回路１９に伝える。またエンコーダ１８は、データの変調区間に対応した記録ゲート信号を記録開始位置判定回路８と記録終了位置判定回路９に出力する。１９はパワー制御回路でレーザのパワーを制御する。２０はレーザ駆動回路でレーザを記録パワーで発光させる。
【００３８】
２１はランドプリピット検出回路で前述のランドプリピットを検出する。２２はウインドウ保護回路で、ランドプリピット信号の出現位置を予測したウインドウを生成し、そのウインドウ内のみのランドプリピットを通過させることにより、ランドプリピットの誤検出を防止する。
【００３９】
次に実施の形態１の動作について説明する。ウォブル信号検出回路６で得られたウォブル信号は、周期平均化回路７で一定区間の平均周期が求められる。平均周期の求め方としては、例えば、ウォブル信号の１６周期、すなわち、周期平均化区間にわたる時間を測定し、その測定時間を１６で除算することにより得られる。ウォブル周期を所定数（例えば１６）を含む期間を単位期間と言い、ひとつまたは複数の単位区間を含む期間を周期平均化区間と言う。また、単位区間ごとにプリピットが形成されている。ランドプリピット検出回路２１で検出されたランドプリピットは、ウインドウ保護回路２２を経由して周期平均化回路７に入力され、周期平均化区間の開始点を決めるのに使用される。周期平均化回路７の詳細動作は図５および図６で説明する。
【００４０】
タイマー１５のタイマー値は、原則として前記周期平均値がロードされる。タイマーの動作クロックは固定周波数であり、前記周期平均値に対して充分高い固定周波数発振器１４で動作させることにより、周期平均値と略同一の周期の安定した方形波を発生させることができる。周波数逓倍ＰＬＬ１６は、タイマーの出力を周波数逓倍して記録クロックを発生する。
【００４１】
ここで、記録開始直後すなわちレーザが再生パワーから記録パワーに遷移した直後、あるいは記録終了直後すなわちレーザが記録パワーから再生パワーに遷移した直後は、ＲＦアンプ４のＡＧＣが応答するまでの間、プッシュプル信号が大きく振られ、一時的にウォブル信号が検出できなくなったり、ウォブル信号の周期が乱れたりすることが想定される。この場合には、記録開始位置判定回路８による記録開始から一定時間を示す信号、記録終了位置判定回路９による記録終了時から一定時間を示す信号、またはウォブル欠落検出回路１０によるウォブル信号の欠落を示す信号の少なくともいずれかひとつが検出されたとき、第１のタイマー制御回路１１の動作によりタイマー１５に新たな平均周期がロードされるのが抑制され、タイマーの出力矩形波の周期はホールドされる。これにより記録クロックの過渡状態における安定性を向上させることができる。典型的な光ディスク装置では、ＡＧＣ応答時間は２００μ秒前後であり、この程度の時間であれば時間記録クロックの周期をホールドすることは実用上問題がない。
【００４２】
また、ウォブル欠落検出は、ディスク表面の傷やごみの付着によるウォブル信号の周期の乱れに対しても有効である。ウォブルの欠落検出は、ウォブル周期が標準的な周期より著しく長いことや、ディスク表面のほこりや傷によりディテクタ全加算信号が所定値以下になったことにより検出可能である。
また、周期比較回路１２は、周期平均化回路７で算出された平均周期Ｑと、周期保持回路３０に保持されている前回のタイマー出力周期Ｔ０の比較を行う。第２のタイマー制御回路１３は、周期比較回路で一定以上の周期差を検出した場合、周期平均化回路４からタイマー５にロードされる更新周期の変動量を所定値以下に制限するように動作する。周期比較回路の詳細は図７および図８で説明する。
【００４３】
エンコーダ１８は、インタフェース１７より送られてくるデータを、周波数逓倍ＰＬＬ１６から出力される記録クロックのタイミングに合わせて変調する。変調されたデータはパワー制御回路１９、レーザ駆動回路２０を通してヘッド３内部のレーザを駆動する。また、エンコーダ１８は、データ変調区間に対応した記録ゲート信号を記録開始位置判定回路８、記録終了位置判定回路９に送出する。
【００４４】
次に、周期平均化回路７の詳細動作について説明する。図５は周期平均化回路７のブロック図、図６は周期平均化回路の動作説明図である。この動作例では、ウォブル信号１６周期の平均を求める場合を、一例として説明する。図５において５０１はＤフリッププロップ、５０２は積算周期計測カウンタでウォブル周期の合計時間を計測する。５０３はウォブル周期カウンタでウォブル信号の周期数をカウントする。５０４は一致検出器でウォブル１６周期が入力されたことを判定する。５０５は計測時間を保持するためのラッチ、５０６は除算を行うためのシフタ、５０７はランドプリピット位置から平均区間を生成する平均区間生成回路である。図６において、５１０はプッシュプル信号、５１１はウォブル信号、５１２は計測区間、５１３はタイマーのカウント値を模式的に表したタイマー動作、５１４はタイマーの矩形波出力を表す。
【００４５】
図５の平均区間生成回路５０７は、ランドプリピットのタイミングをもとに図６の計測区間５１２に対応した２フレーム分の計測区間、すなわち単位区間、を表わす信号を出力する回路であり、ウォブル信号立ちあがりエッジ、すなわち２フレーム分の先端エッジのやや手前から計測区間信号を出力する。区間計測信号は、ウォブル１６周期目の終端エッジ、すなわち次の２フレームの先端エッジが確実に含まれ、かつその手前のエッジは含まれないようなタイミングで出力する必要があるが、これは計測中のウォブル信号周期より容易に推定可能である。周期の計測開始点は、あくまでＤフリップフロップ５０１にウォブル信号が入力された時点である。Ｄフリップフロップ５０１には平均区間生成回路５０７が出力する計測区間信号と、ウォブル信号が接続されている。Ｄフリップフロップはカウンタ５０２をウォブル信号の立ちあがりエッジで正確にスタートさせるために用いる。
計測区間信号が出力され、ウォブル信号の立ち上がりエッジが入力されてＤフリップフロップ５０１がセットされると、積算周期計測カウンタ５０２のクリアが解除され、固定周波数クロックによる時間計測が始まる。ウォブル周期カウンタ５０３は入力されてくるウォブル信号の周期数をカウントする。一致検出器５０４はウォブル信号が１６周期入力された時点でクロックを出力し、その時点のカウンタ５０２のカウント値を例えばＶ１とすると、ラッチ５０５にＶ１がコピーされる。従ってラッチされた値はウォブル信号１６周期を固定周波数の分解能で計測した値になる。ラッチ出力はシフタ５０６で４ビット右シフトすることにより１６で除算され、Ｖ１／１６すなわち１６周期の平均値が求まる。以上周期計測の回路構成例について判りやすく述べたが、１６周期の時間計測を連続的に行う場合には積算周期計測カウンタ５０２を連続的に計測できる構成に変形する必要がある。これは容易であるので説明を省略する。
【００４６】
平均区間生成回路５０７の計測区間について、図６を用いて追加説明する。ウォブル信号の周期平均値を求めるための計測区間は、計測区間５１２に示すようにランドプリピットの存在するウォブル１周期の立ち上がり点を開始点とし、毎回１６周期の時間を計測する。ランドプリピットは図３および表１で説明したように２フレームごとに周期的に現れるので、計測区間生成回路はランドプリピットの出現パターンをチェックし、予測することができる。表１に示すランドプリピットの先頭パルス（（１１１）または（１１０））の出現位置を予測し、その出現位置を含むウォブル信号周期の先頭から１６周期の計測区間信号を出すように構成すればよい。以上の区間で計測した１６周期の合計時間Ｖ１を１６で除算することにより、１ウォブル周期すなわちウォブル信号周期の平均値を求めることができる。以降ウォブル１６周期ごとに同様時間計測を行い、そこで得られた値を１６で除算した値を平均周期としてタイマー１５にロードする。タイマー１５は平均周期がロードされた以降、次の平均周期がロードされるまで、５１３に示すように同じ周期で発振を続ける。なお、平均周期の計測区間を１６周期としているのは、前述したようにランドプリピットが２フレーム（ウォブル１６周期相当）ごとに現れるためであり、例えばウォブル６４周期ごとに平均周期を算出する構成も考えられる。
【００４７】
図６に示した例では、周期計測区間の開始点をランドプリピットの先頭位置、区間幅を出現間隔の整数倍とすることにより、ランドプリピットによるウォブル波形歪の影響を、周期平均化区間毎におおむね均等に分散することができる。
図６の時点Ｔ１における動作を説明する。時点Ｔ１にＶ１／１６を計算し、計算結果Ｖ１／１６をタイマー１５にロードすると共に、周期保持回路３０にもロードする。時点Ｔ１以降は、タイマー１５が、ロードした期間（Ｖ１／１６）毎にタイマー出力としてパルスを出力する（５１４で示す）。また、周期平均化回路７では、時点Ｔ１以降は、次のウォブル１６周期の期間Ｖ２のカウントを開始する。
【００４８】
なお、周期平均化区間は図９に示した例のように取ってもよい。図９は周期平均化回路の第２の動作説明図である。この例では周期平均化区間７０２を、ディスク内周側にも外周側にもランドプリピットが存在しないウォブル８周期区間とした。ランドプリピットの無い区間で周期平均を求めることにより、ウォブル信号周期に対するランドプリピットの影響を外周側についても内周側についても完全に排除することができる。ランドプリピットのない区間は、プッシュプル信号に対して上側（外周側）と下側（内周側）の両方向のランドプリピットを２値化検出することにより検出可能である。
【００４９】
次に、周期比較回路１２の詳細動作について説明する。図７は周期比較回路１２のブロック図、図８は周期比較回路１２の動作説明図である。図７において、６０１はＱ−Ｔ０を計算する減算器、６０２はＴ０−Ｑを計算する減算器、６０３は所定範囲を特定する所定値（制限値とも言う）Ａの設定レジスタ、６０４はＱ−Ｔ０とＡとの比較器、６０５はＴ０−ＱとＡとの比較器、６０６はＴ０＋Ａの加算器、６０７はＴ０−Ａの減算器、６０８はセレクタである。図８のフローチャートにおいて、６１０は記号の定義、６１１、６１２は平均周期とタイマー周期の比較、６１３〜６１５はタイマーロード値の更新内容を示す。
【００５０】
最初に図８のフローチャート６１０に示されている記号の定義について説明する。周期平均化回路７で求められた平均周期はＱ、タイマーの発振周期すなわち直前にロードされたタイマー値はＴ０、更新量制限値はＡとする。理想状態では、ＱとＴ０は同じ値のはずである。次に減算器６０１は、平均周期Ｑからタイマー周期Ｔ０を減算した結果を比較器６０４に出力している。減算器６０２はタイマー周期Ｔ０から平均周期Ｑを減算した結果を比較器６０５に出力している。制限値設定レジスタ６０３には制限値Ａが設定されているとする。フローチャートの６１１と６１３に示すように、平均周期Ｑが、タイマー周期Ｔ０よりＡ以上大きい場合には、比較器６０４が動作し、セレクタ６０８は加算器６０６の出力を選択する。加算器６０８はＴ０＋Ａを出力しているので、タイマーに出力される平均周期はＱではなく、Ｔ０＋Ａになる。また、６１２と６１４に示すように、平均周期Ｑがタイマー周期Ｔ０よりＡ以上小さい場合には、比較器６０５が動作し、セレクタ６０８は減算器６０７の出力を選択する。減算器６０７はＴ０−Ａを出力しているので、タイマーに出力される平均周期はＱではなく、Ｔ０−Ａになる。いずれの比較器も動作しなかった場合には、セレクタ６０８は平均周期Ｑをセレクトし、タイマーの周期更新値もＱになる。
【００５１】
ＤＶＤ−Ｒディスクにおいて、例えば直径４８ｍｍの内周位置を考えると、ウォブル１６周期に相当する長さは３９６μｍであるから、図６で１回転あたりのタイマーロード回数、すなわちウォブル平均周期の計測回数は、
４８（ｍｍ）×３．１４×１０００÷３９６（μｍ）＝３８０（回）
になる。一方、ディスクモータの最大加減速時の速度変動は、典型的な光ディスク装置では、ディスク１回転あたり１０％以下であるから、タイマーロードごとの周期計測値の変動は、
１０（％）÷３８０（回）＝０．０２６（％）
程度である。実際には、ディスク偏心による周期変動の影響も考慮する必要があるが、制限値Ａの設定例としては、タイマー値Ｔ０が１０，０００カウント程度のとき３程度が妥当である。
【００５２】
上記を踏まえ、図６の時点Ｔ２における動作を説明する。時点Ｔ２にＶ２／１６を計算し、計算結果Ｖ２／１６を周期保持回路３０に保持されていた値Ｖ１／１６と比較する。この場合、周期保持回路３０に保持されていた値が基準値となる。Ｖ２／１６とＶ１／１６の差が所定範囲外（±Ａ外）の場合は、Ｖ２／１６は適切な値で無いとし、同差が所定範囲内（±Ａ内）の場合は、Ｖ２／１６は適切な値であるとする。Ｖ２／１６が適切な値で無い場合は、計算結果Ｖ１／１６に所定値Ａを加算または減算した値をタイマー１５にロードする。Ｖ２／１６が適切な値である場合は、計算結果Ｖ２／１６をタイマー１５にロードする。タイマー１５にロードされた値は、更に、周期保持回路３０にもロードする。時点Ｔ２においてタイマー１５のカウントは開始するようにし、タイマー１５へのロードは、カウント開始後に行なうようにしてもよい。
【００５３】
適切な値で無いと判断される場合の例として、ウォブル１６周期をカウントしたはずであるが、ホコリやキズにより不要なカウントアップがなされた場合がある。この場合は、実際にはウォブル１５周期の期間をカウントしているが、ホコリやキズにより不要なカウントアップが１つなされている場合である。不要なカウントアップが１つなされている場合は、本来のカウント値よりも１５／１６（＝０．９３７５）の割合で小さくなっている。この場合は、Ｖ１／１６に対して所定値Ａが減算された値（上記例で計算すると本来のカウント値に対して０．９９９７になる）がタイマーにロードされ、大幅に値の異なるＶ２／１６は捨てられる。
【００５４】
適切な値で無いと判断される場合の別の例として、ウォブル１６周期をカウントしたはずであるが、ウォブル周期の信号をひとつ分読み取ることができなかった場合がある。この場合は、実際にはウォブル１７周期の期間をカウントしていることとなる。ウォブル周期の信号をひとつ分読み取ることができなかった場合は、本来のカウント値よりも１７／１６（＝１．０６２５）の割合で大きくなっている。この場合は、Ｖ１／１６に対して所定値Ａが加算された値（上記例で計算すると本来のカウント値に対して１．０００３）がタイマーにロードされ、大幅に値の異なるＶ２／１６は捨てられる。
【００５５】
以上の動作により、予期せぬ理由によりウォブルの周期が大きく乱れた場合でも、タイマー出力の急激な変動を抑えられ、更新される周期の変動量は所定値Ａ以下となる。ウォブル信号の周期がディスクの偏心やディスクモータの最大加速度を超えて大きく変動することは、正常な動作状態では原理的にあり得ないので、これを超える周期変動を抑圧するのは記録クロックの安定性を向上させるのに効果がある。
【００５６】
以上、実施の形態１では、ランドプリピットの影響や記録パワー変調の影響で局所的に周期変動を起こしているウォブル信号に対して、周期平均化手段でその影響を軽減して正確なウォブル周期を検出することができる。平均周期化回路の動作例としては、ランドプリピットの影響を受けにくい２種類の方法を示した。記録パワー変調によるウォブル位相変動やノイズによる影響については、位相の変動方向はランダムに発生すると考えられるので、ウォブル周期を平均化することが有効である。また、記録開始直後、終了直後やディスクの表面のほこり等の要因によりウォブル信号の周期が局所的に不正になっても、その期間タイマー出力周期をホールドして正しい記録クロックを発生することができる。
【００５７】
なお周期平均化区間は、長いほど外乱の影響を受けにくくなるが、記録クロックの線速度変動に対する応答特性を考慮し決定する必要がある。例えば線速度変動に対する記録クロックの応答周波数特性として２ＫＨｚ程度が要求される場合は、周期平均化区間は５００マイクロ秒以下に設定するのが適切である。
【００５８】
（実施の形態２）
図１０は、本発明の第２の実施形態におけるブロック図である。図１０において、１は光ディスク、２はディスクモータ、３はヘッド、４はＲＦアンプ、５はデコーダ、６はウォブル信号検出回路、８は記録開始位置判定回路、９は記録終了位置判定回路、１０はウォブル欠落判定回路、１１は第１のタイマー制御回路、１２は周期比較回路、１３は第２のタイマー制御回路、１４は固定周波数発振器、１５はタイマー、１６は周波数逓倍ＰＬＬ、１７はインタフェース、１８はエンコーダ、１９はパワー制御回路、２０はレーザ駆動回路で、以上は実施の形態１と同じであるから詳細な説明は省略する。２３は位相比較回路で、ウォブル信号とタイマー出力の位相を比較する。２４は周期平均化回路で、ウォブル信号検出回路６で検出されたウォブル周期と位相比較回路２３で検出された位相差にもとづき、タイマーロード値を決定する。
【００５９】
次に、周期平均化回路と位相比較回路の詳細動作について説明する。図１１は周期平均化回路の動作説明図である。図１１において９０１はウォブル信号、９０２は周期計測区間１を示し、区間１の長さは長方形の長さで表わす。周期計測はウォブル信号のＮ周期（Ｎは所定の整数）について行うことを仮定している。同様に９０３は周期計測区間２を示し、区間２の長さは長方形の長さで表わし、９０４は周期計測区間３を示し、区間３の長さは長方形の長さで表わす。本実施形態では、ウォブル周期のほかにウォブル信号とタイマー出力の位相誤差も計測しており、９０５は位相差計測区間１を示し、長方形の長さで表わされた区間１で発生した位相誤差の合計値、言い換えると区間１の終端で残留しているウォブル信号とタイマー矩形波の位相誤差をＺ１で示す。同様９０６は位相差計測区間２を示し、長方形の長さで表わされた区間２の終端で残留している位相誤差をＺ２で示し、９０７は位相差計測区間３を示し、長方形の長さで表わされた区間３の終端で残留している位相誤差をＺ３で示す。９０８はタイマー動作を、９０９はタイマーの矩形波出力を示す。
【００６０】
実施の形態１では、ウォブル１６周期ごとに重複区間なく時間計測し周期平均値を求めたが、本実施形態ではウォブル周期の計測値と位相誤差の計測値の両方を使用して平均周期を算出する。まずウォブル周期の計測方法について説明する。本実施形態では、ウォブル信号が１周期入力されるごとに平均周期を計算し直し、移動平均をとることにより周期平均値を算出する。具体的には、９０２周期計測区間１で計測されたウォブル信号Ｎ周期の時間がＶ１とし、Ｖ１計測後のウォブル信号入力周期をＸ２、Ｘ３…とするとき、Ｖ１からＶ１（１／Ｎ）を減算し、Ｘ２を加算したものを新しい周期積算値Ｖ２とする。すなわちＶ２＝（（Ｎ−１）／Ｎ）×Ｖ１＋Ｘ２となる。Ｖ２として計測値そのものを用いるのではなく、Ｖ１とＸ２を用いた近似式を用いる理由は、計測区間の開始点をすべて記憶しておく必要がないためである。すなわち近似式を用いなければ、Ｎ個の区間をすべて並列に測定しなければならず、区間計測用のカウンタがＮ倍になるためである。同様に次のウォブル信号周期Ｘ３が入力された時点で、計測区間３に対応する積算値Ｖ３は、Ｖ２からＶ２（１／Ｎ）を減じたものにＸ３を加算したものとするので、Ｖ３＝（（Ｎ−１）／Ｎ）×Ｖ２＋Ｘ３となる。
【００６１】
次にウォブル信号とタイマー出力の位相誤差について説明する。周期平均値を算出してタイマーロードするだけでも、ウォブル周期と略同一の周期の矩形波を得ることは可能であるが、周期平均化の切り捨て誤差、切り上げ誤差、あるいは周期平均値の計測分解能により、もとのウォブル信号とタイマー矩形波出力との間に位相差が累積する可能性がある。各計測区間での位相誤差はわずかなものであっても、それが累積することにより、記録クロックとディスク上のランドプリピットとの間の位相誤差が増大し、好ましくない場合が考えられる。従って、本実施形態では、ウォブル信号とタイマー出力矩形波の間の位相誤差Ｚをタイマーロード値に反映し、位相誤差Ｚを常に少なくなるように制御する。具体的な動作としては、９０９に示すようにウォブルＮ周期を計測した時点でのウォブル信号とタイマー矩形波出力の位相差をＺ１、位相誤差の積算値の初期値をＷ１＝Ｚ１としたとき、次にタイマーにロードする値は、Ｖ１の１／ＮとＷ１の１／Ｎの和にする。位相差Ｗ１を１／Ｎにする理由は、位相誤差をＮ周期にわたって分散してタイマー設定に反映することにより急激なタイマー周期変動を避け、記録クロックのジッタ性能向上を図るためである。
Ｗ１は位相誤差が少なくなる方向、すなわちタイマー位相がウォブル信号に対して遅れている場合にはＶ１に対して加算、タイマー位相が進んでいる場合にはＶ１からの減算となる。同様に次のウォブル信号入力時点での位相誤差がＺ２であるとき、位相差積算値Ｗ２としてタイマー設定に反映させる値は、周期計測と同様Ｗ１よりＷ１（１／Ｎ）を減じてＺ２を加算した値、すなわちＷ２＝（（Ｎ−１）／Ｎ）×Ｗ１+Ｚ２となり、タイマーにロードされる値は（Ｖ２＋Ｗ２）／Ｎになる。次の周期Ｘ３、位相差Ｚ３についても同様、（Ｖ３＋Ｗ３）／Ｎがタイマーにロードされる。図１１の９０５、９０６、９０７で示す位相誤差の補正は、省略することも可能である。
【００６２】
以上、本発明の実施の形態２では、ウォブル１周期ごとに周期平均値を更新していくので、タイマーの出力周期の変動を実施の形態１に比較してよりスムースにすることができ、タイマー出力を逓倍して得られる記録クロックのジッタ性能の改善が期待できる。また、ウォブル信号とタイマー出力の位相差をタイマーロード値に反映させることにより、周期平均化の切り捨て誤差、切り上げ誤差、タイマー分解能の誤差がある程度存在してもその累積を抑え、ウォブル信号とタイマー出力の位相が常に一致するように動作させることができる。
【００６３】
（実施の形態３）
図１は、本発明の実施の形態３である。図１において、１は光ディスク、２はディスクモータ、３はヘッド、４はＲＦアンプ、５はデコーダ、６はウォブル信号検出回路、８は記録開始位置判定回路、９は記録終了位置判定回路、１０はウォブル欠落検出回路、１１は第１のタイマー制御回路、１２は周期比較回路、１３は第２のタイマー制御回路、１４は固定周波数発振器、１５はタイマー、１７はインタフェース、１８はエンコーダ、１９はパワー制御回路、２０はレーザ駆動回路、２３は位相比較回路、２４は周期平均化回路で、以上は実施の形態２と同じであるから詳細な説明は省略する。２１はランドプリピット検出回路、２２はウインドウ保護回路で、これは実施の形態１で説明したものである。２５はラッチで、ランドプリピットがウインドウ内で検出された時点のタイマー１５のカウント値をラッチする。すなわちラッチにはタイマー出力矩形波の立ちあがりからランドプリピットまでの位置を計測した結果が入る。２６は減算器でラッチの内容に対して所定数を減算する。２７は低域フィルタで、減算器出力に対して低域成分のみを通過させるデジタルフィルタである。２８は周波数逓倍ＰＬＬで基本的なＰＬＬ動作は実施の形態１ないし２と同じであるが、低域フィルタ２７の出力値に応じて記録クロックの位相を補正できるように構成している。
【００６４】
次にウォブル信号とランドプリピット信号間の位相差検出方法について図１２を用いて説明する。図１２は位相差検出の動作説明図である。図１２において、１００１はランドプリピット信号、１００２は検出ウインドウ、１００３はタイマーカウント動作、１００４はウォブル信号、１００５はラッチ出力、１００６は減算器出力を示す。ランドプリピット信号１００１は、検出ウインドウ１００２によりウインドウ外で誤検出された成分は除去される。タイマーは１００３に示すように常時カウントダウン動作を行っており、ゼロカウント時には新たな平均周期がロードされる。ロードされる平均周期は図にＬ１、Ｌ２で示している。ウインドウ内でランドプリピット信号が検出されると、その検出位置に対応するタイマーカウント値Ｃ１がラッチ１００５にコピーされる。ウォブル信号とランドプリピット信号の位相差Ａ１は、ラッチされた値を用いてＡ１＝Ｌ１−Ｃ１として算出可能である。ここでトラック間クロストークのない理想状態でのウォブル信号とランドプリピットの位相差ＡＮが予め既知であれば、周波数逓倍ＰＬＬに対して、Ａ１−ＡＮ、すなわち、Ｌ１−Ｃ１−ＡＮの位相補正を行うことにより、ウォブル信号とランドプリピット信号の位相差を常にトラック間クロストークのない状態に保つことができる。Ｌ１−Ｃ１−ＡＮは減算器２６により行われる。減算器２６の出力はカットオフ数ＫＨｚの低域フィルタ２７を通して位相補正信号として周波数逓倍ＰＬＬ２８に送られる。低域フィルタを用いる理由は、ランドプリピット信号は記録時の記録パルスのマーク部、スペース部による受光光量の違い、および再生時のマーク部、スペース部の受光光量の違いによりジッタ成分を持つので、それを除去するためである。またランドプリピットの未検出や誤検出に対する周波数逓倍ＰＬＬ２８の応答を抑制するためである。
【００６５】
次に、周波数逓倍ＰＬＬについて図１３を用いて説明する。図１３は周波数逓倍ＰＬＬのブロック図である。図１３において１１０１は位相比較器でタイマー出力と一致検出器の立ち上がり位相を比較する。１１０２はチャージポンプ、１１０３はＶＣＯ、１１０４は７４４分周カウンタ、１１０５は一致検出器、１１０６は記録クロックを出力するための４分周カウンタである。
【００６６】
本実施の形態においては、位相補正の分解能を記録クロックの４分の１周期とするため、ＶＣＯの発振周波数は記録クロックの４倍としている。従って、記録クロックはＶＣＯ１１０３の出力を４分周カウンタ１１０６で分周したものとなる。また、ウォブル信号の周波数は記録クロックの１８６分の１なので、分周器としてはさらにその４倍、すなわち１８６×４＝７４４分周となり、７４４分周カウンタ１１０４を設けている。一致検出器７０５は、位相補正のない状態では、７４４分周カウンタのカウント値が０になるごとに立ち上がりパルスが含まれるような矩形波を発生するように動作する。一致検出器１１０５の出力する矩形波とタイマー出力矩形波の立ち上がりエッジ同志が位相比較器１１０１で比較され、その位相差量に応じてチャージポンプ１１０２が駆動され、ＶＣＯ１１０３の出力周波数が制御される。
【００６７】
次に、周波数逓倍ＰＬＬの位相補正動作を図１４を用いて説明する。図１４は周波数逓倍ＰＬＬの位相補正動作の説明図である。図１４において、１２０１は７４４分周器のカウント値を示す。この分周器は７４４分周の固定分周比のカウンタなので、カウント値としては７４３から０にカウントダウンを繰り返している。１２０２に低域フィルタ２７から出力された位相補正値を示す。この例では説明の都合上、タイミングチャートの前半部分が補正値−１０、後半部分が補正値＋１０として示しているが、実際にはカットオフ数ｋＨＺの低域フィルタ２７を挿入しているため、補正値が−１０から瞬時に＋１０に急激に変動することはない。一致検出器１１０５は、補正値が−１０のときには７４４分周カウンタのカウント値が−１０（７３３）になった場合に立ち上がり波形を発生し、補正値が＋１０のとき７４４分周カウンタのカウント値が＋１０になった場合に立ち上がり波形を発生する。つまり、一致検出器から出力される矩形波は、設定値に応じて記録クロックの４分の１周期単位で位相が補正されることになる。トラック間クロストークによりランドプリピット信号に対してウォブル信号の位相が進みタイマー出力の位相も進んでいる場合には、一致検出器の出力位相も低域フィルタの出力量だけ進める方向に制御することにより、ＰＬＬの出力位相変動をキャンセルするように制御することができる。逆にウォブル信号の位相が遅れている場合には、一致検出器の位相も遅らせる方向に制御すればよい。位相比較器１１０１は立ち上がりエッジのみ比較するように構成できるので、一致検出器１１０５が出力する矩形波の立下り位置は厳密に決める必要なないが、例えばカウント値が半分の３７０カウント近傍でたち下がるように設計すればよい。
なお、ウォブル信号とランドプリピット信号の位相差は固定クロック発振器１４の周波数分解能で計測され、周波数逓倍ＰＬＬ２８の位相補正単位はＶＣＯ１１０３の発振周波数で決定されるので、両者の周波数が異なる場合には、補正値の設定単位の変換が必要になる場合がある。
なお、本実施例では、ＶＣＯ１１０３の出力に対して位相補正を行なったが、タイマー出力に対して位相補正を行なっても同様の効果が得られる。この場合、タイマーと同じクロックを用いてタイマー出力の位相補正を行なえば、上記補正値の設定単位の変換は不要である。
以上のように本実施の形態によれば、比較的回路規模が小さくデジタル的に構成可能な周期平均化回路と低域フィルタ、１個の周波数逓倍ＰＬＬを効果的に組み合わせることにより、ウォブル信号とランドプリピット信号の位相を容易に検出し、ランドプリピット信号を用いた記録クロックの位相補正を容易に行うことができる。
【００６８】
またＤＶＤ−Ｒディスクにおいて、ウォブル周波数は１４０ＫＨｚ、ランドプリピットの出現間隔は２フレーム（約１０ＫＨｚ）、ディスクの偏心に追従するためのＰＬＬ応答帯域は１ＫＨｚ程度でウォブルのトラック間干渉は５．３回転周期と遅い。従って、周期平均化回路におけるタイマーの位相補正の応答速度１４０ＫＨｚは、約１０ＫＨｚで現れるのランドプリピットとウォブル信号の位相差を測定するのに十分である。また、低域フィルタのカットオフ周波数を１ＫＨｚ程度に選ぶことにより、ディスクの線速度変動に追従し、ランドプリピットの高域ジッタ成分抑圧しつつ周波数逓倍ＰＬＬの位相補正を行うことができる。また低域フィルタを用いることによりランドプリピットの誤検出や未検出が存在しても記録クロックのジッタ増加を最小限度に抑えることができ、本発明の実用的効果は大きい。
【００６９】
（実施の形態４）
次に周期平均化回路の更に別の詳細動作例について説明する。図１５は、実施の形態４における周期平均化回路の動作説明図である。周期平均化回路のブロック図は実施の形態２と同様であり、説明を省略する。図１５において１５０１はウォブル信号、１５０２は周期計測区間１、１５０３は周期計測区間２、１５０４は周期計測区間３を示す。１５０５は位相差計測区間１、１５０６は位相差計測区間２、１５０７は位相差計測区間３を示す。１５０８はタイマー動作を、１５０９はタイマーの矩形波出力を示す。
【００７０】
実施の形態４においてウォブル周期の計測方法について説明する。周期積算値Ｖ１、Ｖ２、Ｖ３・・・の計測方法は実施の形態２と同様であるが、位相誤差の積算値の計算方法、位相誤差のタイマーロード値の計算方法が実施の形態２とは異なる。実施の形態４では、ウォブル信号とタイマー出力矩形波の間の位相誤差に対して一定の減衰定数をかけたものをタイマーロード値に反映する。
【００７１】
具体的な動作としては、１５０９に示す様に、ウォブルＮ周期を計測した時点でのウォブル信号とタイマー矩形波出力の位相差をＺ１としたとき、Ｗ１の初期値はＺ１とし、次にタイマーにロードする値は、Ｖ１／ＮとＷ１／（Ｄ×Ｎ）の合計値にする。Ｄは減衰定数である。位相差のタイマーへの反映値をＷ１／（Ｄ×Ｎ）にする理由は、位相誤差に一定の減衰定数Ｄをかけて、Ｎ周期にわたって分散してタイマー設定に反映することにより、タイマー周期をウォブル周期に対して、より安定に追随させるためである。次のウォブル信号入力時点での位相誤差がＺ２であるとき、位相差積算値Ｗ２は、Ｗ２＝（（Ｎ−Ｃ）／Ｎ）×Ｗ１＋Ｚ２とする。Ｃは減算定数である。定数Ｃを減算している理由は、積算値Ｗｉに対する位相誤差量のゲインを調整するためである。このときのタイマーロード値は、Ｖ２／ＮとＷ２／（Ｄ×Ｎ）の合計値である。以降周期でも同様のタイマーロードが行なわれる。
【００７２】
たとえば、周期平均化区間が、１２８のウォブル周期に相当する場合（Ｎ＝１２８）、本実施の形態で減算定数Ｃ＝４、減衰定数Ｄ＝２程度に設定することにより、実施の形態３よりも位相誤差の帰還量を低く抑えることができ、特に入力ウォブル信号の周期変動が激しい場合において、タイマー出力すなわち平均化ウォブル信号の周期変動を抑える効果がある。なお、周期平均化区間は、周期積算値の計測と位相誤差積算値の計測で別個の値としてもよい。
【００７３】
以上、本発明の実施の形態３では、ウォブル信号とタイマー出力の位相差を一定の減衰定数を掛けてゆるやかにタイマーロード値に反映させることにより、ウォブル信号とタイマー出力の位相差が累積するのを防ぐことができ、かつウォブル信号の周期変動が激しい場合でも位相誤差量が過剰に帰還されてタイマー出力が不安定になるのを防ぐことができる。
【００７４】
【発明の効果】
本発明の記録クロック発生装置では、隣接トラックの影響によるウォブル信号の位相変動、ランドプリピット信号の漏れこみによるウォブル信号の位相変動、記録パワー変調成分の漏れこみによるウォブル信号の位相変動、その他ノイズによるウォブル信号の周期変動に対して、周期平均化を行うことにより安定した記録クロックを発生することができる。
【００７５】
また、記録開始時、記録終了時のＲＦアンプの過渡応答や、ディスク表面のごみなどによりウォブル信号が欠落した場合でも、ウォブル信号の平均周期にて発振しているタイマーの出力周期をホールドすることにより、周波数逓倍ＰＬＬの出力、すなわち記録クロックのジッタ悪化を最低限に抑えることができる。
【００７６】
また、ランドプリピット信号に高域ジッタ、誤検出、未検出が存在した場合でも、記録クロックに対する位相補正信号として低域通過型フィルタを通した信号を用いることにより、高域ジッタや欠落の影響を抑え、記録クロックのディスクに対する位相ジッタを大きく改善することができる。
さらに本発明によれば、周期平均化回路、タイマー、低域フィルタなど、いずれも比較的小規模なデジタル回路で構成可能であり、基本的に１個の周波数逓倍ＰＬＬでランドプリピット信号による位相補正を行ったジッタの少ない記録クロックを生成することができ、その実用的効果は大きい。
【図面の簡単な説明】
【図１】 実施の形態３のブロック図
【図２】 ディスクの溝形状図
【図３】 ディスクの記録フォーマット図
【図４】 実施の形態１のブロック図
【図５】 実施の形態１における周期平均化回路のブロック図
【図６】 実施の形態１における周期平均化回路の動作説明図
【図７】 実施の形態１における周期比較回路のブロック図
【図８】 実施の形態１における周期比較回路の動作説明図
【図９】 実施の形態１における周期平均化回路の第２の動作説明図
【図１０】 実施の形態２のブロック図
【図１１】 実施の形態２における周期平均化回路の動作説明図
【図１２】 実施の形態３における位相差検出の動作説明図
【図１３】 実施の形態３における周波数逓倍ＰＬＬのブロック図
【図１４】 実施の形態３における周波数逓倍ＰＬＬの動作説明図
【図１５】 実施の形態４における周期平均化回路の動作説明図
【符号の説明】
１ 光ディスク
２ ディスクモータ
３ ヘッド
４ ＲＦアンプ
５ デコーダ
６ ウォブル信号検出回路
７、２４ 周期平均化回路
８ 記録開始位置判定回路
９ 記録終了位置判定回路
１０ ウォブル欠落判定回路
１１ 第１のタイマー制御回路
１２ 周期比較回路
１３ 第２のタイマー制御回路
１４ 固定周波数発振器
１５ タイマー
１６ 周波数逓倍ＰＬＬ
１７ インタフェース
１８ エンコーダ
１９ パワー制御回路
２０ レーザ駆動回路
２１ ランドプリピット検出回路
２２ ウインドウ保護回路
２３ 位相比較回路
２５、５０５ ラッチ
２６ 減算器
２７ 低域フィルタ
２８ 周波数逓倍ＰＬＬ
２０１ グルーブ
２０２ ランド
２０３ ランドプリピット
２０４ 記録マーク
３０３ 外周側ランドプリピット信号
３０４ 内周側ランドプリピット信号
５０１ Ｄフリップフロップ
５０２ 積算周期計測カウンタ
５０３ ウォブル周期カウンタ
５０４ 一致検出器
５０６ シフタ
５０７ 平均区間生成回路
６０１ 減算器（Ｑ−Ｔ０）
６０２ 減算器（Ｔ０−Ｑ）
６０３ 制限値設定レジスタ
６０４ 比較器（Ｑ−Ｔ０とＡ）
６０５ 比較器（Ｔ０−ＱとＡ）
６０６ 加算器（Ｔ０＋Ａ）
６０７ 減算器（Ｔ０−Ａ）
６０８ セレクタ
１１０１ 位相比較器
１１０２ チャージポンプ
１１０３ ＶＣＯ
１１０４ ７４４分周カウンタ
１１０５ 一致検出器
１１０６ ４分周カウンタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a recording clock generation apparatus and a recording clock generation method for recording data on an optical disc having a wobbled recording groove, typically a DVD-R disc or a DVD-RW disc.
[0002]
[Prior art]
As a method for generating a recording clock for an optical disc having a wobbled recording groove, for example, a DVD-R disc, there is one disclosed in, for example, Japanese Patent Application Laid-Open No. 10-293926. In this example, the wobble signal is a continuous signal having a frequency component synchronized with the rotation of the disk, and a clock signal phase-synchronized with the continuous signal is generated by the frequency multiplying PLL so that the rotation of the disk can be accurately performed. A synchronized clock signal for recording is generated. A normal wobble signal is obtained by receiving reflected light from a groove by a detector divided in the tracking direction, and obtaining a signal (referred to as a push-pull signal) obtained by taking a differential signal from each detector (BPF (Band Pass)).
It is obtained by binarizing after passing through (Filter).
[0003]
By the way, in recent optical discs, the track pitch is narrowed as the recording density is improved, and crosstalk between adjacent groove tracks cannot be ignored. In particular, since the DVD-R disc is in the CLV format, the wobble phase shifts every time the disc rotates, and the wobble phases between tracks are not uniform. That is, there is a unique problem that the wobble signal is modulated by crosstalk between tracks. Therefore, in the conventional example, the phase of the land prepit signal detected from the optical disc and the wobble signal are compared by utilizing the fact that the prepit signal is recorded in the land portion of the optical disc at a predetermined interval (this is called the land prepit). Thus, a phase difference signal is output, and the phase of the recording clock signal is corrected based on the phase difference signal. In other words, the fluctuation on the time axis of the clock signal generated based on the wobble signal where the influence of crosstalk between tracks cannot be ignored is corrected by using the land pre-pits that are not affected by crosstalk, and the rotation of the disk is high. A recording clock signal synchronized with accuracy is generated.
[0004]
It is known that phase correction in a DVD-R disc requires a correction amount of about ± 30 ° when one wobble period is 360 °. Since the recording clock of the DVD-R disk is obtained by multiplying the wobble signal by 186, the phase correction amount is 186 × (30/360) = 16 with respect to the recording clock, that is, the phase for 16 clocks must be corrected. Don't be. Since it is difficult to stably correct the phase of the recording clock over one period or more, as a practical configuration example, as shown in FIG. 10 of Japanese Patent Laid-Open No. 10-293926, the wobble signal period is relatively low. A method using two PLLs has been devised in which a first PLL that oscillates is provided, a phase is shifted with respect to the output of the first PLL, and then a recording clock is generated by frequency multiplication by the second PLL. ing.
[0005]
In addition, if wobble period fluctuations exist in a period in which no land pre-pits exist, there is an adverse effect of deteriorating the jitter characteristics of the recording clock. In the conventional example, the response characteristic of the second PLL is made variable between the period in which the land pre-pits are present and the period in which the land pre-pits are not present, thereby reducing the PLL response characteristic in the period in which no land pre-pits are present, thereby improving the jitter performance of the recording clock. A method of making it happen has also been proposed.
[0006]
[Problems to be solved by the invention]
In the following, a problem in generating a recording clock for an optical disk having a wobbled recording groove will be described.
[0007]
First, as mentioned in the conventional example, the crosstalk between adjacent groove tracks can no longer be ignored. For example, a 4.7 GB DVD-R disc has a track pitch of 0.74 μm and a wobble period of 24.7 μm, and the track pitch is narrower than that of the original 3.9 GB DVD-R disc, about 5.3 rotations. There is a problem that the phase of the wobble varies periodically with a relatively slow period. In the conventional example, by performing the phase correction of the recording clock generation PLL using the land pre-pit signal, a certain effect can be expected against the jitter deterioration of the recording clock due to crosstalk. However, in the section where the land pre-pit does not exist. On the other hand, only a method for reducing the response characteristic of the PLL is shown. A method corresponding to the erroneous detection of the land prepit is not shown.
[0008]
Further, in the conventional example, in order to configure a realistic phase shift circuit, two PLLs in total, that is, a PLL having a wobble frequency of 140 KHz and a frequency multiplying PLL of 26 MHz for generating a recording clock are required. There is a problem that increases. In particular, in recent digital LSIs, process miniaturization has progressed, and development has been focused on high-speed and highly integrated circuits. In these digital LSIs, there is a problem that a PLL with a wobble frequency of about 140 KHz has a low frequency band and is difficult to be incorporated in the LSI. In addition, when many charge pumps and VFOs, which are analog PLL components, are built in a digital LSI, not only the chip area of the LSI is occupied, but also high-accuracy noise management is required to ensure the jitter performance of the PLL. Thus, there is a problem of making LSI design difficult. Further, in order to transition the output phase of a PLL that oscillates at a wobble frequency of about 140 KHz, it is common to use a phase transition circuit based on an analog circuit in view of the frequency band, and there is a problem that the affinity with a digital LSI is poor. is there.
[0009]
Second, the wobble signal is obtained by binarizing a push-pull signal after passing through a BPF (Band Pass Filter), and a land pre-pit signal is superimposed on the push-pull signal. Since this land pre-pit signal cannot be completely removed by the BPF (Band Pass Filter), the edge of the wobble signal is shifted particularly when the land pre-pit exists near the wobble binarized slice level, and the correct wobble is detected. There is a problem that the period of the signal cannot be obtained.
[0010]
Third, at the time of recording, the light receiving level of the detector of the head changes greatly according to the modulation of the laser power in the recording mark portion and the recording space portion. In a DVD-R disc, for example, the laser is modulated with a recording mark portion of 11 mW and a recording space portion of 0.7 mW, so the amount of light from the detector fluctuates 10 times or more. The extraction of the wobble signal takes a push-pull signal with respect to the output from the detector, and further passes through a BPF (Band Pass Filter). Part of the influence remains in the signal after differential, and particularly the influence of the recording power fluctuation in the vicinity of the wobble binarized slice level causes the edge shift of the wobble signal, and the correct wobble signal period cannot be obtained. is there.
[0011]
Fourth, since the laser power changes from the reproduction power to the recording power at the time of recording, both the amplitude of the received light amount of the detector and the DC level greatly vary. In a typical DVD-R disc, the reproduction power is 0.7 mW, and the average recording power of the mark portion and the space portion during recording is 7 mW, which is a difference of about 10 times. If this fluctuation is binarized through a BPF (Band Pass Filter) as it is, the amplifier is saturated during recording, and the signal is buried in noise during reproduction. Therefore, in order to absorb this variation, an AGC (Automatic Gain Control) circuit is usually inserted in the RF amplifier and feedback control is performed so as to keep the signal amplitude before binarization constant. In a transient state immediately after the end of recording, a correct binarization operation cannot be expected until the AGC responds, and there is a problem that the wobble signal cycle is greatly disturbed or the detection of the wobble signal is temporarily difficult. is there.
[0012]
Fifth, the effect of crosstalk can be reduced by performing phase correction with land pre-pits, but there is a problem that the recording clock is shifted in response to erroneous detection or non-detection of land pre-pits. Further, there is a problem that the land pre-pit detection itself has a high-frequency jitter component due to the recording power fluctuation described in the third problem.
[0013]
In the conventional example, no concrete solution is shown for the second to fifth problems.
[0016]
[Means for Solving the Problems]
  In order to solve the above problems, the present invention is configured as follows.
(1) A recording clock generator for recording data on an optical disc in which a recording groove wobbled at a predetermined period in the radial direction and a prepit signal is formed for each unit section including a predetermined number of wobble periods,
  Recording grooveFromofBy obtaining a push-pull signal obtained from the reflected light, and binarizing the push-pull signal after passing through a band-pass filterWobble signal detection means for outputting a wobble signal;
  SaidThe push-pull signal is acquired, and the pre-pit positions on the outer peripheral side and inner peripheral side are detected by binarizing and detecting the high peak value and the instantaneous low peak value for the amplitude value of the push-pull signal. The section in which none of the binarized signals is detected for a certain period is defined as a section in which no pre-pit exists on the outer peripheral side or the inner peripheral side.Pre-pit detecting means for detecting;
  Period averaging means for obtaining an average period of the wobble signal;
  A timer that generates a rectangular wave having substantially the same period as the average period obtained by the period averaging means;
  A frequency multiplying PLL for multiplying the timer output to generate a recording clock;
  The period averaging means includesAboveA recording clock generator characterized in that an average period is calculated in a section where no pre-pit exists on either the inner peripheral side or the outer peripheral side of a recording groove.
[0017]
By setting the period averaging section to a section where no pre-pits exist, wobble period fluctuations due to the influence of pre-pits are eliminated, and by using the average value of the period, the influence of wobble edge shift due to recording power fluctuations is reduced. An accurate recording clock can be obtained.
[0018]
(2) A recording clock generation method for recording data on an optical disc in which a recording groove wobbled in a radial direction at a predetermined period and a prepit signal is formed for each unit section including a predetermined number of wobble periods,
Obtaining a push-pull signal obtained from reflected light from the recording groove, and outputting the wobble signal by binarizing the push-pull signal after passing through a band-pass filter;
The push-pull signal is acquired, and the pre-pit positions on the outer peripheral side and the inner peripheral side are detected by binarizing and detecting an instantaneously high peak value and an instantaneously low peak value with respect to the amplitude value of the push-pull signal. Detecting and detecting a section in which any of the binarized signals is not detected for a certain period of time as a section in which no prepit exists on the outer peripheral side or the inner peripheral side;
Obtaining an average period of the wobble signal;
Generating a rectangular wave having substantially the same period as the average period determined in the step of determining the average period;
Multiplying the rectangular wave to generate a recording clock,
The recording clock generation method characterized in that the step of obtaining the average period calculates the average period in a section where no prepits exist on either the inner peripheral side or the outer peripheral side of the recording groove.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 2 shows a typical disk groove shape assumed in the present invention. In FIG. 2, 201 is a groove, 202 is a land, 203 is a land pre-pit formed on the land, and 204 is a recording mark recorded in the groove. The waviness of the groove, which is a recording groove, is called wobble and is used to detect the linear velocity of the disk. That is, it is used for recording clock generation and CLV control. In a DVD-R disc or DVD-RW disc, the wobble cycle is 186 times the recording clock cycle. The land pre-pit 203 is used for detecting an accurate position on the disc in addition to encoding address information.
[0028]
Next, a recording format diagram on the disc is shown in FIG. In FIG. 3, 301 is a recording format, and one sector is composed of 26 frames, and one frame corresponds to the length of eight wobble periods. A push-pull signal 302 is obtained by receiving the reflected light from the groove with a detector divided along a line substantially parallel to the tracking direction, and taking a differential signal from each detector. The wobble signal can be obtained by removing the noise component through a BPF (Band Pass Filter) that passes only the wobble frequency through the push-pull signal and binarizing it. The land pre-pit signal appears above and below the push-pull signal. Although depending on the polarity of the differential, for example, the land pre-pit signal 303 on the outer periphery side of the disc appears above the push-pull signal, and the land pre-pit signal 304 on the inner periphery side of the disc appears below the push-pull signal. appear.
[0029]
When the address information is actually decoded, only the outer land pre-pit signal is sliced and extracted, and the inner land pre-pit signal is ignored. As shown in FIG. 3, the land pre-pit signal is normally arranged in the first three out of the eight wobble periods of an even frame, and the land pre-pit position on the inner peripheral side overlaps with the land pre-pit position on the outer peripheral side to cause interference. Arranged in odd frames. This relationship will be described in more detail below.
[0030]
As shown in FIG. 3, in principle, the land pre-pits are formed for the first three wobble signal periods (first period, second period, and third period) of each even frame in one sector. That is, the land prepit is formed for each unit section including a predetermined number of wobble periods. In the example of FIG. 3, the unit section corresponds to a two-frame section. A land prepit signal which is a 3-bit signal (bit2, bit1, bit0) is formed depending on the presence or absence of the land prepit. In frame 0 of each sector, a land pre-pit signal (111) indicating the head frame is formed. The land pre-pit signal (101) or (100) is formed in the first three wobble signal periods of the remaining even frames 2, 4, 6,. The land pre-pit signal (101) represents data “1”, and the land pre-pit signal (100) represents data “0”. These data are collected to represent address information and other information. In this case, synchronization is obtained in even frames, and address information and the like are obtained.
[0031]
The outer side land pre-pits and the inner week side land pre-pits are generally not aligned in a straight line in the radial direction, but are shifted from each other. Circumferential land pre-pits may be aligned. Where to line up can be calculated. This is because the wobble phase is shifted every rotation of the disk because of the CLV format. If the land prepits on the inner peripheral side and the land prepits on the outer peripheral side are arranged in the radial direction, they cancel each other on the push-pull signal, and the land prepit signal cannot be obtained. In this case, as an exception, the position where the land pre-pit is formed is changed from the even frame to the next odd frame. That is, if the position aligned in the frame is frame 0, the land pre-pit signal (110) is formed in the frame 1 to indicate that it is the leading position of the odd frame, and if the position aligned in the straight line is the frame 2, it is changed to the odd frame 3. A land pre-pit signal (101) or (100) is formed, representing data "1" or data "0". The same applies to the frames 4, 6, 8,.
[0032]
Table 1 shows the land pre-pit decoding table.
[Table 1]

[0033]
For example, when a land pre-pit is detected only in the first and last periods of three periods, decoding is performed according to the column “101” in the table. This represents “1” of the data. By collecting and decoding the land prepits over 16 sectors, the address on the disk can be specified.
As described above, the push-pull signal has waveform distortion due to the influence of crosstalk between adjacent tracks, and the relative relationship between the land pre-pit position on the inner peripheral side and the land pre-pit position on the outer peripheral side is also determined for each rotation of the disk. 0.74 × 3.14≈2.3 μm.
[0034]
Next, a block diagram according to the first embodiment of the present invention is shown in FIG. In FIG. 4, 1 is an optical disk, 2 is a disk motor, and 3 is a head. The head 3 has a two-divided detector that receives reflected light from the optical disk and converts it into an electrical signal. Reference numeral 4 denotes an RF amplifier which sends a fully added RF signal obtained by adding two outputs from the two-divided detector to the decoder 5, while a push-pull signal which is the difference between the two outputs from the two-divided detector is sent to the wobble signal detection circuit 6. This is sent to the land pre-pit detection circuit 21. In order to operate the apparatus, focus tracking control of the head is also necessary, but since it is a known technique irrespective of the essence of the present invention, it is not shown in the block diagram.
[0035]
A decoder 5 demodulates data. 6 is a wobble signal detection circuit which extracts a wobble signal from a push-pull signal. Reference numeral 7 denotes a period averaging circuit which obtains an average value of wobble periods. A recording start position determination circuit 8 detects a predetermined time from the start of recording based on the recording gate signal output from the encoder 18. The recording gate signal is a signal indicating a section in which data is modulated by the encoder 18 and the laser is subjected to recording power modulation. A recording end position determination circuit 9 detects a predetermined time from the end of recording based on the recording gate signal output from the encoder. Reference numeral 10 denotes a wobble missing detection circuit that detects a missing wobble signal. Reference numeral 11 denotes a first timer control circuit that inhibits the timer 15 from being loaded with an average period and holds the output period of the timer.
[0036]
Reference numeral 30 denotes a period holding circuit that holds an average period loaded into the timer 15 every 16 wobbles. Reference numeral 12 denotes a period comparison circuit, which is held by the period holding circuit 30 and an average period Q obtained by the period averaging circuit 7. In addition, the previous rectangular wave output period T0 of the timer 15 is compared to determine whether there is a difference greater than a predetermined value. Reference numeral 13 denotes a second timer control circuit, which applies a certain limit to the average period loaded into the timer 15 when the period comparison circuit 12 has a period difference greater than or equal to a predetermined value. Details of this will be described later.
[0037]
A fixed frequency oscillator 14 generates a clock for operating a timer. The oscillation frequency of the fixed frequency oscillator needs to be set to a frequency sufficiently higher than the wobble signal period. A timer 15 is loaded with the value of the average period obtained by the period averaging circuit 7 and generates a rectangular wave having the same period as the average period. A frequency multiplying PLL 16 generates a recording clock having a frequency multiplied by 186 with respect to the timer output rectangular wave. Reference numeral 17 denotes an interface for transmitting and receiving data to and from the computer. Reference numeral 18 denotes an encoder which modulates the recording data sent from the interface 17 in accordance with the timing of the recording clock output from the frequency multiplication PLL 16 and transmits the data to the power control circuit 19. The encoder 18 outputs a recording gate signal corresponding to the data modulation section to the recording start position determination circuit 8 and the recording end position determination circuit 9. A power control circuit 19 controls the laser power. Reference numeral 20 denotes a laser driving circuit that emits light with a recording power.
[0038]
21 is a land pre-pit detection circuit for detecting the above-mentioned land pre-pits. A window protection circuit 22 generates a window in which the appearance position of the land pre-pit signal is predicted, and passes the land pre-pit only in the window, thereby preventing erroneous detection of the land pre-pit.
[0039]
Next, the operation of the first embodiment will be described. For the wobble signal obtained by the wobble signal detection circuit 6, the average period of a certain section is obtained by the period averaging circuit 7. The average period can be obtained, for example, by measuring 16 periods of the wobble signal, that is, the time over the period averaging period, and dividing the measurement time by 16. A period including a predetermined number (for example, 16) of wobble periods is referred to as a unit period, and a period including one or a plurality of unit sections is referred to as a period averaging section. A pre-pit is formed for each unit section. The land prepit detected by the land prepit detection circuit 21 is input to the period averaging circuit 7 via the window protection circuit 22 and used to determine the start point of the period averaging section. The detailed operation of the period averaging circuit 7 will be described with reference to FIGS.
[0040]
As the timer value of the timer 15, in principle, the period average value is loaded. The operation clock of the timer has a fixed frequency, and a stable square wave having a period substantially the same as the period average value can be generated by operating the fixed frequency oscillator 14 which is sufficiently higher than the period average value. The frequency multiplication PLL 16 multiplies the output of the timer to generate a recording clock.
[0041]
Here, immediately after the start of recording, that is, immediately after the laser transitions from the reproduction power to the recording power, or immediately after the end of recording, that is, immediately after the laser transitions from the recording power to the reproduction power, the push is performed until the AGC of the RF amplifier 4 responds. It is assumed that the pull signal is greatly shaken and the wobble signal cannot be detected temporarily or the period of the wobble signal is disturbed. In this case, a signal indicating a certain time from the start of recording by the recording start position determining circuit 8, a signal indicating a certain time from the end of recording by the recording end position determining circuit 9, or a wobble signal missing by the wobble missing detection circuit 10 is detected. When at least one of the signals shown is detected, the operation of the first timer control circuit 11 prevents the timer 15 from being loaded with a new average period, and the period of the output rectangular wave of the timer is held. . As a result, the stability of the recording clock in the transient state can be improved. In a typical optical disc apparatus, the AGC response time is around 200 μs, and if this time is about this, there is no practical problem in holding the period of the time recording clock.
[0042]
The wobble loss detection is also effective for the disturbance of the wobble signal period due to scratches on the disk surface or the adhering of dust. Detection of missing wobbles can be detected when the wobble period is significantly longer than the standard period, or when the detector total addition signal becomes less than a predetermined value due to dust or scratches on the disk surface.
The cycle comparison circuit 12 compares the average cycle Q calculated by the cycle averaging circuit 7 with the previous timer output cycle T0 held in the cycle holding circuit 30. The second timer control circuit 13 operates so as to limit the fluctuation amount of the update period loaded from the period averaging circuit 4 to the timer 5 to a predetermined value or less when the period comparison circuit detects a certain period difference or more. To do. Details of the period comparison circuit will be described with reference to FIGS.
[0043]
The encoder 18 modulates the data sent from the interface 17 in accordance with the timing of the recording clock output from the frequency multiplication PLL 16. The modulated data drives the laser inside the head 3 through the power control circuit 19 and the laser drive circuit 20. The encoder 18 sends a recording gate signal corresponding to the data modulation section to the recording start position determination circuit 8 and the recording end position determination circuit 9.
[0044]
Next, the detailed operation of the period averaging circuit 7 will be described. FIG. 5 is a block diagram of the cycle averaging circuit 7, and FIG. 6 is an operation explanatory diagram of the cycle averaging circuit. In this operation example, a case where the average of 16 periods of the wobble signal is obtained will be described as an example. In FIG. 5, reference numeral 501 denotes a D flip-prop, and 502 denotes an integration period measurement counter that measures the total time of the wobble period. Reference numeral 503 denotes a wobble cycle counter that counts the number of cycles of the wobble signal. Reference numeral 504 denotes a coincidence detector that determines that 16 wobble periods have been input. 505 is a latch for holding the measurement time, 506 is a shifter for performing division, and 507 is an average interval generation circuit for generating an average interval from the land pre-pit position. In FIG. 6, 510 is a push-pull signal, 511 is a wobble signal, 512 is a measurement section, 513 is a timer operation schematically representing a timer count value, and 514 is a rectangular wave output of the timer.
[0045]
The average section generation circuit 507 in FIG. 5 is a circuit that outputs a signal representing a measurement section for two frames corresponding to the measurement section 512 in FIG. 6, that is, a unit section, based on the land pre-pit timing. A measurement section signal is output from a signal rising edge, that is, slightly before the leading edge of two frames. The section measurement signal needs to be output at a timing such that the end edge of the 16th wobble period, that is, the leading edge of the next two frames is surely included and the previous edge is not included. It can be easily estimated from the middle wobble signal period. The period measurement start point is the time when the wobble signal is input to the D flip-flop 501 to the last. A measurement interval signal output from the average interval generation circuit 507 and a wobble signal are connected to the D flip-flop 501. The D flip-flop is used to accurately start the counter 502 at the rising edge of the wobble signal.
When the measurement interval signal is output, the rising edge of the wobble signal is input, and the D flip-flop 501 is set, the clearing of the integration period measurement counter 502 is released and time measurement using the fixed frequency clock starts. The wobble cycle counter 503 counts the number of cycles of the input wobble signal. The coincidence detector 504 outputs a clock when the wobble signal is input for 16 periods. When the count value of the counter 502 at that time is V1, for example, V1 is copied to the latch 505. Therefore, the latched value is a value obtained by measuring 16 periods of the wobble signal with a fixed frequency resolution. The latch output is divided by 16 by shifting 4 bits to the right by the shifter 506, and V1 / 16, that is, an average value of 16 periods is obtained. Although the example of the circuit configuration of the cycle measurement has been described in an easy-to-understand manner, when the time measurement of 16 cycles is continuously performed, the integration cycle measurement counter 502 needs to be modified so that it can be continuously measured. Since this is easy, explanation is omitted.
[0046]
The measurement interval of the average interval generation circuit 507 will be additionally described with reference to FIG. As shown in the measurement section 512, the measurement section for obtaining the period average value of the wobble signal starts at the rising point of one period of wobble where the land prepits exist, and measures the time of 16 periods each time. Since the land pre-pits appear periodically every two frames as described with reference to FIG. 3 and Table 1, the measurement section generating circuit can check and predict the appearance pattern of the land pre-pits. If the appearance position of the leading pulse ((111) or (110)) of the land pre-pit shown in Table 1 is predicted, a measurement interval signal of 16 periods is output from the beginning of the wobble signal period including the appearance position. Good. By dividing the total time V1 of 16 periods measured in the above section by 16, an average value of one wobble period, that is, a wobble signal period can be obtained. Thereafter, the same time measurement is performed every 16 wobble cycles, and the value obtained by dividing the time by 16 is loaded into the timer 15 as an average cycle. After the average period is loaded, the timer 15 continues to oscillate at the same period as indicated by 513 until the next average period is loaded. The reason why the measurement period of the average period is 16 periods is that the land pre-pit appears every 2 frames (equivalent to 16 wobble periods) as described above. For example, the average period is calculated every 64 wobble periods. Is also possible.
[0047]
In the example shown in FIG. 6, the start point of the period measurement section is set to the start position of the land prepit, and the section width is set to an integral multiple of the appearance interval. It can be distributed almost evenly every time.
The operation at time T1 in FIG. 6 will be described. V1 / 16 is calculated at time T1, and the calculation result V1 / 16 is loaded into the timer 15 and also loaded into the period holding circuit 30. After the time T1, the timer 15 outputs a pulse as a timer output (indicated by 514) every loaded period (V1 / 16). Further, the period averaging circuit 7 starts counting the period V2 of the next 16 wobble periods after the time point T1.
[0048]
The period averaging section may be taken as in the example shown in FIG. FIG. 9 is a diagram illustrating a second operation of the period averaging circuit. In this example, the period averaging section 702 is a wobble eight period section in which no land prepits exist on the inner and outer peripheral sides of the disc. By obtaining the period average in the section without the land pre-pits, the influence of the land pre-pits on the wobble signal period can be completely eliminated for both the outer peripheral side and the inner peripheral side. A section having no land pre-pits can be detected by binarizing and detecting land pre-pits in both directions (outer peripheral side) and lower (inner peripheral side) with respect to the push-pull signal.
[0049]
Next, the detailed operation of the period comparison circuit 12 will be described. FIG. 7 is a block diagram of the cycle comparison circuit 12, and FIG. In FIG. 7, 601 is a subtractor for calculating Q-T0, 602 is a subtractor for calculating T0-Q, 603 is a setting register for a predetermined value (also referred to as a limit value) A for specifying a predetermined range, and 604 is Q- A T0 and A comparator, 605 is a T0-Q and A comparator, 606 is a T0 + A adder, 607 is a T0-A subtractor, and 608 is a selector. In the flowchart of FIG. 8, reference numeral 610 denotes a symbol definition, reference numerals 611 and 612 denote a comparison between an average period and a timer period, and reference numerals 613 to 615 denote update contents of the timer load value.
[0050]
First, the definition of symbols shown in the flowchart 610 in FIG. 8 will be described. The average period obtained by the period averaging circuit 7 is Q, the timer oscillation period, that is, the timer value loaded immediately before is T0, and the update amount limit value is A. In the ideal state, Q and T0 should have the same value. Next, the subtractor 601 outputs the result of subtracting the timer period T0 from the average period Q to the comparator 604. The subtractor 602 outputs the result of subtracting the average period Q from the timer period T0 to the comparator 605. It is assumed that the limit value A is set in the limit value setting register 603. As shown in the flowcharts 611 and 613, when the average period Q is larger than the timer period T0 by A or more, the comparator 604 operates and the selector 608 selects the output of the adder 606. Since the adder 608 outputs T0 + A, the average period output to the timer is not Q but T0 + A. As indicated by 612 and 614, when the average period Q is smaller than the timer period T0 by A or more, the comparator 605 operates, and the selector 608 selects the output of the subtractor 607. Since the subtractor 607 outputs T0-A, the average period output to the timer is not Q but T0-A. If none of the comparators operate, the selector 608 selects the average period Q, and the timer period update value is also Q.
[0051]
In the DVD-R disc, for example, when considering the inner circumferential position with a diameter of 48 mm, the length corresponding to 16 wobbles is 396 μm. Therefore, in FIG. 6, the number of times of timer load per rotation, that is, the number of measurements of the wobble average period is ,
48 (mm) × 3.14 × 1000 ÷ 396 (μm) = 380 (times)
become. On the other hand, the speed fluctuation at the maximum acceleration / deceleration of the disk motor is 10% or less per rotation of the disk in a typical optical disk apparatus.
10 (%) 380 (times) = 0.026 (%)
Degree. Actually, it is necessary to consider the influence of the periodic fluctuation due to the disk eccentricity, but as an example of setting the limit value A, about 3 is appropriate when the timer value T0 is about 10,000 counts.
[0052]
Based on the above, the operation at time T2 in FIG. 6 will be described. V2 / 16 is calculated at time T2, and the calculation result V2 / 16 is compared with the value V1 / 16 held in the cycle holding circuit 30. In this case, the value held in the cycle holding circuit 30 is the reference value. When the difference between V2 / 16 and V1 / 16 is outside the predetermined range (outside ± A), V2 / 16 is not an appropriate value. When the difference is within the predetermined range (within ± A), V2 / 16 16 is an appropriate value. When V2 / 16 is not an appropriate value, a value obtained by adding or subtracting the predetermined value A to the calculation result V1 / 16 is loaded into the timer 15. When V2 / 16 is an appropriate value, the calculation result V2 / 16 is loaded into the timer 15. The value loaded into the timer 15 is also loaded into the period holding circuit 30. The timer 15 may start counting at time T2, and the timer 15 may be loaded after the count starts.
[0053]
As an example of a case where it is determined that the value is not an appropriate value, 16 wobble periods should have been counted, but there is a case where unnecessary count-up has been performed due to dust or scratches. In this case, the period of 15 wobble periods is actually counted, but one unnecessary count-up is performed due to dust or scratches. When one unnecessary count-up is made, it is smaller than the original count value at a rate of 15/16 (= 0.9375). In this case, a value obtained by subtracting the predetermined value A from V1 / 16 (calculated in the above example becomes 0.9997 with respect to the original count value) is loaded into the timer, and V2 / 16 is thrown away.
[0054]
As another example of a case where it is determined that the value is not appropriate, there may be a case where 16 wobble periods should have been counted, but one wobble period signal could not be read. In this case, the period of 17 wobble cycles is actually counted. When one wobble cycle signal cannot be read, it is larger than the original count value by 17/16 (= 1.0625). In this case, a value obtained by adding a predetermined value A to V1 / 16 (calculated in the above example is 1.0003 relative to the original count value) is loaded into the timer, and V2 / 16 having a significantly different value is Thrown away.
[0055]
With the above operation, even when the wobble cycle is greatly disturbed for an unexpected reason, the rapid fluctuation of the timer output can be suppressed, and the fluctuation amount of the updated cycle becomes the predetermined value A or less. In principle, it is impossible for the wobble signal period to fluctuate greatly beyond the disk eccentricity or the maximum acceleration of the disk motor. Under normal operating conditions, it is impossible to suppress the period fluctuation exceeding this. It is effective in improving the performance.
[0056]
As described above, in the first embodiment, an accurate wobble period can be obtained by reducing the influence by the period averaging means on the wobble signal having a period fluctuation locally due to the influence of the land pre-pit and the influence of the recording power modulation. Can be detected. As an example of the operation of the average periodic circuit, two methods that are not easily affected by the land pre-pits are shown. Regarding the influence of wobble phase fluctuation and noise due to recording power modulation, it is considered that the phase fluctuation direction occurs at random, so it is effective to average the wobble period. Also, even if the wobble signal cycle becomes locally incorrect due to factors such as immediately after the start of recording, immediately after the end, or dust on the surface of the disc, the timer output cycle can be held during that period to generate a correct recording clock. .
[0057]
Note that the longer the period averaging section, the less affected by disturbance, but it is necessary to determine the period in consideration of the response characteristics to the linear velocity fluctuation of the recording clock. For example, when the response frequency characteristic of the recording clock with respect to the linear velocity fluctuation is required to be about 2 KHz, it is appropriate to set the period averaging interval to 500 microseconds or less.
[0058]
(Embodiment 2)
FIG. 10 is a block diagram according to the second embodiment of the present invention. In FIG. 10, 1 is an optical disk, 2 is a disk motor, 3 is a head, 4 is an RF amplifier, 5 is a decoder, 6 is a wobble signal detection circuit, 8 is a recording start position determination circuit, and 9 is a recording end position determination circuit. Is a wobble missing determination circuit, 11 is a first timer control circuit, 12 is a period comparison circuit, 13 is a second timer control circuit, 14 is a fixed frequency oscillator, 15 is a timer, 16 is a frequency multiplication PLL, 17 is an interface, Reference numeral 18 denotes an encoder, 19 denotes a power control circuit, and 20 denotes a laser drive circuit. Since the above is the same as in the first embodiment, detailed description thereof is omitted. A phase comparison circuit 23 compares the phases of the wobble signal and the timer output. A period averaging circuit 24 determines a timer load value based on the wobble period detected by the wobble signal detection circuit 6 and the phase difference detected by the phase comparison circuit 23.
[0059]
Next, detailed operations of the period averaging circuit and the phase comparison circuit will be described. FIG. 11 is a diagram for explaining the operation of the period averaging circuit. In FIG. 11, 901 indicates a wobble signal, 902 indicates a period measurement section 1, and the length of the section 1 is represented by a rectangular length. It is assumed that the period measurement is performed for N periods (W is a predetermined integer) of the wobble signal. Similarly, 903 indicates the period measurement section 2, the length of the section 2 is represented by a rectangular length, 904 indicates the period measurement section 3, and the length of the section 3 is represented by a rectangular length. In this embodiment, in addition to the wobble period, the phase error of the wobble signal and the timer output is also measured. 905 indicates the phase difference measurement section 1 and the phase error generated in the section 1 represented by the rectangular length. The phase error between the wobble signal remaining at the end of section 1 and the timer rectangular wave is denoted by Z1. Similarly, 906 indicates the phase difference measurement section 2, Z2 indicates the phase error remaining at the end of the section 2 represented by the length of the rectangle, 907 indicates the phase difference measurement section 3, and the length of the rectangle The phase error remaining at the end of the section 3 represented by is represented by Z3. Reference numeral 908 denotes a timer operation, and 909 denotes a rectangular wave output of the timer.
[0060]
In the first embodiment, the period average value is obtained by measuring the time every 16 wobble periods without overlapping sections, but in this embodiment, the average period is calculated using both the measured value of the wobble period and the measured value of the phase error. To do. First, a method for measuring the wobble cycle will be described. In this embodiment, every time a wobble signal is input for one period, the average period is recalculated, and a period average value is calculated by taking a moving average. Specifically, when the period of the wobble signal N period measured in the 902 period measurement section 1 is V1, and the wobble signal input period after the measurement of V1 is X2, X3,..., V1 to V1 (1 / N) A value obtained by subtracting and adding X2 is set as a new cycle integrated value V2. That is, V2 = ((N−1) / N) × V1 + X2. The reason why the approximate expression using V1 and X2 is used instead of the measurement value itself as V2 is that it is not necessary to store all the start points of the measurement section. That is, if the approximate expression is not used, all N sections must be measured in parallel, and the section measurement counter becomes N times. Similarly, when the next wobble signal period X3 is input, the integrated value V3 corresponding to the measurement section 3 is obtained by adding X3 to V2 minus V2 (1 / N), so V3 = ((N−1) / N) × V2 + X3.
[0061]
Next, the phase error between the wobble signal and the timer output will be described. It is possible to obtain a rectangular wave with the same period as the wobble period simply by calculating the period average value and loading the timer, but depending on the period average rounding error, rounding error, or period average measurement resolution The phase difference may accumulate between the original wobble signal and the timer rectangular wave output. Even if the phase error in each measurement section is slight, the phase error between the recording clock and the land pre-pit on the disc increases due to the accumulation of the phase error. Therefore, in this embodiment, the phase error Z between the wobble signal and the timer output rectangular wave is reflected in the timer load value, and control is performed so that the phase error Z is always reduced. Specifically, as shown in 909, when the phase difference between the wobble signal and the timer rectangular wave output at the time of measuring the wobble N period is Z1, and the initial value of the integrated value of the phase error is W1 = Z1, Next, the value loaded into the timer is the sum of 1 / N of V1 and 1 / N of W1. The reason for setting the phase difference W1 to 1 / N is to avoid abrupt timer period fluctuations by dispersing the phase error over N periods and reflecting it in the timer setting, thereby improving the recording clock jitter performance.
W1 is added to V1 when the phase error decreases, that is, when the timer phase is delayed with respect to the wobble signal, and subtracted from V1 when the timer phase is advanced. Similarly, when the phase error at the time of the next wobble signal input is Z2, the value reflected in the timer setting as the phase difference integrated value W2 is obtained by subtracting W1 (1 / N) from W1 and adding Z2 as in the period measurement. That is, W2 = ((N−1) / N) × W1 + Z2, and the value loaded into the timer is (V2 + W2) / N. Similarly, for the next cycle X3 and phase difference Z3, (V3 + W3) / N is loaded into the timer. Correction of the phase error indicated by 905, 906, and 907 in FIG. 11 can be omitted.
[0062]
As described above, in the second embodiment of the present invention, since the cycle average value is updated every wobble cycle, the variation in the output cycle of the timer can be made smoother than that in the first embodiment, and the timer The jitter performance of the recording clock obtained by multiplying the output can be expected. In addition, by reflecting the phase difference between the wobble signal and the timer output in the timer load value, even if there are some period averaging rounding errors, rounding errors, and timer resolution errors, the accumulation is suppressed, and the wobble signal and timer output Can be operated so that their phases always match.
[0063]
(Embodiment 3)
FIG. 1 is a third embodiment of the present invention. In FIG. 1, 1 is an optical disk, 2 is a disk motor, 3 is a head, 4 is an RF amplifier, 5 is a decoder, 6 is a wobble signal detection circuit, 8 is a recording start position determination circuit, 9 is a recording end position determination circuit, 10 Is a wobble missing detection circuit, 11 is a first timer control circuit, 12 is a period comparison circuit, 13 is a second timer control circuit, 14 is a fixed frequency oscillator, 15 is a timer, 17 is an interface, 18 is an encoder, 19 is The power control circuit, 20 is a laser drive circuit, 23 is a phase comparison circuit, and 24 is a period averaging circuit. Since the above is the same as in the second embodiment, detailed description thereof is omitted. Reference numeral 21 denotes a land pre-pit detection circuit, and reference numeral 22 denotes a window protection circuit, which has been described in the first embodiment. A latch 25 latches the count value of the timer 15 when the land pre-pit is detected in the window. That is, the result of measuring the position from the rise of the timer output rectangular wave to the land pre-pit is entered in the latch. A subtracter 26 subtracts a predetermined number from the contents of the latch. Reference numeral 27 denotes a low-pass filter, which is a digital filter that allows only a low-frequency component to pass through the subtracter output. Reference numeral 28 denotes a frequency multiplication PLL, which has the same basic PLL operation as that of the first and second embodiments, but is configured so that the phase of the recording clock can be corrected according to the output value of the low-pass filter 27.
[0064]
Next, a method for detecting a phase difference between a wobble signal and a land pre-pit signal will be described with reference to FIG. FIG. 12 is a diagram for explaining the operation of phase difference detection. In FIG. 12, 1001 is a land pre-pit signal, 1002 is a detection window, 1003 is a timer count operation, 1004 is a wobble signal, 1005 is a latch output, and 1006 is a subtractor output. In the land pre-pit signal 1001, a component erroneously detected outside the window by the detection window 1002 is removed. The timer always performs a countdown operation as indicated by 1003, and a new average period is loaded at the time of zero count. The average period to be loaded is indicated by L1 and L2 in the figure. When the land pre-pit signal is detected in the window, the timer count value C1 corresponding to the detected position is copied to the latch 1005. The phase difference A1 between the wobble signal and the land pre-pit signal can be calculated as A1 = L1-C1 using the latched value. Here, if the phase difference AN between the wobble signal and the land prepit in an ideal state without crosstalk between tracks is known in advance, the phase correction of A1-AN, that is, L1-C1-AN is performed with respect to the frequency multiplication PLL. As a result, the phase difference between the wobble signal and the land pre-pit signal can always be kept free from crosstalk between tracks. L1-C1-AN is performed by the subtractor 26. The output of the subtractor 26 is sent to the frequency multiplication PLL 28 as a phase correction signal through a low-pass filter 27 having a cutoff number KHz. The reason for using the low-pass filter is that the land pre-pit signal has a jitter component due to the difference in the amount of light received by the mark portion and space portion of the recording pulse during recording, and the difference in the amount of light received by the mark portion and space portion during playback. To remove it. Another reason is to suppress the response of the frequency multiplication PLL 28 to the undetected or erroneously detected land prepits.
[0065]
Next, the frequency multiplication PLL will be described with reference to FIG. FIG. 13 is a block diagram of the frequency multiplication PLL. In FIG. 13, reference numeral 1101 denotes a phase comparator which compares the timer output with the rising phase of the coincidence detector. 1102 is a charge pump, 1103 is a VCO, 1104 is a 744 frequency dividing counter, 1105 is a coincidence detector, and 1106 is a frequency dividing counter for outputting a recording clock.
[0066]
In the present embodiment, the resolution of phase correction is set to a quarter period of the recording clock, so that the oscillation frequency of the VCO is four times that of the recording clock. Therefore, the recording clock is obtained by dividing the output of the VCO 1103 by the divide-by-4 counter 1106. Further, since the frequency of the wobble signal is 1/186 of the recording clock, the frequency divider is four times that, that is, 186 × 4 = 744, and a 744 frequency dividing counter 1104 is provided. When there is no phase correction, the coincidence detector 705 operates so as to generate a rectangular wave including a rising pulse every time the count value of the 744 frequency division counter becomes zero. The rising edges of the rectangular wave output from the coincidence detector 1105 and the timer output rectangular wave are compared by the phase comparator 1101, the charge pump 1102 is driven according to the phase difference amount, and the output frequency of the VCO 1103 is controlled.
[0067]
Next, the phase correction operation of the frequency multiplication PLL will be described with reference to FIG. FIG. 14 is an explanatory diagram of the phase correction operation of the frequency multiplication PLL. In FIG. 14, reference numeral 1201 denotes the count value of the 744 frequency divider. Since this frequency divider is a counter having a fixed frequency division ratio of 744, the count value is repeatedly counted down from 743 to 0. 1202 shows the phase correction value output from the low-pass filter 27. In this example, for convenience of explanation, the first half of the timing chart is shown as a correction value −10, and the second half is shown as a correction value +10. However, since the low-pass filter 27 having a cutoff number kHZ is actually inserted, The correction value does not change rapidly from -10 to +10 instantaneously. The coincidence detector 1105 generates a rising waveform when the count value of the 744 frequency division counter becomes -10 (733) when the correction value is -10, and the count value of the 744 frequency division counter when the correction value is +10. A rising waveform is generated when becomes +10. That is, the phase of the rectangular wave output from the coincidence detector is corrected in units of a quarter cycle of the recording clock according to the set value. If the phase of the wobble signal is advanced and the phase of the timer output is advanced with respect to the land pre-pit signal due to crosstalk between tracks, the output phase of the coincidence detector is also controlled to advance by the output amount of the low-pass filter. Thus, control can be performed so as to cancel the output phase fluctuation of the PLL. On the contrary, when the phase of the wobble signal is delayed, the phase of the coincidence detector may be controlled to be delayed. Since the phase comparator 1101 can be configured to compare only the rising edges, the falling position of the rectangular wave output from the coincidence detector 1105 does not need to be determined strictly, but, for example, falls in the vicinity of 370 counts where the count value is half. Should be designed as follows.
Note that the phase difference between the wobble signal and the land pre-pit signal is measured with the frequency resolution of the fixed clock oscillator 14, and the phase correction unit of the frequency multiplying PLL 28 is determined by the oscillation frequency of the VCO 1103. In some cases, it is necessary to convert the setting unit of the correction value.
In this embodiment, the phase correction is performed on the output of the VCO 1103. However, the same effect can be obtained by performing the phase correction on the timer output. In this case, if the phase of the timer output is corrected using the same clock as that of the timer, conversion of the correction value setting unit is unnecessary.
As described above, according to the present embodiment, a wobble signal can be obtained by effectively combining a period averaging circuit, a low-pass filter, and one frequency multiplication PLL, which are relatively small in circuit scale and can be configured digitally. It is possible to easily detect the phase of the land pre-pit signal and easily correct the phase of the recording clock using the land pre-pit signal.
[0068]
In a DVD-R disc, the wobble frequency is 140 KHz, the appearance interval of land prepits is 2 frames (about 10 KHz), the PLL response band for following the eccentricity of the disc is about 1 KHz, and the inter-track interference of the wobble is 5.3. Rotation cycle and slow. Therefore, the phase correction response speed 140 KHz of the timer in the period averaging circuit is sufficient to measure the phase difference between the land pre-pit and the wobble signal appearing at about 10 KHz. Further, by selecting the cut-off frequency of the low-pass filter to be about 1 KHz, it is possible to perform phase correction of the frequency multiplying PLL while following the linear velocity fluctuation of the disk and suppressing the high-frequency jitter component of the land prepit. Further, the use of a low-pass filter can suppress the increase in jitter of the recording clock to the minimum even if the land pre-pit is erroneously detected or not detected, and the practical effect of the present invention is great.
[0069]
(Embodiment 4)
Next, another detailed operation example of the period averaging circuit will be described. FIG. 15 is an operation explanatory diagram of the cycle averaging circuit according to the fourth embodiment. The block diagram of the period averaging circuit is the same as that of the second embodiment, and the description is omitted. In FIG. 15, 1501 indicates a wobble signal, 1502 indicates a period measurement section 1, 1503 indicates a period measurement section 2, and 1504 indicates a period measurement section 3. Reference numeral 1505 denotes a phase difference measurement section 1, 1506 denotes a phase difference measurement section 2, and 1507 denotes a phase difference measurement section 3. 1508 indicates a timer operation, and 1509 indicates a rectangular wave output of the timer.
[0070]
A method for measuring a wobble period in Embodiment 4 will be described. The method of measuring the periodic integrated values V1, V2, V3,... Is the same as that of the second embodiment, but the method of calculating the phase error integrated value and the method of calculating the phase error timer load value are different from those of the second embodiment. Different. In the fourth embodiment, a value obtained by multiplying the phase error between the wobble signal and the timer output rectangular wave by a constant attenuation constant is reflected in the timer load value.
[0071]
Specifically, as shown in 1509, when the phase difference between the wobble signal and the timer rectangular wave output at the time of measuring the wobble N period is Z1, the initial value of W1 is Z1, and then the timer The value to be loaded is the sum of V1 / N and W1 / (D × N). D is an attenuation constant. The reason why the reflection value of the phase difference to the timer is set to W1 / (D × N) is that a constant attenuation constant D is applied to the phase error, and it is distributed over the N periods and reflected in the timer setting. This is to follow the wobble cycle more stably. When the phase error at the time when the next wobble signal is input is Z2, the phase difference integrated value W2 is W2 = ((NC) / N) × W1 + Z2. C is a subtraction constant. The reason why the constant C is subtracted is to adjust the gain of the phase error amount with respect to the integrated value Wi. The timer load value at this time is a total value of V2 / N and W2 / (D × N). The same timer loading is performed in subsequent cycles.
[0072]
For example, when the period averaging interval corresponds to 128 wobble periods (N = 128), by setting the subtraction constant C = 4 and the attenuation constant D = 2 in this embodiment, In addition, the feedback amount of the phase error can be suppressed to a low level, and particularly when the periodic fluctuation of the input wobble signal is severe, there is an effect of suppressing the periodic fluctuation of the timer output, that is, the averaged wobble signal. The period averaging section may be a separate value for the period integrated value measurement and the phase error integrated value measurement.
[0073]
As described above, in the third embodiment of the present invention, the phase difference between the wobble signal and the timer output is accumulated by gradually reflecting the phase difference between the wobble signal and the timer output on the timer load value by multiplying the constant attenuation constant. It is possible to prevent the timer output from becoming unstable due to an excessive feedback of the phase error amount even when the wobble signal has a significant period fluctuation.
[0074]
【The invention's effect】
In the recording clock generator of the present invention, the wobble signal phase fluctuation due to the influence of the adjacent track, the wobble signal phase fluctuation due to the leakage of the land pre-pit signal, the wobble signal phase fluctuation due to the leakage of the recording power modulation component, and other noises. A stable recording clock can be generated by performing period averaging with respect to the wobble signal period fluctuations.
[0075]
Also, even if the wobble signal is lost due to the transient response of the RF amplifier at the start or end of recording or dust on the disk surface, the output cycle of the timer that oscillates with the average cycle of the wobble signal must be held. Thus, the output of the frequency multiplication PLL, that is, the jitter deterioration of the recording clock can be minimized.
[0076]
Even if high frequency jitter, false detection, or no detection is present in the land pre-pit signal, the effect of high frequency jitter or missing can be obtained by using a signal that has passed through a low-pass filter as the phase correction signal for the recording clock. And the phase jitter of the recording clock with respect to the disk can be greatly improved.
Further, according to the present invention, all of the period averaging circuit, the timer, the low-pass filter, and the like can be configured by a relatively small-scale digital circuit. Basically, the phase based on the land pre-pit signal is generated by one frequency multiplication PLL. A corrected recording clock with little jitter can be generated, and its practical effect is great.
[Brief description of the drawings]
FIG. 1 is a block diagram of a third embodiment.
[Fig. 2] Disk groove shape
[Figure 3] Disc recording format diagram
FIG. 4 is a block diagram according to the first embodiment.
FIG. 5 is a block diagram of a period averaging circuit in the first embodiment.
6 is an operation explanatory diagram of a cycle averaging circuit in Embodiment 1. FIG.
FIG. 7 is a block diagram of a period comparison circuit in the first embodiment
8 is an operation explanatory diagram of a cycle comparison circuit in Embodiment 1. FIG.
FIG. 9 is a diagram illustrating a second operation of the period averaging circuit in the first embodiment.
FIG. 10 is a block diagram according to the second embodiment.
FIG. 11 is an operation explanatory diagram of a cycle averaging circuit according to the second embodiment.
FIG. 12 is a diagram for explaining the operation of phase difference detection in the third embodiment.
FIG. 13 is a block diagram of a frequency multiplication PLL in the third embodiment
FIG. 14 is an operation explanatory diagram of a frequency multiplication PLL in the third embodiment.
FIG. 15 is an operation explanatory diagram of a cycle averaging circuit according to the fourth embodiment.
[Explanation of symbols]
1 Optical disc
2 Disc motor
3 heads
4 RF amplifier
5 Decoder
6 Wobble signal detection circuit
7, 24 period averaging circuit
8 Recording start position judgment circuit
9 Recording end position judgment circuit
10 Wobble missing circuit
11 First timer control circuit
12 Period comparison circuit
13 Second timer control circuit
14 Fixed frequency oscillator
15 timer
16 Frequency multiplication PLL
17 Interface
18 Encoder
19 Power control circuit
20 Laser drive circuit
21 Land pre-pit detection circuit
22 Window protection circuit
23 Phase comparison circuit
25, 505 latch
26 Subtractor
27 Low-pass filter
28 Frequency multiplication PLL
201 Groove
202 rand
203 Land Prepit
204 Record mark
303 Outer land pre-pit signal
304 Inner peripheral land pre-pit signal
501 D flip-flop
502 Integration cycle measurement counter
503 Wobble cycle counter
504 coincidence detector
506 Shifter
507 Average interval generation circuit
601 Subtractor (Q-T0)
602 Subtractor (T0-Q)
603 Limit value setting register
604 Comparator (Q-T0 and A)
605 Comparator (T0-Q and A)
606 Adder (T0 + A)
607 Subtracter (T0-A)
608 selector
1101 Phase comparator
1102 Charge pump
1103 VCO
1104 744 frequency division counter
1105 coincidence detector
1106 Divide-by-4 counter

Claims (2)

A recording clock generator for recording data on an optical disc in which a recording groove wobbled at a predetermined period in the radial direction and a prepit signal is formed for each unit section including a predetermined number of wobble periods,
A wobble signal detecting means for obtaining a push-pull signal obtained from reflected light from a recording groove, and outputting the wobble signal by binarizing the push-pull signal after passing through a band-pass filter ;
The push-pull signal is acquired, and the pre-pit positions on the outer peripheral side and the inner peripheral side are detected by binarizing and detecting an instantaneously high peak value and an instantaneously low peak value with respect to the amplitude value of the push-pull signal. Pre-pit detecting means for detecting and detecting a section in which none of the binarized signals is detected for a certain period as a section in which no pre-pit exists on the outer peripheral side or the inner peripheral side ;
Period averaging means for obtaining an average period of the wobble signal;
A timer that generates a rectangular wave having substantially the same period as the average period obtained by the period averaging means;
A frequency multiplying PLL for multiplying the timer output to generate a recording clock;
It said periodic averaging means, a recording clock generator and calculates the average period in the recording groove nonexistent sections of the pre-pit in the outer peripheral side to the inner circumferential side of the. A recording clock generation method for recording data on an optical disc in which a recording groove wobbled in a radial direction at a predetermined cycle and a prepit signal is formed for each unit section including a predetermined number of wobble cycles,
Obtaining a push-pull signal obtained from reflected light from the recording groove, and outputting the wobble signal by binarizing the push-pull signal after passing through a band-pass filter ;
The push-pull signal is acquired, and the pre-pit positions on the outer peripheral side and the inner peripheral side are detected by binarizing and detecting an instantaneously high peak value and an instantaneously low peak value with respect to the amplitude value of the push-pull signal. Detecting and detecting a section in which any of the binarized signals is not detected for a certain period of time as a section in which no prepit exists on the outer peripheral side or the inner peripheral side ;
Obtaining an average period of the wobble signal;
Generating a rectangular wave having substantially the same period as the average period determined in the step of determining the average period;
Multiplying the rectangular wave to generate a recording clock,
The recording clock generation method characterized in that the step of obtaining the average period calculates the average period in a section where no prepits exist on either the inner peripheral side or the outer peripheral side of the recording groove.

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