JP2002108700A - Sdram interface circuit and sdram control method and image processor equipped with the same sdram interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SDRAM interface circuit capable of reducing the load of a controller such as a DPS and a CPU, and simplifying the constitution of a program or a circuit. SOLUTION: In an SDRAM interface circuit 200 in which a DSP 100 is connected to an SDRAM 300, a reception data buffer 700 successively preserves reading addresses inputted from the DSP 100 in plural buffers, and a command control block 800 judges the continuity of the reading addresses preserved in the plural buffers, and at the time of judging that the continuity is not present any more in the reading addresses, generates and outputs a read command with the first reading address as a start address. The SDRAM 300 outputs read data corresponding to the read command. The reception data buffer 700 successively preserves the read data in the plural buffers, and outputs the preserved read data to the DSP 100 as necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SDRAM interface circuit, an SDRAM control method, and an SDRAM.
The present invention relates to an image processing device having a RAM interface circuit.

[0002]

2. Description of the Related Art In recent years, high-speed DR replacing asynchronous DRAM
As AM, synchronous DRAM (hereinafter, SDRAM)
Has been developed. SDRAM is a conventional DR
In addition to the features of AM, it has features such as an input / output circuit configuration synchronized with an external clock, access in command format, continuous access by burst transfer, and a multi-bank configuration. If such an SDRAM is used for an image buffer or the like, a loss during access can be reduced by using a common clock for the SDRAM and a processing circuit such as a CPU or DPS. Also, by using burst transfer, DPS and CP can be used.
U can be operated with no weight.

In order to read and write data from a DSP or the like to the above-mentioned SDRAM, the DSP or the like
An SDRAM interface circuit is placed between the RAM and the RAM. The conventional SDRAM interface circuit has a D
The control signal from the SP or the like is received, converted into a signal for SDRAM, and the SDRAM is controlled.

[0004]

However, the conventional SDRAM interface circuit is constituted by a passive circuit which receives a control signal from a DSP or the like and converts it into a signal for SDRAM.
M is managed. For this reason, the program executed by the DSP or the like is provided with a procedure for controlling the SDRAM.
For example, it is necessary to execute an operation for controlling the SDRAM.

For example, an SDRAM needs to be refreshed every unit time. This refresh is SDRA
This is performed by inputting a refresh command to M. Therefore, when the SDRAM is under the control of a DSP or the like, the DSP or the like measures the time, and
A control signal for instructing refresh is input to the M interface circuit. The SDRAM interface circuit is
This control signal is converted into a refresh command, and SDR
Input to AM.

When data is read / written from / to an SDRAM, a bank is activated by a bank active (ACT) command in a state where a clock enable (CKE) signal for the SDRAM is activated, and then a read (RD) / write is performed. (WT) command to S
Input to DRAM, specify address, read data /
Write.

In order to perform this read / write operation, D
The SP or the like outputs some control signal to activate the CKE signal to the SDRAM to the SDRAM interface circuit. Next, the address data is input to the SDRAM interface circuit. The SDRAM interface circuit determines a bank and an address from address data, and inputs a bank active command and a read / write command to the SDRAM.

Since data read / write must be performed between the refreshes, the DSP or the like needs
It is necessary to monitor the state of the DRAM and input a command to the SDRAM at an optimal timing. If the command is input at an inappropriate timing, the data that should have been written may be destroyed, or the data may not be read properly.

Although the SDRAM interface circuit is provided as described above, when the control of the SDRAM is under the DSP or the like, the load of the DSP or the like is large, and the programs and circuits executed by the DSP or the like are complicated, and the programmer is complicated. Are suffering from complicated SDRAM control.

[0010] The present invention has been made in view of the above points, and reduces the load on a control device such as a DSP and a CPU.
SD that can simplify the configuration of programs and circuits
It is an object to provide a RAM interface circuit, an SDRAM control method, and an image processing apparatus including the SDRAM interface circuit.

[0011]

In order to solve this problem, an SDRAM interface circuit for connecting a control device such as a DSP or CPU to an SDRAM receives an access request (read access, write access, etc.) from the control device. Hold, check the continuity of the address, and if there is no more continuity of the address, generate and output the address according to the access request held until then,
M was controlled.

As a result, the SDRAM interface circuit controls the SDRAM in place of the control device.
By reducing the load on the DSP and the like, programmers and circuit designers can escape from complicated SDRAM control.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, in order to achieve the above object, the present invention provides an SD card for connecting a control device to an SDRAM.
A RAM interface circuit, comprising: a plurality of address buffer means for storing a read address input from the control device; a determining means for determining continuity of the read address stored in the plurality of address buffer means; When it is determined that there is no more continuity in the read address, a command generating means for generating and outputting a read command with the first read address stored in the plurality of address buffer means as a start address so far, In response to the read command,
An SD comprising: a plurality of data buffer means for storing read data input from a DRAM; and a read data output means for outputting the read data stored in the plurality of data buffer means to the control device.
A RAM interface circuit is provided.

According to the present invention, with this configuration, even if there is no special command from the control device, the continuity of the address is determined by itself, a read command is generated and output at an appropriate timing, and the read data input from the SDRAM is output. Is appropriately output to the control device, so that the control device need not generate a read command to the SDRAM.

Further, in the present invention, there is further provided a read counter means for counting a read access from the control device, and the command generation means is configured to determine the optimum burst value for the count value based on the count value of the read counter means and the burst length of the SDRAM. A command for determining the length and changing the length may be generated and output.

With this configuration, even if there is no special command from the control device, the optimum burst length can be obtained and the SDRAM can be obtained.
The controller changes the burst length of the SDRAM.
It is not necessary to generate a mode set command to the CAM.

Further, in the present invention, a read counter means for counting read accesses from a control device, and when read data exceeding the count value of the read counter means is input from the SDRAM, the read data is transferred to a plurality of data buffer means. And input control means for discarding without saving the information.

With this configuration, even if there is no special command from the control device, the deviation between the number of data required by the control device and the burst length is adjusted, and only the necessary read data is output to the control device. The device does not need to perform unnecessary truncation of read data.

Secondly, the present invention provides an SDRAM interface circuit for connecting a control device to an SDRAM, wherein the write data and the write address inputted from the control device are stored. A plurality of buffer means, and determination means for determining the continuity of the write address stored in the plurality of buffer means,
A command generating unit that generates and outputs a write command having a first write address stored in the plurality of buffer units as a start address up to which the determining unit determines that the write address has no further continuity; And a write data output means for sequentially outputting the write data stored in the plurality of buffer means at a predetermined timing after the output of the write command.

According to the present invention, with this configuration, even if there is no special command from the control device, the continuity of the address is determined by itself, a write command is generated and output at an appropriate timing, and the write data is appropriately output to the SDRAM. So
The control device does not need to generate a write command to the SDRAM.

The present invention may further comprise a write counter means for counting write accesses from the control device, and the command generation means may determine an optimum burst for the count value from the count value of the write counter means and the burst length of the SDRAM. A command for determining the length and changing the length may be generated and output.

With this configuration, even if there is no special command from the control device, the optimum burst length is obtained and the SDRA
The controller changes the burst length of M.
There is no need to generate a mode set command for M.

Further, in the present invention, write counter means for counting write accesses from a control device, and output control for masking output of write data from a buffer means for storing write data exceeding a count value of the write counter means. Means may be further provided.

With this configuration, even if there is no special command from the control device, the deviation between the number of data to be written by the control device and the burst length is adjusted, and unintended write data is transmitted to the S.
Since the data is not output to the DRAM, the control device can output the write data without considering such a situation.

In the first and second aspects of the present invention, the apparatus further comprises a refresh cycle counting means for measuring an interval of the refresh timing by itself and notifying the command generating means of the refresh timing. If so, a refresh command may be generated and output to cause the SDRAM to execute the refresh.

With this configuration, even if there is no special command from the control device, the SD memory card can be read at appropriate refresh timing.
Since a refresh command is generated and output to the RAM,
The control unit can use the SDRA
There is no problem even if an access request is made to M.

In the first and second aspects of the present invention, S
The information processing apparatus may further include setting holding means for holding setting contents of the mode register of the DRAM, and the command generating means may generate and output a mode set command according to the setting contents to set the mode register.

With this configuration, even if there is no special command from the control device, the mode set command is generated and output to the SDRAM at the time of startup.
There is no need to perform control for setting the mode of the DRAM. Also, by setting the setting contents from the control device, the command register of the SDRAM can be appropriately set and changed.

In the first and second aspects of the present invention, it is determined whether or not address carry-over is ignored in an addressing sequence in an SDRAM based on an input address from a control device, and address carry-over is ignored. In this case, the apparatus may further include a command regeneration determination unit that instructs the command generation unit to regenerate a command.

With this configuration, the inconvenience that the carry-over of the address is ignored in the SDRAM and the control device reads / writes data at an unintended address is avoided.
Since the processing is canceled without a special command from the control device, the control device does not need to consider ignoring the carry-up of the address when making an access request to the SDRAM.

Third, the present invention provides an SDRAM control method for controlling an SDRAM based on a signal from a control device, wherein the read address input from the control device is stored. Judging the continuity of the stored read address, and generating a read command with the first read address stored up to the start address when the judging means judges that the read address is no longer continuous. And outputting the read data input from the SDRAM to the control device in response to the read command.

According to the present invention, even if there is no special command from the control device, the present invention determines the continuity of the address, generates and outputs a read command at an appropriate timing, and controls the read data input from the SDRAM. Since the data is appropriately output to the device, the control device does not need to generate a read command to the SDRAM or the like.

In the present invention, the number of read accesses from the control device is counted, and the counted value and SD
The optimum burst length for the count value may be obtained from the burst length of the RAM, and a command for changing the burst length may be generated and output.

According to this method, even if there is no special command from the control device, the optimum burst length is obtained, and the SDRA
The controller changes the burst length of M.
There is no need to generate a mode set command for M.

In the present invention, read accesses from the control device are counted, and when read data exceeding the count value is input from the SDRAM, the read data is discarded without being stored in a plurality of data buffer means. Is also good.

According to this method, even if there is no special command from the control device, the deviation between the number of data required by the control device and the burst length is adjusted, and only the necessary read data is output to the control device. The device does not need to perform unnecessary truncation of read data.

Fourth, the present invention provides an SDRAM control method for controlling an SDRAM based on a signal from a control device, in order to achieve the above object. The address is stored, the continuity of the stored write address is determined, and if it is determined that the write address has no further continuity, a write command having the first write address stored up to that start address is generated. And outputting the stored write data in sequence at a predetermined timing after the output of the write command.

According to the present invention, according to the method, even if there is no special command from the control device, the continuity of the address is determined by itself, a write command is generated and output at an appropriate timing, and the write data is appropriately output to the SDRAM. So
The control device does not need to generate a write command to the SDRAM.

In the present invention, the number of write accesses from the control device is counted, and the count value and SD
The optimum burst length for the count value may be obtained from the burst length of the RAM, and a command for changing the burst length may be generated and output.

According to this method, even if there is no special command from the control device, the optimum burst length is obtained, and the SDRA
The controller changes the burst length of M.
There is no need to generate a mode set command for M.

In the present invention, the number of write accesses from the control device may be counted, and the output of write data exceeding the count value may be masked.

According to this method, even if there is no special command from the control device, the deviation between the number of data to be written by the control device and the burst length is adjusted, and unintended write data is transmitted to the S.
Since the data is not output to the DRAM, the control device can output the write data without considering such a situation.

In the third and fourth aspects, the refresh timing interval may be measured by itself, and a refresh command may be generated and output at the refresh timing to cause the SDRAM to execute the refresh.

According to this method, even if there is no special command from the control device, SD can be performed at an appropriate refresh timing.
Since a refresh command is generated and output to the RAM,
The control unit can use the SDRA
There is no problem even if an access request is made to M.

In the third and fourth aspects of the present invention, S
The setting contents of the mode register of the DRAM may be held, and a mode set command may be generated and output according to the setting contents to set the mode register.

According to this method, even if there is no special command from the control device, the mode set command is generated and output to the SDRAM at the time of startup.
There is no need to perform control for setting the mode of the DRAM. Further, by setting the setting contents from the control device, the command register of the SDRAM can be set and changed as appropriate.

In the third and fourth aspects of the present invention, it is determined whether or not address carry-over is ignored in an addressing sequence in an SDRAM based on an input address from a control device, and address carry-over is ignored. In such a case, the command may be regenerated and output.

According to this method, the inconvenience that the carry-over of the address is ignored in the SDRAM and the control device reads / writes data at an unintended address is avoided.
Since the processing is canceled without a special command from the control device, the control device does not need to consider ignoring the carry-up of the address when making an access request to the SDRAM.

Fifthly, in order to achieve the above object, according to the present invention, image data read by scanning an original image and a scanning position corresponding to the image data are sequentially inputted, and SDRAM based on the image data
An image processing apparatus that detects a positional shift of the scanning position from the image data and the stored data stored in the SDRAM in an overlapped scanning area that performs overlapping scanning, and corrects the positional shift. A displacement detection unit that outputs a correction value to be corrected, a correction unit that corrects the scanning position based on the correction value, and a mapping unit that stores the image data in the SDRAM based on the corrected scanning position.
And an SDRAM interface circuit according to the first and second aspects of the present invention for connecting the SDRAM with the misalignment correcting means and / or the mapping means.

The present invention provides an SDRAM having such a configuration.
As described in the first and second aspects of the present invention, the interface circuit generates and outputs a command conforming to the SDRAM specifications without a special command from the displacement correcting means and / or the mapping means, and outputs the SDRAM. Under the control, the image data is read / written to / from the SDRAM.
There is no need to generate a read command, a write command, a refresh command, etc. for the SDRAM.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows an SDRAM interface circuit and a DSP according to Embodiment 1 of the present invention.
FIG. 3 is a block diagram showing a relationship between the SDRAM and the SDRAM.

The DSP 100 has an output configuration for connection to a general SRAM. That is, it has pins for outputting or inputting address signals, write signals, read signals, data signals, and status signals.

The DSP 100 and the SDRAM interface circuit 200 are connected by a signal line (hereinafter, referred to as a DSP-side signal line) 101. The DSP-side signal line 101 includes an address line 102, a data bus 103, a write signal line (WT) 104, and a read signal line (RD) 10.
5, a status signal line (STU) 106 and a clock signal line (CLK) 107 are included.

On the other hand, the SDRAM interface circuit 2
00 and the SDRAM 300 are connected to a signal line (hereinafter, SDRA).
(Referred to as an M-side signal line) 201. This SD
The RAM side signal line 201 includes an address line 202, a data bus 203, a chip select signal line (NCS) 204,
Write signal line (NWT) 205, row address strobe signal line (NRAS) 206, column address strobe signal line (NCAS) 207, output disable / write mask signal line (UDQM, LDQM) 20
8, 209 and a clock signal line (CLK) 210.

Here, output disable / write mask signal lines (UDQM, LDQM) 208, 209
Is used as an output control signal in a read cycle, and is used to mask input data in a write cycle. For example, when DQM is high at the rising edge of the clock signal (CLK), data output at the next CLK edge is disabled in the read cycle,
In the write cycle, input data of the cycle is masked. In this example, byte data control is enabled by UDQM and LDQM.

FIGS. 2 and 3 show the signal line 101 on the DSP side.
FIG. 4 is a diagram showing a timing chart for the SDRAM side signal line 201, respectively. On the DSP 100 side, it is the same as a general SRAM. That is, for example, at the time of writing, the DSP 100 activates the write signal (Low level in this example) and sends out the address signal and the data signal. At the time of reading, the read signal is activated, an address signal is transmitted, and a data signal is received.

On the other hand, on the SDRAM 300 side, the DSP 1
Data read / write is performed in synchronization with a clock signal input from 00. For example, SDRAM 300
When the chip selector signal (NCS) is activated, the SDRAM 3 is activated at the rising edge of the clock signal.
00 is designed to take in a command.

In a write cycle, when a write command is input after a lapse of a predetermined time from a bank active command, data is continuously input in synchronization with a rising edge of a clock signal. More specifically, as shown in FIG. 3, NCS = Low, NRAS = Low, NCAS
= High and NWT = High, the contents of these settings are fetched at the rising edge A of the clock signal, whereby the bank active command is selected and the bank selected by BS becomes active. A few clocks later, NCS = Low, NRAS = High
When h, NCAS = Low, and NWT = Low, the contents of these settings are captured at the next rising edge B of the clock signal, thereby selecting a write command, starting column access, and inputting data.

On the other hand, in the read cycle, the bank is activated by executing a bank active command for an idle bank, and when a read command is input after a lapse of a predetermined time, the SDRAM 300 is synchronized with the rising edge of the clock signal. Data is output continuously. More specifically, as shown in FIG. 3, first, NCS = Low, NRAS = Low, NCAS = H
When high and NWT are set to High, the contents of these settings are SDR at the rising edge C of the clock signal.
The bank active command is selected by the AM 300, whereby the bank selected by the BS is activated. After a few clocks, NCS = Low, NRAS
= High, NCAS = Low, and NWT = High, these settings are fetched at the rising edge D of the next clock signal, thereby selecting a write command, starting column access, and performing SDRA.
Data is output from M300.

As described above, the signal on the DSP side and the SDRAM
The SDRAM interface circuit 200 interprets the signal from the DSP 100, generates a command and inputs the command to the SDRAM 300, inputs data to the SDRAM 300 at an appropriate timing, It is necessary to perform control such as outputting to

FIG. 4 shows SDRA according to the first embodiment.
FIG. 3 is a block diagram illustrating an internal configuration of an M interface circuit. The SDRAM interface circuit 200 includes a transmission data buffer 500, a reception data buffer 700, a command control block 800, and an input / output selector 900.
It is composed of

FIG. 5 is a diagram showing the SDRA according to the first embodiment.
FIG. 3 is a block diagram illustrating an internal configuration of a transmission data buffer of the M interface circuit. Transmission data buffer 500
Is a circuit for temporarily storing data to be written (hereinafter referred to as write data) and an address to be written (hereinafter referred to as a write address) from the DSP 100 during transmission, that is, during a write operation. The transmission data buffer 500 mainly includes a buffer block 501 having eight buffers 1 to 8, a write counter 502, a write selector 503, an address selector 504, and an output counter 505.

The write counter 502 increments by one when it receives one write signal from the DSP 100. Then, data and a write address are input to buffers 1 to 8 corresponding to the count value. As a result, the write data and the write address output from the DSP 100 are sequentially stored in the buffers 1 to 8.

The write selector 503 is a circuit for selecting one of the buffers 1 to 8 and outputting the write data and write address stored therein to the SDRAM 300. In the first embodiment, it is necessary to selectively output an arbitrary number of write data stored in the buffers 1 to 8 of the buffer block 501. FIG.
The input / output selector 900 shown in FIG. 4 receives data and a write address from the transmission data buffer 500 during a write operation, and inputs and outputs
Since data and a write address are input from 00, it is necessary to prevent data collision. Therefore, an output counter 505 is connected to the write selector 503, and the output from the transmission data buffer 500 is controlled using an output enable signal output from the command control block 800.

More specifically, the output enable signal is activated when outputting data from the transmission data buffer 500 during a write operation. The amount (time) of activating the output enable signal in accordance with the amount of data output from the transmission data buffer 500
Lengthen. The output counter 505 measures the amount of active output enable signal in synchronization with the clock. More specifically, the output counter 505 detects the falling edge of the output enable signal (active when the output enable signal is low), counts one, and thereafter counts the counter value every one clock if the output enable signal is active. Is incremented by one. As a result, the write selector 503 selects a buffer corresponding to the count value of the output counter 505 from the buffers 1 to 8, and outputs the write data and the write address stored therein. As a result, an arbitrary number of data and write addresses stored in the buffers 1 to 8 can be sequentially output from the buffer 1 at an arbitrary timing.

The write address output from the write selector 503 is input to the address selector 504. The address selector 504 uses the DSP 100 and the SDR
The difference in the number of address signal lines of the AM 300 is matched. FIG. 6 is a block diagram showing the internal configuration of the address selector of the transmission data buffer according to the first embodiment.

In this example, the address signal lines from the DSP 100 are 24 MA [0] to MA [23].
A logical address space is represented by a 24-bit address. On the other hand, the pin configuration of the chip configuring the SDRAM 300 includes one chip select (CS), bank selectors (BS0 and BS1), and address inputs (A0 to A11) 1.
There are two. Also, the address A0 is input to the row address input.
To A11 are always used, and eight of A0 to A7, A0 to A7 are used for column address input depending on chip specifications.
Either 9 of 8 or 10 of A0 to A9 are used. Accordingly, of the input address from the DSP 100, the lowest 8 to 10 bits are allocated to the column address, and the upper 12 bits are allocated to the row address. The order of the column address and the row address may be reversed.

Since SDRAM 300 of this example has a four-bank configuration, two bank select signals BS0 and BS0 are provided.
1 is used to indicate which bank of BANKs 1 to 4 is accessed. Therefore, the upper two bits of the row address of the input address are assigned to the bank select.

Further, when the SDRAM 300 is composed of a plurality of chips, it is necessary to specify which chip is to be accessed, and the chip select (C
S) is used. Therefore, 0 bits for one chip, 1 bit for two chips, and 2 bits for four chips are assigned to the highest order of the input address. The address selector 504 shown in FIG. 6 is a circuit configured to generate an output address from such an input address.

Specifically, in the address selector 504, two of the 24 address lines are sequentially assigned to the CS selector 601, two to the BS selector 602, twelve to the row address selector 603, and There are cases where eight lines are respectively distributed to column addresses 604,
This will be described as an example. In this example, the SDRAM 300
Has a total capacity of 256 MBit and 64 chips per chip.
This is when four SDRAM chips having a storage capacity of MBit are combined.

The CS selector 601 generates a CS signal from the upper two digits of the input address and inputs the CS signal to the pin <NCS> of the SDRAM 300. The CS signal is used to specify a chip to which data is to be written when the memory is composed of a plurality of SDRAM chips.

In the BS selector 602, B is calculated from the next two digits.
An S signal is generated and input to pin <BS> of SDRAM 300. When the SDRAM 300 has a bank configuration, the BS signal is used to specify a bank to which data is to be written.

In the row address selector 603, the following 1
A row address is generated from two digits. Similarly, the column address selector 604 generates a column address from the next eight digits. The output destination of the row address selector 603 and the column address selector 604 is
A column selector 605 is provided. SDRAM3
Since the address input of 00 is shared by the row address and the column address, it is necessary to select whether to input a row address or a column address. Therefore, the row / column selector 605 selectively outputs a row address and a column address to the SDRAM 300 according to RAS and CAS output from a command control block 800 described later. The circuit of the address selector 504 described here is only an example, and the SDRAM 30
Needless to say, it is appropriately changed according to the specification of 0.

In the transmission data buffer 500 described above, the number of buffers in the buffer block 501 is
This corresponds to the maximum burst length of the SDRAM 300. In this example, since the maximum burst length of the SDRAM 300 is “8”, eight buffers 1 to 8 are provided. This is because, in a write cycle, write data of a burst length is continuously output to the SDRAM 300 in synchronization with CLK in a write cycle, so that the write data and write address of the maximum burst length are stored in the buffer block 501.
Because it is necessary to save it.

Next, the reception data buffer 700 will be described. FIG. 7 is an SDRAM according to the first embodiment.
FIG. 3 is a block diagram illustrating an internal configuration of a reception data buffer of the interface circuit.

The reception data buffer 700 temporarily stores an address to be read from the DSP 100 (hereinafter, referred to as a read address) at the time of reception, that is, a read operation, and data read from the SDRAM 300 (hereinafter, referred to as read data). Is a circuit for temporarily storing a pair with a read address.

The reception data buffer 700 mainly includes a buffer block 701 having eight buffers 1 to 8, a read counter 702, a read request selector 703, a readout selector 704, and an address selector 705. Here, the number of buffers corresponds to the maximum burst length of SDRAM 300 as in transmission data buffer 500.

The read counter 702 provided on the input side of the buffer block 701 increments the count value by one when it receives one read signal from the DSP 100. Then, the read address is stored in the buffers 1 to 8 corresponding to the count value. Thereby, buffers 1 to
The read addresses are sequentially stored in 8.

The read request selector 703 provided on the output side of the buffer block 701 selects one of the buffers 1 to 8 and sets the read address stored therein to SD.
This is a circuit for outputting to the RAM 300.

As with the transmission data buffer 500 described above, an input counter 706 is connected to control the output of the read request selector 703. The input counter 706 controls the command control block 80
It measures the amount by which the input enable signal output from 0 is active and outputs a count value. The read request selector 703 selects a buffer corresponding to the count value of the input counter 706 from the buffers 1 to 8, and outputs a read address stored in the buffer. The write address stored in any one of the buffers 1 to 8 can be output at an arbitrary timing.

The read address output from the read request selector 703 is input to the address selector 705 and is converted into information that can be received and recognized by the SDRAM 300. The address selector 705 has the same configuration as the address selector 504 shown in FIG.

On the other hand, read data transmitted from SDRAM 300 is stored in buffers 1 to 3 of buffer block 701.
8 in turn. More specifically, the read data is input to all the buffers 1 to 8 in parallel. on the other hand,
Input enable signals from the input counter 706 are separately input to the buffers 1 to 8. The buffers 1 to 8 permit data input only when the input enable signal is active (Low in this example). The command control block 800 activates the input enable signal for only one of the buffers 1 to 8. Thus, the read data from SDRAM 300 can be stored in an arbitrary buffer.

On the output side of the buffer block 701, a readout selector 704 is provided. The readout selector 704 selects one of the buffers 1 to 8 according to the output of the read counter 702 and outputs the read data stored therein to the DSP 100.

The operation of the read cycle of the DSP 100 will be described in further detail. First, the DSP 100 confirms by status that there is no data that has not been read as valid data, activates the read signal, and transmits a read address at the same time. (Hereinafter, this operation is called read access). The SDRAM interface circuit 200 stores the read address as described above, generates a command and outputs the command to the SDRAM 300,
The read data returned by M300 is stored. DSP10
In the case of 0, the status is confirmed again, the data is recognized as valid data, and read access is performed. In response to the read access, the read data stored in the SDRAM interface circuit 200 is output. Thus, DS
P100 can read the read data starting with the second read access, with the first read access as the read request. At this time, since the operation speed of the DSP 100 is much lower than the operation speed of the SDRAM 300, the operation on the SDRAM side is completed between the first and second times.

Note that the DSP 100 and the CPU execute the above read access, but the JPEG-IC circuit of the image scanner described later does not perform the read access. You need to generate an address.

Next, the command control block 800 will be described with reference to FIG. FIG. 8 shows the first embodiment.
FIG. 2 is a block diagram showing an internal configuration of a command control block according to FIG.

The command control block 800 includes an access counter 801, a command register 802, a comparison block 803, a refresh cycle (RC) count block 804, and a command generation block 805.

One characteristic of the SDRAM 300 is that it continuously reads / writes data having continuous addresses. However, since the DSP 100 performs read / write without considering the specifications of the SDRAM 300, the DSP 100
The SDRAM interface circuit 200 needs to check the read / write continuity instead of the SP 100.

The SDRAM 300 needs to be refreshed every unit time, but the DSP 100 does not operate in consideration of the refresh. So, SDRAM
The interface circuit 200 must measure the time and instruct the SDRAM 300 to refresh for a predetermined period. Since read / write cannot be performed at the time of refresh, it is necessary to determine read / write execution timing.

Access counter 801 counts the number of accesses of both the read signal and the write signal, and outputs the value as the number of valid data. Comparison block 803
Temporarily stores a write address and a read address input from the DSP 100 at the time of reading and writing, compares them with the next input address, and outputs a command generation pulse if the address is non-consecutive as a result. It has become. Further, it stores whether the signal accessed last time is a write signal or a read signal, and outputs a command generation pulse when switching from a read signal to a write signal or from a write signal to a read signal. In other words, the comparison block 803 determines D
The SP 100 is configured to detect that data with consecutive addresses is being read / written.

In the RC count block 804, the DSP 100 sets the interval according to the clock frequency and measures the refresh interval. Then, the RC count block 804 outputs a refresh start pulse when a refresh timing comes. In addition, a predetermined period including a refresh timing (hereinafter, referred to as a refresh cycle) is defined as an access counter 80.
1. A refresh cycle signal to be notified to the command register 802 and the comparison block 803 is output. For example,
The refresh cycle signal becomes active when the refresh cycle starts, and becomes inactive when the refresh cycle ends.

The command register 802 stores the SDRAM3
This is a circuit for setting a mode register of 00. The command register 802 holds the default mode set data, and outputs the default mode set data at startup. Also, the command register 802 stores the DS
When a mode setting is requested from P100,
The mode set data is generated and output according to this request.

The command generation block 805 generates a command for controlling the SDRAM 300 according to the output of the access counter 801, the comparison block 803, the RC count block 804, and the command register 802.
This is a circuit for outputting to the SDRAM 300. In addition, the command generation block 805, as shown in FIG.
It is connected to M300 via an external control line 806 and to the transmission data buffer 500, the reception data buffer 700 and the input / output selector 900 via an internal control line 807. The operation of the command generation block 805 will be described later.

Next, the input / output selector 900 shown in FIG.
This will be described with reference to FIG. FIG. 9 is a block diagram showing a selector of the SDRAM interface circuit according to the first embodiment.

The input / output selector 900 is a circuit for appropriately selecting a signal for accessing the SDRAM 300 from signals output from the transmission data buffer 500, the reception data buffer 700, the command control block 800, and the RC count block 804. The selection of the input / output selector 900 is performed according to the cycle information from the command generation block 805.

A description will be given of refresh, mode set, read and write operations in SDRAM interface circuit 200 according to the first embodiment having the above-described configuration.

<Refresh> As described above, the RC count block 804 sets the DS according to the frequency of the clock.
P100 sets the interval, measures the refresh interval,
When the refresh timing comes, a refresh start pulse is output to the command generation block 805. In response, command generation block 805 outputs a refresh command to SDRAM 300. Thus, the SDRAM interface circuit 200 includes the DSP
Even if there is no special command from 100, the SDRAM 300 can autonomously execute the refresh.

Further, the RC count block 804
Since the start of the refresh is notified to the comparison block 803 and the like before the timing of the refresh by the refresh cycle signal, the comparison block 803 can complete the read / write before the refresh. As a result, the refresh can be performed with the highest priority.

<Mode Set> According to the SDRAM interface circuit 200, at the time of startup, the command register 802 outputs the held default mode set data to the command generation block 805. The mode set data held by the command register 802 can be set from the DSP 100. Also in this case, the command register 802 outputs the set mode set data to the command generation block 805.
The command generation block 805 generates a mode set command according to the input mode set data,
Input to RAM 300. Thereby, the SDRAM 30
The setting is made to the mode selector of 0. Where SDR
The setting contents of the mode selector of the AM 300 are, for example, burst length, address mode, CAS latency, and the like.

More specifically, the SDRAM interface circuit 200 first transmits an all-bank precharge command to the SDRAM 300 to make all the banks idle. With this, SDR
The mode setting of the AM 300 is enabled. Next, a mode set command is transmitted, and an auto-refresh command is transmitted eight times after two clock cycles.
0 is an idle state.

As described above, according to the SDRAM interface circuit 200, even if there is no special command from the DSP 100 at the time of start-up, the SDRAM interface circuit 200 follows the default mode set data held by the command register 802.
300 mode sets can be performed. Also, the mode set can be performed directly from the DSP 100 as needed.

<Read> During the read operation, the DSP 100
Performs a read access by activating a read signal and outputting a read address, as shown in FIG. The DSP 100 repeats read access for the required address.

In the SDRAM interface circuit 200, the read addresses from the DSP 100 are sequentially stored in the buffers 1 to 8 of the buffer block 701 of the reception data buffer 700.

At the same time, in the command control block 800, the access counter 801 counts read signal accesses. The command control block 800 recognizes how many read data the DSP 100 requests. That is, the comparison block 803 is
The read address is held for each read access, and the read address is compared with the read address received in the next read access to determine whether or not both are continuous.
If both are continuous, it is determined that the read data has continuity, and a read access is subsequently received. But,
If both are not continuous, it is determined that the read data has no further continuity, and the command generation block 805 is determined.
Output a command generation pulse. Further, the comparison block 803 holds the type of read / write for each access, and outputs a command generation pulse to the command generation block 805 also when switching from read to write at the next access.

When a command generation pulse is input, the command generation block 805 uses the read address specified by the first read access (the read address stored in the buffer 1) as a start address and executes a read cycle as shown in FIG. Execute In response, SDR
The read data corresponding to the burst set in the mode register is returned from the AM 300. The read data is sequentially stored in the buffers 1 to 8 corresponding to the read address.

However, in practice, there is a difference between the number of words of the read data required by the DSP 100 and the number of words of the read data output by the SDRAM 300.

First, the command generation block 805 includes:
The number of valid data at the time when the command generation pulse is input is compared with the burst length set in the mode selector of SDRAM 300, and it is determined whether or not the burst length is optimal. The set burst length is stored in command register 8
02 is obtained as burst information. If the set burst length is not the optimum burst length for the number of valid data, a mode set command is generated in accordance with the operation of <mode set> and output to SDRAM 300.
As a result, the burst length of the SDRAM 300 is changed to the optimum burst length.

Here, the optimum burst length is a burst length that is equal to or larger than the number of valid data and is closest to the number of valid data. Normally, the burst length is a multiple of 1 and 2, such as 1, 2, 4, and 8. Therefore, for example, if the number of valid data is 3 words, the optimal burst length is 4.

Second, the number of valid data and the SDRAM 300
May not match the burst length (the number of words of read data). In such a case, the SDRAM interface circuit 200 needs to cut off excess read data. This control is based on the reception data buffer 7 described above.
This is performed by using the input enable signal described with reference to FIG. The read data having the burst length is received from the SDRAM 300. Read data into buffer block 701
The buffer 1 is sequentially stored from the buffer 1, and when the number of valid data exceeds the number of valid data, the input enable signal is made inactive for all the buffers 1 to 8, so that the storage of the read data is restricted.

After that, in response to the second read access from the DSP 100, the reception data buffer 700 reads the read data stored in the buffer block 701.

More specifically, when the number of words requested by the DSP 100 is three and the burst length of the SDRAM 300 is four, four words of read data are output from the SDRAM 300, but only three words of the receive data buffer 700 are output. To save. Thereafter, the DSP 100 can read three words of read data from the reception data buffer 700 without delay.

Thus, the SDR according to the first embodiment
According to the AM interface circuit 200, the DSP 10
Without a special command from the 0 side, the burst length of the SDRAM 300 can be appropriately changed, and the excess of read data from the SDRAM 300 can be cut off.

In the above description, SDRAM interface circuit 200 executes a read cycle for SDRAM 300 when read access continuity is lost, but the refresh cycle is performed in accordance with the refresh cycle signal from RC count block 804. At the start, a read cycle is performed on SDRAM 300. This allows the SDRAM 300 to execute the refresh with priority over the read.

<Write> During the write operation, the DSP 100
As shown in FIG. 2, write access is performed by activating a write signal and outputting write data and a write address. The DSP 100 repeats the write access by the number of words of the write data.

In the SDRAM interface circuit 200, the write data and the write address from the DSP 100 are sequentially stored in the buffers 1 to 8 of the buffer block 501 of the transmission data buffer 500.

At the same time, the command control block 800 recognizes the number of words of write data to be written by the DSP 100. That is, the access counter 801 counts the number of write accesses, and outputs the value as the number of valid data. The comparison block 803 holds the write address for each write access, compares the write address with the write address received at the next write access, and if both are continuous, receives the write access continuously. However, if both are not continuous, it is determined that the write data has no further continuity, and a command generation pulse is output to the command generation block 805.

The comparison block 803 holds the type of read / write for each access, determines that there is no continuity in the write data even when switching from write to read at the next access, and issues a command generation block. 805
Output a command generation pulse.

When a command generation pulse is input, the command generation block 805 uses the write address specified in the first write access (the write address stored in the buffer 1) as a start address and executes a write cycle as shown in FIG. Execute

As in the read operation, the burst length is checked for conformity, and the write data is masked. That is, the command generation block 805 determines the number of valid data at the time of input of the command generation pulse and the SDRAM
A comparison is made with the burst length set to 300 to determine whether or not the burst length is optimal. The criterion is the same as that of the lead.

If the burst length is not optimal, a mode set command is generated in accordance with the operation of <mode set> to change the burst length to the optimal burst length.
Output to 00. Then, the command generation block 805
Performs a write cycle. On the other hand, if the burst length is appropriate, the write cycle is executed without performing the mode set.

In the write cycle, there is a difference between the number of valid data of the write data and the burst length. That is, in the write cycle,
The transmission data buffer 500 shown in FIG.
8 write data stored in SDRA by burst
Output to M300 sequentially. However, DSP100
Needs to output only the write data requested to be written, the transmission data buffer 500 masks data output from buffers exceeding the number of valid data.

More specifically, when the burst length is 8
When the number of valid data is 7, the write data is stored in the buffers 1 to 7 of the transmission data buffer 500. Therefore, the transmission data buffer 500
The write data of the 7th word to the 7th word are sequentially output. Since the 8th word, in other words, the data stored in the buffer 8 is invalid, the output of this data is masked.

The masking of the data output is performed by using the above-mentioned output enable signal. That is, when writing in the burst mode, write data of a burst length is continuously output to the SDRAM 300 as shown in FIG. 3, but at the timing when write data to be masked is output, all of the buffers 1 to 8 are written. The output enable signal is made non-active. Thus, data output to SDRAM 300 at this timing can be masked.

As described above, according to the SDRAM interface circuit 200, the continuity of the write address of the write data is recognized at the time of writing without receiving a special command from the DSP 100, and the number of valid data of the continuous write data is determined. SDRAM 30 with optimal burst length
Writing to 0 can be performed.

Similarly to the read operation, when the refresh cycle starts in accordance with the refresh cycle signal from RC count block 804, SDRAM 300
Execute a write cycle. Thereby, SD
It is possible to cause the RAM 300 to execute the refresh with priority over the write.

<Command Generation> The operation of the command generation block 805 for generating commands in <refresh>, <mode set>, <read>, and <write> described above will be described in further detail. FIG. 10 is a flowchart showing the operation of the command generation block according to the first embodiment.

The command generation block 805 releases the reset (step (hereinafter referred to as ST) 100
1) Wait for an access request to the SDRAM 300 from the DSP 100 (ST1002). Next, it is determined whether or not refresh is to be performed (whether or not a refresh cycle is being performed) (ST1003). This determination is made using RC as described above.
This is performed based on the refresh cycle signal from the count block 804. If the refresh is not executed, the read / write continuity is determined (ST100).
4). If there is continuity, suspend the access request and ST
It returns to 1002 and waits for the next access request. On the other hand, if there is no read / write continuity, a command is generated in accordance with the access request suspended up to that point (ST100).
5). Here, the suspension of the access request means, for example, that the write data and the write address are stored in the transmission data buffer 500 at the time of writing, and that the read address is stored in the reception data buffer 700 at the time of reading, as described above. Say.

On the other hand, when refreshing is performed in ST1003, it is determined whether there is an access request suspended up to that point (ST1006). If there is a suspended access request, a command is generated according to the suspended access request before refreshing (ST1).
007), and then execute a refresh (ST100)
8). If there is no pending access request up to that point, the refresh is executed as it is (ST1008). After the execution of the refresh, to wait for the next access request, the ST
Return to 1002.

Thus, the command generation block 805
Determines in ST1004 whether the read / write continuity from the DSP 100 is continuous, that is, whether the read address and the write address from the DSP 100 are continuous. Then, a command is generated according to the data held so far, and the SDRAM 300 is accessed. This allows the command generation block 805 to use the SDRAM without the DSP 100 performing special control.
Generate a command that meets the specifications of the SDRAM3
00 to read / write.

Further, the command generation block 805
Since it is determined at T1003 whether to execute the refresh before other processes, the refresh can always be performed prior to the read / write. Also, when performing a refresh, it is checked in ST1006 whether there is an address request held up to that time,
If there is, read / write is executed for SDRAM 300. Thus, it is possible to respond to the command request of the DSP 100 as soon as possible while giving priority to the refresh.

At the end of the refresh cycle,
In other words, at the timing when the refresh cycle signal switches from active to non-active, the transmission data buffer 500, the reception data buffer 700, and the comparison block 803 perform a soft reset to clear the buffers and counters, and to perform subsequent access requests from the DSP 100. Respond to

In addition, when the read / write access reaches the maximum burst length, even if the address has continuity, it responds to the command request suspended so far.

<Regeneration of Command> Next, regeneration of an address will be described. In the read / write cycle, the SDRAM 300 starts reading from the input start address and performs reading / writing on sequentially incremented addresses. At this time, SDRA
Due to the specifications of M300, different digits depend on the burst length
CARRY is now ignored. Specifically, in the sequential mode, when the burst length is 2 words, the CARRY from A0 to A1 is ignored. When the burst length is 4 words, CARRY from A1 to A2 is ignored. When the burst length is 8 words, CARRY from A2 to A3 is ignored. In such a case, DS
Address requested for access from P100 and SDRAM
There is a discrepancy between the address at which 300 reads and writes.

A specific description will be given with reference to FIG. FIG.
FIG. 1 is a diagram showing an example of an addressing sequence in the SDRAM in the sequential mode. In the sequential mode, when a read request is issued to the SDRAM 300 by designating address 5 as a start address, data is sequentially output in the order of data 0, 1, 2,... While incrementing the address from address 5 (“00101”) by one.
However, as described above, in the case of 8 bursts, the CARRY from A2 to A3 bits is ignored, so address 7 ("0")
After “0111”), the address returns to address 0 (“00000”) instead of address 8 (“01000”), and such a state is referred to as “ignore address carry”.

To ignore the carry of this address,
In the DSP 100, even if it is requested to read data of 8 words continuously from the address 5 to the address 12, the DSP 100
Data of addresses 5 to 7 and 0 to 4 are returned from M300. Therefore, the SDRAM interface circuit 200 includes the DSP 100 and the SDRAM
An adjustment between 300 and 300 is required.

FIG. 12 shows an SDR according to the first embodiment.
FIG. 3 is a block diagram illustrating an internal configuration of a command regeneration block in the AM interface circuit. The selector 1201 of the command regeneration block 1200 includes DSP1
Lower 3 bits of the address input from address 00
[0] to MA [2] are input. Further, burst information is input from the command register 802 shown in FIG.
The selector 1201 uses the SDRAM 30 from the burst information.
The burst length currently set to 0 is obtained, and the output to the determination unit 1202 is changed according to this.

FIG. 13 shows an SDR according to the first embodiment.
FIG. 4 is a diagram illustrating an operation of a selector of a command regeneration block of the AM interface circuit. When the burst length is 1, as shown in FIG. 13A, the selector 1201 fixes all outputs corresponding to MA [0] to MA [2] to low level (Low). When the burst length is 2, the selector 1201 outputs the address input MA [0].
Is output as it is, and the remaining MA [1], MA
[2] is fixed to L. Similarly, when the burst length is 4, only MA [2] is fixed to L as shown in FIG. 13C, and when the burst length is 8, FIG.
As shown in (D), all address inputs MA [0]
ＭＡMA [2] is output as it is.

When a signal is input from the selector 1201, the determination section 1202 outputs a command reproduction pulse to the command generation block 805 unless all signals are L. This is because if any one of the outputs from the selector 1201 is at a high level (High), address carry-over is ignored. For example, when the burst length is 1, the output of the selector 1201 is fixed at "Low" since the carry-over of the address does not occur regardless of the start address. On the other hand, when the burst length is 8, the start address is address 0 (“000”), that is, only when the outputs of MA [0] to MA [2] are all “Low”, Since carry-over is not ignored, all outputs of the selector 1201 are output to the determination unit 1202. If at least one of the outputs of MA [0] to MA [2] is “High”, the start address is 0.
Since the address is other than the address, it is determined that command regeneration is necessary.

The command generation block 805, which has received the command regeneration pulse, first designates the first input address from the DSP 100 as a start address (hereinafter, designated address), and generates the first read / write command. Output to SDRAM 300. However, after the address carry-over is ignored, data is written to an unintended address or data at an unintended address is output. Therefore, the command generation block 805 uses an output disable / write mask signal (DQM). The command generation block 805 sets DQM to High at the rising edge of CLK.
In the write cycle, the input data of the cycle is masked, and in the read cycle, the data output at the next CLK edge is disabled.

When the processing of the first read / write command is completed, a second read / write command is newly generated and output to the SDRAM 300. The designated address here (hereinafter referred to as a re-designated address) is DSP1
00 in the logical address space recognized by SDRAM
300 is the address next to the address where the carry-over of the address was ignored. Data after this address has not been read / written yet.

This redesignated address can be calculated from the designated address. Hereinafter, the calculation method will be specifically described. FIG. 14 is a diagram illustrating a method of calculating a redesignated address in the SDRAM interface circuit according to the first embodiment.

The input address from DSP 100 is MA
[23: 0], burst length is 8, designated address is x'0
Assume 0004A. This designated address is represented by a binary number as shown in FIG. FIG. 14 (B)
As shown in the figure, the SDRAM 300 reads / writes data from the designated address while incrementing the address by one, and obtains the address x'00004F (111
Since address carry-over is ignored in 1), the process returns to address x'000004 (1000). Therefore, the re-designated address is x'000050 (0000). This is the same when the designated address is other than x'000004 (1000). Therefore, the designated address M
By adding 1 to A [23: 3], the redesignated address can be calculated.

Thus, the SDR according to the first embodiment
The AM interface circuit 200 determines whether or not address carry-over is ignored in the SDRAM 300 without receiving a special command from the DSP 100. If the address carry-over is ignored, the AM interface circuit 200 regenerates an access request command. In this way, necessary read / write can be performed. As a result, the DSP 100
There is no need to consider address carry ignoring at 300.

Here, the case where the addressing sequence is the sequential mode has been described, but the same applies to the case where the addressing sequence is the interleave mode.

As described above, according to SDRAM interface circuit 200 of the first embodiment, D
Even if there is no special command from SP100, DSP1
The SDRAM 300 can be controlled by generating and outputting a command in response to an access request from 00. As a result, the DSP 100 does not need to control the SDRAM 300, so that the load can be reduced and the DSP 100 can operate at high speed. Further, when designing the DSP 100, the designer is released from the complexity of considering the specifications of the SDRAM 300, and can shorten the development period and reduce the cost.

In the first embodiment, the DSP 100 has been described as an example. However, the present invention is not limited to this. For example, the present invention can be applied to an interface between a CPU and an SDRAM. In this case, as in the case of the DSP, there is no need to control the SDRAM, so that the load can be reduced and high-speed operation can be performed. In addition, when designing software, the programmer must consider the specifications of the SDRAM. From software development, shortening the software development period and reducing costs.

(Embodiment 2) Next, Embodiment 1 is described.
A handy scanner is illustrated as an example of an electronic device equipped with the SDRAM interface circuit according to the above. The handy scanner described below employs the configuration of an image processing device disclosed in Japanese Patent Application Laid-Open No. 8-107479.

FIG. 15 is a block diagram showing a handy scanner according to Embodiment 2 of the present invention. The handy scanner 1500 includes a document reading unit 1510. The document reading unit 1510 includes a line image sensor 1511 for reading a document image, and encoder units 151 provided at both ends of the line image sensor 1511.
2 and 1513.

The original reading unit 1510 is connected to an LSI 1600 via an analog / digital converter (ADC) (not shown). LSI 1600
Processes the image data input from the line image sensor 1511 and the position data signal input from the encoder units 1512 and 1513, and processes S
DRAM 300, JPEGIC 1520, DSP 100
Functions as an interface controller between them.

The SDRAM 300 has a plurality (n) of SDs.
It is composed of a RAM chip. This SDRAM 300
Is used as a work area of the DSP 100. More specifically, the SDRAM 300 stores image data,
A memory area such as a code data storage area and a shading correction value storage area is provided.

A memory card slot 1530 is a slot for detachably connecting a memory card 1531 such as an SD memory card or a flash memory card. LCD 1540 displays image data and the like.
The USB connector 1550 is a connector for connecting a USB cable, and performs connection with an external device such as a personal computer via the USB cable.
The connection cable is not limited to USB, but IEEE 139
4. A serial cable, a parallel cable, or the like can be used.

The DSP 100 is a handy scanner 150
Controls all 0s. The ROM 1560 stores a program executed by the DSP 100. RAM 1570 contains D
Provide a working memory area and the like of the SP 100.

With such a configuration, the handy scanner 1500 compresses the image data read from the line image sensor 1511 by the JPEGIC 1520, accumulates the image data in the SDRAM 300, stores it in the memory card 1531 as necessary, and stores it in a PC or the like. hand over. Also, the read image data is displayed on LCD 1540.

FIG. 16 is a block diagram showing the internal configuration of the LSI of the handy scanner according to the second embodiment. The LSI 1600 includes a shading unit 1601, an image memory 1602, a JPEG image interface 16
03, JPEG code interface 1604, DSP
Interface 1605, control register 1606, memory card interface 1607, USB interface 1608, LCD interface 1609,
It comprises an image synthesis processing block 1610 and an SDRAM interface circuit 200.

The original is manually scanned by the original reading unit 1510 so that the line image sensor 1511 generates image data. The generated image data is digitized by the ADC and then
1600.

The input digital image data is subjected to shading correction by the shading unit 1601 in order to correct the sensitivity variation between the pixels of the line image sensor 1511. The corrected digital image data is temporarily stored on the image memory 1602. This digital image data is transmitted to a JPEG IC 15 via a JPEG image interface 1603.
20. The JPEGIC 1520 compresses the digital image data and sends it back to the LSI 1600. The returned compressed image data is input to the SDRAM interface circuit 200 via the JPEG code interface 1604. The compressed image data is stored in the SDRAM according to the <write> operation described in the first embodiment.
Written to 300. This compressed image data is written to the SDRAM 300 as it is because the address has continuity. The compressed image data stored in the SDRAM 300 is temporarily read from the SDRAM 300 prior to the image synthesis processing described later, and
The image is developed in the image storage area on the AM 300.

On the other hand, encoder units 1512 and 1513
Detects the rotation of a wheel (not shown) when the original reading unit 1510 scans over the original, detects the moving distance from this detection signal, and outputs it to the LSI 1600. This moving distance is determined by the LSI 1600 and the encoder register 16.
11 is stored for each line.

The DSP 100 adds the DSP to the LSI 1600.
Access is made via the interface 1605, and the moving distance of each wheel is read from the encoder register 1611. The DSP 100 calculates the coordinates of the wheels on the document based on the moving distance, further converts the coordinates of the wheels into the coordinates of each read pixel at both ends of the line image sensor 1511, and uses the image combining process of the LSI 1600 as the scanning position coordinates. Output to block 1610.

Next, an image synthesizing process in the handy scanner 1500 according to the second embodiment will be described. FIG.
FIG. 8 is an explanatory diagram of a scanning area of a line image sensor in the handy scanner according to the second embodiment. FIG.
As shown in FIG. 7, when the width of the reading area of the original 1701 is larger than that of the line image sensor
01, the operator operates the handy scanner 1
The document 500 is brought into contact with the document 1701 and manually scanned while reciprocating on the document 1701. At this time, as shown in FIG. 17, the forward scanning area 1702 when the handy scanner is moved in the forward direction and the backward scanning area 1703 when the handy scanner is moved in the backward direction overlap with the scanning area 1704. Occurs.

[0161] The handy scanner 1 according to the second embodiment.
At 500, the images of the forward scan area 1702 and the backward scan area 1703 are combined into one image.

For this purpose, the image synthesizing processing block 161
At 0, position deviation detection / correction and mapping processing are performed as disclosed in JP-A-8-107479. The image composition processing block 1610 is described in
It has the same function as the image shift detection circuit and the mapping circuit described in Japanese Patent No. 7479.

The image synthesis processing block 1610 densifies the image data by the pixel density conversion processing to generate high-density image data. Further, the storage address of each pixel data of the high-density image data in the image storage area on the SDRAM 300 is calculated using the scanning position coordinates.

Logically, in the overlap scanning area 1704, the pixel data of the forward scanning area 1702 already stored in the SDRAM 300 is overwritten by the pixel data of the backward scanning area 1703 which is newly drawn. However, scanning position coordinates include errors due to mechanical tolerances of the document reading unit 1510 and rounding errors in coordinate calculation. For this reason, the forward scanning area 17
When the images of 02 and the backward scanning area 1703 are combined, a shift occurs in the combined image.

To eliminate this image shift, the image synthesis processing block 1610 uses the image data of the forward scan area 1702 and the image data of the backward scan area 1703 to calculate a correlation value indicating the degree of correlation therebetween. I do. Further, the image synthesis processing block 1610 calculates a position correction amount for correcting the scanning position coordinates based on the correlation value. Further, the image synthesis processing block 1610 corrects the scanning position coordinates according to the position correction amount.

Next, an image synthesis processing block 1610
Generates a storage address of each pixel data in the image data in accordance with the corrected scanning position coordinates, specifies the storage address, and requests the SDRAM interface circuit 200 to write to the SDRAM 300. The SDRAM interface circuit 200 writes each pixel data to the designated storage address according to the procedure of <Write> described in the first embodiment.

The correction of the displacement will be described in more detail. When the backward scanning is performed, the image of the forward scanning has already been mapped and stored in the image storage area on the SDRAM 300. Based on digital image data of the forward scan read from the image storage area and newly generated high-density image data, a correlation is detected in the overlap scanning area 1704. The correlation is calculated in 9 patterns shifted ± 1 pixel up, down, left and right from the pixel of interest.
Furthermore, a position correction pixel group of a total of 27 patterns in which the angle is shifted by ± θ in each pattern is generated. The sum of the differences between the already mapped pixel data and the pixel data mapped therefrom is calculated, and the pixel having the smallest value has the highest correlation. Therefore, position correction is performed on the pixel with the highest correlation.

Thus, in this example, ± 1 from the target pixel
Since the three patterns, ie, 3 × 3 pixels, are used as a reference, the image synthesis processing block 1610 instructs the SDRAM interface circuit to read three consecutive pixels when reading the forward scan pixel data from the SDRAM 300. Request.

FIG. 18 is a diagram showing a position correction pixel group in the position shift correction processing in the handy scanner according to the second embodiment. The image composition processing block 1610 includes:
27 pixel data of the position correction pixel group 1801
In order to read from the image storage area of the M300, it is necessary to read, for example, three rows of pixel data continuous in the x-axis direction for three rows.

The image synthesis processing block 1610 corresponds to the DSP 100 in the first embodiment, and the SDRAM 30
Read access to 0 is performed. When reading three consecutive pixel data in the first row, the image synthesis processing block 1610 sets the storage address of each pixel data to the SDRAM
The signals are sequentially input to the interface circuit 200. SDRA
The M interface circuit 200 stores the storage addresses in the reception data buffer 700 sequentially from the buffer 1.

When the read access of the pixel data of the first row is completed, the DSP 100 starts the read access of the pixel data of the second row. As described in the first embodiment, the SDRAM interface circuit 200 detects that the read access has lost continuity in the comparison block 803 of the command control block 800 here.

SDRAM interface circuit 200
Compares the number of valid data 3 so far with the burst length set in the SDRAM 300 to determine whether or not the burst length is the optimum burst length.
Mode setting for the SDRAM 300
Change the settings of. In this example, the optimal burst length is “4”.

The SDRAM interface circuit 2
00 generates a read command with the storage address of the first pixel as a start address and outputs it to the SDRAM 300.

The SDRAM 300 outputs pixel data of the burst length (4 words) from the storage address of the first pixel in response to a command from the SDRAM interface circuit 200. The SDRAM interface circuit 200 receives four words of pixel data from the SDRAM 300, and stores
Although the data is stored in order, the pixel data of the fourth word exceeding the valid data number “3” is redundant, so that the writing to the buffer 4 is masked. As a result, the pixel data of the fourth word is discarded.

When the image synthesis processing block 1610 performs the second read access, the SDRAM interface circuit 200 outputs the three pixel data stored in the buffers 1 to 3 to the image synthesis processing block 1610. By reading such pixel data for three rows,
The image synthesis processing block 1610 includes the position correction pixel group 18
01 can be read from the image storage area of the SDRAM 300.

As described above, in the handy scanner 1500 according to the second embodiment, the image synthesis processing block 161 is used.
0 performs the position shift correction processing, the SDRAM 300
The pixel data can be read from the SDRAM 300 without considering the specification of. More specifically, the image synthesis processing block 1610 needs to recognize the setting content of the burst length of the SDRAM 300, compare it with the number of pixel data to be read by itself, and determine whether or not the burst length is optimal. There is no. Also, there is no need to perform a mode set in order to change the burst length to the optimal one. In addition, SDR
It is not necessary to perform a process of cutting off unnecessary pixel data from the pixel data output from the AM 300 by itself. Of course, there is no need to regenerate the address for the SDRAM 300, and no need to consider refresh.

As a result, the image composition processing block 1610
, And the displacement correction processing and the mapping processing can be performed at high speed. Also, an image synthesis processing block 1
In 610, it is necessary to incorporate a circuit for performing refresh and mode setting, to provide a buffer for temporarily storing pixel data of a burst length output from the SDRAM 300, and to provide a circuit for cutting off unnecessary pixel data. Since there is no circuit, the circuit configuration of the image synthesis processing block 1610 can be greatly simplified. Further, in designing the image synthesis processing block 1610, the designer is freed from complicated work for matching the specifications of the SDRAM 300.

The image synthesis processing block 1610 may be changed in circuit design for reasons such as increasing the accuracy of image synthesis, but it is not necessary to redesign the circuit for controlling SDRAM each time. Costs can be reduced.

In the second embodiment, the interface between the image synthesizing processing block 1610 and the SDRAM 300 has been described as an example. In addition, the present invention is also applied to the interface between various processing devices and the SDRAM in the image reading apparatus. The effect of can be obtained. Further, when the CPU performs the image synthesizing process, the CPU and the SDRA
It can be applied to the interface with M.

[0180]

As described above, according to the present invention,
Since the interface circuit between the control device and the SDRAM can control the SDRAM by generating and outputting a command according to a request from the control device without receiving a special command from the control device, the control device considers the control of the SDRAM. This eliminates the need to reduce the load on the control unit and increase the speed of operation, while simplifying the design and software programming of the control unit, shortening the development period and reducing development costs. It has the effect of being able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a relationship between an SDRAM interface circuit and a DSP and an SDRAM according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a timing chart of a DSP-side signal line in the first embodiment.

FIG. 3 is a diagram showing a timing chart for an SDRAM side signal line in the first embodiment.

FIG. 4 is a block diagram showing an internal configuration of the SDRAM interface circuit according to the first embodiment;

FIG. 5 is a block diagram showing an internal configuration of a transmission data buffer of the SDRAM interface circuit according to the first embodiment.

FIG. 6 is a block diagram showing an internal configuration of an address selector of a transmission data buffer according to the first embodiment.

FIG. 7 is a block diagram showing an internal configuration of a reception data buffer of the SDRAM interface circuit according to the first embodiment.

FIG. 8 is a block diagram showing an internal configuration of a command control block according to the first embodiment.

FIG. 9 is a block diagram showing a selector of the SDRAM interface circuit according to the first embodiment;

FIG. 10 is a flowchart showing the operation of the command generation block according to the first embodiment.

FIG. 11 is a diagram showing an example of an addressing sequence in the SDRAM in the sequential mode

FIG. 12 is a block diagram showing an internal configuration of a command regeneration block in the SDRAM interface circuit according to the first embodiment;

FIG. 13 is a diagram showing the operation of the selector of the command regeneration block of the SDRAM interface circuit according to the first embodiment.

FIG. 14 is a view for explaining a method of calculating a redesignated address in the SDRAM interface circuit according to the first embodiment;

FIG. 15 is a block diagram showing a handy scanner according to Embodiment 2 of the present invention.

FIG. 16 is a block diagram showing an internal configuration of an LSI of the handy scanner according to the second embodiment.

FIG. 17 is an explanatory diagram of a scanning area of a line image sensor in the handy scanner according to the second embodiment.

FIG. 18 is a diagram showing a position correction pixel group in a position shift correction process in the handy scanner according to the second embodiment.

[Explanation of symbols]

100 DSP 200 SDRAM interface circuit 500 Transmission data buffer 501, 701 Buffer block 502 Write counter 503 Write selector 504 Address selector 505 Output counter 601 CS selector 602 BS selector 603 Row address selector 604 Column address selector 605 Row / column selector 700 Receive data Buffer 702 Read counter 703 Read request selector 704 Readout selector 705 Address selector 706 Input counter 800 Command control block 801 Access counter 802 Command register 803 Comparison block 804 Refresh cycle (RC) count block 805 Command generation block 900 Input / output selector 1 200 Command regeneration block 1500 Handy scanner 1510 Document reading unit 1511 Line image sensor 1512, 1513 Encoder section 1610 Image synthesis processing block

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/00 597 G06F 12/00 597C G06T 1/60 450 G06T 1/60 450G G11C 11/407 G11C 11 / 34 362S 11/401 371H

Claims (19)

[Claims] An SD for connecting a control device and an SDRAM.
A RAM interface circuit, comprising: a plurality of address buffer means for storing a read address input from the control device; a determining means for determining continuity of the read address stored in the plurality of address buffer means; When it is determined that there is no more continuity in the read address, a command generating means for generating and outputting a read command with the first read address stored in the plurality of address buffer means as a start address so far, A plurality of data buffer means for storing read data input from the SDRAM in response to a read command; and a read data output means for outputting the read data stored in the plurality of data buffer means to the control device. SDRAM interface characterized by the following: Base circuit. 2. The apparatus further comprises read counter means for counting read accesses from a control device, wherein the command generation means obtains an optimum burst length for the count value from the count value of the read counter means and the burst length of the SDRAM, 2. The SDRAM interface circuit according to claim 1, wherein a command to be changed is generated and output. 3. A read counter for counting read accesses from a controller, and when read data exceeding a count value of the read counter is input from an SDRAM, the read data is stored in a plurality of data buffers. Input control means for discarding without
The SDRAM interface circuit according to claim 1 or 2, further comprising: 4. An SD for connecting a control device to an SDRAM.
A RAM interface circuit, comprising: a plurality of buffer means for storing write data input from the control device and a write address thereof; a determination means for determining continuity of the write addresses stored in the plurality of buffer means; When the determination means determines that there is no more continuity in the write address, a command generation means that generates and outputs a write command with the first write address stored in the plurality of buffer means as a start address so far, An SDRAM interface circuit, comprising: write data output means for sequentially outputting the write data stored in the plurality of buffer means at a predetermined timing after the output of the write command. 5. A write counter means for counting write accesses from a control device, wherein the command generation means obtains an optimum burst length for the count value from the count value of the write counter means and a burst length of the SDRAM. 5. The SDRAM interface circuit according to claim 4, wherein a command to change is generated and output. 6. A write counter means for counting write accesses from a control device, and an output control means for masking output of write data from a buffer means for storing write data exceeding a count value of the write counter means. 5. The apparatus according to claim 4, further comprising:
Or the SDRAM interface circuit according to claim 5. 7. A refresh cycle counting means for measuring a refresh timing interval by itself and notifying the command generation means of a refresh timing, wherein the command generation means generates and outputs a refresh command when the notification is received. 7. The SDRAM interface circuit according to claim 1, wherein the SDRAM performs a refresh operation by performing a refresh operation. 8. An SDRAM further comprising setting holding means for holding the setting contents of a mode register, wherein the command generating means generates and outputs a mode set command according to the setting contents to set the mode register. S according to any one of claims 1 to 7,
DRAM interface circuit. 9. It is determined whether or not address carry-over is ignored in an addressing sequence in an SDRAM based on an input address from a control device. 9. The apparatus according to claim 1, further comprising a command regeneration determination unit for instructing regeneration.
The SDRAM interface circuit according to any one of the above. 10. An SDR based on a signal from a control device.
An SDRAM control method for controlling an AM, wherein a read address input from the control device is stored, and continuity of the stored read address is determined.
If the determination means determines that the read address is no longer continuous, a read command is generated and output starting from the first read address stored so far, and the SD command is generated in response to the read command.
SDRA for outputting read data inputted from a RAM to said control device.
M control method. 11. A read access from a control device is counted, a burst length optimal for the count value is obtained from the count value and a burst length of the SDRAM, and a command for changing is generated and output. 1
0 SDRAM control method. 12. A read access from the control device is counted, and read data exceeding the count value is sent to the SDR.
12. The SDRAM control method according to claim 10, wherein when read from the AM, the read data is discarded without being stored in a plurality of data buffer means. 13. An SDR based on a signal from a control device.
An SDRAM control method for controlling an AM, comprising: storing write data input from the control device and a write address thereof; determining continuity of the stored write address; and determining that the write address has no further continuity. Generating a write command with the first write address stored so far as a start address, outputting the write command, and sequentially outputting the stored write data at a predetermined timing after the output of the write command. SDRAM control method. 14. The method according to claim 1, wherein a write access from the control device is counted, a burst length optimum for the count value is obtained from the count value and a burst length of the SDRAM, and a command for changing the burst length is generated and output. 1
3. The SDRAM control method according to 3. 15. The method according to claim 13, wherein write accesses from the control device are counted, and output of write data exceeding the count value is masked.
5. The SDRAM control method according to 4. 16. The method according to claim 10, wherein the refresh timing interval is measured by itself, and a refresh command is generated and output at the refresh timing to cause the SDRAM to execute the refresh. SDRAM control method. 17. The mode register according to claim 10, wherein the mode register of the SDRAM is held, and a mode set command is generated and output in accordance with the set content to set the mode register. 3. The SDRAM control method according to 1. 18. A method of determining whether address carry-over is ignored in an addressing sequence in an SDRAM based on an input address from a control device, and regenerating and outputting a command when address carry-over is ignored. 18. The SDRAM control method according to claim 10, wherein: 19. An image data read by scanning a document image and a scanning position corresponding to the image data are sequentially input, and the image data is converted to an SDRA based on the scanning position.
An image processing apparatus for storing the image data and the SDRAM in an overlapping scanning area for performing overlapping scanning.
A position shift detecting unit that detects a position shift of the scanning position from the stored data stored therein, and outputs a correction value for correcting the position shift, and a correction unit that corrects the scanning position based on the correction value. And mapping means for storing the image data in the SDRAM based on the corrected scanning position, and connecting the position shift correcting means and / or the mapping means to the SDRAM. An image processing apparatus comprising the SDRAM interface circuit according to any one of claims 9 to 13.